Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a first electrode layer, a gate layer, a second electrode layer, a phase change storage layer and a third electrode layer which are stacked in sequence; wherein the value of the surface root mean square roughness of at least one of the first electrode layer, the second electrode layer and the third electrode layer is between 0.1 nm and 0.4 nm.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As an emerging non-volatile memory, phase-change random access memory (PCM) has great advantages in many aspects such as read and write speed, read and write times, data retention time, storage density per unit area, etc., and has become the focus of current storage technology research.

[0003] However, with the continuous development of storage technology, higher requirements are placed on the electrical performance of phase change memory. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same. To achieve the above-mentioned objectives, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a first electrode layer, a gating layer, a second electrode layer, a phase change storage layer, and a third electrode layer stacked in sequence; wherein the surface root mean square roughness value of at least one electrode layer is between 0.1 nanometers (nm) and 0.4 nanometers (nm).

[0006] In some embodiments, the method further includes: a preparation process used to form the at least one electrode layer includes a first deposition process; and a power parameter value range of the first deposition process is: 800W to 1500W.

[0007] In some embodiments, the method also includes: the preparation process used to form the at least one electrode layer also includes a second deposition process; the second deposition process is performed after the first deposition process, and the power parameter value of the second deposition process is greater than the power parameter value of the first deposition process.

[0008] In some embodiments, the power parameter value range of the second deposition process is: 1800W to 2800W.

[0009] In some embodiments, the method further includes: forming a first conductive layer on the gating layer using the first deposition process, and forming a second conductive layer on the first conductive layer using the second deposition process to form the second electrode layer.

[0010] In some embodiments, the first deposition process and the second deposition process both include physical vapor deposition processes.

[0011] In some embodiments, the first conductive layer and the second conductive layer are formed of a material comprising one of carbon and titanium nitride.

[0012] In some embodiments, a thickness ratio of the first conductive layer to the second conductive layer in the stacking direction is 2 to 2.5.

[0013] In some embodiments, the deposition rate parameter value range of the first deposition process is: (Angstroms per second); the deposition rate parameter value range of the second deposition process is:

[0014] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, which is prepared using the method described in the above-mentioned embodiment of the present disclosure; wherein, the semiconductor device includes: a first electrode layer, a gating layer, a second electrode layer, a phase change storage layer and a third electrode layer stacked in sequence; the surface root mean square roughness value of at least one of the first electrode layer, the second electrode layer and the third electrode layer is between 0.1 nanometers and 0.4 nanometers.

[0015] In the embodiment of the present disclosure, by setting the surface root mean square roughness value of at least one electrode layer among the first electrode layer, the second electrode layer and the third electrode layer to between 0.1 nanometers and 0.4 nanometers, the scattering effect of surface peaks and valleys on electrons during transmission in the electrode layer can be reduced, thereby changing the direction and speed of electron movement, improving electron mobility, and reducing resistance, thereby improving the conductivity, optical properties, mechanical properties and chemical stability of the electrode layer, and thereby improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of an exemplary system having a memory device according to an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0019] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0020] Figures 5 to 25 A schematic cross-sectional view of the manufacturing process of a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0022] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0023] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0024] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0025] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0026] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0027] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0028] The semiconductor device involved in the embodiments of the present disclosure is at least a portion of a final device structure that will be used in subsequent processes. Here, the final device may include a memory device composed of horizontally and vertically staggered bit lines, word lines, and memory cells. The memory device may be volatile or non-volatile. Non-volatile memory can maintain its stored logical state for a long time in the absence of an external power supply. Volatile memory will lose its stored state over time after power is lost, and usually needs to be periodically refreshed by an external power supply.

[0029] In some embodiments, memory devices include, but are not limited to, phase change memory (PCM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), selector only memory (SOM), and others. The following description uses phase change memory (PCM) as an example. However, it should be noted that the description of phase change memory (PCM) in the following embodiments is intended only to illustrate the present disclosure and is not intended to limit the scope of the present disclosure.

[0030] It should be understood that phase change memory (PCM) can use the Joule heat generated by electric pulses to convert phase change materials between crystalline state (low resistance state) and amorphous state (high resistance state). The resistance difference between the low resistance state and the high resistance state is obvious, thereby realizing the writing and erasing of information. The reading of information is achieved by measuring the change in resistance.

[0031] The phase change memory provided by the present disclosure is described in detail below with reference to the accompanying drawings and embodiments. Before introducing the embodiments of the present disclosure, various directions that may be involved in the following text are defined. In the following embodiments, the stacking direction of each layer in the memory cell is defined as a third direction, namely the Z-axis direction. In a plane perpendicular to the third direction, a first direction and a second direction intersecting therewith are defined, namely the X-axis direction and the Y-axis direction. In a specific embodiment, the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0032] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or retrieve data from the memory device 104.

[0033] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Universal Serial Bus (USB) flash drive or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise memory cell arrays.

[0034] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0035] The memory controller 106 and one or more memory devices 104 may be integrated into various types of memory devices. Figure 2In one example shown in FIG, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 3 In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0036] A memory device may include a memory cell array and peripheral circuitry, which may be integrated on the same or different dies, which may allow for wider buses and higher operating speeds.

[0037] The peripheral circuitry may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory device. For example, the peripheral circuitry may include control logic, a data buffer, a decoder (a decoder may also be referred to as a decoder), a driver, and read / write circuitry. When the control logic receives a read / write operation command and address data, the decoder, under the control of the control logic, may apply the corresponding voltage generated by the driver to the corresponding word line (WL) and bit line (BL) based on the decoded address to implement a data read or write operation, and exchange data with the external device through the data buffer. Exemplarily, after receiving a read or write operation command and address data, the control logic may, under the control of the decoder, determine the selected word line and selected bit line corresponding to a selected memory cell from a plurality of memory cells. Exemplarily, the memory cells may be controlled by a row decoder and a column decoder. Specifically, the row decoder may receive a row address from the memory controller and activate the appropriate word line based on the received row address. The column decoder may receive a column address from the memory controller and activate the appropriate bit line, thereby activating the memory cell at the intersection of the word line and bit line.

[0038] The memory cell array may include at least one memory array block, each memory array block may include multiple memory cell layers stacked along the Z-axis direction, and each memory cell layer may include multiple memory cells. Each memory cell may include a first electrode layer, a gate layer, a second electrode layer, a phase change memory layer, and a third electrode layer stacked / laminated along the Z-axis direction, wherein each row of memory cells is connected to an address line (e.g., a word line), and each column of memory cells is connected to an address line (e.g., a bit line). It should be understood that a memory cell may be located at the intersection of two address lines, and this intersection may be referred to as the address of the memory cell; other memory cells connected to a common conductive line may be referred to as unselected memory cells.

[0039] Exemplary, reference Figure 4 The memory cell array may include a first memory cell layer and a second memory cell layer stacked together, wherein the first memory cell layer includes a plurality of first memory cells 302, each of which may include a first electrode layer 3021 (also called a bottom electrode, BE), a gating layer 3022, a second electrode layer 3023 (also called a middle electrode, ME), a phase change memory layer 3024 and a third electrode layer 3025 (also called a top electrode, TE); the second memory cell layer includes a plurality of second memory cells 305, each of which includes a fourth electrode layer 3051, a gating layer 3052, a fifth electrode layer 3053, a phase change memory layer 3054 and a sixth electrode layer 3055, or other film layer structures. Here, the gating layer 3022 in the first memory cell and the gating layer 3052 in the second memory cell may be the same or different, and the phase change memory layer 3024 in the first memory cell and the phase change memory layer 3054 in the second memory cell may be the same or different.

[0040] In some embodiments, the first memory cell layer is located between the first and second class address lines, the second memory cell layer is located between the third and fourth class address lines, and the second and third class address lines are arranged adjacent to each other. The first class address lines may include multiple first address lines 301, the second class address lines may include multiple second address lines 303, the third class address lines may include multiple third address lines 304, and the fourth class address lines may include multiple fourth address lines 306. The first address lines 301 are perpendicular to the second address lines 303, the second address lines 303 are parallel to the third address lines 304, and the first address lines 301 are parallel to the fourth address lines 306. Exemplarily, the first and fourth class address lines are bit lines BL, and the second and third class address lines are word lines WL. It should be understood that word lines WL and bit lines BL can be interchangeable. In some embodiments, the second and third class address lines can be combined into a shared word line (Share WL). Here, each address line can be coupled to a row of memory cells in the direction in which it extends.

[0041] In some embodiments, the memory device may further include a connection structure 307 (also referred to as a contact structure, CT). The connection structure 307 is coupled to the memory cell through an address line (bit line or word line) for transmitting an electrical signal.

[0042] It should be noted that in the above embodiment, the memory cell layers in the memory cell array are stacked in a two-layer architecture (a first memory cell layer and a second memory cell layer); in other embodiments, the memory cell layers in the memory cell array may also be stacked in a single layer, or in a three-layer, four-layer, or other stacked architecture. The following embodiments are described using only two layers as an example, but it should be understood that the following description of the memory cell layers in the memory cell array is intended only to illustrate the present disclosure and is not intended to limit the scope of the present disclosure.

[0043] In practical applications, the surface roughness of the electrode layer may affect the optical properties, electrical properties, mechanical properties and chemical stability of the storage unit or even the memory device. For example, if the surface roughness of the electrode layer is too large, electrons will be scattered by the peaks and valleys on the surface when transmitting in the electrode layer film, changing the direction and speed of electron movement, resulting in reduced electron mobility and increased resistance, thereby affecting the conductive performance of the electrode layer.

[0044] In response to one or more of the above-mentioned problems, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The method includes forming a first electrode layer, a gate layer, a second electrode layer, a phase-change memory layer, and a third electrode layer stacked in sequence; wherein the root mean square roughness of at least one of the first, second, and third electrode layers is between 0.1 nanometers and 0.4 nanometers.

[0045] In this way, by setting the surface root mean square roughness value of at least one electrode layer among the first electrode layer, the second electrode layer and the third electrode layer to be between 0.1 nanometers and 0.4 nanometers, the scattering effect of surface peaks and valleys on electrons when transmitting in the electrode layer can be reduced, thereby changing the direction and speed of electron movement, improving electron mobility, and reducing resistance, thereby improving the conductivity, optical properties, mechanical properties and chemical stability of the electrode layer, and thus improving the electrical performance of the semiconductor device.

[0046] Figures 5 to 25 This is a schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. Figures 5 to 13 、 Figure 25 is a schematic cross-sectional view of a semiconductor device on the XZ plane; Figures 14 to 24 is a schematic cross-sectional view of a semiconductor device on the YZ plane; the following describes the manufacturing process of the semiconductor device in detail in conjunction with the accompanying drawings and embodiments. Here, to more clearly describe the inventive concept of the present disclosure, the following embodiments are described using the example of the at least one electrode layer mentioned above being the second electrode layer. However, it should be understood that the at least one electrode layer mentioned above may also be the first electrode layer or the third electrode layer, etc.

[0047] refer to Figure 5 , the method comprises: providing a substrate ( Figure 5 (not shown), and forming a first address line material layer 501 on the substrate. The constituent materials of the substrate may include semiconductor materials, such as silicon, germanium or gallium arsenide. The constituent materials of the first address line material layer 501 include conductive materials, and the conductive materials include but are not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped polysilicon or any other suitable materials. The method of forming the first address line material layer 501 includes but is not limited to a deposition process. Here, the deposition process includes, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0048] refer to Figure 6The method includes forming a first electrode material layer 502 on a first address line material layer 501; the first electrode material layer 502 is composed of one of carbon (C) and titanium nitride (TiN). Methods for forming the first electrode material layer 502 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0049] refer to Figure 7 The method includes forming a gate material layer 503 on the first electrode material layer 502. The gate material layer 503 may be made of, but not limited to, Ovonic Threshold Switching (OTS) materials, such as zinc telluride (ZnaTeb), germanium telluride (GeaTeb), niobium oxide (NbaOb), or silicon arsenic telluride (SiaAsbTec). Methods for forming the gate material layer 503 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0050] Next, the method includes: forming a second electrode material layer 504 on the gating material layer 503, and the constituent material of the second electrode material layer 504 may include one of carbon and titanium nitride. In some embodiments, a first deposition process may be used to form the second electrode material layer 504, and the power parameter value range of the first deposition process is: 800W to 1500W. Exemplarily, the first deposition process includes a physical vapor deposition process (PVD), specifically, the first deposition process is a vacuum sputtering process in the physical vapor deposition process. When the second electrode material layer is formed using a vacuum sputtering device, the process parameters of the device may include multiple, for example, vacuum parameters, power parameters, voltage parameters, deposition rate parameters, etc. Here, the power parameter value of the vacuum sputtering device in the process of forming the second electrode material layer 504 is between 800W and 1500W.

[0051] In such a low power (800W-1500W) mode, on the one hand, the energy of the sputtered particles is insufficient to cause excessive surface rearrangement or stress accumulation, thereby reducing the formation of defects (such as holes, cracks, and gaps) in the second electrode material layer (such as the carbon film layer). On the other hand, the low power mode can reduce the damage to the carbon film layer caused by high-energy ions (plasma) and is more conducive to the formation of carbon atoms in the Sp2 hybridization mode. The resulting carbon film layer has a more ordered structure and a denser film layer, reducing the overall roughness of the carbon film layer and having a more uniform chemical bond distribution, thereby improving the mechanical properties and stability of the electrode material layer.

[0052] In some embodiments, the root mean square roughness (Rq) of the surface of the second electrode material layer 504 is between 0.1 nm and 0.4 nm, that is, 0.1≤Rq≤0.4. The thickness of the second electrode material layer 504 can be set according to actual needs.

[0053] It should be noted that the smaller the root mean square roughness of the thin film layer, the denser the arrangement of the atomic or molecular particles, and the smoother the surface of the thin film layer. This can reduce the scattering effect caused by surface peaks and valleys when electrons are transmitted in the thin film layer, increase the mobility of electrons, reduce the resistance of the thin film layer, and thus improve the conductivity of the thin film layer.

[0054] Here, the first electrode material layer is formed only through the first deposition process.

[0055] In some embodiments, in order to increase the deposition rate of the second electrode material layer, the preparation process used when forming the second electrode material layer may further include a second deposition process, that is, the first electrode material layer may be prepared by a first deposition process and a second deposition process. Here, the second deposition process is performed after the first deposition process, wherein the power parameter value of the second deposition process is greater than the power parameter value of the first deposition process. The second deposition process may be the same as the first deposition process, for example, both include a physical vapor deposition process (PVD), specifically, the second deposition process is a vacuum sputtering process in a physical vapor deposition process. The specific method for forming the second electrode material layer may be: forming a first conductive material layer on the gating material layer using a first deposition process, and forming a second conductive material layer on the first conductive material layer using a second deposition process to form a second electrode material layer. Exemplarily, the power parameter value range of the second deposition process is: 1800W to 2800W.

[0056] Exemplary, reference Figure 8 and Figure 9 A first conductive material layer 5041 is formed on the gate material layer 503 using a first deposition process, and a second conductive material layer 5042 is formed on the first conductive material layer 5041 using a second deposition process, thereby forming the second electrode material layer 504. Here, both the first deposition process and the second deposition process are vacuum sputtering processes. During the formation of the first conductive material layer 5041, the power parameter value of the vacuum sputtering equipment is between 800W and 1500W, and during the formation of the second conductive material layer 5042, the power parameter value of the vacuum sputtering equipment is between 1800W and 2800W. The first conductive material layer 5041 and the second conductive material layer 5042 are composed of the same material, for example, both include carbon or titanium nitride.

[0057] The first conductive material layer formed in the low power (800W-1500W) mode has a high density and low surface roughness. For example, the surface root mean square roughness of the first conductive material layer is between 0.1 nanometers and 0.4 nanometers. In this case, the first conductive material layer provides a good epitaxial substrate for the deposition of the second conductive material layer, which can reduce the interface defects of the second conductive material layer, making the structure of the second conductive material layer more ordered and dense, with low porosity and low roughness. Exemplarily, the surface root mean square roughness of the second conductive material layer is also between 0.1 nanometers and 0.4 nanometers.

[0058] In high power (1800W-2800W) mode, on the one hand, the overall preparation efficiency of the second electrode material layer can be improved; on the other hand, the stability of the plasma can be increased. At the same time, combined with the adjustment of the pressure parameter, the collision rate of gas molecules can be reduced to balance the negative effects brought about by the short mean free path, such as many defects and voids, and thus reduce the roughness of the second conductive material layer, thereby achieving the purpose of improving the roughness of the surface of the second conductive material layer (i.e., the surface of the second electrode material layer).

[0059] Here, the first electrode material layer is formed through a first deposition process and a second deposition process.

[0060] In some embodiments, the thickness of the first conductive material layer in the stacking direction (Z-axis direction) and the thickness of the second conductive material layer in the stacking direction (Z-axis direction) may be the same or different. In some specific embodiments, the thickness ratio of the first conductive material layer to the second conductive material layer in the stacking direction is 2 to 2.5. The total thickness range of the first conductive material layer and the second conductive material layer in the stacking direction is: 17nm to 25nm. It should be noted that the thickness of the first conductive material layer, the thickness of the second conductive material layer, the thickness ratio of the two, and the total thickness of the two can all be controlled by adjusting the deposition time, deposition rate and other parameter conditions in the vacuum sputtering equipment. Based on the different requirements for the thickness of the second electrode material layer, this is not limited here.

[0061] In some embodiments, the deposition rate parameter value range of the first deposition process is: The deposition rate parameter value range of the second deposition process is:

[0062] It should be understood that the above deposition rate parameter values ​​are applicable to the deposition rate corresponding to the deposition process when the conductive material layer is composed of carbon. When the conductive material layer is composed of other materials, such as titanium nitride, the deposition rate of the deposition process can also be other values.

[0063] refer to Figure 10The method further includes forming a phase-change memory material layer 505 on the second electrode material layer 504. The phase-change memory material layer 505 may be composed of a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase-change material. Methods for forming the phase-change memory material layer 505 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0064] refer to Figure 11 The method further includes forming a third electrode material layer 506 on the phase-change memory material layer 505. The third electrode material layer 506 may be formed of one of carbon and titanium nitride. Methods for forming the third electrode material layer 506 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0065] refer to Figure 12 The method further includes: using a self-aligned double patterning (SADP) process to form a plurality of first grooves extending along the Y-axis and spaced apart along the X-axis, wherein the plurality of first grooves penetrate the first address line material layer 501, the first electrode material layer 502, the gate material layer 503, the first conductive material layer 5041, the second conductive material layer 5042, the phase-change memory material layer 505, and the third electrode material layer 506 along the Z-axis to form first address lines 601, first electrode strips 602, the gate material strips 603, the first conductive material strips 6041, the second conductive material strips 6042, the phase-change memory material strips 605, and the third electrode material strips 606. The plurality of first address lines 601 extend along the Y-axis and spaced apart along the X-axis.

[0066] The method further includes filling the plurality of first recesses with an insulating material to form a plurality of first isolation structures 507. The first isolation structures 507 may be formed of materials including, but not limited to, silicon oxide (SiO2). Methods for forming the first isolation structures 507 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0067] refer to Figure 13 The method further includes forming a second address line material layer 508 on the third electrode material strips 606 and the first isolation structure 507. The second address line material layer 508 may be formed of a material including, but not limited to, tungsten (W). The second address line material layer 508 may be formed using methods including, but not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0068] refer to Figure 14The method further includes forming a plurality of second grooves extending along the X-axis direction and spaced apart along the Y-axis using a self-aligned double patterning (SADP) technique. The plurality of second grooves penetrate the first electrode strips 602, the gate material strips 603, the first conductive material strips 6041, the second conductive material strips 6042, the phase-change memory material strips 605, the third electrode material strips 606, and the second address line material layer 508 along the Z-axis direction to form a first electrode layer 702, a gate layer 703, a first conductive layer 7041, a second conductive layer 7042, a phase-change memory layer 705, a third electrode layer 706, and second address lines 708. Here, the first conductive layer 7041 and the second conductive layer 7042 constitute the second electrode layer 704. The plurality of second address lines 708 extend along the X-axis direction and spaced apart along the Y-axis direction.

[0069] The method further includes filling the second grooves with an insulating material to form a plurality of second isolation structures 509. The second isolation structures 509 may be formed of materials including, but not limited to, silicon oxide (SiO2). Methods for forming the second isolation structures 509 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0070] In this way, a first address line 601, a second address line 708, and a first memory cell located between the first address line 601 and the second address line 708 are formed. The first memory cell includes a first electrode layer 702, a gate layer 703, a second electrode layer 704, a phase-change memory layer 705, and a third electrode layer 706. Each first address line 601 is coupled to the first electrode layer 702 in a plurality of first memory cells arranged along the Y-axis direction; each second address line 708 is coupled to the third electrode layer 706 in a plurality of first memory cells extending along the X-axis direction. The positions of the phase-change memory layer and the gate layer can be interchanged.

[0071] It should be noted that when the phase change memory layer undergoes a phase change, the resistance of the phase change memory layer changes. The phase change memory can store and read data according to the change in the resistance state of the phase change memory layer.

[0072] refer to Figure 15 The method further includes: forming a third address line material layer 510 on the second address line 708 and the second isolation structure 509, wherein the constituent material of the third address line material layer 510 includes tungsten (W), and the method of forming the third address line material layer 510 includes but is not limited to CVD, LPCVD, PECVD, PVD and ALD.

[0073] refer to Figure 16The method further includes forming a fourth electrode material layer 511 on the third address line material layer 510. The fourth electrode material layer 511 may be formed of one of carbon and titanium nitride. Methods for forming the fourth electrode material layer 511 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD. The fourth electrode material layer 511 may be the same as the first electrode material layer 502.

[0074] refer to Figure 17 The method further includes forming a gate material layer 512 on the fourth electrode material layer 511. The gate material layer 512 may be formed of, but not limited to, Ovonic Threshold Switching (OTS) materials, such as zinc telluride (ZnaTeb), germanium telluride (GeaTeb), niobium oxide (NbaOb), or silicon arsenic telluride (SiaAsbTec). Methods for forming the gate material layer 512 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0075] refer to Figure 18 The method further includes forming a third conductive material layer 5131 on the gating material layer 512 using a first deposition process, wherein the third conductive material layer 5131 is composed of one of carbon and titanium nitride. The power parameter value of the first deposition process ranges from 800W to 1500W. Exemplarily, the first deposition process is a vacuum sputtering process in a physical vapor deposition process. During the formation of the third conductive material layer 5131, the power parameter value of the vacuum sputtering equipment is between 800W and 1500W. The third conductive material layer 5131 can be the same as the first conductive material layer 5041.

[0076] refer to Figure 19 , the method further includes: forming a fourth conductive material layer 5132 on the third conductive material layer 5131 using a second deposition process, wherein the third conductive material layer 5131 and the fourth conductive material layer 5132 are composed of the same material, for example, both may include one of carbon and titanium nitride. The power parameter value range of the second deposition process is: 1800W to 2800W. Exemplarily, the second deposition process is a vacuum sputtering process in a physical vapor deposition process. During the formation of the fourth conductive material layer 5132, the power parameter value of the vacuum sputtering equipment is between 1800W and 2800W. The fourth conductive material layer 5132 may be the same as the second conductive material layer 5042. In this way, the fifth electrode material layer 513 can be formed by the first deposition process and the second deposition process.

[0077] In this way, forming the third conductive material layer 5131 at low power (800W to 1500W) can reduce defects (such as holes, cracks, gaps, etc.) in the third conductive material layer (such as a carbon film layer), and can also reduce damage to the carbon film layer by high-energy ions (plasma). It is more conducive to the carbon atoms tending to form a film in an Sp2 hybrid manner, resulting in a more ordered structure of the carbon film layer, a denser film layer, and a more uniform distribution of chemical bonds. It can also reduce the overall roughness of the third conductive material layer. Here, the third conductive material layer provides a good epitaxial substrate for the deposition of the fourth conductive material layer, which can reduce the interface defects of the fourth conductive material layer.

[0078] In this way, forming the fourth conductive material layer 5132 at high power (1800W-2800W) can reduce interface defects in the fourth conductive material layer, making the structure of the fourth conductive material layer more ordered and dense, with low porosity and minimal roughness. It can also increase plasma stability. Combined with the adjustment of the pressure parameter, the collision rate of gas molecules can be reduced to balance the negative effects of a short mean free path, such as numerous defects and voids, thereby reducing the roughness of the fourth conductive material layer, thereby improving the surface roughness of the fifth electrode material layer 513. Furthermore, the high power mode can improve the overall preparation efficiency of the fifth electrode material layer 513.

[0079] In some embodiments, the root mean square roughness (Rq) of the surface of the fifth electrode material layer 513 is between 0.1 nanometers and 0.4 nanometers, that is, 0.1 ≤ Rq ≤ 0.4. This can reduce the scattering effect caused by surface peaks and valleys when electrons are transmitted in the fifth electrode material layer 513, improve electron mobility, reduce resistance, and thus improve the conductivity, mechanical properties, and chemical stability of the fifth electrode material layer 513.

[0080] It should be noted that the fifth electrode material layer 513 can be formed only by the first deposition process, or can be formed by both the first deposition process and the second deposition process, with the second deposition process being performed after the first deposition process. The first deposition process and the second deposition process have been described above and will not be repeated here.

[0081] refer to Figure 20The method further includes forming a phase-change memory material layer 514 on the fifth electrode material layer 513. The phase-change memory material layer 514 may be composed of a chalcogenide-based alloy, such as a GST (Ge-Sb-Te) alloy, or any other suitable phase-change material. Methods for forming the phase-change memory material layer 514 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0082] refer to Figure 21 The method further includes forming a sixth electrode material layer 515 on the phase-change memory material layer 514. The sixth electrode material layer 515 may be formed of one of carbon and titanium nitride. Methods for forming the sixth electrode material layer 515 may include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0083] refer to Figure 22 The method further includes forming a plurality of third grooves extending along the X-axis direction and spaced apart along the Y-axis direction using a self-aligned double patterning (SADP) process, wherein the plurality of third grooves penetrate the third address line material layer 510, the fourth electrode material layer 511, the gate material layer 512, the third conductive material layer 5131, the fourth conductive material layer 5132, the phase-change memory material layer 514, and the sixth electrode material layer 515 along the Z-axis direction to form third address lines 610, fourth electrode strips 611, the gate material strips 612, the third conductive material strips 6131, the fourth conductive material strips 6132, the phase-change memory material strips 614, and the sixth electrode material strips 615. The plurality of third address lines 610 extend along the X-axis direction and spaced apart along the Y-axis direction.

[0084] The method further includes filling the plurality of third recesses with an insulating material to form a plurality of third isolation structures 516. The third isolation structures 516 may be formed of materials including, but not limited to, silicon oxide (SiO2). Methods for forming the third isolation structures 516 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0085] It should be noted that the third isolation structure 516 may be made of the same material and prepared using the same method as the second isolation structure 509. The third isolation structure 516 may be aligned with the second isolation structure 509 along the Z-axis direction.

[0086] refer to Figure 23The method further includes forming a fourth address line material layer 616 on the sixth electrode material strip 615 and the third isolation structure 516. The fourth address line material layer 616 may be formed of a material including, but not limited to, tungsten (W). Methods for forming the fourth address line material layer 616 may include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0087] refer to Figure 24 and Figure 25 , Figure 24 is a schematic cross-sectional view of a semiconductor device in the YZ plane; Figure 25 The schematic diagram of the cross-section of the semiconductor device in the XZ plane is shown. The method further includes: using a self-aligned double patterning (SADP) technique to form a plurality of fourth grooves extending along the Y-axis and spaced apart along the X-axis. The plurality of fourth grooves extend along the Z-axis through the fourth electrode strip 611, the gate material strip 612, the third conductive material strip 6131, the fourth conductive material strip 6132, the phase-change memory material strip 614, the sixth electrode material strip 615, and the fourth address line material layer 616 to form a fourth electrode layer 711, the gate layer 712, the third conductive layer 7131, the fourth conductive layer 7132, the phase-change memory layer 714, the sixth electrode layer 715, and the fourth address line 716. Here, the third conductive layer 7131 and the fourth conductive layer 7132 constitute the fifth electrode layer 713. A plurality of fourth address lines 716 extend along the Y-axis and spaced apart along the X-axis.

[0088] The method further includes filling the fourth recess with an insulating material to form a plurality of fourth isolation structures 717. The fourth isolation structures 717 may be formed of materials including, but not limited to, silicon oxide (SiO2). Methods for forming the fourth isolation structures 717 include, but are not limited to, CVD, LPCVD, PECVD, PVD, and ALD.

[0089] It should be noted that the fourth isolation structure 717 may be made of the same material and prepared using the same method as the first isolation structure 507. The fourth isolation structure 717 may be aligned with the first isolation structure 507 along the Z-axis.

[0090] In this way, a third address line 610, a fourth address line 716, and a second memory cell located between the third address line 610 and the fourth address line 710 are formed. The second memory cell includes a fourth electrode layer 711, a gate layer 712, a fifth electrode layer 713, a phase-change memory layer 714, and a sixth electrode layer 715. Each third address line 610 is coupled to the fourth electrode layer 711 in a plurality of second memory cells arranged along the X-axis direction; and each fourth address line 716 is coupled to the sixth electrode layer 715 in a plurality of second memory cells extending along the Y-axis direction. Here, the positions of the phase-change memory layer and the gate layer can be interchanged.

[0091] In the embodiment of the present disclosure, the first address line 601 and the fourth address line 716 may be bit lines BL, and the second address line 708 and the third address line 610 may be word lines WL.

[0092] It should be noted that, in the above embodiments, it is described in detail that the second electrode layer and the fifth electrode layer can be formed by the first deposition process and the second deposition process; in other embodiments, the first electrode layer, the third electrode layer, the fourth electrode layer and the sixth electrode layer can all be formed by the first deposition process and the second deposition process. In this way, the roughness of each electrode layer can be reduced, and the electron mobility of the storage unit and even the semiconductor device can be further improved, so as to improve the electrical performance of the memory device.

[0093] Thus, in the embodiment of the present disclosure, at least one electrode layer among the multiple electrode layers is prepared by adopting the first deposition process, and the power parameter value range of the first deposition process is set to 800W to 1500W, so that in the process of forming the electrode layer, the energy of the sputtered particles is low, and the deposited atoms or molecules gather on the substrate with lower kinetic energy, and have more time to self-assemble and arrange, making the film layer more dense, thereby improving the structural stability and durability of the electrode layer. In addition, during the deposition process, the collision rate between gas molecules is reduced, reducing the probability of defects and voids in the electrode layer, so that the structure of the formed electrode layer is more orderly, thereby improving the electron mobility of the electrode layer, reducing the resistance, and thus improving its conductive performance.

[0094] Based on the above-mentioned method for manufacturing a semiconductor device, an embodiment of the present disclosure further provides a semiconductor device, which is prepared using the method described in the above-mentioned embodiment of the present disclosure; wherein, the semiconductor device includes: a first electrode layer, a gating layer, a second electrode layer, a phase change storage layer and a third electrode layer stacked in sequence; the surface root mean square roughness value of at least one electrode layer among the first electrode layer, the second electrode layer and the third electrode layer is between 0.1 nanometers and 0.4 nanometers.

[0095] In some embodiments, the second electrode layer includes a first conductive layer and a second conductive layer arranged along a stacking direction, and the first conductive layer is located between the second conductive layer and the gate layer.

[0096] In some embodiments, the first conductive layer is formed by a first deposition process; the second conductive layer is formed by a second deposition process. The first deposition process and the second deposition process both include physical vapor deposition processes, and the range of power parameter values ​​in the first deposition process is different from the range of power parameter values ​​in the second deposition process. Here, the range of power parameter values ​​in the first deposition process is smaller than the range of power parameter values ​​in the second deposition process; illustratively, the range of power parameter values ​​in the first deposition process is: 800W to 1500W; the range of power parameter values ​​in the second deposition process is: 1800W to 2800W.

[0097] In some embodiments, the first conductive layer and the second conductive layer are each composed of one of carbon and titanium nitride.

[0098] In some embodiments, a thickness ratio of the first conductive layer to the second conductive layer in the stacking direction is 2 to 2.5.

[0099] In some embodiments, the deposition rate parameter value range of the first deposition process is: The deposition rate parameter value range of the second deposition process is:

[0100] In some embodiments, the semiconductor device further includes: a first address line, the first address line being located on one side of the first electrode layer away from the selection layer on two opposite sides along the stacking direction; and a second address line, the second address line being located on one side of the third electrode layer away from the phase change storage layer on two opposite sides along the stacking direction.

[0101] Here, the extending direction of the first address line and the extending direction of the second address line are both perpendicular to the stacking direction. For example, the extending direction of the first address line is the X-axis direction, the extending direction of the second address line is the Y-axis direction, and the stacking direction is the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are mutually perpendicular.

[0102] In a third aspect, an embodiment of the present disclosure provides a storage system, comprising: a semiconductor device as described in the above embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0103] Here, the semiconductor device may be at least a portion of a memory device. The memory device may be, for example, the memory device of the aforementioned embodiment and the accompanying drawings. Figure 1 、 Figure 2 and Figure 3 The memory device mentioned in has been mentioned before and will not be repeated here.

[0104] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0105] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a first electrode layer, a gate layer, a second electrode layer, a phase change memory layer, and a third electrode layer stacked in sequence; The root mean square roughness of at least one of the first electrode layer, the second electrode layer and the third electrode layer is between 0.1 nanometers and 0.4 nanometers.

2. The method according to claim 1, characterized in that The method further comprises: The preparation process used to form the at least one electrode layer includes a first deposition process; the power parameter value range of the first deposition process is: 800W to 1500W.

3. The method according to claim 2, characterized in that The method further comprises: The preparation process used to form the at least one electrode layer also includes a second deposition process; the second deposition process is performed after the first deposition process, and the power parameter value of the second deposition process is greater than the power parameter value of the first deposition process.

4. The method according to claim 3, characterized in that The power parameter value range of the second deposition process is: 1800W~2800W.

5. The method according to claim 4, characterized in that The method further comprises: A first conductive layer is formed on the gating layer by using the first deposition process, and a second conductive layer is formed on the first conductive layer by using the second deposition process to form the second electrode layer.

6. The method according to claim 5, characterized in that The first deposition process and the second deposition process both include physical vapor deposition processes.

7. The method according to claim 5, characterized in that The first conductive layer and the second conductive layer are formed of a material selected from the group consisting of carbon and titanium nitride.

8. The method according to claim 5, characterized in that A thickness ratio of the first conductive layer to the second conductive layer in the stacking direction is 2 to 2.

5.

9. The method according to claim 3, characterized in that The deposition rate parameter value range of the first deposition process is: The deposition rate parameter value range of the second deposition process is:

10. A semiconductor device, characterized in that: The semiconductor device is prepared using the method described in any one of claims 1 to 9; wherein the semiconductor device includes: a first electrode layer, a gating layer, a second electrode layer, a phase change memory layer, and a third electrode layer stacked in sequence; the surface root mean square roughness value of at least one of the first electrode layer, the second electrode layer, and the third electrode layer is between 0.1 nanometers and 0.4 nanometers.

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