Octagonal cellular array structure with high performance and low on-resistance and preparation method thereof
By designing an octagonal cell array structure, optimizing the contact area of the N+ source region, the problems of large gate leakage capacitance and high on-resistance in traditional cell array structures are solved, and the low on-resistance and high frequency performance are improved.
Patent Information
- Application Number
- CN202510627878.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-08-26
AI Technical Summary
Traditional bar, square and hexagonal cell array structures have problems with large gate leakage capacitance and high on-resistance in high-frequency applications, resulting in poor high-frequency performance of power MOSFET devices.
Using an octagonal cell array structure, by superimposing a plurality of four symmetrically distributed child cell structures arranged periodically on the substrate, including the first and second daughter cell structures, and superimposing an ohmic contact layer and gate structure on the surface of the cell array structure, the contact area of the N+ source region is optimized, and the cell structure area is reduced to reduce the characteristic on-resistance.
It effectively reduces the device's characteristic on-resistance, improves high-frequency performance, reduces power consumption, and improves the device's high-frequency switching speed.
Smart Images
Figure CN120547902A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to an octagonal cell array structure with high performance and low on-resistance and a preparation method thereof. Background Art
[0002] Amidst the overall positive momentum of the power electronics industry, power semiconductor devices, which play a decisive role in power electronics, have become a direct factor influencing the cost and efficiency of power electronics equipment. As power MOSFETs (metal-oxide semiconductor field-effect transistors) devices gradually develop towards high power, high frequency, and low power consumption, the traditional MOSFET cell array structure has many shortcomings and is gradually unable to meet the needs of current high-frequency switching applications.
[0003] The high-frequency performance of power MOSFET devices mainly focuses on their on-state characteristics and gate-drain capacitance. The gate-drain capacitance of the device becomes the dominant factor in the switching speed of the device due to the amplification of the Miller effect, while the on-state characteristics of the device determine the power consumption of the device in high-frequency application scenarios. In high-frequency switching applications, power semiconductor devices are required to have low gate-drain capacitance (C GD ) or low gate-drain charge (Q GD ) and low characteristic on-resistance (R on,sp When comparing the high-frequency performance of devices, researchers use HF (High Frequency)-FOM (Figure of Merit) to measure the high-frequency performance. Generally, HF-FOM = C GD *R on.sp Or HF-FOM=Q GD *R on.sp .
[0004] The traditional strip cell array structure has low channel density, high on-resistance, and high gate-drain capacitance; the square and hexagonal cell array structures have high channel density and low on-resistance, but the gate-drain contact area is large, resulting in large gate-drain capacitance.
[0005] To address the problems with the aforementioned strip cell array structures, square cell arrays, and hexagonal cell array structures, the Baliga team proposed an octagonal cell array structure for OCTFETs, which reduces the gate-drain contact area, lowers the device gate-drain capacitance, and improves the high-frequency performance of power devices. However, the device cell structure obtained based on this existing octagonal cell array structure is large, resulting in a high characteristic on-resistance of the device, which in turn leads to poor high-frequency performance. Summary of the Invention
[0006] In order to solve the above problems existing in the prior art, the present invention provides an octagonal cell array structure with high performance and low on-resistance and a preparation method thereof.
[0007] The technical problem to be solved by the present invention is achieved through the following technical solutions:
[0008] In a first aspect, the present invention provides an octagonal cell array structure with high performance and low on-resistance, the octagonal cell array structure comprising:
[0009] substrate;
[0010] A cellular array structure superimposed on the substrate; the cellular array structure includes a plurality of periodically arranged cellular structures; the cellular structure includes four symmetrically distributed sub-cellular structures; the sub-cellular structures include a first sub-cellular structure and a second sub-cellular structure;
[0011] The first sub-cell structure includes a first epitaxial layer, a JFET region, a first P-well region, and a first N+ source region; the second sub-cell structure includes a second epitaxial layer, a second P-well region, a P+ source region, and a second N+ source region;
[0012] an ohmic contact layer, superimposed on a side of the upper surface of the cell array structure away from the JFET region;
[0013] A gate structure is superimposed on a side of the upper surface of the cell array structure close to the JFET region.
[0014] Optionally, the first P-well region is superimposed on a first area of the upper surface of the first epitaxial layer; the JFET region is superimposed on a second area of the upper surface of the first epitaxial layer; the first N+ source region is located above the first P-well region; and the first P-well region wraps around the side of the first N+ source region close to the JFET region.
[0015] Optionally, the P+ source region is superimposed on a first area of the upper surface of the second epitaxial layer; the second P-well region is superimposed on a second area of the upper surface of the second epitaxial layer; and the second N+ source region is superimposed on the second P-well region.
[0016] Optionally, the gate structure includes an oxide layer and a polysilicon layer stacked on the oxide layer.
[0017] Optionally, the thickness of the substrate is in the range of 100 μm to 360 μm; the doping concentration of the substrate is in the range of 5e18 cm -3 -1e20cm -3 .
[0018] Optionally, the thickness of the first epitaxial layer ranges from 5 μm to 150 μm; the thickness of the first P-well region ranges from 0.5 μm to 3 μm; and the thickness of the first N+ source region ranges from 0.1 μm to 0.5 μm.
[0019] Optionally, the doping concentration of the first epitaxial layer is in the range of 1e14 cm -3 -1e18cm -3 The doping concentration range of the JFET region is 1e14cm -3 -2e18cm -3 The doping concentration of the first P-well region is in the range of 1e15cm -3 -1e19cm -3 ; The doping concentration range of the first N+ source region is 5e18cm -3 -1e20cm -3 .
[0020] Optionally, the doping concentration of the second epitaxial layer is in the range of 1e14 cm -3 -1e18cm -3 The doping concentration of the second P-well region is in the range of 1e15cm -3 -1e19cm -3 The doping concentration range of the P+ source region is 1e18cm -3 -1e20cm -3 The doping concentration of the second N+ source region is in the range of 5e18cm -3 -1e20cm -3 .
[0021] Optionally, the thickness range of the second epitaxial layer is 5μm-150μm; the thickness range of the second P well region is 0.5μm-3μm; the thickness range of the P+ source region is 0.5μm-3μm; and the thickness range of the second N+ source region is 0.1μm-0.5μm.
[0022] In a second aspect, the present invention provides a method for preparing an octagonal cell array structure with high performance and low on-resistance, the preparation method comprising:
[0023] Select a substrate;
[0024] An initial epitaxial layer is grown on the substrate, and a cellular array structure is prepared by ion implantation from the upper surface of the initial epitaxial layer downward into a P-well region, an N+ source region, a P+ source region, and a JFET region; the cellular array structure includes a plurality of periodically arranged cellular structures; the cellular structure includes four symmetrically distributed sub-cellular structures; the sub-cellular structures include a first sub-cellular structure and a second sub-cellular structure; the first sub-cellular structure includes a first epitaxial layer, a JFET region, a first P-well region, and a first N+ source region; the second sub-cellular structure includes a second epitaxial layer, a second P-well region, a P+ source region, and a second N+ source region;
[0025] Growing an ohmic contact layer on a side of the upper surface of the cell array structure away from the JFET region;
[0026] A gate structure is grown on a side of the upper surface of the cell array structure close to the JFET region.
[0027] The present invention provides a high-performance, low-on-resistance octagonal cell array structure in which the cell array structure includes multiple periodically arranged cell structures; the cell structure includes four symmetrically distributed sub-cell structures; the sub-cell structure includes a first sub-cell structure and a second sub-cell structure. The first sub-cell structure includes a first epitaxial layer, a JFET region, a first P-well region, and a first N+ source region; the second sub-cell structure includes a second epitaxial layer, a second P-well region, a P+ source region, and a second N+ source region. By superimposing the ohmic contact layer on the upper surface of the cell array structure and the first N+ source region in the first sub-cell structure, the requirement for the N+ source region and the ohmic contact layer to have sufficient contact area to achieve the device conduction characteristics in the power MOSFET device is met. On this basis, in the second sub-cell structure, there is no need to require the ohmic contact layer to extend a certain distance beyond the P+ source region to contact the second N+ source region, thereby reducing the area of the cell structure and lowering the characteristic on-resistance, thereby improving the high-frequency performance of the device.
[0028] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a top view of the existing cell array structure;
[0030] Figure 2 It is a schematic diagram of a single existing cell structure;
[0031] Figure 3 It is a cross-sectional view of the existing cellular structure cut along the NM direction;
[0032] Figure 4 is a cross-sectional view of an octagonal cell array structure cut along the BA direction provided by an embodiment of the present invention;
[0033] Figure 5 is a cross-sectional view of an octagonal cell array structure cut along the B1A1 direction provided by an embodiment of the present invention;
[0034] Figure 6 1 is a top view of an octagonal cell array structure with high performance and low on-resistance provided by an embodiment of the present invention;
[0035] Figure 7 is a top view of a single cellular structure provided by an embodiment of the present invention;
[0036] Figure 8 1 is a schematic flow chart of a method for preparing an octagonal cell array structure provided by an embodiment of the present invention;
[0037] Figure 9 This is a schematic diagram of the preparation process of an octagonal cell array structure provided by an embodiment of the present invention.
[0038] Figure numerals: 1. substrate; 2. first epitaxial layer; 3. JFET region; 4. first P-well region; 5. first N+ source region; 6. ohmic contact layer; 7. gate structure; 8. second epitaxial layer; 9. second P-well region; 10. P+ source region; 11. second N+ source region. DETAILED DESCRIPTION
[0039] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.
[0040] The existing cell structure includes N+sub (N+ substrate), N EPI (N-type epitaxial layer), P well, P+ structure, N+ structure, ohmic contact, oxide (oxide layer) and Poly-Si (polysilicon). Figure 1 、 Figure 2 and Figure 3 , Figure 1 is a top view of the existing cell array structure. Figure 2 is a schematic diagram of a single existing cell structure. Figure 3 This is a cross-sectional view of the existing cell structure cut along the NM direction. According to the existing cell structure, in order to avoid process errors in the subsequent device manufacturing process that may lead to device manufacturing failure, the design of polysilicon and ohmic contact requires an isolation distance of more than 0.2μm between the two. At the same time, the pattern area used for lithography needs to meet a minimum area of not less than 1μm. 2 The design rules and the ohmic contact need to extend more than 0.5μm beyond the P+ structure to ensure sufficient contact area between the ohmic contact and the N+ source region. This results in the original cell array structure design having to meet the above specific requirements in both the horizontal and vertical dimensions, making it impossible to reduce the existing cell area, limiting further cell size reduction, resulting in a large cell area and high characteristic on-resistance of the device obtained by this cell array arrangement structure.
[0041] In order to solve the problem that the existing cell array structure causes the device cell area to be large and the characteristic on-resistance of the device to be high, the embodiment of the present invention provides an octagonal cell array structure with high performance and low on-resistance, see Figure 4 、 Figure 5 and Figure 6 , Figure 4 is a cross-sectional view of an octagonal cell array structure cut along the BA direction provided by an embodiment of the present invention, Figure 5 is a cross-sectional view of an octagonal cell array structure cut along the B1A1 direction provided by an embodiment of the present invention, Figure 61 is a top view of an octagonal cell array structure with high performance and low on-resistance provided by an embodiment of the present invention. The octagonal cell array structure includes a substrate 1, a cell array structure, an ohmic contact layer 6, and a gate structure 7.
[0042] In semiconductor devices, such as chips, LEDs (Light Emitting Diodes), and solar cells, the substrate 1 is a base material that supports functional layers.
[0043] In the embodiment of the present invention, the substrate 1 is an N-type substrate, and its thickness can range from 100 μm to 360 μm. The substrate 1 is a highly doped substrate, and its doping concentration can range from 5e18 cm -3 -1e20cm -3 .
[0044] Specifically, the material of the substrate 1 may be SiC (silicon carbide) or any other semiconductor material. For example, the substrate 1 may be a 4H-SiC substrate.
[0045] In the embodiment of the present invention, a cell array structure is superimposed on the substrate 1. Figure 6 , the cell array structure includes multiple periodically arranged cell structures.
[0046] In the embodiment of the present invention, see Figure 7 , Figure 7 1 is a top view of a single cellular structure provided by an embodiment of the present invention. The cellular structure includes four symmetrically distributed sub-cellular structures. Specifically, each cellular structure includes four centrally symmetrically distributed sub-cellular structures.
[0047] For example, the four sub-cell structures are sub-cell structure 1, sub-cell structure 2, sub-cell structure 3 and sub-cell structure 4. Figure 7 , constructing a coordinate system with the center point of the top view of a single cellular structure as the origin o, then sub-cellular structure 1 is located in the first quadrant, sub-cellular structure 2 is located in the second quadrant, sub-cellular structure 3 is located in the third quadrant, and sub-cellular structure 4 is located in the fourth quadrant. It can be understood that the four sub-cellular structures are centrally symmetrically distributed. Specifically, sub-cellular structure 1 is symmetrical with sub-cellular structure 2 along the y-axis, sub-cellular structure 2 is symmetrical with sub-cellular structure 3 along the x-axis, sub-cellular structure 3 is symmetrical with sub-cellular structure 4 along the y-axis, and sub-cellular structure 4 is symmetrical with sub-cellular structure 1 along the x-axis.
[0048] In the embodiment of the present invention, the sub-cell structure includes a first sub-cell structure and a second sub-cell structure, wherein the first sub-cell structure and the second sub-cell structure are periodically arranged along the upper surface of the substrate 1 in a direction perpendicular to BA, that is, perpendicular to B1A1.
[0049] In the embodiment of the present invention, the first sub-cell structure includes a first epitaxial layer 2 , a JFET (Junction Field Effect Transistor) region 3 , a first P-well region 4 and a first N+ source region 5 .
[0050] In one implementation, the first epitaxial layer 2 is superimposed on the substrate 1, and the upper surface of the first epitaxial layer 2 includes a first region and a second region along the BA direction, wherein the region of the upper surface of the first epitaxial layer 2 close to the A end is the second region of the upper surface of the first epitaxial layer 2, and the region close to the B end is the first region of the upper surface of the first epitaxial layer 2.
[0051] Specifically, the material of the first epitaxial layer 2 can be SiC or any other semiconductor material, the thickness can be in the range of 5 μm-150 μm, and the doping concentration can be 1e14 cm -3 -1e18cm -3 .
[0052] In the embodiment of the present invention, the first P-well region 4 is superimposed on a first region of the upper surface of the first epitaxial layer 2, and the JFET region 3 is superimposed on a second region of the upper surface of the first epitaxial layer 2. The side of the first P-well region 4 close to the A terminal contacts the side of the JFET region 3 close to the B terminal.
[0053] Specifically, the first P-well region 4 can be formed by ion implantation, wherein the ions can be boron ions. The doping concentration of the first P-well region 4 can be in the range of 1e15 cm -3 -1e19cm -3 , the thickness can range from 0.5μm to 3μm.
[0054] In the embodiment of the invention, the JFET region 3 can be formed by phosphorus or other N-type ion implantation, and the doping concentration of the JFET region 3 can be in the range of 1e14 cm -3 -2e18cm -3 , and its implantation depth is deeper than that of the first P-well region 4.
[0055] In the embodiment of the present invention, the first N+ source region 5 is located above the first P-well region 4. Specifically, the first N+ source region 5 is located above the first P-well region 4 on a side close to terminal B. Furthermore, the first P-well region 4 surrounds the side of the first N+ source region 5 close to the JFET region 3, i.e., terminal A. It will be understood that the lower surface of the first N+ source region 5 and the side close to terminal A are both in contact with the first P-well region 4.
[0056] In the embodiment of the present invention, the doping concentration range of the first N+ source region 5 is 5e18cm -3 -1e20cm -3 , thickness range is 0.1μm-0.5μm.
[0057] In the embodiment of the present invention, the second sub-cell structure includes a second epitaxial layer 8 , a second P-well region 9 , a P+ source region 10 and a second N+ source region 11 .
[0058] In one implementation, the second epitaxial layer 8 is superimposed on the substrate 1, the P+ source region 10 is superimposed on the first area of the upper surface of the second epitaxial layer 8; the second P-well region 9 is superimposed on the second area of the upper surface of the second epitaxial layer 8; and the second N+ source region 11 is superimposed on the second P-well region 9.
[0059] In the embodiment of the present invention, the upper surface of the second epitaxial layer 8 includes a first region and a second region along the B1A1 direction. The region near the A1 end of the upper surface of the second epitaxial layer 8 is the second region of the upper surface of the second epitaxial layer 8, and the region near the B1 end is the first region of the upper surface of the second epitaxial layer 8.
[0060] The second epitaxial layer 8 can be made of SiC or any other semiconductor material, with a thickness ranging from 5 μm to 150 μm and a doping concentration ranging from 1e14 cm -3 -1e18cm -3 .
[0061] In the embodiment of the present invention, the P+ source region 10 is superimposed on the first region of the upper surface of the second epitaxial layer 8, and the second P-well region 9 is superimposed on the second region of the upper surface of the second epitaxial layer 8. The side of the P+ source region 10 near the A1 end contacts the second P-well region 9 near the B1 end.
[0062] Among them, the doping concentration range of the P+ source region 10 is 1e18cm -3 -1e20cm -3 The thickness range is 0.5μm-3μm. The doping concentration range of the second P well region 9 is 1e15cm -3 -1e19cm -3 The thickness ranges from 0.5 μm to 3 μm. The implantation depths of the P+ source region 10 and the second P-well region 9 are usually the same.
[0063] In the embodiment of the present invention, the second N+ source region 11 is superimposed on the second P-well region 9. A side of the second N+ source region 11 close to the B1 end is in contact with a side of the P+ source region 10 close to the A1 end.
[0064] The doping concentration of the second N+ source region 11 is in the range of 5e18cm -3 -1e20cm -3 , thickness range is 0.1μm-0.5μm.
[0065] In the embodiment of the present invention, the first epitaxial layer 2 and the second epitaxial layer 8 are formed together, the first N+ source region 5 and the second N+ source region 11 are formed together, and the first P-well region 4 and the second P-well region 9 are formed together. The first P-well region 4, the second P-well region 9, and the P+ source region 10 are formed by boron or other P-type ion implantation, and the first N+ source region 5 and the second N+ source region 11 are formed by phosphorus or other N-type ion implantation.
[0066] In the embodiment of the present invention, the ohmic contact layer 6 is superimposed on a side of the upper surface of the cell array structure away from the JFET region 3 .
[0067] See also Figure 1 and Figure 2 The lower surface of the ohmic contact layer 6 contacts a portion of the upper surface of the first N+ source region 5 and the upper surface of the P+ source region 10. The ohmic contact layer 6 is made of Ni (nickel) and has a thickness ranging from 0.02 μm to 1 μm.
[0068] In the embodiment of the present invention, the ohmic contact layer 6 made of Ni is beneficial to the input and output of current.
[0069] In the embodiment of the present invention, the gate structure 7 is superimposed on a side of the upper surface of the cell array structure close to the JFET region 3. The gate structure 7 includes an oxide layer and a polysilicon layer superimposed on the oxide layer.
[0070] The lower surface of the oxide layer contacts the portion of the upper surface of the first P-well region 4 that is not covered by the first N+ source region 5, and the lower surface of the oxide layer contacts the portion of the first N+ source region 5 that is not covered by the ohmic contact layer 6. In addition, the lower surface of the oxide layer also covers the upper surface of the second N+ source region 11.
[0071] In the embodiment of the present invention, the oxide layer can play an isolation role and protect the structure located thereunder.
[0072] Specifically, the material of the oxide layer is SiO2 (silicon dioxide), and the thickness thereof is in the range of 5 nm to 100 nm.
[0073] In the embodiment of the present invention, the polysilicon layer is specifically located on the upper surface of the oxide layer near end A. The polysilicon layer does not completely cover the oxide layer, that is, the width of the polysilicon layer along the BA direction is smaller than the width of the oxide layer.
[0074] Specifically, the thickness of the polysilicon layer ranges from 0.5 μm to 2 μm. Along the BA direction, the width of the polysilicon layer is at least 0.2 μm less than the width of the oxide layer to ensure an isolation distance of at least 0.2 μm between the polysilicon layer and the ohmic contact layer 6, thereby preventing process errors in subsequent device fabrication from causing device fabrication failure.
[0075] In an embodiment of the present invention, a cellular array structure includes a plurality of periodically arranged cellular structures; the cellular structure includes four symmetrically distributed sub-cellular structures; and the sub-cellular structures include a first sub-cellular structure and a second sub-cellular structure. The first sub-cellular structure includes a first epitaxial layer 2, a JFET region 3, a first P-well region 4, and a first N+ source region 5; and the second sub-cellular structure includes a second epitaxial layer 8, a second P-well region 9, a P+ source region 10, and a second N+ source region 11. The ohmic contact layer 6 superimposed on the upper surface of the cellular array structure and the first N+ source region 5 in the first sub-cellular structure satisfy the requirement in power MOSFET devices that the N+ source region and the ohmic contact layer 6 have sufficient contact area to achieve device conduction characteristics. On this basis, in the second sub-cellular structure, the ohmic contact layer 6 no longer needs to extend a certain distance beyond the P+ source region 10 to contact the second N+ source region 11, thereby reducing the area of the cellular structure and lowering the characteristic on-resistance, thereby improving the high-frequency performance of the device.
[0076] In one implementation, see Figure 6 , the polysilicon layer is in a strip-shaped structure, and the ohmic contact layer 6 is in a strip-shaped structure. The use of a strip-shaped polysilicon layer and a strip-shaped ohmic contact layer 6 eliminates the isolation distance required in one direction in the cell array design, greatly reduces the length of the cell array structure in one direction, and reduces the cell area provided by the embodiment of the present invention by 39%. The characteristic on-resistance is related to the area of the cell structure. The smaller the cell structure area, the smaller the characteristic on-resistance. The characteristic on-resistance of the device with this array structure design is reduced by 30%. At the same time, the gate-drain contact area of the structure is small, and the significant reduction in the characteristic on-resistance improves the high-frequency performance of the device and reduces the power consumption level of the device.
[0077] The octagonal cell array structure provided by the embodiment of the present invention is applied, and the lateral size of a single cell structure obtained is 3.8 μm, the longitudinal size is 2.3 μm, and the area is 8.74 μm. 2 Compared with the existing cell design structure, the horizontal size is 3.8μm, the vertical size is 3.8μm, and the area is 14.44μm. 2 The area of a single cell structure in the octagonal cell array structure provided by the embodiment of the present invention is reduced by 39%.
[0078] Based on the same inventive concept, the present invention also provides a method for preparing an octagonal cell array structure with high performance and low on-resistance, see Figure 8 , Figure 8 This is a flow chart of a method for preparing an octagonal cell array structure provided by an embodiment of the present invention, see Figure 9 , Figure 9 FIG. 1 is a schematic diagram of a preparation process of an octagonal cell array structure provided by an embodiment of the present invention. The preparation method specifically includes the following steps:
[0079] Step S801: Select substrate 1.
[0080] In the embodiment of the present invention, an N-type substrate made of 4H-SiC may be selected.
[0081] Step S802, growing an initial epitaxial layer on the substrate 1, and completing the preparation of the cellular array structure by ion implantation from the upper surface of the initial epitaxial layer downward into the P-well region, the N+ source region, the P+ source region 10, and the JFET region 3; the cellular array structure includes a plurality of periodically arranged cellular structures; the cellular structure includes four symmetrically distributed sub-cellular structures; the sub-cellular structure includes a first sub-cellular structure and a second sub-cellular structure; the first sub-cellular structure includes a first epitaxial layer 2, a JFET region 3, a first P-well region 4, and a first N+ source region 5; the second sub-cellular structure includes a second epitaxial layer 8, a second P-well region 9, a P+ source region 10, and a second N+ source region 11.
[0082] See also Figure 9 In (a), an initial epitaxial layer is grown on substrate 1. The material of the initial epitaxial layer can be 4H-SiC.
[0083] In the embodiment of the present invention, the formation principle of the first sub-cell structure and the second sub-cell structure is the same. The formation process of the second sub-cell structure will be used as an example to illustrate the preparation method provided by the embodiment of the present invention. Ion implantation is performed downwardly on the upper surface of the initial epitaxial layer to implant ions into the P well region, N+ source region, P+ source region 10 and JFET region 3. Taking the second sub-cell structure as an example, see Figure 9 In (b), a second P well region 9, a P+ source region 10 and a second N+ source region 11 are formed by ion implantation.
[0084] In the embodiment of the present invention, the first P-well region 4 and the second P-well region 9 are simultaneously formed by ion implantation into the P-well region, and the first N+ source region 5 and the second N+ source region 11 are simultaneously formed by ion implantation into the N+ source region. Specifically, the first P-well region 4, the second P-well region 9, and the P+ source region 10 are formed by boron or other P-type ion implantation, and the first N+ source region 5 and the second N+ source region 11 are formed by phosphorus or other N-type ion implantation.
[0085] In the embodiment of the present invention, the doping type of the first P-well region 4 , the second P-well region 9 and the P+ source region 10 is P-type doping, and the doping type of the first N+ source region 5 and the second N+ source region 11 is N-type doping.
[0086] In the embodiment of the present invention, after ion implantation from the upper surface of the initial epitaxial layer downwards into the P well region, the N+ source region, the P+ source region 10 and the JFET region 3, the first epitaxial layer 2 and the second epitaxial layer 8 are formed in the areas not implanted with ions.
[0087] Step S803 : growing an ohmic contact layer 6 on a side of the upper surface of the cell array structure away from the JFET region 3 .
[0088] In the embodiment of the present invention, a magnetron sputtering method or other growth methods may be used to grow Ni with a thickness of 0.02 μm to 1 μm on the side of the upper surface of the cell array structure away from the JFET region 3 to form the ohmic contact layer 6 .
[0089] Step S804 : growing a gate structure 7 on a side of the upper surface of the cell array structure close to the JFET region 3 .
[0090] In the embodiment of the present invention, the gate structure 7 may be grown on the region of the upper surface of the device that is not covered by the ohmic contact layer 6 .
[0091] Specifically, a 5nm-100nm oxide layer (Oxide) can be grown on the area of the device surface not covered by the ohmic contact layer 6, wherein the material of the oxide layer is SiO2. Then, a 0.5μm-2μm polysilicon layer (Poly-Si) is grown on the side of the oxide layer away from the ohmic contact layer 6 to obtain the gate structure 7, see Figure 9 (c) in the figure, the preparation of the octagonal cell array structure is completed.
[0092] In this embodiment of the present invention, the ohmic contact layer 6 superimposed on the upper surface of the cellular array structure and the first N+ source region 5 in the first sub-cellular structure meet the power MOSFET device's requirement for sufficient contact area between the N+ source region and the ohmic contact layer 6 to achieve device conduction characteristics. Furthermore, in the second sub-cellular structure, the ohmic contact layer 6 no longer needs to extend a certain distance beyond the P+ source region 10 to contact the second N+ source region 11, reducing the area of the cellular structure and lowering the characteristic on-resistance, thereby improving the device's high-frequency performance.
[0093] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.
[0094] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.
[0095] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "a" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.
[0096] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.
[0097] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.
[0098] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.
[0099] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A high-performance, low-on-resistance octagonal cell array structure, characterized in that: The octagonal cell array structure includes: substrate; A cellular array structure superimposed on the substrate; the cellular array structure includes a plurality of periodically arranged cellular structures; the cellular structure includes four symmetrically distributed sub-cellular structures; the sub-cellular structures include a first sub-cellular structure and a second sub-cellular structure; The first sub-cell structure includes a first epitaxial layer, a JFET region, a first P-well region, and a first N+ source region; the second sub-cell structure includes a second epitaxial layer, a second P-well region, a P+ source region, and a second N+ source region; an ohmic contact layer, superimposed on a side of the upper surface of the cell array structure away from the JFET region; A gate structure is superimposed on a side of the upper surface of the cell array structure close to the JFET region.
2. The octagonal cell array structure according to claim 1, characterized in that: The first P-well region is superimposed on a first area of the upper surface of the first epitaxial layer; the JFET region is superimposed on a second area of the upper surface of the first epitaxial layer; the first N+ source region is located above the first P-well region; and the first P-well region wraps around the side of the first N+ source region close to the JFET region.
3. The octagonal cell array structure according to claim 1, wherein: The P+ source region is superimposed on the first area of the upper surface of the second epitaxial layer; the second P-well region is superimposed on the second area of the upper surface of the second epitaxial layer; and the second N+ source region is superimposed on the second P-well region.
4. The octagonal cell array structure according to claim 1, wherein: The gate structure includes an oxide layer and a polysilicon layer stacked on the oxide layer.
5. The octagonal cell array structure according to claim 1, wherein: The thickness of the substrate ranges from 100 μm to 360 μm; the doping concentration of the substrate ranges from 5e18 cm -3 -1e20cm -3 .
6. The octagonal cell array structure according to claim 1, characterized in that: The thickness of the first epitaxial layer ranges from 5 μm to 150 μm; the thickness of the first P-well region ranges from 0.5 μm to 3 μm; and the thickness of the first N+ source region ranges from 0.1 μm to 0.5 μm.
7. The octagonal cell array structure according to claim 1, wherein: The doping concentration range of the first epitaxial layer is 1e14cm -3 -1e18cm -3 The doping concentration range of the JFET region is 1e14cm -3 -2e18cm -3 The doping concentration of the first P-well region is in the range of 1e15cm -3 -1e19cm -3 ; The doping concentration range of the first N+ source region is 5e18cm -3 -1e20cm -3 .
8. The octagonal cell array structure according to claim 1, wherein: The doping concentration of the second epitaxial layer is in the range of 1e14 cm -3 -1e18cm -3 The doping concentration of the second P-well region is in the range of 1e15cm -3 -1e19cm -3 The doping concentration range of the P+ source region is 1e18cm -3 -1e20cm -3 The doping concentration of the second N+ source region is in the range of 5e18cm -3 -1e20cm -3 .
9. The octagonal cell array structure according to claim 1, wherein: The thickness of the second epitaxial layer ranges from 5 μm to 150 μm; the thickness of the second P-well region ranges from 0.5 μm to 3 μm; the thickness of the P+ source region ranges from 0.5 μm to 3 μm; and the thickness of the second N+ source region ranges from 0.1 μm to 0.5 μm.
10. A method for preparing a high-performance, low-on-resistance octagonal cell array structure, characterized in that: The preparation method comprises: Select a substrate; An initial epitaxial layer is grown on the substrate, and a cellular array structure is prepared by ion implantation from the upper surface of the initial epitaxial layer downward into a P-well region, an N+ source region, a P+ source region, and a JFET region; the cellular array structure includes a plurality of periodically arranged cellular structures; the cellular structure includes four symmetrically distributed sub-cellular structures; the sub-cellular structures include a first sub-cellular structure and a second sub-cellular structure; the first sub-cellular structure includes a first epitaxial layer, a JFET region, a first P-well region, and a first N+ source region; the second sub-cellular structure includes a second epitaxial layer, a second P-well region, a P+ source region, and a second N+ source region; An ohmic contact layer is grown on a side of the upper surface of the cell array structure away from the JFET region; and a gate structure is grown on a side of the upper surface of the cell array structure close to the JFET region.