Configurations for four-quadrant III-nitride switches

Abstract

An electronic assembly includes a semiconductor device including a four-quadrant switch (FQS), a first enhancement mode transistor, and a second enhancement mode transistor. The FQS is a depletion mode III-N device including a first power electrode, a second power electrode, and a second gate. The FQS further includes a III-N material structure in which a composition difference in the III-N material structure forms a 2DEG channel therein, and a first internal resistor formed from a first portion of the 2DEG channel, and a second internal resistor formed from a second portion of the 2DEG channel. A first drain of the first enhancement mode transistor is electrically connected and physically mounted to the first power electrode, and a second drain of the second enhancement mode transistor is electrically connected and physically mounted to the second power electrode.

Description

Technical Field

[0001] The disclosed technology relates to semiconductor devices and modules designed to achieve improved performance and reliability. Background Art

[0002] Currently, typical power semiconductor devices, including transistors, diodes, power MOSFETs, bidirectional switches, and insulated-gate bipolar transistors (IGBTs), are fabricated using silicon (Si) semiconductor materials. Recently, wide-bandgap materials (SiC, III-N, III-O, diamond) have been considered for use in power devices due to their superior properties. III-nitride or III-N semiconductor devices, such as gallium nitride (GaN), are now emerging as attractive candidates for carrying high currents, supporting high voltages, and offering very low on-resistance with fast switching times.

[0003] One type of semiconductor device gaining attention is one that can block both positive and negative voltages and modulate both positive and negative currents. Such devices are often referred to as four-quadrant switches (FQSs). They are of interest for high-frequency operation in extremely low-loss resonant-mode topologies for motor drives, bidirectional converters, solar inverters and microinverters, high-performance adapters and LED drivers, battery / supercapacitor power management systems, current source inverters, or matrix inverters. If well designed, such devices can exhibit low losses, low on-resistance, fast switching times, and are typically capable of withstanding high voltages, typically 600-1200V.

[0004] For some applications, FQS devices are enhancement-mode (i.e., E-mode) devices that are normally off and have a positive threshold voltage. The use of E-mode devices can prevent damage to the device or other circuit components and prevent any unintended turn-on of the device in the event of a circuit fault. For some applications, FQS devices are superior to traditional III-N HEMT transistors because they can allow substantial current flow in both directions and block substantial voltages in both directions (e.g., voltages similar to the device's maximum rating in both directions).

[0005] Figure 1A circuit schematic of a prior art enhancement-mode FQS switch 100 is shown, which includes a transistor 110. The switch includes a first electrode 123 that can alternate between a drain electrode or a source electrode (e.g., a D / S electrode) depending on the voltage polarity of the circuit. The switch further includes a second electrode 133 that can alternate between a source electrode or a drain electrode (e.g., an S / D electrode), regardless of which the first electrode is, depending on the voltage polarity of the circuit. Switch 100 includes a first gate electrode 122 and a second gate electrode 132. Switch 100 also includes a node 111, which can represent the substrate of transistor 110. Applying a voltage bias to node 111 biases the voltage of the sub-states of transistor 110.

[0006] When used as Figure 1 One type of device that shows promising benefits when designing enhancement-mode FQS switches 100 is the III-N high electron mobility transistor (HEMT). However, the reliable design, fabrication, and operation of high-voltage normally-off III-N bidirectional switches have so far proven to be very difficult. The main challenges are (1) back-gating crosstalk between the two sides of each FQS and (2) assembly complexity. Therefore, alternative configurations are needed to accelerate the market adoption of III-N FQS switches. Summary of the Invention

[0007] This document describes four-quadrant III-N switches and corresponding modules, any of which are suitable for operation as a four-quadrant switch (i.e., FQS). These devices or modules can be incorporated into an electronic component package. The design of the module, coupled with the design of the III-N devices used in the module, can result in reduced inductance and other parasitic effects, thereby allowing for greater circuit stability and improved performance. The electronic module can also have a reduced size and can be easier to assemble than traditional FQS switches such as silicon IGBTs, thereby allowing for lower production costs and higher reliability. When no distinction is needed between transistors, switches, or diodes, the term "device" will be used generically for any transistor, switch, or diode.

[0008] In a first aspect, an electronic component is described. The component includes a four-quadrant switch (FQS), a first enhancement-mode transistor, and a second enhancement-mode transistor. The FQS is a depletion-mode III-N device including a first power electrode, a second power electrode, and a second gate. The FQS further includes a III-N material structure, wherein compositional differences in the III-N material structure form a 2DEG channel therein, a first internal resistor formed by a first portion of the 2DEG channel, and a second internal resistor formed by a second portion of the 2DEG channel. A first drain of the first enhancement-mode transistor is electrically connected and physically mounted to the first power electrode, and a second drain of the second enhancement-mode transistor is electrically connected and physically mounted to the second power electrode, wherein a first terminal of the first internal resistor is connected to the first gate of the III-N device, a second terminal of the first internal resistor is electrically connected to the first drain of the enhancement-mode transistor, a first terminal of the second internal resistor is connected to the second gate of the III-N device, and a second terminal of the second internal resistor is electrically connected to the second drain of the second enhancement-mode transistor.

[0009] In a second aspect, an electronic assembly is described. The electronic assembly includes a package, a first terminal, a second terminal, a third terminal, a fourth terminal, a structural packaging substrate, an insulating spacer, and a hybrid enhancement-mode four-quadrant switch. The four-quadrant switch includes a III-N depletion-mode device, a first enhancement-mode transistor, and a second enhancement-mode transistor. The depletion-mode III-N device includes a substrate, a first power electrode, a second power electrode, a first gate, a second gate, and a III-N material structure, wherein compositional differences within the III-N material structure form a 2DEG channel therein. The first enhancement-mode transistor includes a first drain, a first source, and a third gate. The second enhancement-mode transistor includes a second drain, a second source, and a fourth gate. The first drain of the first enhancement-mode transistor is electrically connected to and physically mounted on the first power electrode, and the second drain of the second enhancement-mode transistor is electrically connected to and physically mounted on the second power electrode. The insulating spacer includes an insulating layer, a first metal layer, and a second metal layer located on a side of the insulating layer opposite the first metal layer, and the second metal layer is physically mounted to the structural packaging substrate. The first metal layer includes at least five sections, each section electrically isolated from one another by a trench formed through the first metal layer. The substrate of the III-N depletion mode device is attached to the first portion of the first metal layer, and the third gate of the first enhancement mode transistor is electrically connected to the second portion of the first metal layer, the third portion of the first metal layer is electrically connected to the first terminal of the electronic package, and a first ferrite bead is connected between the second and third portions of the first metal layer, and the fourth gate of the second enhancement mode transistor is electrically connected to the fourth portion of the first metal layer, the fifth portion of the first metal layer is electrically connected to the second terminal, and the second ferrite bead is connected between the fourth and fifth portions of the first metal layer.

[0010] In a third aspect, an electronic circuit is described. The electronic circuit includes a high voltage node, a ground node, a first resistor, a second resistor, a four-quadrant switch (FQS), a first enhancement-mode transistor, and a second enhancement-mode transistor. The FQS is a depletion-mode III-N device including a first power electrode, a second power electrode, a first gate, and a second gate. The first enhancement-mode transistor includes a first drain, a first source, and a third gate. The second enhancement-mode transistor includes a second drain, a second source, and a fourth gate. The first drain of the first enhancement-mode transistor is electrically connected to the first power electrode, and the second drain of the second enhancement-mode transistor is electrically connected to the second power electrode. The first gate of the depletion-mode III-N device and the first source of the first enhancement-mode transistor are electrically connected to the high voltage node. The second gate of the depletion-mode III-N device and the second source of the second enhancement-mode transistor are electrically connected to the ground node, wherein a first terminal of the first resistor is connected to the first gate of the III-N device, a second terminal of the first internal resistor is electrically connected to the first drain of the first enhancement-mode transistor, a first terminal of the second resistor is connected to the second gate of the III-N device, and a second terminal of the second resistor is electrically connected to the second drain of the second enhancement-mode transistor.

[0011] Each of the electronic modules and / or transistors described herein may include one or more of the following features. The first and second internal resistors may have a resistance between 1 Mohm and 100 Mohm. The resistance of the first and second internal resistors may be formed using a portion of the 2DEG channel charge. The electronic package may be a TO-type package. A first ferrite bead may be connected between the first gate and the first terminal of the first enhancement-mode transistor, and a second ferrite bead may be connected between the second gate and the fourth terminal of the second enhancement-mode transistor. The first and second ferrite beads may form a low-pass filter configured to reduce oscillations having a frequency greater than 100 MHz. The first gate of the depletion-mode III-N device and the first source of the first enhancement-mode device may be electrically connected to a third terminal of the electronic package. The second gate of the depletion-mode III-N device and the second source of the second enhancement-mode device may be electrically connected to a fourth terminal of the electronic package. The substrate of the depletion-mode device and the first portion of the first metal layer may be electrically isolated from the first, second, third, and fourth terminals of the electronic package. The substrate of the depletion-mode device may be maintained at a floating potential. The high-voltage node may be greater than 600 V. When the first gate is biased below a first threshold voltage and the second gate is biased above a second threshold voltage, a substantial current can flow through the channel of the depletion-mode III-N device in a first direction. When the first gate is biased above the first threshold voltage and the second gate is biased below the second threshold voltage, a substantial current can flow through the channel of the depletion-mode III-N device in a second direction. When the first gate is biased below the first threshold voltage and the second gate is biased below the second threshold voltage, a substantial current can be blocked through the channel of the depletion-mode III-N device in both the first and second directions. The depletion-mode III-N device may be an AlGaN / GaN HEMT.

[0012] As used herein, a "hybrid enhancement-mode electronic device or component," or simply a "hybrid device or component," is an electronic device or component formed from a depletion-mode transistor and an enhancement-mode transistor, wherein the depletion-mode transistor is capable of having a higher operating and / or breakdown voltage than the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor having the same high breakdown and / or operating voltage as the depletion-mode transistor. That is, the hybrid enhancement-mode device or component includes at least three nodes having the following properties: When a first node (source node) and a second node (gate node) are maintained at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage (i.e., a voltage greater than the maximum voltage that the enhancement-mode transistor can block) applied to a third node (drain node) relative to the source node. When the gate node is maintained at a sufficiently positive voltage relative to the source node (i.e., greater than the threshold voltage of the enhancement-mode transistor), current passes from the source node to the drain node, or when a sufficiently positive voltage is applied to the drain node relative to the source node, current passes from the drain node to the source node. When the enhancement mode transistor is a low voltage device and the depletion mode transistor is a high voltage device, the hybrid assembly can operate similarly to a single high voltage enhancement mode transistor. The depletion mode transistor can have a breakdown and / or maximum operating voltage that is at least two times, at least three times, at least five times, at least ten times, or at least twenty times greater than the breakdown and / or maximum operating voltage of the enhancement mode transistor.

[0013] As used herein, the term Group III nitride or III-N material, layer, device, etc. refers to a material composed of a stoichiometric A material or device composed of a compound semiconductor material having a ratio of w + x + y + z of approximately 1, where 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. The III-N material, layer, or device can be formed or prepared by growing directly on a suitable substrate (e.g., by metal organic chemical vapor deposition) or grown on a suitable substrate, separated from the original substrate, and bonded to another substrate.

[0014] As used herein, two or more contacts or other items such as conductive channels or components are said to be “electrically connected” if they are connected by a material that is sufficiently conductive to ensure that the electrical potential at each of the contacts or other items is intended to be the same, e.g., approximately the same, at all times under any biasing conditions.

[0015] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent a significant current from flowing through the transistor, device, or component, such as a current greater than 0.001 times the operating current during normal conduction, when a voltage is applied across the transistor, device, or component. In other words, when the transistor, device, or component blocks a voltage applied across it, the total current passing through the transistor, device, or component will be no greater than 0.001 times the operating current during normal conduction. Devices with off-state currents greater than this value exhibit high losses and low efficiency and are generally unsuitable for many applications, particularly power switching applications.

[0016] As used herein, a "high voltage device," such as a high voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device that is optimized for high voltage applications. That is, when the device is off, it is capable of blocking high voltages, such as about 300 V or higher, about 600 V or higher, or about 1200 V or higher, and when the device is on, it has a sufficiently low on-resistance (R) for the application in which it is used. ON ), for example, when a large amount of current passes through the device, it experiences sufficiently low conduction losses. A high voltage device may be capable of blocking at least a voltage equal to the high voltage supply or the maximum voltage in the circuit in which it is used. A high voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high voltage device may block 0V and at least V max All voltages between which V max is the maximum voltage that can be supplied by a circuit or power supply, and V max It can be, for example, 300V, 600V, 1200V, 1700V, 2500V or other suitable blocking voltage required by the application. For a bidirectional or four-quadrant switch, when the switch is in the off state ( , such as or 、 When the switch is on, the blocking voltage can be of any polarity less than a certain maximum value, and the current can be in either direction when the switch is on.

[0017] As used herein, a "III-N device" is a device having a conductive channel formed in III-N material. III-N devices can be designed to operate as transistors or switches, where the device's state is controlled by a gate terminal, or as two-terminal devices that, in the absence of a gate terminal, prevent current flow in one direction and conduct current in the other. III-N devices can be high-voltage devices suitable for high-voltage applications. In such high-voltage devices, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is capable of supporting at least all source-drain voltages less than or equal to the high voltage in the application in which the device is used, which can be, for example, 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher. When the high-voltage device is biased on (e.g., the voltage on the gate relative to the source or associated power terminal is greater than the device threshold voltage), it is capable of conducting significant current at a low on-state voltage (i.e., a low voltage between the source and drain terminals or between opposing power terminals). The maximum allowable on-state voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

[0018] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one layer with respect to other layers. Thus, for example, a layer positioned above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer positioned between two layers may be in direct contact with both layers or may have one or more intervening layers. In contrast, a first layer "above" a second layer is in contact with the second layer. Furthermore, assuming that operations are performed relative to a substrate without regard to the substrate's absolute orientation, the relative position of one layer with respect to other layers is provided.

[0019] In a typical power switching application using a high-voltage switching transistor, the transistor spends most of its time in one of two states. In the first state, often referred to as the "on-state," the voltage at the gate electrode relative to the source electrode is higher than the transistor threshold voltage, and significant current flows through the transistor. In this state, the voltage difference between the source and drain is typically low, often no more than a few volts, such as approximately 0.1-5 volts. In the second state, often referred to as the "off-state," the voltage at the gate electrode relative to the source electrode is lower than the transistor threshold voltage, and no significant current flows through the transistor other than the off-state leakage current. In this second state, the voltage between the source and drain can range anywhere from approximately 0V to the value of the circuit's high voltage supply—which in some cases can be as high as 100V, 300V, 600V, 1200V, 1700V, or even higher—but can be less than the transistor's breakdown voltage. In some applications, inductive elements in the circuit can cause the voltage between the source and drain to be even higher than the circuit's high voltage supply. In addition, there is a short time immediately after the gate has been turned on or off, during which the transistor is in a transition mode between the two states. When the transistor is in the off state, it is said to "block" the "voltage" between the source and drain.

[0020] As used herein, an "electrode" refers to a metal layer within a device or transistor that is connected to the source, gate, or drain region of the semiconductor material of the device. A "pad," such as a "source pad, drain pad, or gate pad," refers to the uppermost, unpassivated portion of an electrode that is used to electrically connect the device or transistor to a package, for example, using solder, epoxy, wire bonds, and / or metal clips.

[0021] The details of one or more disclosed embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Additional features and variations may also be included in the embodiments. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 4 is a circuit diagram of an enhancement mode FQS switch in the prior art.

[0023] Figure 2A and Figure 2B Schematic diagram of a FQS switch using a high-voltage depletion-mode III-N device and a low-voltage enhancement-mode device.

[0024] Figure 3A is a cross-sectional view of a hybrid III-N FQS device.

[0025] Figure 3B and Figure 3C yes Figure 3A Floor plan of the hybrid III-N bidirectional device.

[0026] Figure 3D and Figure 3E A plan view and a cross-sectional view of an electronic component package are shown respectively.

[0027] Figure 3F Shows a plan view of an electronic component package.

[0028] Figure 4A Cross-sectional view of a hybrid FQS III-N device using an insulating substrate.

[0029] Figure 4B and Figure 4C A plan view and a cross-sectional view of an electronic component package are shown respectively.

[0030] Figure 5A and Figure 5B A cross-sectional view and a plan view of a hybrid FQS III-N device are shown, respectively.

[0031] Figure 5C and Figure 5D A plan view and a cross-sectional view of an electronic component package are shown respectively.

[0032] Figure 6A and Figure 6B A cross-sectional view and a plan view of an enhancement-mode FQS III-N device are shown, respectively.

[0033] Figure 6C and Figure 6D A plan view and a cross-sectional view of an electronic component package are shown respectively.

[0034] Figure 7 Shows a plan view of an electronic component package.

[0035] Figure 8A A circuit schematic showing a hybrid FQS III-N switch using a common-source topology.

[0036] Figure 8B and Figure 8C A plan view and a cross-sectional view are respectively shown of an electronic component package using a common source topology.

[0037] Figure 9A and Figure 9B A plan view and a cross-sectional view are respectively shown of an electronic component package using a common source topology.

[0038] Figure 9C Shown is a cross-sectional view of an integrated enhancement mode silicon FET device.

[0039] Figure 10AA circuit schematic showing a hybrid FQS III-N switch using an integrated driver circuit.

[0040] Figure 10B A plan view of an electronic component package using a common-source topology and integrated driver circuitry.

[0041] Like reference numbers in the various drawings indicate like elements. DETAILED DESCRIPTION

[0042] Described herein are III-N devices and corresponding modules, any of which are suitable for operation as four-quadrant switches (i.e., FQS). These devices or modules can be incorporated into electronic component packages. The module's design, coupled with the design of the III-N devices used in the module, can result in reduced inductance and other parasitic effects, thereby allowing for greater circuit stability and improved performance. The electronic module can also have a reduced size and can be easier to assemble than traditional FQS switches such as silicon IGBTs, resulting in lower production costs and higher reliability.

[0043] As previously mentioned, reliable design, fabrication, and operation of high voltage normally-off FQS III-N devices have so far proven to be very difficult. The main challenges are (1) back-gate crosstalk between the two sides of the FQS and (2) assembly complexity. Back-gate crosstalk can occur when the FQS is implemented on a conductive substrate such as silicon. The device designer must decide the potential to which the silicon substrate should be connected. The silicon substrate can be connected to the same potential as terminal 1. However, in this configuration, the device operates reliably only when terminal 1 is biased at a ground potential such as 0V (equivalent to the source terminal in a conventional 3-terminal device) and terminal 2 is biased at a high positive voltage such as 400V or 800V (equivalent to the drain terminal in a conventional 3-terminal device). But when the FQS is operated in the opposite direction, that is, terminal 1 is biased at a high positive voltage and terminal 2 is biased at ground potential, the silicon substrate connected to terminal 1 will also be biased at high voltages such as 400V and 800V. When the silicon substrate is biased at a high positive voltage, it generates a strong vertical field beneath Terminal 2 and Gate 2, attracting electrons from the 2DEG toward the substrate. This not only results in parasitic leakage currents but also in severe electron trapping in the buffer layer. This, in turn, causes a severe positive threshold voltage shift of Gate 2 by several volts and a significant increase in dynamic on-resistance, compromising the switching performance and reliability of the device. Conversely, if the substrate is electrically connected to Terminal 2, the device will only operate reliably when Terminal 2 is biased at ground potential and Terminal 1 is biased at a high voltage.

[0044] To prevent this, device and circuit designers have invented complex substrate switching schemes, in which the substrate is switched to connect from Terminal 1 to Terminal 2 depending on the bias conditions of the FQS. However, this solution introduces significant device and circuit complexity and suboptimal switching efficiency. Another option is to leave the substrate connection floating, that is, not electrically connected to either terminal. In this case, when Terminal 1 is biased at 0V and Terminal 2 is biased at a high voltage, such as 400V, the substrate will be capacitively coupled to both Terminal 1 and Terminal 2, resulting in an intermediate potential, such as 200V. This situation is less severe than the previously described scenario, but it will still cause buffer injection under Gate 1 or Gate 2 and a threshold voltage shift of several volts. This is unacceptable in E-mode devices, where the threshold must be precisely controlled to ensure proper operation. A shift of several volts in either direction (positive or negative) would render the E-mode device unusable.

[0045] An alternative to a single high-voltage E-mode FQS device is to combine a high-voltage depletion-mode (i.e., D-mode) III-N device with first and second low-voltage silicon enhancement-mode (i.e., E-mode) FETs in a cascode-type configuration. In this configuration, the substrate terminal can be left floating without affecting the threshold voltages of Gate 1 and Gate 2. In effect, Gate 1 and Gate 2 are implemented on separate silicon FETs from the GaN HEMT and are therefore unaffected by back-gate crosstalk. Back-gate crosstalk can still affect the gate of the GaN HEMT, increasing the dynamic Ron by, for example, 20%-30%, but it will not prevent device operation as it does with an E-mode device.

[0046] Figure 2AA circuit schematic of an FQS switch 200 including a high-voltage D-mode III-N device 210 is shown. Switch 200 includes a first low-voltage E-mode transistor 220 coupled to a first power electrode of device 210 at node 224. Switch 200 includes a second low-voltage E-mode transistor 230 coupled to a second power electrode of device 210 at node 234. Switch 200 includes a first terminal 223 coupled to the source of first E-mode transistor 220 and a first gate of D-mode III-N device 210 via connector 225. Switch 200 includes a second terminal 233 coupled to the source of second E-mode transistor 230 and a second gate of D-mode III-N device 210 via connector 235. Switch 200 further includes a third terminal 222 connected to the gate of first transistor 220 and a fourth terminal 232 connected to the gate of second transistor 230. Optionally, switch 200 may include a first Kelvin connection 212 configured to the source of first transistor 220 , a second Kelvin connection 213 configured to the source of second transistor 230 , and a substrate connection 211 configured to be electrically connected to the substrate of III-N device 210 .

[0047] However, when the switch 200 is operated under certain bias conditions, such as fast switching with high di / dt or dv / dt values, the first or second transistor 220 or 230 may enter avalanche mode and the switch 200 may fail. To improve the reliability of the switch 200, a bleeder resistor may be incorporated. Figure 2B As shown, the switch 202 includes a first resistor 226 (ie, a first bleeder resistor) and a second resistor 236 (ie, a second bleeder resistor), but is otherwise similar to the switch 202 shown in FIG. Figure 2A The switch 200 is the same as the switch 200 of the III-N device 210. Resistor 226 may have a first terminal connected between the first power electrode of III-N device 210 and the drain of the first E-mode transistor 220, and a second terminal connected between the first gate of device 210 and the source of the first E-mode transistor 220. Second resistor 236 may have a first terminal connected between the second power electrode of III-N device 210 and the drain of the second E-mode transistor 230, and a second terminal connected between the second gate of device 210 and the source of the second E-mode transistor 220. These first and / or second bleeder resistors can allow leakage current to double-pass the first and / or second E-mode transistors to prevent avalanche breakdown, thereby improving reliability.

[0048] Figure 3A 、 3B and 3C respectively show the Figure 2AFigure 2 shows a cross-sectional view, a first plan view, and a second plan view of a cascode FQS switch 300 in a circuit of FIG. 1B or FIG. The cascode FQS switch 300 includes a first low-voltage E-mode transistor 20 (e.g., a silicon FET) mounted directly to the first power electrode 18A of the high-voltage D-mode III-N device 10, with the drain pad 21 of the first E-mode transistor 20 directly bonded to the first electrode 18A of the D-mode III-N device 10. The switch 300 further includes a second low-voltage E-mode transistor 30 (e.g., a silicon FET) mounted directly to the second power electrode 18B of the high-voltage D-mode III-N device 10, with the drain pad 31 of the second E-mode transistor 30 directly bonded to the second electrode 18B. The FQS switch 300 can be operated in the same manner as a single high-voltage E-mode FQS switch and, in many cases, achieves the same or similar output characteristics as a single high-voltage E-mode FQS switch. The D-mode III-N device 10 has a greater breakdown voltage (e.g., at least three times greater) than each of the first E-mode transistor 20 and the second E-mode transistor 30. When biased in the OFF state, the maximum voltage that can be blocked by the FQS switch 300 is at least as great as the maximum blocking or breakdown voltage of the D-mode FQS III-N device 10.

[0049] refer to Figure 3A The first E-mode transistor 20 includes a semiconductor body layer 24. The transistor 20 further includes a first source electrode 23 and a first gate electrode 22 on a first side of the semiconductor body layer 24, and a first drain electrode 21 on a second side of the semiconductor body layer 24 opposite to the first source electrode 23.

[0050] The second E-mode transistor 30 includes a semiconductor body layer 34 , and further includes a second source electrode 33 and a second gate electrode 32 on a first side of the semiconductor body layer 34 , and a second drain electrode 31 on a second side of the semiconductor body layer 34 opposite the second source electrode 33 .

[0051] The D-mode III-N device 10 includes a III-N material structure 40, such as a combination of GaN and AlGaN, grown on a suitable substrate 11. The suitable substrate 11 can be a conductive semiconductor such as silicon (e.g., p-type or n-type doped Si), GaN (e.g., p-type or n-type GaN), or any other sufficiently conductive substrate or a semi-insulating (e.g., semi-insulating silicon carbide or silicon) substrate. A back metal layer 25 can be formed on the side of the substrate opposite the III-N material structure 40. The back metal layer 25 can be Ti / Ni / Ag or another suitable material and can serve as an adhesion layer to physically and / or electrically connect the substrate to a package shim.

[0052] The III-N material structure 40 may include a III-N buffer layer 12, such as GaN or AlGaN, grown over the substrate 11. The buffer layer 12 may be rendered insulating or substantially free of unintentional n-type carriers. The buffer layer 12 may have a composition that is substantially uniform throughout, or the composition may vary. The thickness and composition of the buffer layer 12 may be optimized for high voltage applications. That is, the buffer layer may be capable of blocking a voltage equal to the high voltage supply or the maximum voltage in the circuit in which it is used. For example, the buffer layer 12 may be capable of blocking greater than 600V or greater than 900V. The thickness of the buffer layer 12 may be greater than 2 For example, the III-N buffer layer may have a and 10 For the purposes of this application, if a buffer layer is rated to block a particular voltage, then the buffer layer is considered to be electrically insulating when the device is operated at a voltage less than the rated blocking voltage.

[0053] The III-N material structure 40 may further include a III-N channel layer 13 (e.g., GaN) over the III-N buffer layer 12 and a III-N barrier layer 14 (e.g., AlGaN, AlInN, or AlGaInN) over the III-N channel layer 13. The band gap of the III-N barrier layer 14 is greater than the band gap of the III-N channel layer 13. The III-N channel layer 13 has a different composition than the III-N barrier layer 14, and the thickness and composition of the III-N barrier layer 14 are selected such that a two-dimensional electron gas (2DEG) channel 19 (formed by Figure 3A (indicated by the dashed line in FIG) is induced in the III-N channel layer 13 adjacent to the interface between layers 14 and 13. When the device is operated below the rated blocking voltage of the device, the III-N channel layer 13 is considered to be electrically isolated from the substrate by the insulating III-N buffer layer 12. In addition, Figure 2B The bleeder resistors 226 and 235 shown in FIG can be internal resistors integrated into the III-N material structure using 2DEG channel charge (in Figure 3F ). The length and width of the bleeder resistor can be determined based on the channel charge to obtain an appropriate resistor value.

[0054] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). The III-N material structure can be grown in a group III polar (e.g., Ga polar) orientation, such as the [0 0 0 1] (C-plane) orientation, as shown in Figure 2. Figure 3ADevice shown. Alternatively, a III-N HEMT can be formed on a III-N material structure grown in an N-polar (i.e., N-face) orientation, such as a [000-1] orientation (not shown). In an N-polar device, a III-N barrier layer can be above the III-N buffer layer, and a III-N channel layer can be above the III-N barrier layer. N-polar III-N material has a polarization field that is opposite to that of Group-III polar III-N material, thus enabling III-N device structures that cannot be formed using Group-III polar structures.

[0055] An insulator layer 15 (eg, a dielectric layer) is grown or deposited over the top surface of the III-N material structure 40. The insulator layer 15 may be formed of or include, for example, aluminum oxide ( ), silicon dioxide ( )、 、 、 、 Or any other wide bandgap insulator. Although the insulator layer 15 is shown as a single layer, it may alternatively be formed of several layers and / or materials deposited during different processing steps to form a single combined insulator layer.

[0056] First and second power electrodes 18A, 18B are formed on a side of the III-N material structure 40 opposite the substrate 11, characterizing the device 10 as a lateral III-N device (i.e., the first and second power electrodes are on the same side of the device, and when the device is biased ON, current flows laterally through the device between the first and second electrodes 18A, 18B). The first and second power electrodes may include portions exposed on the top surface of the device, unenclosed by the insulator layer 15. This portion may serve as bonding pads for mounting the first and second E-mode transistors 20, 30. The first and second power electrodes 18A, 18B may have a separation 41 along the top surface of the device 10 that is at least sufficiently large to prevent breakdown voltage or arcing during device operation. Depending on the voltage polarity of the circuit, the first power electrode 18A may alternate between being a drain electrode or a source electrode (e.g., a D / S electrode). Depending on the voltage polarity of the circuit, the second power electrode 18B may alternate between being a source electrode or a drain electrode (e.g., an S / D electrode). The first electrode 18A and the second electrode 18B are in ohmic contact and electrically connected to the device 2DEG channel 19 formed in the layer 13. The first electrode 18A and the second electrode 18B can each be formed by a stack of multiple metal layers. Each metal stack can be, for example, Ti / Al / Ni / Au, Ti / Al, or other suitable metal layer stacks.

[0057] The D-mode III-N device 10 further includes a first D-mode gate electrode 16 and a second D-mode gate electrode 17. The first D-mode gate electrode 16 and the second D-mode gate electrode 17 can be formed such that the insulator layer 15 extends between and separates the gate electrodes from the III-N material structure 40, as shown in FIG. Figure 3A As shown. Alternatively, the first D-mode gate electrode 16 and the second D-mode gate electrode 17 can be formed so that they are in contact with the III-N material structure 40 (not shown). The first D-mode gate 16 may include a portion 16' extending toward the second power electrode 18B and may function as an electric field plate. The second D-mode gate 17 may include a portion 17' extending toward the first power electrode 18A and may function as an electric field plate. The first D-mode gate 16 and the second D-mode gate 17 are separated by a minimum distance, which is Figure 3A The gap 42 is shown as a gap 42. The gap 42 is large enough to support reliable device operation and support large voltages. For example, the gap 42 can be 5-50 The first D-mode gate electrode 16 and the second D-mode gate electrode 17 can be formed of a suitable conductive material, such as a metal stack, for example, titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au). The gate electrode can alternatively be another conductive material or a material stack including one or more materials with a large work function, such as a semiconductor material with a large work function (for example, p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0058] A first E-mode transistor 20 is electrically connected to the first power electrode 18A of the high-voltage D-mode III-N device 10, and a second E-mode transistor 30 is electrically connected to the second power electrode 18B to form a cascode FQS switch 300, which can be a normally-off hybrid III-N FQS device. Here, a first drain electrode 21 of the first E-mode transistor 20 is directly in contact with (e.g., mounted on) and electrically connected to the first power electrode 18A of the III-N device 10, and a second drain electrode 31 of the second E-mode transistor is directly in contact with (e.g., mounted on) and electrically connected to the second power electrode 18B. The first drain electrodes 21 and the second drain electrodes 31 of the first E-mode transistor 20 and the second E-mode transistor 30 can be connected to the first power electrode 18A and the second power electrode 18B of the D-mode III-N device 10, respectively, using, for example, solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods that allow high-quality mechanical, thermal, and electrical connections between the E-mode FET drain electrodes 21 and 31 and the D-mode III-N device first power electrode 18A and the second power electrode 18B. The E-mode transistors 20 and / or 30 may be mounted above the 2DEG channel 19, as shown in FIG. Figure 3AAs shown, transistors 20 and / or 30 may be partially or fully mounted in regions outside the active region of the device, such that the E-mode transistors are not above the 2DEG channel layer.

[0059] The first gate electrode 22 of the first E-mode transistor 20 can be configured to be connected to a first gate terminal of the electronic package, and the second gate electrode 32 of the second E-mode transistor 30 can be configured to be connected to a second gate terminal of the electronic package. The D-mode device and the E-mode transistor of a conventional cascode FQS switch are typically co-packaged side by side on a ceramic insulating substrate such as an AlN pad, and an external wire connector is required to connect the E-mode drain to the III-N device power electrode in a cascode FQS configuration. However, as Figure 3A 、 3B As shown in Figures 3C and 3C , mounting E-mode transistors 20 and 30 directly on D-mode III-N device 10 eliminates the need for external wire connectors and ceramic isolation pads. This can significantly reduce the parasitic inductance of the switching circuit, allowing for higher current ratings, faster switching speeds, and lower component-related costs.

[0060] Although the first gate electrode 16 and the second gate electrode 17 of the D-mode device 10 are Figure 3A 、 3B 3C, respectively connected to the first source electrode 23 and the second source electrode 33 of the first E-mode transistor 20 and the second E-mode transistor 30 (as shown in the schematic diagram) Figure 2A and 2B ), but once the cascode FQS switch 300 is mounted into a module or electronic component package, such as Figure 3D and 3E In the package shown in , these electrodes are actually electrically connected because these respective electrodes are wire-bonded to a common metal layer, as will be shown later in Figure 3D As shown in .

[0061] Figure 3B FIG is a top plan view of the hybrid FQS switch 300. Figure 3B As seen in FIG. 1 , section A-AA (indicated by the dotted line) shows the Figure 3A . The first gate electrode 16 of the D-mode III-N device 10 includes a first gate pad 16A and (optionally) a second gate pad 16B, which can be used to bond an external connection wire to the first gate electrode 16. The second gate electrode 17 of the D-mode III-N device 10 includes a third gate pad 17A and (optionally) a fourth gate pad 17B, which can be used to bond an external connection wire to the second gate electrode 17.

[0062] Depletion mode III-N devices often exhibit switching issues due to high GaN HEMT gate resistance and / or GaN HEMT gate inductance. If the gate width of the depletion mode device is greater than a certain size (e.g., Wg is greater than 100 mm), the device performance may be negatively affected. One solution to reduce the HEMT gate resistance and gate inductance and overcome these switching issues is to have multiple gate pads on the device to allow gate wire connections on opposite sides of the gate electrode width. When the depletion mode III-N device is a bidirectional device, four external gate connection pads may be used. For example, in switch 300, the first gate electrode 16 may have a first end connected to the first gate pad 16A, a second end connected to the second gate pad 16B, and a first gate width Wg between the first and second ends. Additionally, the second gate electrode 17 may have a third end connected to the third gate pad 17A, a fourth end connected to the fourth gate pad 17B, and a second gate width Wg between the third and fourth ends. As Figure 3B As shown, the plan view of switch 300 includes a left side, a right side, a top side, and a bottom side. First gate pad 16A and second gate pad 16B are arranged between the left side of switch 300 and first E-mode transistor 20. Third gate pad 17A and fourth gate pad 17B are arranged between the right side of switch 300 and second E-mode transistor 30.

[0063] Figure 3C An alternative embodiment switch 302 is shown in FIG. Switch 302 is similar to Figure 3B The switch 300 has an alternative arrangement except for the location of the gate pad, which allows for different packaging. Figure 3C As shown, first gate pad 16A and third gate pad 17A are arranged on the bottom side of switch 302 such that first gate pad 16A is between the bottom side of switch 302 and first E-mode transistor 20, and third gate pad 17A is between the bottom side of switch 302 and second E-mode transistor 30. Second gate pad 16B and fourth gate pad 17B are arranged on the top side of switch 302 such that second gate pad 16B is between the top side of switch 302 and first E-mode transistor 20, and fourth gate pad 17B is between the top side of switch 302 and second E-mode transistor 30. When designing and selecting electronic component packaging, it is possible to allow for the following: Figure 3B and 3C The multiple gate pad locations shown give the designer more freedom. This can help reduce gate wire bond lengths or prevent wire bonds from crossing each other when limited design freedom is allowed.

[0064] Figure 3D and 3E304. The package 304 includes a package housing 308. The package 304 also includes a direct bonded copper (DBC) substrate 310 (on the Figure 3E The DBC substrate is made by directly bonding pure copper to a substrate such as AlN or It is formed by ceramic insulators. Figure 3E As shown, DBC substrate 310 includes an insulating (e.g., ceramic or AlN) substrate 315, upon which a top metal layer (e.g., copper or nickel) is patterned into at least a first portion serving as a first power plate 311, a second portion serving as a floating plate 312, and a third portion serving as a second power plate 313. Portions 311, 312, and 313 are each electrically isolated from one another by trenches 314 formed through the top metal layer. The DBC substrate may include a back metal layer 316 (e.g., copper or nickel) on the side of insulating substrate 315 opposite the top metal layers (311 / 312 / 313). This back metal layer can be used to physically mount the DBC to a conductive structural package substrate (i.e., leadframe 323) using solder or other methods. A heat sink 332 is mounted and thermally connected to leadframe 323. Leadframe 323 can be configured to connect to circuit ground; however, to mitigate backgate crosstalk as described above, the circuit can be simplified by disconnecting leadframe 323 from the circuit at a "floating" voltage potential. The substrate 11 of the III-N FQS III-N device 300 is attached to a floating plate 312. The back metal layer 25 (not shown) is attached to the floating plate 312 using solder, epoxy, or another suitable adhesive material.

[0065] The electronic component package 304 may be various types of industry standard packages. Figure 3D An "SO-type" package (sometimes referred to as an SOP or SOIC-type package) is shown, including a first power terminal 322 and a second power terminal 321. During operation, the first and second power terminals 321, 322 can switch between source and drain terminals, depending on the polarity of the FQS switch. The source electrode 33 of the second low-voltage FET 30 is electrically connected to the first power plate 311 using a wire bond 46 (which may be multiple wire bonds). The second gate electrode pads 17A and 17B are electrically connected to the first power plate 311 using wire bonds 45A and 45B, respectively. The first power plate 311 is electrically connected to the first power terminal 322 using a wire bond 58. The source electrode 23 of the first low-voltage FET 20 is electrically connected to the second power plate 313 using a wire bond 41 (which may be multiple wire bonds). The first gate electrode pads 16A and 16B are electrically connected to the second power plate 313 using wire bonds 42A and 42B, respectively. The second power plate 313 is electrically connected to the second power terminal 321 using a wire bond 57.

[0066] Figure 3D The electronic component package 304 further includes a first gate terminal 326 and a second gate terminal 327. The first gate terminal 326 is electrically connected to the gate electrode 22 of the first low-voltage FET 20 using a wire bond 53, and the second gate terminal 327 is electrically connected to the gate electrode 32 of the second low-voltage FET 30 using a wire bond 54. Optionally, the electronic component package 304 may further include a first Kelvin terminal 325 and a second Kelvin terminal 328. The first Kelvin terminal 325 is electrically connected to the source electrode 23 of the first low-voltage FET 20 using a wire bond 52, and the second Kelvin terminal 327 is electrically connected to the source electrode 33 of the second low-voltage FET 30 using a wire bond 55. Although the electrical connections of the component package 304 have been described using wire bonds, other suitable methods such as copper clips or lead tape may be used.

[0067] When device 300 is used in component package 304 (and the device is mounted directly to DBC substrate 310), device substrate 11 is floating and electrically isolated from the power input signal of the electronic component. Therefore, during operation, substrate 11 does not need to be switched to match the input supply voltage of first power terminal 322 or second power terminal 321, as would be required if a similar silicon enhancement-mode device substrate were electrically connected and mounted directly to the package leadframe. This benefit significantly reduces circuit complexity and improves switching efficiency, allowing for faster switching speeds, among other benefits.

[0068] Figure 3F is a plan view of a III-N device 305, which is similar to Figure 3D The device 300 is shown, except that the III-N device 305 includes a first internal resistor terminal 28 and a second internal bleeder resistor terminal 29. The first internal resistor terminal 28 extends at least under a portion of the first E-mode transistor 20 and is electrically connected to the drain of the E-mode transistor 20. The second internal resistor terminal 29 extends at least under a portion of the second E-mode transistor 30 and is electrically connected to the drain of the E-mode transistor 30. Return to Reference Figure 2B , switch 202 shows a first bleeder resistor 226 and a second bleeder resistor 236. Resistor 226 has a terminal connected between the first power electrode of device 210 and the drain of transistor 220. Resistor 236 has a terminal connected between the second power electrode of device 210 and the drain of transistor 230.

[0069] Return Reference Figure 3FSwitch 305 may have a first internal bleeder resistor with a first resistor terminal 28 electrically connected to the drain of transistor 20, and a second terminal of the first internal bleeder resistor internally connected (not shown) to the first gate of III-N device 10. Switch 205 may have a second internal bleeder resistor with a first resistor terminal 29 electrically connected to the drain of transistor 30, and a second terminal of the second bleeder resistor internally connected (not shown) to the second gate of III-N device 10. The resistances of the first and second internal bleeder resistors may be formed using the 2DEG channel of III-N device 10. The first and second bleeder resistors may have values ​​between 1 Mohm and 100 Mohm, but typically between 5 Mohm and 20 Mohm.

[0070] Figure 4A Shown available for Figure 2A 4 or 2B. The switch 400 of FIG4 is similar to Figure 3A 300, except that the D-mode III-N 410 in the switch 400 is fabricated on an insulating substrate 411 (e.g., a sapphire substrate) rather than the conductive or semiconductive substrate (e.g., silicon or silicon carbide) of the switch 300. Fabricating the switch 400 with a sapphire substrate can have several advantages when the switch is integrated into an electronic component package, such as eliminating the need for an insulating DBC substrate between the switch 400 and the package base (i.e., lead frame), as shown in FIG. Figure 4B and 4C As further shown in [1], an insulating substrate such as sapphire will also eliminate back-gate crosstalk issues. Indeed, being insulating and non-conductive, the potential in the substrate will vary across the length of the device and will not capacitively couple to Terminals 1 and 2. This will prevent high potentials from being transferred from one terminal to the other, causing Vth shift and dynamic Ron issues.

[0071] Figure 4B and 4C 4 and 5 show a plan view and a cross-sectional view of an electronic component package 402, respectively. The package 402 includes a package housing 408. The package 402 further includes a direct bonded copper (DBC) substrate 410 (on the Figure 4C DBC substrate 410 is similar to Figure 3E The DBC substrate 310 is shown, except that the second portion of the DBC (floating plate 312) is eliminated and the substrate 411 of the switch 400 is directly mounted and thermally connected to the lead frame 323. The first power plate 311 remains on the first DBC portion 410', and the second power plate 313 remains on the third DBC portion 410" (the second DBC portion has been removed in the electronic component package 402). Figure 4BOther features of package 402 seen in / 4C are similar to those in Figure 3D Features of package 304 as seen in / 3E.

[0072] Similar to that described in package 304, when device 400 is used in assembly package 402 (and the device is mounted directly to lead frame 323), device substrate 411 does not need to be switched to match the input power voltage of first power terminal 322 or second power terminal 321 during operation, as would be required if the silicon enhancement mode device substrate were electrically connected and mounted directly to the package lead frame. This benefit greatly reduces circuit complexity and improves switching efficiency, thereby allowing for faster switching speeds, among other benefits.

[0073] Figure 5A and Figure 5B A cross-sectional view and a plan view of a hybrid cascode FQS III-N switch 500 are shown, respectively. Figure 5A The switch 500 is similar to Figure 3A Unlike switch 300 , switch 500 uses epitaxial through-hole vias (TEVs) to connect the first and second gate electrodes 16 and 17 of the D-mode III-N 520 to a conductive substrate, such as a highly doped silicon substrate. A portion 512 of the conductive substrate is completely removed beneath the III-N material structure 40 to create a first substrate portion 511A electrically connected to the first gate electrode 16 and a second substrate portion 511B electrically connected to the second gate electrode 17. Multiple TEVs are formed by etching recesses (or trenches) through the entire thickness of the III-N material structure 40 in a region outside the device's active area (i.e., the region between the first and second power electrodes 18A and 18B), exposing the surface of the conductive substrate. A portion of a metal layer 516 is formed within the TEVs and electrically connects the first gate electrode 16 to the substrate. Similarly, a metal layer 517 is at least partially formed within the TEVs and electrically connects the second gate electrode 17 to the substrate. Next, portion 512 of the substrate may be removed (eg, by dry or wet etching) to electrically isolate first substrate portion 511A from second substrate portion 511B.

[0074] Figure 5B A top plan view of the switch 500 is shown. Section B-BB (indicated by the dashed line) shows Figure 5A Example cross-section locations depicted in . Figure 5B As shown, there is no external gate pad on the top side of the device, such as Figure 3B Eliminating the need for top-side gate pads can significantly reduce the complexity of mounting the switch 500 into an electronic component package, such as Figure 5C and 5D As further shown in .

[0075] Figure 5C and 5D Shown separately include Figure 5A The electronic component package 502 is similar to the FQS III-N switch 500. Figure 3D The electronic component package 304 has the following differences. The package 502 includes a direct bonded copper (DBC) substrate 510 (in Figure 5D ), which can be a base substrate for packaging. The DBC substrate 510 includes an insulating (e.g., ceramic or AlN) substrate 315 on which a top metal layer (e.g., copper or nickel) is patterned into at least a first portion for a first power plate 511 and a second portion for a second power plate 513. Portions 511 and 513 are electrically isolated from each other by trenches 514 formed through the top metal layer. The second substrate portion 511B of the III-N FQS III-N switch 500 is electrically connected and physically mounted to the first power plate 511. The first substrate portion 511A of the III-N FQS III-N switch 500 is electrically connected and physically mounted to the second power plate 513. The back metal layer 25 (shown in FIG. 1 for simplicity) is bonded to the back metal layer 25 using solder, epoxy, or other suitable adhesive material. Figure 5D ) are attached to the first power board 511 and the second power board 513.

[0076] like Figure 5D As shown, the first gate electrode 16 is electrically connected to the second power board 513 through the first substrate portion 511A, and the second gate electrode 17 is electrically connected to the first power board 511 through the second substrate portion 511B, thereby eliminating the need for Figure 3D This eliminates the need for external gate bond wires 42A / B and 45A / B as shown in package 304. This reduces the switching inductance of package 504 and reduces assembly costs associated with component packaging complexity.

[0077] Figure 6A and Figure 6B Shows that it can be Figure 1 FIG. 6 is a cross-sectional view and a plan view of an enhancement mode III-N FQS switch 600 used in a circuit of FIG. FIG. 6 is a cross-sectional view and a plan view of an enhancement mode III-N FQS switch 600 used in a circuit of FIG. Figure 4AThe switch 600 further includes a substrate 411 as described in relation to the switch 400. A III-N buffer layer 612 is formed over the substrate 411. A III-N channel layer 613 and a III-N barrier layer 614 are formed over the III-N buffer layer 612, and the compositional difference between the barrier layer 614 and the channel layer 613 allows a 2DEG channel 19 to be formed therein. The III-N buffer layer 612, the III-N channel layer 613, and the III-N barrier layer 614 form a III-N material stack 640. An insulating layer 615 is formed over the III-N material stack 640. A first power electrode 618 and a second power electrode 620 are electrically connected to the 2DEG channel 19. A first gate electrode 616 and a second gate electrode 617 are used to modulate charge in the 2DEG channel 19. First gate electrode 616 and second gate electrode 617 are configured such that III-N switch 600 is an enhancement-mode device. That is, when first gate electrode 616 is biased at 0V relative to the first power electrode and / or second gate electrode 617 is biased at 0V relative to the second power electrode 620, 2DEG channel 19 is discontinuous between first power electrode 618 and second power electrode 620. First gate electrode 616 and / or second gate electrode 617 may be partially or completely recessed into III-N barrier layer 614. A gate dielectric layer (not shown), such as an oxide or nitride layer, may be formed between the gate electrodes and the III-N material structure layer. Gate electrodes 616 and 617 are separated by a distance 42 to ensure high-voltage operation of switch 600. Enhancement-mode operation of the III-N FQS switch can be achieved by any number of suitable methods known in the art and not specifically described herein in connection with enhancement-mode III-N transistors (e.g., using a vertical gate module as described in U.S. Patent No. 10,756,207).

[0078] like Figure 6A As shown, a back metal layer is formed on the side of the insulating substrate 411 opposite the III-N material structure. A portion 625 of the back metal layer is etched away, leaving a first back metal portion 25A and a second back metal portion 25B. Through-substrate vias (TSVs) 626 and 627 are formed through the III-N material structure 640 and the insulating substrate 411. A metal wiring layer 628 is partially formed in the TSVs 626 and electrically connects the first power electrode 618 to the first back metal portion 25A. A metal wiring layer 629 is at least partially formed in the TSVs 627 and electrically connects the second power electrode 620 to the second back metal portion 25B.

[0079] Figure 6B FIG is a top view of an enhanced mode (E-mode) FQS switch 600. Figure 3B As can be seen, the cross section C-CC (indicated by the dotted line) shows the Figure 6A The first gate electrode 616 of the E-mode III-N switch 600 includes a first gate pad 616A and (optionally) a second gate pad 617A, which can be used to bond external connection wires to component package terminals.

[0080] Figure 6C and Figure 6D A plan view and a cross-sectional view are respectively shown of an electronic component package 604, which includes Figure 6A Enhanced mode FQS III-N switch 600. Electronic component package 604 is similar to Figure 5C The electronic component package 504 is shown. The package 604 includes a package housing 608. The package 604 includes a DBC substrate 510, which can be used to physically mount the DBC to a conductive structure package base (i.e., lead frame 323) using solder or other methods, as described in package 504. The second back metal portion 25B of the III-N FQS switch 600 is electrically connected and physically mounted to the first power board 511. The first back metal portion 25A of the III-N FQS switch 600 is electrically connected and physically mounted to the second power board 513. The back metal layer is attached to the first power board 511 and the second power board 513 using solder, epoxy, or other suitable adhesive material. Figure 6C As seen in Figure 3D Compared to the electronic component package 304 shown in , packaging complexity and component count can be reduced.

[0081] Figure 7 is a plan view of an electronic component package 700 including a III-N FQS switch, such as Figure 3A and 3B The switch 300 described in the foregoing. The package 700 further includes a package housing 702 that may be formed of a molding compound. The assembly package 700 further includes a direct bonded copper (DBC) substrate 710 that may be similar to Figure 3DDBC substrate 310 as described in

[15] is shown. DBC substrate 710 comprises an insulating (e.g., ceramic or AlN) substrate on which a top metal layer is patterned into several sections that serve as metal wiring layers. The top metal layer sections include at least sections 1 through 7, each numerically labeled 711-717. Sections 711-717 are each electrically isolated from one another by trenches formed through the top metal layer. DBC substrate 710 is physically mounted to a structural package base 704, which can be formed from a conductive material such as copper or nickel (i.e., a leadframe) using solder or other methods. A heat sink (not shown) can be mounted and thermally connected to the reverse side of package base 704. The substrate of III-N FQS III-N device 300 is attached to the first section 711 of the top metal layer using solder, epoxy, or another suitable adhesive material.

[0082] Figure 7 The electronic component package 700 in FIG. 1 shows a "TO-type" package (e.g., TO-220, TO-247, TO-263, etc.). The package substrate 704 may include a through-hole 705 formed therethrough, which can be used to mount the electronic component using screws. The component package 700 further includes a first power terminal 727 and a second power terminal 723. The component package 700 includes a first gate terminal 726 and a second gate terminal 725. During operation, the first power terminal 727 and the second power terminal 723 can switch between a source terminal and a drain terminal depending on the polarity of the FQS switch 300. Figure 7 The TO-type package shown has four terminal leads extending from the package; however, other package types may include more leads as needed, for example, to include Kelvin connection terminals. The substrate and first portion 711 of device 300 are electrically isolated from all four terminal leads. Thus, the substrate of device 300 is maintained at a floating potential relative to first power terminal 727 and / or second power terminal 723.

[0083] The second gate electrode 32 of the switch 300 is connected to the second top metal layer portion 712 using a wire bond 61. The third top metal portion 713 is electrically connected to the first gate terminal 726 using a wire bond 65. A ferrite bead 720 is formed between the second portion 712 and the third portion 713, such that the ferrite bead 720 is electrically connected between the gate electrode 32 of the switch 300 and the first gate terminal 726 of the assembly 700. Ferrite beads are passive electrical components and are typically hollow magnetic beads or cylinders made of ferrite, a semi-magnetic substance made of iron oxide alloyed with other metals. Ferrite beads can be used to suppress noise from electromagnetic interference (EMI) in circuits. The first gate electrode 22 of the switch 300 is connected to the fifth top metal portion 715 using a wire bond 71. The sixth top metal portion 716 is electrically connected to the second gate terminal 725 using a wire bond 75. A ferrite bead 721 (which may be similar to ferrite bead 720) is formed between fifth portion 715 and sixth portion 716, such that ferrite bead 721 is electrically connected between gate electrode 22 of switch 300 and second gate terminal 725 of assembly 700. Ferrite beads 720 and 721 may be selected to form a passive low-pass filter configured to reduce oscillations having frequencies above approximately 100 MHz or 300 MHz and to pass switching frequencies in the range of, for example, tens or hundreds of kHz or 1 MHz. Alternatively, ferrite beads 720 and 721 may be hybrid devices including both resistive and capacitive components. This may result in improved switching performance, which would otherwise be degraded due to the inherent inductance of the connecting wires.

[0084] The first gate pad 16A and the second gate pad 16B of the switch 300 are electrically connected to the seventh top metal portion 717 using wire bonds 72 and 74, respectively. The third gate pad 17A and the fourth gate pad 17B of the switch 300 are electrically connected to the fourth top metal portion 714 using wire bonds 62 and 64, respectively. The second source electrode 33 of the switch 300 is electrically connected to the fourth top metal portion 714 using wire bond 63, and the fourth top metal portion 714 is electrically connected to the first power electrode 727 using wire bond 66. The first source electrode 22 of the switch 300 is electrically connected to the seventh top metal portion 717, and the seventh top metal portion 717 is electrically connected to the second power terminal 723 using wire bond 76. Figure 7 As shown, fourth portion 714 and seventh portion 717 can be formed along two adjacent sides of switch 300 to allow for improved wire bonding connections. When FQS switch 300 is configured in electronic assembly 700 as described above, packaging complexity can be reduced and device efficiency can be improved.

[0085] Figure 8AFIG2 is a circuit schematic of a hybrid III-N FQS switch 800 incorporating a cascode common-source topology. FQS switch 800 includes a first cascode hybrid III-N device 801 and a second cascode hybrid III-N device 804 (indicated in the dashed area). First cascode hybrid III-N device 801 includes a first high-voltage depletion-mode III-N HEMT device 802 in a cascode configuration with a first low-voltage enhancement-mode device 803, wherein the source of device 802 is electrically connected to the drain of device 803. Second cascode hybrid III-N device 804 includes a second high-voltage depletion-mode III-N HEMT device 805 in a cascode configuration with a second low-voltage enhancement-mode device 808, wherein the source of device 805 is electrically connected to the drain of device 808. The drain of first III-N device 802 is connected to a first power terminal T1, and the drain of second III-N device 805 is connected to a second power terminal T2. The gate of the first enhancement mode device 803 is connected to the first gate terminal G1 , and the gate of the second enhancement mode device 808 is connected to the second gate terminal G2 .

[0086] The source of the first enhancement-mode device 803 and the source of the second enhancement-mode device 808 are both electrically connected to a common source terminal CS. Furthermore, the gate of the first III-N device 802 and the gate of the second III-N device 804 are both electrically connected to the common source terminal CS. In this configuration, the sources of both enhancement-mode transistors can be connected to a shared terminal. Furthermore, the first III-N device 802 and the second III-N device 804 can be formed on a common substrate using a shared III-N material structure layer. This allows for reduced complexity when integrating the components of the FQS switch 800 into a common package. Further details of this integration will be described below.

[0087] Figure 8B and 8C A plan view and a cross-sectional view, respectively, of an electronic component package 810 are shown, which includes a hybrid III-N FQS switch, which may be similar to a switch formed using a common source topology. Figure 8A 800 is schematically shown in FIG. Component 810 further includes a package lead frame 814, which may be a conductive structure package substrate and serves as a common source (CS) terminal. Component 810 includes an integrated III-N device 812. III-N device 812 includes a first depletion mode III-N device 802 and a second III-N depletion mode III-N device 805 (composed of Figure 8B802 and second device 805 are formed on a common substrate and share a III-N material structure layer within integrated III-N device 812. Assembly 810 further includes a first enhancement-mode device 803 having a drain physically mounted and electrically connected to a drain 815 of first depletion-mode III-N device 802 and a second enhancement-mode device 808 having a drain physically mounted and electrically connected to a drain 816 of second depletion-mode III-N device 805.

[0088] The hybrid III-N bidirectional switch is configured in an electronic assembly 810 as follows: the drain of a first III-N device 802 is electrically connected to a first terminal T1 via one or more wire bonds 821 (not shown). The drain of a second III-N device 805 is electrically connected to a second terminal T2 using one or more wire bonds 822 (not shown). The gate of the first enhancement-mode device 803 is connected to the first gate terminal G1 using a wire bond 823. The gate of the second enhancement-mode device 808 is connected to the second gate terminal G2 using a wire bond 824. The source 817 of the first enhancement-mode device 803 is connected to the CS terminal 814 using a wire bond 825, and the source 818 of the second enhancement-mode device 808 is connected to the CS terminal 814 using a wire bond 826. Although wire bonding has been described above, the electronic assembly may also be configured using metal clips, metal ribbons, or other suitable methods.

[0089] The gate of the first III-N device 802 is electrically connected to the CS terminal 814 using a through-epitaxial via (TEV) 831, and the gate of the second III-N device 805 is electrically connected to the CS terminal 814 using a TEV 832. TEV 831 and TEV 832 are connected to the CS terminal 814 in a manner similar to that of FIG. Figure 5A TEV 516 and TEV 517 are shown formed in a similar manner.

[0090] Figure 9A and 9B 1 and 2 show a plan view and a cross-sectional view, respectively, of an electronic assembly 900 including a hybrid III-N bidirectional switch similar to Figure 8A . However, assembly 900 differs from assembly 810 in that assembly 900 is configured using an integrated low-voltage enhancement-mode device 910 (e.g., dual integrated Si-FETs). Integrated device 910 combines the functionality of first enhancement-mode device 803 and second enhancement-mode device 808 of assembly 810 into a single integrated silicon device formed on a common substrate.

[0091] Figure 9CDetailed cross section of an integrated enhancement mode device 910 is shown. Figure 9C As shown, device 910 includes a semiconductor body 911 (e.g., silicon) and a common source electrode or pad 930 formed on a first side of semiconductor body 911, which can serve as a common source for first and second enhancement-mode devices integrated into device 910. Device 910 includes a first gate 921 and a second gate 923. First gate 921 can be configured to connect to a first gate terminal G1 of component 900, and second gate 923 can be configured to connect to a second gate terminal G2 of component 900, also formed on the first side of semiconductor body. Integrated device 910 includes a first drain 925 connected to a first drain pad 925a on a second side of semiconductor body 911 (where the second side is opposite the first side) using a first through-substrate via (TSV) 931. Device 910 further includes a second drain 926 connected to a second drain pad 926a on the second side of semiconductor body 911 using a second TSV 932. First drain pad 925a and second drain pad 926a are electrically isolated from each other.

[0092] The integrated low voltage enhancement mode device 910 can be fabricated using methods and material structures similar to those used to form LDMOS Si-FET transistors. The device 910 can be a lateral device, that is, the drain, gate, and source of the device 910 are all formed on the same side of the semiconductor body 911, and then, subsequently, a drain electrode is formed on the opposite side of the semiconductor body 911 using a via formed through the substrate of the device 910 to allow an electrical drain connection to external circuitry on the side opposite the source and gate connections.

[0093] Return Reference Figure 9B , integrated enhancement-mode device 910 is mounted and physically attached to hybrid III-N device 812. A first drain pad 925a of device 910 is electrically connected and physically attached to a first source 815 of III-N device 812. A second drain pad 926a of device 910 is electrically connected and physically attached to a second source 816 of III-N device 812.

[0094] refer to Figure 9A , the first gate 921 of the integrated device 910 is electrically connected to the first gate terminal G1 using a wire bond 823, and the second gate 923 of the integrated device 910 is electrically connected to the second gate terminal G2 using a wire bond 824. The common source pad 930 of the integrated device 910 is electrically connected to the common source (CS) terminal 814 using a wire bond 935. Figure 8BCompared to the electronic assembly 810 of FIG. 8 , the use of an integrated enhancement mode device 910 in the electronic assembly 900 may reduce packaging complexity and improve switching performance.

[0095] Figure 10A FIG. 1 is a circuit diagram of a hybrid integrated III-N bidirectional switch 1000. The FQS switch 1000 includes a circuit similar to Figure 8A The switch 800 is a hybrid III-N FQS that incorporates a cascode topology. The switch 1000 further includes a first gate driver 1002 and a second gate driver 1004. The first gate driver 1002 is used to drive the gate of the enhancement mode device 803, and the second gate driver 1004 is used to drive the gate of the enhancement mode device 808. The components of the first gate driver 1002 and the second gate driver 1004 (shown in the dashed area) and the first enhancement mode device 803 and the second enhancement mode device 808 can be integrated into a single silicon IC, as shown in FIG. Figure 10B As further shown in .

[0096] Figure 10B A plan view of an electronic assembly 1010 forming a hybrid integrated III-N FQS switch is shown. Assembly 101 includes a silicon IC 1020 that includes a first gate driver 1002, a second gate driver 1004, a first enhancement-mode device 803, and a second enhancement-mode device 808, all integrated into a single discrete silicon semiconductor assembly. The electronic assembly also includes a III-N device 812, with silicon IC 1020 mounted and physically attached to the III-N device 812.

[0097] The gate controller input 961 of the first gate driver 1004 is connected to the G1 logic input 970 using a wire bond 946, and the gate controller input 963 of the second gate driver 1006 is connected to the G2 logic input 971 using a wire bond 947. DD 940 can be connected to a single or multiple VDD input terminals. For example, Figure 10B A first VDD input terminal 942a is shown connected to a voltage input VDD 940 using a wire bond 941a and a second VDD input terminal 942b is shown connected to a voltage input VDD 940 using a wire bond 941b. Silicon IC 1020 includes a common source pad 960 electrically connected to a common source CS terminal 814 using a wire bond 965. The common source pad 960 of IC 1020 is electrically connected to the source of the first enhancement mode device 803, the source of the second enhancement mode device 804, and the ground connections of the first gate driver 1002 and the second gate driver 1004 (e.g., Figure 10A 1000 in the circuit diagram).

[0098] Compared to the alternative configurations described previously, using Figure 10B The silicon IC 1020 integrating the driving components of the hybrid III-N FQS switch with the electronic components 1010 can reduce circuit complexity and improve switching performance.

[0099] A number of embodiments have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of the technology and devices described herein. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. An electronic component comprising: a four-quadrant switch (FQS), the four-quadrant switch (FQS) being a depletion-mode III-N device, the depletion-mode III-N device including a first power electrode, a second power electrode, a first gate, and a second gate, wherein the FQS comprises a III-N material structure, and a composition difference in the III-N material structure forms a 2DEG channel therein; a first internal resistor formed by a first portion of the 2DEG channel, wherein a first terminal of the first internal resistor is connected to the first gate of the III-N device; a second internal resistor formed by a second portion of the 2DEG channel, wherein a first terminal of the second internal resistor is connected to the second gate of the III-N device; a first enhancement mode transistor having a first drain electrically connected and physically mounted to the first power electrode, wherein the second terminal of the first internal resistor is electrically connected to the first drain of the first enhancement mode transistor; and A second enhancement mode transistor having a second drain electrically connected and physically mounted to the second power electrode, wherein the second terminal of the second internal resistor is electrically connected to the second drain of the second enhancement mode transistor.

2. The electronic component according to claim 1, wherein The first internal resistor and the second internal resistor have a resistance between 1 Mohm and 100 Mohm.

3. The electronic component according to claim 2, wherein The resistances of the first internal resistor and the second internal resistor are formed using a portion of the 2DEG channel charge.

4. The electronic assembly of claim 1 , further comprising an electronic package having the first terminal, the second terminal, the third terminal, and the fourth terminal; and A first gate of the first enhancement mode transistor is electrically connected to the first terminal, a first source of the first enhancement mode transistor and the first gate of the depletion mode III-N device are electrically connected to the second terminal, a second source of the second enhancement mode transistor and the second gate of the depletion mode III-N device are electrically connected to the third terminal, and a second gate of the second enhancement mode transistor is electrically connected to the fourth terminal.

5. The electronic component according to claim 4, wherein The electronic package is a TO-type package. The electronic component according to claim 4 , wherein: A first ferrite bead is connected between the first gate and the first terminal of the first enhancement mode transistor, and a second ferrite bead is connected between the second gate and the fourth terminal of the second enhancement mode transistor.

7. The electronic component according to claim 6, wherein The first ferrite bead and the second ferrite bead form a low-pass filter configured to reduce oscillations having a frequency higher than 100 MHz.

8. An electronic package comprising: a first terminal, a second terminal, a third terminal, a fourth terminal and a structural packaging substrate; A hybrid enhancement mode four-quadrant switch, the hybrid enhancement mode four-quadrant switch comprising: A III-N depletion mode device, the III-N depletion mode device comprising a substrate, a first power electrode, a second power electrode, a first gate, a second gate, and a III-N material structure, wherein the III-N depletion mode device wherein a composition difference in the III-N material structure forms a 2DEG channel therein, a first enhancement mode transistor comprising a first drain, a first source, and a third gate, wherein the first drain of the first enhancement mode transistor is electrically connected to and physically mounted to the first power electrode, and a second enhancement mode transistor, the second enhancement mode transistor comprising a second drain, a second source, and a fourth gate, wherein the second drain of the second enhancement mode transistor is electrically connected to and physically mounted to the second power electrode; an insulating spacer comprising an insulating layer, a first metal layer, and a second metal layer on a side of the insulating layer opposite the first metal layer, and the second metal layer is physically mounted to the structural package substrate, wherein the first metal layer comprises at least five portions, each portion being electrically isolated from each other by a trench formed through the metal layer, the substrate of the III-N depletion mode device is attached to the first portion of the first metal layer, the third gate of the first enhancement mode transistor is electrically connected to the second portion of the first metal layer, the third portion of the first metal layer is electrically connected to the first terminal of the electronic package, the fourth gate of the second enhancement mode transistor is electrically connected to the fourth portion of the first metal layer, and the fifth portion of the first metal layer is electrically connected to the second terminal; a first ferrite bead connected between the second portion and the third portion of the first metal layer; and A second ferrite bead is connected between the fourth portion and the fifth portion of the first metal layer.

9. The electronic package according to claim 8, wherein: The first gate of the depletion mode III-N device and the first source of the first enhancement mode device are electrically connected to the third terminal of the electronic package.

10. The electronic package of claim 9, wherein: The second gate of the depletion mode III-N device and the second source of the second enhancement mode device are electrically connected to the fourth terminal of the electronic package.

11. The electronic package according to claim 10, wherein: The first ferrite bead and the second ferrite bead form a low-pass filter configured to reduce oscillations having a frequency higher than 100 MHz.

12. The electronic package of claim 8, wherein: The substrate of the depletion mode device and the first portion of the first metal layer are electrically isolated from the first, second, third, and fourth terminals of the electronic package.

13. The electronic package of claim 12, wherein: The substrate of the depletion mode device is maintained at a floating potential.

14. An electronic circuit comprising: a high voltage node, a ground node, a first resistor, and a second resistor; A four-quadrant switch (FQS), wherein the four-quadrant switch is a depletion-mode III-N device including a first power electrode, a second power electrode, a first gate, and a second gate; a first enhancement-mode transistor comprising a first drain, a first source, and a third gate, wherein the first drain of the first enhancement-mode transistor is electrically connected to a first power electrode, and the first gate of the depletion-mode III-N device and the first source of the first enhancement-mode transistor are electrically connected to the high voltage node; and a second enhancement-mode transistor comprising a second drain, a second source, and a fourth gate, wherein the second drain of the second enhancement-mode transistor is electrically connected to the second power electrode, and the second gate of the depletion-mode III-N device and the second source of the second enhancement-mode transistor are electrically connected to the ground node; wherein a first terminal of the first resistor is connected to the first gate of the III-N device, and a second terminal of the first internal resistor is electrically connected to the first drain of the first enhancement mode transistor; and A first terminal of the second resistor is connected to the second gate of the III-N device, and a second terminal of the second resistor is electrically connected to the second drain of the second enhancement mode transistor.

15. The electronic circuit of claim 14, further comprising a first ferrite bead connected between the first gate of the depletion mode transistor and the high voltage node, and a second ferrite bead connected between the second gate of the depletion mode transistor and the ground node.

16. The electronic circuit according to claim 15, wherein The high voltage node can be greater than 600V.

17. The electronic circuit according to claim 16, wherein When the first gate is biased below a first threshold voltage and the second gate is biased above a second threshold voltage, a substantial current flows in a first direction through the channel of the depletion-mode III-N device.

18. The electronic circuit according to claim 17, wherein When the first gate is biased above the first threshold voltage and the second gate is biased below the second threshold voltage, a substantial current flows in a second direction through the channel of the depletion-mode III-N device.

19. The electronic circuit according to claim 18, wherein When the first gate is biased below the first threshold voltage and the second gate is biased below the second threshold voltage, substantial current is blocked through the channel of the depletion mode III-N device in both the first direction and the second direction.

20. The electronic circuit according to claim 19, wherein The depletion mode III-N device is an AlGaN / GaN HEMT.

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