Data reading method and system of daisy chain system
By introducing a cache unit into the daisy chain system and controlling the data transmission sequence, the problem of chip power consumption is solved, power consumption equalization and data reading accuracy are achieved, and additional costs are avoided.
Patent Information
- Application Number
- CN202510596728.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-09
- Publication Date
- 2025-08-29
AI Technical Summary
The existing daisy chain communication systems have the problem of unbalanced chip power consumption when reading cascading chip data. The chips close to the bridge chips have low power consumption, while the terminal chips have high power consumption, resulting in increased circuit costs.
In the daisy chain system, each cascade chip integrates a cache unit and controls data transmission through a confirmation signal, so that each cascade chip only transmits data to the previous cache unit after receiving the confirmation signal, and simultaneously transmits the confirmation signal to the next chip, ensuring that each chip uses the cache unit evenly and avoids the additional increase in the number of cache units.
On the basis of no increase in costs, the power consumption equalization of the cascade chip is improved, the risk of data coverage is reduced, and the accuracy of data reading and power consumption equalization is improved.
Smart Images
Figure CN120560486A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communications, and in particular to a data reading method and system for a daisy chain system. Background Art
[0002] In a daisy-chain communication system, the MCU accesses the bridge chip via the SPI (Serial Peripheral Interface) interface, while the bridge chip and the cascade chips communicate via the daisy chain. Because the daisy-chain communication rate is faster than SPI, when reading data via SPI, the data transmission rate from the cascade chip to the bridge chip is higher than the SPI data reading rate. Therefore, the bridge chip and each cascade chip need to have integrated buffers to buffer data transmitted by the subsequent cascade chip.
[0003] However, the prior art generally has the problem of uneven chip power consumption when reading data from various cascaded chips. Summary of the Invention
[0004] The present invention provides a data reading method and system for a daisy chain system, so as to improve the power consumption balance of each cascaded chip when the daisy chain system reads data at low cost.
[0005] To solve the above technical problems, the technical solution of the present invention provides a data reading method for a daisy chain system, wherein the daisy chain system includes a main control module and N cascade chips connected in series, wherein the input end of the first cascade chip is coupled to the output end of the main control module, and the output end of the first cascade chip is coupled to the input end of an adjacent cascade chip, and each cascade chip integrates n k-bit cache units, and each cascade chip stores m-bit data, N, n, k, and m are all positive integers, and N>1, 1≤k≤m, and n≥m / k. The method includes:
[0006] The main control module outputs a read signal to the first of N serially connected cascade chips, where N is an integer greater than 1;
[0007] The N serially connected cascade chips transmit the stored data to the main control module through the first cascade chip according to the read signal, so that the main control module sequentially reads the stored data of each of the N cascade chips, and the method of transmitting the stored data to the main control module through the first cascade chip according to the read signal includes:
[0008] Whenever the main control module reads k bits of data, the main control module outputs a confirmation signal to the first cascade chip;
[0009] The i-th cascade chip transmits the k-bit data stored in itself to a cache unit in the i-1-th cascade chip only after receiving the confirmation signal, and transmits the confirmation signal to the i+1-th cascade chip, where i is a positive integer and 2<i≤N.
[0010] Optionally, transmitting the stored data to the main control module through the first cascade chip so that the main control module sequentially reads the stored data of each of the N cascade chips, specifically includes:
[0011] The main control module first reads the m bit data stored in the first cascade chip;
[0012] After reading the m bits of data stored in the first cascade chip, the main control module sequentially reads the data of the n cache units in the first cascade chip until all the stored data in the N cascade chips are read.
[0013] Optionally, the i-th cascade chip transfers k bits of data stored in the cascade chip to a cache unit in the i-1-th cascade chip, specifically including:
[0014] The i-th cascade chip transmits the data stored in itself to the n cache units of the i-1-th cascade chip in sequence at every k bits according to the confirmation signals received in sequence.
[0015] Optionally, when the main control module reads data from n cache units in the first cascade chip, the data storage and data transmission of n cache units in the i-th cascade chip specifically include:
[0016] When the main control module reads the data of the n cache units in the first cascade chip, the i-th cascade chip transmits the data in the n cache units to the n cache units in the i-1th cascade chip in sequence according to the confirmation signals received in sequence and in the order in which the data is stored.
[0017] Optionally, the first time is less than the sum of the second time and the third time;
[0018] The first time is used to represent the time for the main control module to read k bit data;
[0019] The second time is used to represent the total time for the i-th cascade chip to transmit the confirmation signal to the i+1-th cascade chip and receive k bits of data transmitted by the i+1-th cascade chip;
[0020] The third time is used to represent the time when the k-bit data transmitted by the (i+1)th cascade chip is written into the i-th cascade chip.
[0021] Optionally, when the i-th cascade chip receives the confirmation signal and its corresponding cache unit has no stored data, the corresponding cache unit outputs redundant data.
[0022] The technical solution of the present invention further provides a daisy chain system, comprising:
[0023] The main control module is used to read the data after outputting the data read signal and output a confirmation signal every time k bits of data are read;
[0024] N cascade chips are connected in series, the input end of the first cascade chip is coupled to the output end of the main control module, the output end of the first cascade chip is coupled to the input end of the adjacent cascade chip, and each cascade chip integrates n kbit cache units, and each cascade chip stores mbit data, the i-th cascade chip is used to transfer the kbit data stored in itself to a cache unit in the i-1-th cascade chip only after receiving the confirmation signal, and transmit the confirmation signal to the i+1-th cascade chip, N, n, m, k and i are all positive integers, and 2<i≤N, 1≤k≤m, n≥m / k.
[0025] Optionally, the i-th cascade chip is further configured to sequentially transmit the data in the n cache units to the n cache units in the i-1-th cascade chip according to the sequentially received confirmation signals and in the order in which the data are stored.
[0026] The technical solution of the present invention further provides an electronic device, comprising a processor and a memory,
[0027] The memory is used to store codes and related data;
[0028] The processor is configured to execute the code in the memory to implement the data reading method of the daisy chain system.
[0029] The technical solution of the present invention further provides a storage medium on which a computer program is stored. When the program is executed by a processor, the data reading method of the daisy chain system is implemented.
[0030] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:
[0031] The data reading method for a daisy-chain system provided by the technical solution of the present invention, with the exception of the first cascaded chip, transmits the k-bit data stored in each cascaded chip to the cache unit of the preceding adjacent chip only after receiving the confirmation signal, and simultaneously transmits the received confirmation signal to the following adjacent chip. This allows each chip to perform the same data upload and data storage steps, thereby ensuring that each cascaded chip uses the same number of cache units for data storage, thereby improving power consumption balance among different cascaded chips. Furthermore, the embodiments of the present invention do not require an additional number of cache units within the cascaded chips, thereby improving power consumption balance among different cascaded chips without increasing costs.
[0032] Furthermore, the first time is set to be less than the sum of the second time and the third time. The first time is used to represent the time it takes for the main control module to read k bits of data. The second time is used to represent the total time it takes for the i-th cascade chip to transmit the confirmation signal to the i+1-th cascade chip and receive the kbits of data transmitted by the i+1-th cascade chip. The third time is used to represent the time it takes for the kbits of data transmitted by the i+1-th cascade chip to be written to the i-th cascade chip, thereby preventing data overwriting during the data reading process and improving the accuracy of data reading.
[0033] Furthermore, after the i-th cascade chip receives the confirmation signal and its corresponding cache unit has no stored data, the corresponding cache unit outputs redundant data, thereby further improving the power consumption balance of each cascade chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 A schematic diagram of a daisy chain system reading data embodiment;
[0035] Figure 2 A schematic diagram of the structure of a daisy chain system provided by an embodiment of the present invention;
[0036] Figure 3 A schematic diagram of the mechanism of applying the data reading method of the daisy chain system provided by an embodiment of the present invention to the daisy chain system. DETAILED DESCRIPTION
[0037] As described in the background art, the daisy chain system of the prior art often has the problem of uneven chip power consumption when reading data from each cascaded chip. The following example of a daisy chain system reading data illustrates the problems of the prior art:
[0038] Figure 1 A schematic diagram of a daisy chain system reading data embodiment.
[0039] Please refer to Figure 1, Figure 1 The daisy-chain system shown includes an MCU, a bridge chip, and several serially connected cascade chips. The MCU and bridge chip access the bridge chip via the SPI interface, and the bridge and cascade chips communicate with each other via the daisy chain. The bridge chip and each cascade chip are assumed to store 4 x 16-bit data and have four integrated buffers. Each buffer is used to store 16 bits of data.
[0040] When the MCU reads data, it sends a data read signal to the bridge chip to read the data stored in the bridge chip and the cascade chips. Upon receiving the data read signal, the cascade chips enter a data read state and transfer their stored 16-bit data to the buffer of the previous adjacent cascade chip. For example, when the fourth cascade chip enters the data read state, it transfers its stored 16-bit data to the buffer of the third cascade chip.
[0041] Each time the MCU finishes reading 16 bits of data, it outputs an ACK signal (Acknowledgement) to the bridge chip, which then passes it to the cascade chips in sequence. After receiving the ACK signal, each cascade chip transfers the 16 bits of data it has stored to the buffer of the previous adjacent cascade chip.
[0042] Because the MCU reads data via SPI at a slower rate than the daisy-chained data upload rate between connected chips, each connected chip sets a buffer watermark. When the number of full buffers exceeds the watermark, the connected chip stops receiving data until the number of full buffers falls below the watermark, preventing the buffers in the connected chip from bursting while the MCU is reading data.
[0043] However, the data reading problem of this embodiment is:
[0044] 1. Because the cascade chips closer to the bridge chip receive acknowledgment signals faster, they can quickly complete data transmission and enter a low-power state. However, because the ACK signal must pass through multiple stages before reaching the cascade chip at the end, the cascade chip at the end must continue waiting and keep the transmitting circuit active, resulting in greater power consumption.
[0045] 2. Because the cascade chips near the bridge chip need to relay data from the downstream cascade chips, their buffers fill faster, frequently triggering watermark pauses. This causes the cascade chips near the bridge chip to only work intermittently. Since the downstream cascade chips only need to process their own data, their buffers fill more slowly and are less likely to trigger watermarks, resulting in continuous operation and high power consumption.
[0046] Based on the above description, when the MCU reads data, there is a problem of uneven power consumption between the cascade chips. To avoid this problem, more buffers can be set in each cascade chip, but this will increase the area of the cascade chip, thereby increasing the circuit cost.
[0047] In view of this, an embodiment of the present invention provides a new data reading method for a daisy chain system, so as to improve the power consumption balance of cascaded chips when the daisy chain system reads data at a low cost.
[0048] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices.
[0049] Before introducing the data reading method of the daisy chain system provided by the embodiment of the present invention, the daisy chain system to which the method is applied is first described:
[0050] Figure 2 A schematic structural diagram of a daisy chain system provided by an embodiment of the present invention.
[0051] Please refer to Figure 2The daisy chain system provided by an embodiment of the present invention includes a main control module 10 and N serially connected cascade chips 20. The main control module 10 accesses the first cascade chip 20 via an SPI interface. The input of the first cascade chip 20 is coupled to the output of the main control module 10, and the output of the first cascade chip 20 is coupled to the input of the adjacent cascade chip 20. The input of the i-th cascade chip 20 is connected to the output of the i-1th cascade chip 20, and the output of the i-th cascade chip 20 is connected to the input of the i+1th cascade chip 20. Each cascade chip 20 stores m bits of data and is integrated with n cache units 21, each of which is used to store k bits of data. i, N, n, k, and m are all positive integers, 1 < i < N, 1 ≤ k ≤ m, and n ≥ m / k.
[0052] Specifically, the main control module 10 is specifically an MCU, which is used to read and analyze data from the N cascade chips 20. Of course, the main control module 10 can also be other data processing modules, which is not limited here.
[0053] The first cascade chip 20 is specifically a bridge chip, which is used to implement protocol conversion between SPI communication and daisy chain communication. The remaining cascade chips 20 are specifically analog front-end chips, which are used to collect and store specified data.
[0054] based on Figure 2 The daisy chain system shown in FIG. 1 , and the data reading method of the daisy chain system provided by the embodiment of the present invention include the following steps:
[0055] The main control module 10 outputs a read signal SCK to the first of N serially connected cascade chips 20 , where N is an integer greater than 1.
[0056] The N serially connected cascade chips 20 transmit the stored data to the main control module 10 through the first cascade chip 20 according to the read signal SCK, so that the main control module 10 sequentially reads the stored data of each of the N cascade chips 20, and the method of transmitting the stored data to the main control module 10 through the first cascade chip 20 according to the read signal SCK includes:
[0057] Starting from the second cascade chip 20, when the i-th cascade chip 20 receives the confirmation signal ACK, the i-th cascade chip 20 transmits the k-bit data stored in itself to a cache unit 21 in the i-1-th cascade chip 20, and transmits the confirmation signal ACK to the i+1-th cascade chip 20, where i is a positive integer and 2<i≤N.
[0058] When the main control module 10 finishes reading the m bits of data stored in each cascade chip 20, the main control module 10 completes data reading.
[0059] After the main control module 10 outputs the data read signal SCK, the main control module 10 reads the stored data of the first cascade chip 20 through SPI transmission. At this time, each cascade chip 20 does not upload its own data and maintains a low power consumption state.
[0060] Whenever the main control module 10 reads a kbit of data, it outputs an acknowledgment signal ACK to the first cascade chip 20, which then transmits the acknowledgment signal ACK to the second cascade chip 20. Except for the first cascade chip 20, the other cascade chips 20 only transfer their stored kbits of data to the cache unit 21 of the preceding adjacent chip after receiving the acknowledgment signal ACK. Simultaneously, they transmit the received acknowledgment signal ACK to the following adjacent chip, ensuring that each chip performs the same data upload and data storage steps. This ensures that each cascade chip 20 uses the same number of cache units 21 for data storage, thereby improving power consumption balance among different cascade chips 20. Furthermore, embodiments of the present invention eliminate the need to increase the number of cache units 21 within each cascade chip 20, thereby improving power consumption balance among different cascade chips 20 without increasing costs.
[0061] The following takes m as 64, k as 16, and n as 4 as an example to describe in detail the data reading method of the daisy chain system provided by the embodiment of the present invention.
[0062] Figure 3 A schematic diagram of the mechanism of applying the data reading method of the daisy chain system provided by an embodiment of the present invention to the daisy chain system.
[0063] Please refer to Figure 2 and Figure 3 Each cascade chip 20 is provided with four local storage addresses for data, and each local storage address stores 16-bit data. The four cache units 21 in each cascade chip 20 also correspond to four data cache addresses respectively.
[0064] After the main control module 10 outputs the data read signal SCK, the main control module 10 reads the 16-bit data stored at the first local storage address in the first cascade chip 20 via SPI. After reading the data stored at the first local storage address, the main control module 10 outputs an acknowledgment signal ACK to the first cascade chip 20 and continues to read the data stored at the second local storage address. The acknowledgment signal ACK is transmitted from the first cascade chip 20 to the adjacent second cascade chip 20.
[0065] After receiving the confirmation signal ACK, the second cascade chip 20 transfers the 16-bit data in its own first local storage address to the first cache unit 21 corresponding to the first cache address in the first cascade chip 20, and transmits the confirmation unit to the third cascade chip 20. After receiving the confirmation signal ACK, the third cascade chip 20 transfers the 16-bit data in its own first local storage address to the first cache unit 21 corresponding to the first cache address in the second cascade chip 20, and transmits the confirmation unit to the fourth cascade chip 20. Subsequent cascade chips 20, after receiving the confirmation unit, all follow the steps of the second and third cascade chips 20, which will not be repeated here.
[0066] After reading the data stored in the second local storage address, the main control module 10 outputs an acknowledgment signal ACK to the first cascade chip 20 and continues to read the data stored in the third local storage address. The acknowledgment signal ACK is transmitted from the first cascade chip 20 to the adjacent second cascade chip 20.
[0067] After receiving the second confirmation signal ACK, the second cascade chip 20 transfers the 16-bit data in its second local storage address to the second cache unit 21 corresponding to the second cache address in the first cascade chip 20, and transmits the confirmation unit to the third cascade chip 20. After receiving the confirmation signal ACK, the third cascade chip 20 transfers the 16-bit data in its second local storage address to the second cache unit 21 corresponding to the second cache address in the second cascade chip 20, and transmits the confirmation unit to the fourth cascade chip 20. Subsequent cascade chips 20, after receiving the confirmation unit, all follow the steps of the second and third cascade chips 20, which will not be repeated here.
[0068] The subsequent steps of the main control module 10 reading the data in the third local storage address and the fourth local storage address in the first cascade chip 20 are the same as the data in the first local storage address and the second local storage address, which will not be repeated here.
[0069] After the main control module 10 finishes reading the 64-bit data stored in the first cascade chip 20, the four cache units 21 within the first cascade chip 20 also store the 16-bit data stored at the first to fourth local storage addresses within the second cascade chip 20, respectively. Therefore, the main control module 10 begins reading the data stored in the four cache units 21 within the first cascade chip 20, that is, reading the data stored in the second cascade chip 20. Because the data in the four cache units 21 within the first cascade chip 20 is stored sequentially from the first to the fourth cache addresses, the main control module 10 also reads data sequentially from the first to the fourth cache addresses, and outputs an acknowledgment signal ACK to the first cascade chip 20 after reading the data in each cache unit 21.
[0070] When the second cascade chip 20 receives the fifth acknowledgment signal ACK, the second cascade chip 20 will transfer the data corresponding to the first cache unit 21 of its own first cache address to the first cache unit 21 corresponding to the first cache address of the first cascade chip 20, in the order in which the third cascade chip 20 stored the data in its own cache unit 21, and will transmit the fifth acknowledgment signal ACK to the third cascade chip 20. When the third cascade chip 20 receives the fifth acknowledgment signal ACK, the third cascade chip 20 will transfer the data corresponding to the first cache unit 21 of its own first cache address to the first cache unit 21 corresponding to the first cache address of the second cascade chip 20, in the order in which the fourth cascade chip 20 stored the data in its own cache unit 21. After receiving the fifth confirmation signal ACK, the subsequent cascade chips 20 all follow the operations of the second cascade chip 20 and the third cascade chip 20 to transfer the data in their own first cache unit 21 to the first cache unit 21 of the previous adjacent cascade chip 20, which will not be repeated here.
[0071] When the second cascade chip 20 receives the sixth acknowledgment signal ACK, the second cascade chip 20 transfers the data corresponding to the second cache unit 21 of its own second cache address to the second cache unit 21 corresponding to the second cache address of the first cascade chip 20, in the order in which the third cascade chip 20 stored the data in its own cache unit 21, and transmits the sixth acknowledgment signal ACK to the third cascade chip 20. When the third cascade chip 20 receives the sixth acknowledgment signal ACK, the third cascade chip 20 transfers the data corresponding to the second cache unit 21 of its own second cache address to the second cache unit 21 corresponding to the second cache address of the second cascade chip 20, in the order in which the fourth cascade chip 20 stored the data in its own cache unit 21. After receiving the sixth acknowledgment signal ACK, each subsequent cascade chip 20 follows the operations of the second and third cascade chips 20, transferring the data in its own second cache unit 21 to the second cache unit 21 of the immediately preceding adjacent cascade chip 20. This will not be further described here. When the master control module 10 subsequently outputs the seventh and eighth acknowledgment signals ACK, respectively, each cascade chip 20 transfers the data in its own third cache unit 21 corresponding to its third cache address and the data in its own fourth cache unit 21 corresponding to its fourth cache address, respectively, to the third and fourth cache units 21 of the immediately preceding adjacent cascade chip 20. This will not be further described here.
[0072] After the main control module 10 has finished reading the stored data in each of the four cache units 21 within the first cascade chip 20 for the first time, it indicates that the main control module 10 has finished reading the 64-bit data stored in the second cascade chip 20. The four cache units 21 within the first cascade chip 20 also store the 16-bit data stored at the first to fourth local storage addresses within the third cascade chip 20. Therefore, the main control module 10 reads the stored data in the four cache units 21 within the first cascade chip 20 again, i.e., reads the data stored in the third cascade chip 20. Since the data in the four cache units 21 within the first cascade chip 20 is stored sequentially from the first to the fourth cache addresses, the main control module 10 also reads the data sequentially from the first to the fourth cache addresses, and outputs an acknowledgment signal ACK to the first cascade chip 20 after reading the data in each cache unit 21.
[0073] In the process of the main control module 10 reading the data stored in the third cascade chip 20 and all subsequent cascade chips 20, the data transmission steps performed by each cascade chip 20 according to the confirmation signal ACK are the same as the process of the main control module 10 reading the data stored in the second cascade chip 20, and will not be repeated here.
[0074] It can be seen from the process of the main control module 10 reading the stored data of each cascade chip 20 that the data reading method of the daisy chain system provided by the embodiment of the present invention improves the first-in-first-out rule of data in the cache unit 21, that is, the data is stored in the first cache unit 21 to the fourth cache unit 21 in sequence, and when reading the data, it is also read in sequence according to the first cache unit 21 to the fourth cache unit 21, and the subsequent data continues to be stored in sequence according to the first cache unit 21 to the fourth cache unit 21, thereby further improving the power consumption balance of each cascade chip 20.
[0075] As a preferred embodiment, in order to prevent data from being overwritten during the first-out, first-in process, that is, data is overwritten by subsequently transmitted data before being read, it is necessary to increase the first time to be less than the sum of the second time and the third time. The first time is used to represent the time it takes for the main control module 10 to read 16-bit data. The second time is used to represent the total time it takes for the i-th cascade chip 20 to transmit the confirmation signal ACK to the i+1-th cascade chip 20 and receive the 16-bit data transmitted by the i+1-th cascade chip 20. The third time is used to represent the time it takes for the 16-bit data transmitted by the i+1-th cascade chip 20 to be written to the i-th cascade chip 20.
[0076] In a specific application of an embodiment of the present invention, the second time is specifically 1.45 μs. Considering a 10% deviation in the clock frequencies of adjacent cascaded chips 20, the maximum value of the first time is 5.76 μs, and the minimum value of the third time is 4.72 μs. This also increases the probability that the first time is less than the sum of the second and third times. Of course, in different application scenarios, the first, second, and third times may each vary, and this is not limited here.
[0077] As a preferred embodiment, when the main control module 10 reads the storage data of the second cascade chip 20 and reads the storage data of the subsequent cascade chips 20, the cascade chips 20 starting from the Nth cascade chip 20 and sequentially forward will have no data stored in the cache unit 21 due to no data input. However, in order to improve the power consumption balance of each cascade chip 20, after the i-th cascade chip 20 receives the confirmation signal ACK and the corresponding cache unit 21 has no stored data, the corresponding cache unit 21 outputs redundant data.
[0078] In summary, the data reading method for a daisy-chain system provided by the embodiment of the present invention has the following characteristics: except for the first cascade chip, other cascade chips only transfer the kbit data stored in themselves to the cache unit of the previous adjacent chip after receiving the confirmation signal, and simultaneously transmit the received confirmation signal to the next adjacent chip, so that each chip performs the same data upload and data storage steps, thereby ensuring that the number of cache units used by each cascade chip to store data is the same, thereby improving the power consumption balance of different cascade chips. At the same time, the embodiment of the present invention does not require additional increase in the number of cache units in the cascade chip, thereby improving the power consumption balance of different cascade chips without increasing costs.
[0079] Furthermore, the first time is set to be less than the sum of the second time and the third time. The first time is used to represent the time it takes for the main control module to read k bits of data. The second time is used to represent the total time it takes for the i-th cascade chip to transmit the confirmation signal to the i+1-th cascade chip and receive the kbits of data transmitted by the i+1-th cascade chip. The third time is used to represent the time it takes for the kbits of data transmitted by the i+1-th cascade chip to be written to the i-th cascade chip, thereby preventing data overwriting during the data reading process and improving the accuracy of data reading.
[0080] Furthermore, after the i-th cascade chip receives the confirmation signal and its corresponding cache unit has no stored data, the corresponding cache unit outputs redundant data, thereby further improving the power consumption balance of each cascade chip.
[0081] An embodiment of the present invention further provides an electronic device, comprising a processor and a memory,
[0082] The memory is used to store codes and related data;
[0083] The processor is configured to execute the code in the memory to implement the data reading method of the daisy chain system.
[0084] An embodiment of the present invention further provides a storage medium storing a computer program, which implements the data reading method of the daisy chain system when executed by a processor.
[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A data reading method for a daisy chain system, characterized in that: The daisy chain system includes a main control module and N cascade chips connected in series, the input end of the first cascade chip is coupled to the output end of the main control module, the output end of the first cascade chip is coupled to the input end of an adjacent cascade chip, and each cascade chip integrates n k-bit cache units, and each cascade chip stores m-bit data, N, n, k and m are all positive integers, and N>1, 1≤k≤m, n≥m / k, the method includes: The main control module outputs a read signal to the first of N serially connected cascade chips, where N is an integer greater than 1; The N serially connected cascade chips transmit the stored data to the main control module through the first cascade chip according to the read signal, so that the main control module sequentially reads the stored data of each of the N cascade chips, and the method of transmitting the stored data to the main control module through the first cascade chip according to the read signal includes: Whenever the main control module reads k bits of data, the main control module outputs a confirmation signal to the first cascade chip; The i-th cascade chip transmits the k-bit data stored in itself to a cache unit in the i-1-th cascade chip only after receiving the confirmation signal, and transmits the confirmation signal to the i+1-th cascade chip, where i is a positive integer and 2 <i≤N。 2. The data reading method of the daisy chain system according to claim 1, characterized in that: Transmitting the stored data to the main control module through the first cascade chip, so that the main control module sequentially reads the stored data of each of the N cascade chips, specifically includes: The main control module first reads the m bit data stored in the first cascade chip; After reading the m bits of data stored in the first cascade chip, the main control module sequentially reads the data of the n cache units in the first cascade chip until all the stored data in the N cascade chips are read.
3. The data reading method of the daisy chain system according to claim 2, characterized in that: The i-th cascade chip transfers the k-bit data stored in the cascade chip to a cache unit in the i-1-th cascade chip, specifically including: The i-th cascade chip transmits the data stored in itself to the n cache units of the i-1-th cascade chip in sequence at every k bits according to the confirmation signals received in sequence.
4. The data reading method of the daisy chain system according to claim 3, characterized in that: When the main control module reads data from n cache units in the first cascade chip, the data storage and data transmission of n cache units in the i-th cascade chip specifically include: When the main control module reads the data of the n cache units in the first cascade chip, the i-th cascade chip transmits the data in the n cache units to the n cache units in the i-1th cascade chip in sequence according to the confirmation signals received in sequence and in the order in which the data is stored.
5. The data reading method of the daisy chain system according to claim 4, characterized in that: Also includes: The first time is less than the sum of the second time and the third time; The first time is used to represent the time for the main control module to read k bit data; The second time is used to represent the total time for the i-th cascade chip to transmit the confirmation signal to the i+1-th cascade chip and receive k bits of data transmitted by the i+1-th cascade chip; The third time is used to represent the time when the k-bit data transmitted by the (i+1)th cascade chip is written into the i-th cascade chip.
6. The data reading method of the daisy chain system according to claim 5, characterized in that: When the i-th cascade chip receives the confirmation signal and its corresponding cache unit has no stored data, the corresponding cache unit outputs redundant data.
7. A daisy chain system, characterized in that: include: The main control module is used to read the data after outputting the data read signal and output a confirmation signal every time k bits of data are read; N cascade chips are connected in series, the input end of the first cascade chip is coupled to the output end of the main control module, the output end of the first cascade chip is coupled to the input end of the adjacent cascade chip, and each cascade chip integrates n k-bit cache units, and each cascade chip stores mbit data, the i-th cascade chip is used to transfer the kbit data stored in itself to a cache unit in the i-1-th cascade chip after receiving the confirmation signal, and transmit the confirmation signal to the i+1-th cascade chip, N, n, m, k and i are all positive integers, and 2 <i≤N,1≤k≤m,n≥m / k。 8. The daisy chain system according to claim 7, wherein: The i-th cascade chip is further configured to sequentially transmit the data in the n cache units to the n cache units in the i-1-th cascade chip according to the sequentially received confirmation signals and in the order in which the data are stored.
9. An electronic device, characterized in that: Including processor and memory, The memory is used to store codes and related data; The processor is configured to execute the code in the memory to implement the data reading method of the daisy chain system according to any one of claims 1 to 6.
10. A storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the data reading method of the daisy chain system according to any one of claims 1 to 6 is implemented.