Rram memory and computing integrated chip of hybrid analog-digital converter and electronic equipment

Abstract

The application discloses a kind of RRAM memory and computing integrated chip of hybrid analog-digital converter and electronic equipment, belong to memory and computing integrated chip technical field, including RRAM array module, gating module and hybrid analog-digital converter module, the word line, bit line and source line of gating module and RRAM array module are connected, and receive digital control signal, the specific address of RRAM array module is gated, read-write and matrix-vector multiplication operation;Hybrid analog-digital converter is connected on the source line of RRAM array module by gating module, digital control signal is input voltage to the bit line and word line of RRAM array module by controlling gating switch, the source line of RRAM array module generates corresponding convergent current, the current is transmitted to hybrid analog-digital converter by gating module, and the analog-digital converter completes quantization, and output calculation result.The application can greatly improve the computing power of chip, and be more favorable to the storage and matrix-vector multiplication calculation of data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory-computing integrated chips, and particularly relates to a hybrid analog-digital converter RRAM memory-computing integrated chip and electronic equipment. BACKGROUND

[0002] Due to the "memory wall" and "power wall" problems caused by the "von Neumann" architecture, the chip of the traditional architecture has been difficult to cope with the current computing demand of neural networks. The memory-computing integrated technology, as a new type of computing technology, greatly improves the computing energy efficiency through the combination of the computing unit and the storage unit. According to the type of the storage unit, the memory-computing integrated technology can be divided into CMOS-based memory-computing integration and memristor-based memory-computing integration. The storage unit is the core of the memory-computing integration. The storage unit of the CMOS-based memory-computing integration mainly includes static random access memory (SRAM), dynamic random access memory (DRAM) and flash memory (Flash). The memory-computing integration based on the memristor mainly includes PCM, MRAM, FRAM and RRAM. Due to the advantages of good CMOS process compatibility, easy large-scale integration and fast read-write speed of RRAM, RRAM has been favored by many scholars. However, the current RRAM memory-computing integration is limited by the speed and area of the readout circuit, and the computing power density of the RRAM memory-computing integrated chip is difficult to improve. SUMMARY

[0003] In view of the low computing power density of the RRAM memory-computing integrated chip in the prior art, the present application aims to provide a hybrid analog-digital converter RRAM memory-computing integrated chip and electronic equipment.

[0004] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows: a hybrid analog-digital converter RRAM memory-computing integrated chip, comprising: an RRAM array module, configured to be responsible for the storage of weight data and matrix-vector multiplication calculation;

[0005] a gating module, configured to receive a digital control signal, gate specific units of the RRAM array module and perform read-write and matrix-vector multiplication operations, apply read-write voltage, and be connected to a hybrid analog-digital converter module;

[0006] a hybrid analog-digital converter module, connected to the gating module, obtains current from the RRAM array module through the gating module, and quantizes an analog signal into a 5-bit digital signal result output.

[0007] Further, the RRAM array module comprises: mxn 1T1R units, each 1T1R unit is composed of 1 NMOS tube and 1 RRAM device, the state of each RRAM device is represented as 1 / 0 two states according to the resistance value, and n columns of RRAMs constitute n bit weight values. The drain of the NMOS tube in each 1T1R unit is connected to the lower electrode of the RRAM, the sources of the transistors in each column are connected to form a source line, the gates of the transistors in each row are connected to form a word line, and the upper electrodes of the RRAMs in each column are connected to form a bit line.

[0008] Further, for the RRAM array module, the n bit weight values are mapped to the n column RRAM array, the input to be subjected to matrix-vector multiplication is selected by the word line WL, the weight to be involved in the matrix-vector multiplication calculation is selected by the n column bit line, n output current values are generated and output to the hybrid analog-digital converter, and the quantized digital result is output by the analog-digital converter; during the matrix-vector multiplication calculation, the selected word line WL is connected to the VWLREAD voltage through the selection module, and the unselected word line WL is connected to the GND voltage through the selection module; the selected bit line is connected to the VBLREAD voltage through the selection module, and the unselected bit line is connected to the GND voltage through the selection module; the selected source line is connected to the hybrid analog-digital converter through the selection module, and the unselected source line is connected to the GND voltage.

[0009] Further, for the 1T1R unit with coordinates [m, n] in the RRAM array module, when the RESET operation is performed, the word line WL[m] is connected to the VWLRESET voltage through the selection module, the bit line BL[n] is connected to the GND voltage through the selection module, the source line SL[n] is connected to the VSLRESET voltage through the selection module, and the RRAM device will be written to state 0; when the SET operation is performed, the word line WL[m] is connected to the VWLSET voltage through the selection module, the bit line BL[n] is connected to the VBLSET voltage through the selection module, and the source line SL[n] is connected to the GND voltage through the selection module, and the RRAM device will be written to state 1; when the READ operation is performed, the word line WL[m] is connected to the VWLREAD voltage through the selection module, the bit line BL[n] is connected to the VBLREAD voltage through the selection module, and the source line SL[n] is connected to the hybrid analog-digital converter through the selection module and outputs the quantized digital signal result.

[0010] Further, the selection module comprises: a selection unit and a level shift unit, the selection unit accepts a digital input signal, selects the corresponding RRAM unit, and inputs the amplified digital input signal to the RRAM array module through the level shift unit.

[0011] Further, the hybrid analog-digital converter module comprises: a current-to-voltage circuit and a hybrid sensitive amplifier.

[0012] Further, the current-to-voltage circuit comprises: a transistor P5, a transistor P6, a transistor P7, a transistor N7, a transistor N8, a capacitor CLSB, an IMSB generator, switches SW8 and SW9; a source of the transistors P5, P6 and P7 is connected to a power supply voltage VDD, a gate of the transistors P5 and P6 is connected through the switch SW9, a gate and a drain of the transistor P5 are connected; a drain of the transistor P6 is connected to an upper electrode of the capacitor CLSB, a lower electrode of the capacitor CLSB is connected to GND; a gate of the transistor P7 is connected to the IMSB generator, an input signal MACV[4:3] of the IMSB generator comes from the hybrid sensitive amplifier; a drain of the transistor P7 is connected to a gate and a drain of the transistor N8, a source of the transistor N8 is connected to GND; a gate of the transistor N7 is connected to a gate of the transistor N8, a source of the transistor N7 is grounded, and a drain is connected to a drain of the transistor P5 through the switch SW8.

[0013] Further, the hybrid sensitive amplifier comprises: a transistor P1, a transistor P2, a transistor P3, a transistor P4, a transistor N1, a transistor N2, a transistor N3, a transistor N4, a transistor N5, a transistor N6, switches SW1, SW2, SW3, SW4 and SW5; a source of the transistors P1, P2, P3 and P4 is connected to a power supply voltage VDD, a drain of the transistors P2 and P4 is connected to a gate of the transistor P3; a drain of the transistors P1 and P3 is connected to a gate of the transistor P2; a drain of the transistor N1 is connected to a drain of the transistor P2, and a gate of the transistor N1 is connected to a gate of the transistor P2; a gate and a drain of the transistors N2 and P3 are connected; a drain of the transistor N3 is connected to a source of the transistor N1, and a drain of the transistor N4 is connected to a source of the transistor N2; the switches SW1 and SW2 are connected to a gate of the transistor N3; the switches SW3 and SW4 are connected to a gate of the transistor N4, the switch SW6 is connected to a source of the transistor N3, and the switch SW7 is connected to a source of the transistor N4; a source of the transistors N3 and N4 is connected to a drain of the transistors N5 and N6 respectively, and a drain of the transistors N5 and N6 is connected through the switch SW5, and a source is connected to GND.

[0014] The application further provides an electronic device comprising a shell and the RRAM memory and computing integrated chip of the hybrid analog-to-digital converter.

[0015] The beneficial effects of the present application are: the present application adopts a current-voltage hybrid mode sensitive amplifier, the precision of working in current mode is 2 bits, the precision of working in voltage mode is 3 bits, and a total of 5 bits of readout precision can be provided. Compared with the traditional way, the present application can improve the computing power density by 1 times, at the same time, can reduce the energy consumption of the readout circuit, improve the readout delay, and provide a circuit basis for RRAM-based memory-computing integrated application. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 The RRAM memory-computing integrated chip module of the present application is shown in the figure.

[0018] Figure 2 The RRAM array module of the present application is shown in the figure.

[0019] Figure 3 The current-to-voltage circuit of the present application is shown in the figure.

[0020] Figure 4 The hybrid sensitive amplifier of the present application is shown in the figure. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0022] It should be noted that the features in the following embodiments and implementation manners can be combined with each other without conflict.

[0023] As Figure 1As shown, the application provides a hybrid analog-digital converter RRAM memory and computing integrated chip, which comprises a RRAM array module, a gating module and a hybrid analog-digital converter module, the RRAM array module is responsible for the storage of weight data and matrix-vector multiplication calculation; the gating module receives a digital control signal, selects specific units of the RRAM array module and performs read-write and matrix-vector multiplication operations, and when performing read operation and matrix-vector multiplication operation, the source line of the RRAM array is connected to the hybrid analog-digital converter through the gating module; the analog-digital converter quantizes the analog signal into a digital signal result output.

[0024] As shown, Figure 2 The RRAM array module comprises: m*n 1T1R units, each 1T1R unit is composed of 1 NMOS tube and 1 RRAM device, the state of each RRAM device is represented as 1 / 0 two states according to the resistance value, and n columns of RRAMs constitute n bit weight values. The drain of the NMOS tube in each 1T1R unit is connected to the lower electrode of the RRAM, the source of each column of transistors is connected as a source line, the gate of each row of transistors is connected as a word line, and the upper electrode of each column of RRAMs is connected as a bit line.

[0025] Specifically, for the RRAM array module, the n bit weight values are mapped to n columns of RRAM arrays, the input to be operated by the word line is selected, the weight to be involved in the matrix-vector multiplication calculation is selected through the n column bit lines, n output current values are generated and output to the hybrid analog-digital converter, and the hybrid analog-digital converter outputs the digital result of the calculation. When performing matrix-vector multiplication calculation, the selected word line is connected to the VWLREAD voltage through the gating module, and the unselected word line is connected to the GND voltage through the gating module; the selected bit line is connected to the VBLREAD voltage through the gating module, and the unselected bit line is connected to the GND voltage through the gating module; the selected source line is connected to the hybrid analog-digital converter through the gating module, and the unselected source line is connected to the GND voltage.

[0026] Specifically, for the 1T1R cell with coordinates [m, n] in the RRAM array module, when a RESET operation is performed, the word line WL[m] is connected to the VWLRESET voltage through the gating module, the bit line BL[n] is connected to the GND voltage through the gating module, and the source line SL[n] is connected to the VSLRESET voltage through the gating module, and the RRAM device will be written to state 0; when a SET operation is performed, the word line WL[m] is connected to the VWLSET voltage through the gating module, the bit line BL[n] is connected to the VBLSET voltage through the gating module, and the source line SL[n] is connected to the GND voltage through the gating module, and the RRAM device will be written to state 1; when a READ operation is performed, the word line WL[m] is connected to the VWLREAD voltage through the gating module, the bit line BL[n] is connected to the VBLREAD voltage through the gating module, and the source line SL[n] is connected to the hybrid analog-to-digital converter through the gating module and outputs the quantized digital signal result.

[0027] The gating module includes a gating unit and a level shifting unit. The gating unit receives a digital input signal, selects the corresponding RRAM unit, and amplifies the digital input signal through the level shifting unit before inputting it into the RRAM array module.

[0028] The hybrid analog-to-digital converter module includes a current-to-voltage circuit and a hybrid sensitive amplifier.

[0029] like Figure 3 Figure 1 shows a current-to-voltage circuit, comprising transistors P5, P6, P7, N7, N8, capacitor CLSB, an IMSB generator, and switches SW8 and SW9. The sources of transistors P5, P6, and P7 are connected to the power supply voltage VDD. The gates of transistors P5 and P6 are connected via switch SW9, and the gate and drain of transistor P5 are connected. The drain of transistor P6 is connected to the top electrode of capacitor CLSB, and the bottom electrode of capacitor CLSB is connected to GND. The gate of transistor P7 is connected to the IMSB generator, whose input signal MACV[4:3] comes from a hybrid sense amplifier. The drain of transistor P7 is connected to the gate and drain of transistor N8, and the source of transistor N8 is connected to GND. The gate of transistor N7 is connected to the gate of transistor N8, the source of transistor N7 is grounded, and the drain is connected to the drain of transistor P5 via switch SW8.

[0030] like Figure 4As shown, it is a hybrid type sensitive amplifier, including: transistor P1, transistor P2, transistor P3, transistor P4, transistor P5, transistor N1, transistor N2, transistor N3, transistor N4, transistor N5, transistor N6, switch SW1, switch SW2, switch SW3, switch SW4, switch SW5. Wherein, the source of transistor P1, P2, P3, P4 is connected to the power supply voltage VDD, the drain of transistor P2, P4 is connected to the gate of transistor P3. The drain of transistor P1, P3 is connected to the gate of transistor P2. The drain of transistor N1 is connected to the drain of transistor P2, and the gate of transistor N1 is connected to the gate of transistor P2. The transistor N2, P3 and the respective gate and drain are connected. The drain of transistor N3 is connected to the source of transistor N1, and the drain of transistor N4 is connected to the source of transistor N2. Switches SW1 and SW2 are connected to the gate of transistor N3. Switches SW3 and SW4 are connected to the gate of transistor N4, switch SW6 is connected to the source of transistor N3, and switch SW7 is connected to the source of transistor N4. The source of transistor N3 and N4 is connected to the drain of transistor N5 and N6 respectively, and the drain of transistor N5 and N6 is connected through switch SW5, and the source is connected to GND.

[0031] In the embodiment of the application, when the RRAM array performs matrix-vector multiplication calculation and reading operation, the current I SL flows into the hybrid analog-to-digital converter through the gating module. The hybrid analog-to-digital converter has three working stages. In the first stage, the hybrid sensitive amplifier works to generate 2-bit MSB. Switches SW1, SW3, SW6 and SW7 are closed, and points Q and QB will be charged to the VDD voltage. The RRAM array outputs current I SL . REF If I SL >I REF , then EN becomes high level, and the discharging speed of QB point is faster than that of Q point. Due to the positive feedback, the voltage of Q point will be pulled to VDD again after a short drop, and QB point is finally discharged to GND. The EN signal is switched twice to generate two-bit digital output MACV[4:3]. In the second stage, the current-to-voltage circuit starts to work, switches SW8 and SW9 are closed, and IMSB generator generates current I MSB according to the value of MACV[4:3]. After mirroring through transistors N7 and N8, current I MSB flowing through transistor P5 is generated. LSB =I SL -I MSB . Current I LSB charges the capacitor CLSB, and voltage V LSB is generated on the upper plate of the capacitor.In the third stage, the hybrid sensitive amplifier quantizes V LSB , and generates 3-bit LSB. Switches SW2, SW4 and SW5 are closed, and the current-to-voltage circuit generates V LSB , which is compared with V REF . If V LSB is greater than V REF , the current of transistor N3 is greater than that of N4, and the voltage at Q point will be higher than that at QB. Due to positive feedback, the voltage at QB point drops rapidly. When it drops to the threshold voltage of transistor P3, P3 is turned on, and VDD charges Q point through P3. When Q point is charged to VDD, Q point is pulled down to GND, realizing the function of latch amplification. The EN signal is switched for 3 times, realizing 3-bit digital output MACV[2:0]. Splicing MACV[2:0] and MACV[4:3] can obtain 5-bit quantization result of matrix-vector multiplication calculation result.

[0032] The RRAM memory-computing integrated chip of the hybrid analog-to-digital converter provided by the application can improve the overall computing power density of the chip and provide a solid guarantee for neural network calculation.

[0033] The embodiment of the application further provides an electronic device, which comprises a shell and the RRAM memory-computing integrated chip of the hybrid analog-to-digital converter.

[0034] The above description is only preferred embodiments of the application, and does not limit the application in any form. Although the implementation process of the application has been described in detail above, those skilled in the art can still modify the technical solutions recorded in the above examples, or replace some technical features with equivalent ones. Any modification, equivalent replacement, etc. within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A hybrid analog-to-digital converter RRAM computing-in-memory chip, characterized in that, include: RRAM array module for data storage and matrix-vector multiplication calculations; a gating module, configured to receive a digital control signal, gating specific cells of the RRAM array module, applying read and write voltages, and connecting to a hybrid analog-to-digital converter module; a hybrid analog-to-digital converter module, connected to the gating module, acquiring current from the RRAM array module through the gating module and outputting a digital signal result; The hybrid analog-to-digital converter module includes: a current-to-voltage circuit and a hybrid sensitive amplifier, and the hybrid sensitive amplifier includes: a transistor P1, a transistor P2, a transistor P3, a transistor P4, a transistor N1, a transistor N2, a transistor N3, a transistor N4, a transistor N5, a transistor N6, a switch SW1, a switch SW2, a switch SW3, a switch SW4, and a switch SW5; wherein the sources of the transistors P1, P2, P3, and P4 are connected to the power supply voltage VDD, the drains of the transistors P2 and P4 are connected to the gate of the transistor P3; the drains of the transistors P1 and P3 are connected to the gate of the transistor P2; the drain of the transistor N1 is connected to the gate of the transistor P3; The drain of transistor P2 is connected, the gate of transistor N1 is connected to the gate of transistor P2; transistors N2 and P3 are connected to their respective gates and drains; the drain of transistor N3 is connected to the source of transistor N1, and the drain of transistor N4 is connected to the source of transistor N2; switches SW1 and SW2 are connected to the gate of transistor N3; switches SW3 and SW4 are connected to the gate of transistor N4, switch SW6 is connected to the source of transistor N3, and switch SW7 is connected to the source of transistor N4; the sources of transistors N3 and N4 are connected to the drains of transistors N5 and N6 respectively, the drains of transistors N5 and N6 are connected through switch SW5, and the sources are connected to GND.

2. The RRAM computing-in-memory chip of claim 1, wherein, The RRAM array module consists of m×n 1T1R units, each of which consists of an NMOS transistor and an RRAM device. The state of each RRAM device is represented by two states: 1 / 0 according to the resistance value, and n columns of RRAM constitute an n-bit weight value. The drain of the NMOS transistor in each 1T1R unit is connected to the bottom electrode of the RRAM, the source of each column of transistors is connected to the source line SL, the gate of each row of transistors is connected to the word line WL, and the top electrode of each column of RRAM is connected to the bit line BL.

3. The RRAM computing-in-memory chip of claim 2, wherein, For the RRAM array module, the n-bit weight value is mapped to n columns of RRAM array, the input to be operated by matrix-vector multiplication is selected by word line WL, the weight to participate in the matrix-vector multiplication is selected by n columns of bit lines, n output current values are generated and output to the hybrid analog-digital converter, and the quantized digital result is output by the analog-digital converter; during the matrix-vector multiplication, the selected word line WL is connected to VWLREAD voltage through the selection module, and the unselected word line WL is connected to GND voltage through the selection module; the selected bit line is connected to VBLREAD voltage through the selection module, and the unselected bit line is connected to GND voltage through the selection module; the selected source line is connected to the hybrid analog-digital converter through the selection module, and the unselected source line is connected to GND voltage. 4.The hybrid RRAM-in-memory and computing-on-memory chip of claim 2, wherein, For the 1T1R cell with coordinates [m, n] in the RRAM array module, when the RESET operation is performed, the word line WL[m] is connected to VWLRESET voltage through the selection module, the bit line BL[n] is connected to GND voltage through the selection module, and the source line SL[n] is connected to VSLRESET voltage through the selection module, and the RRAM device will be written to state 0; when the SET operation is performed, the word line WL[m] is connected to VWLSET voltage through the selection module, the bit line BL[n] is connected to VBLSET voltage through the selection module, and the source line SL[n] is connected to GND voltage through the selection module, and the RRAM device will be written to state 1; when the READ operation is performed, the word line WL[m] is connected to VWLREAD voltage through the selection module, the bit line BL[n] is connected to VBLREAD voltage through the selection module, and the source line SL[n] is connected to the hybrid analog-digital converter through the selection module and outputs the quantized digital signal result.

5. The hybrid analog-to-digital converter RRAM in-memory computing chip of claim 1, wherein, The selection module comprises a selection unit and a level shift unit, the selection unit receives a digital control signal, selects a corresponding RRAM cell, and inputs the digital control signal to the RRAM array module after amplification by the level shift unit.

6. The RRAM computing-in-memory chip of the hybrid analog-to-digital converter of claim 1, wherein, The current-to-voltage circuit comprises transistors P5, P6, P7, N7, N8, a capacitor CLSB, an IMSB generator, switches SW8 and SW9; wherein the sources of the transistors P5, P6 and P7 are connected to a power supply voltage VDD, the gates of the transistors P5 and P6 are connected through the switch SW9, and the gate and the drain of the transistor P5 are connected; the drain of the transistor P6 is connected to the upper electrode of the capacitor CLSB, and the lower electrode of the capacitor CLSB is connected to GND; the gate of the transistor P7 is connected to the IMSB generator, the input signal MACV[4:3] of the IMSB generator comes from the hybrid sensitive amplifier; the drain of the transistor P7 is connected to the gate and the drain of the transistor N8, and the source of the transistor N8 is connected to GND; the gate of the transistor N7 is connected to the gate of the transistor N8, the source of the transistor N7 is grounded, and the drain is connected to the drain of the transistor P5 through the switch SW8.

7. An electronic device, comprising: The RRAM computing-in-memory chip comprising a shell and the hybrid analog-to-digital converter as claimed in any one of claims 1 to 6, wherein the RRAM computing-in-memory chip is arranged on the shell.

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