Layout method and device considering control signal cost
By introducing control signal cost function to optimize register layout, the detailed layout failure caused by inconsistency between registers and programmable logic block control signals in FPGA layout is solved, and the success rate and resource utilization rate of detailed layout are improved.
Patent Information
- Application Number
- CN202510590520.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-08-29
AI Technical Summary
During the FPGA layout process, the detailed layout failed due to the inconsistency between the control signals of the registers and the programmable logic blocks. The existing technology failed to effectively solve the legitimacy problem in the global layout, resulting in the detailed layout failed.
By introducing the control signal cost function, the register layout method is optimized, so that the registers are more inclined to be placed in programmable logic blocks with the same control signal. The cost function is used to calculate the evaluation value, including line length cost, timing cost, density cost and control signal cost, and optimize the location selection of the registers in programmable logic blocks.
Improve the passability of detailed layout, reduce the waste of register positions in programmable logic blocks, and increase the success rate of detailed layout.
Smart Images
Figure CN120562365A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a layout method and device that considers control signal costs. Background Art
[0002] FPGA layout typically occurs in two phases: global layout and detailed layout. Global layout determines the locations of all logic cells, but these locations may not be legal, and overlaps or other violations may occur. Subsequent detailed layout performs legalization and optimization based on the results of the global layout. Because global layout ignores some location legality issues, the results of the global layout may not ultimately support detailed layout. During detailed layout, sometimes registers (REGs) cannot be found in legal locations, leading to detailed layout failure. This is often caused by inconsistencies in control signals between registers and programmable logic blocks (PLBs). Summary of the Invention
[0003] The purpose of the present invention is to provide a layout method and device that considers the cost of control signals, so that registers are more likely to be placed in programmable logic blocks with the same control signals during layout, thereby improving the passability of detailed layout.
[0004] To achieve the above objectives, in a first aspect, the present invention provides a detailed layout method considering control signal costs, comprising:
[0005] Reading a layout file after global layout, obtaining first control signals of a plurality of registers, a first search range, and second control signals of a plurality of programmable logic blocks; the first control signals and the second control signals include an enable signal, a reset signal, and a clock signal; and the first search range is obtained according to a global algorithm;
[0006] Acquire multiple positions of registers in multiple programmable logic blocks within the first search range, evaluate each position using a cost function to obtain multiple evaluation values, the cost function including control signal costs based on the values of the first control signal and the second control signal; and layout the registers based on the multiple evaluation values.
[0007] Preferably, the first control signal is a group of control signals including an enable signal, a reset signal, and a clock signal, and the second control signal has at most two groups of control signals including an enable signal, a reset signal, and a clock signal; the cost function also includes line length cost, timing cost, and density cost.
[0008] Preferably, the calculation formula of the cost function is expressed as:
[0009] cost=α*wire_cost+β*timing_cost+γ*density_cost+ω*contral_cost
[0010] Among them, cost is the evaluation value, wire_cost is the wire length cost, timing_cost is the timing cost, density_cost is the density cost, control_cost is the control signal cost, α, β, γ, ω are parameters representing their corresponding costs;
[0011] The control signal cost is determined according to the first control signal and the second control signal.
[0012] Specifically, the control signal cost is determined according to the first control signal and the second control signal, including: if the second control signal at the current position includes a group of control signals identical to the first control signal, the control signal cost is 1, otherwise it is 0.
[0013] Specifically, the layout of registers according to the evaluation values includes: comparing multiple evaluation values and selecting a position corresponding to a high evaluation value as a layout position.
[0014] Preferably, the first search range is adjusted according to actual conditions.
[0015] In a second aspect, the present invention provides a layout device that considers control signal costs, comprising:
[0016] an acquisition unit configured to read a layout file after global layout, and acquire first control signals of a plurality of registers, a first search range, and second control signals of a plurality of programmable logic blocks; the first control signals and the second control signals include an enable signal, a reset signal, and a clock signal; and the first search range is obtained according to a global algorithm;
[0017] The layout unit is configured to obtain multiple positions of registers in multiple programmable logic blocks within the first search range, evaluate each position using a cost function to obtain an evaluation value, wherein the cost function includes a control signal cost based on the values of the first control signal and the second control signal; and layout the registers based on the evaluation value.
[0018] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method described in the first aspect.
[0019] In a fourth aspect, the present invention provides a computing device comprising a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the method described in the first aspect is implemented. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A schematic diagram of a partial connection of a programmable logic block provided by an embodiment of the present invention;
[0021] Figure 2 A flow chart of a layout method considering control signal costs provided by an embodiment of the present invention;
[0022] Figure 3 A schematic diagram of a chip provided by an embodiment of the present invention;
[0023] Figure 4 A schematic diagram of an internal unit of a programmable logic block provided by an embodiment of the present invention;
[0024] Figure 5 A schematic diagram of the REG1 layout provided in an embodiment of the present invention;
[0025] Figure 6A A schematic diagram of the first search range of a register provided by the present invention;
[0026] Figure 6B A schematic diagram of an expanded first search range of a register provided by the present invention;
[0027] Figure 7 A structural diagram of a layout device that takes control signal costs into consideration, provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0028] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.
[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0030] In the description of the embodiments of the present invention, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present invention should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.
[0031] Detailed layout, the refinement phase following global layout, is responsible for further refining the locations of logic modules assigned by global layout and determining the specific coordinates of logic units (such as registers) within programmable logic blocks (PLBs). Its core goal is to resolve timing, congestion, and power consumption issues left over from global layout through local optimization, ensuring that the design meets final performance requirements.
[0032] Figure 1 A partial wiring diagram of a programmable logic block provided in an embodiment of the present invention is shown in the figure. Q0 to Q15 are registers (REG for short). REG has a total of five signals, including one data input, one data output, and the remaining three control signals, namely en (enable signal), sr (set / reset signal), and clk (clock signal). The three signals are collectively referred to as a group of control signals. The registers are connected to the control signal LBUF unit. There are only two LBUF units, LBUF1 and LBUF0, in the PLB. The control signals of LBUF1 and LBUF0 can be the same or different. The register selects one of LBUF1 and LBUF0 as the control signal. This structure also means that at most two groups of registers with different control signals are allowed to be placed in a PLB. When there are two groups of registers with different control signals in the PLB, even if there are vacancies, the registers with the third control signal cannot be arranged in this PLB. This will create a situation where, if there are many control signals, if registers with the same control signal are arranged in different PLBs, the REG controlled by a certain group of control signals will occupy multiple PLBs, reducing the actual available layout positions, and ultimately leading to layout failure.
[0033] To overcome the shortcomings of the existing technology and based on the above, a layout method and device that considers control signal costs are proposed. By incorporating control signal costs into the layout of registers, the present invention allows for more registers (REGs) with the same control signals to be placed in the same programmable logic block (PLB), thereby reducing the waste of REG space within the PLB. This increases the likelihood of successful layout for projects with numerous control signals.
[0034] Figure 2 Flowchart of a layout method considering control signal cost provided by an embodiment of the present invention. Figure 2 As shown, the method mainly includes the following steps:
[0035] Step S201: Read the layout file after global layout, obtain first control signals of multiple registers, a first search range, and second control signals of multiple programmable logic blocks; the first control signal and the second control signal are composed of an enable signal, a reset signal, and a clock signal, and the first search range is obtained according to a global algorithm.
[0036] Exemplarily, after completing the global layout of the FPGA, the layout file after the global layout is read to obtain the first control signals of multiple registers, the first search range, and the second control signals of multiple programmable logic blocks; the first control signal and the second control signal are composed of an enable signal, a reset signal, and a clock signal, and the first search range is obtained according to the global algorithm.
[0037] For example, in global layout, the netlist and constraint files (such as timing and physical constraints) are first parsed to divide the logic modules into hierarchies and determine the connectivity between modules. Logic cells are then assigned a primary position using either random or heuristic methods. Algorithms are used to adjust the positions of logic cells, gradually optimizing objective functions (such as timing, congestion, and power consumption). Finally, approximate register locations are generated. Figure 3 A chip schematic diagram provided for an embodiment of the present invention, as shown in the figure, includes multiple programmable logic blocks (PLB) units and other non-PLB heterogeneous units. When the registers are laid out in detail, there will be a first search range in the chip, and this first search range is given by a global algorithm. Figure 4 A schematic diagram of an internal unit of a programmable logic block provided by an embodiment of the present invention is shown as follows: Figure 4 As shown in the figure, there are 8 LUTs (lookup tables), 8 ADDs (adders) and 16 REGs (registers) in a PLB (programmable logic block). The registers are eventually laid out in the PLB unit. Figure 1 The schematic diagram of the connection of the programmable logic block is shown as follows: Figure 4 Detailed diagram.
[0038] Step S202: Acquire multiple positions of registers in multiple programmable logic blocks within the first search range, evaluate each position using a cost function to obtain multiple evaluation values, wherein the cost function includes a control signal cost based on the values of the first control signal and the second control signal; and layout the registers based on the multiple evaluation values.
[0039] In one embodiment, the first control signal is a group of control signals including an enable signal, a reset signal, and a clock signal, and the second control signal is at most two groups of control signals including an enable signal, a reset signal, and a clock signal. The cost function also includes line length cost, timing cost, and density cost. The calculation formula of the cost function is expressed as:
[0040] cost=α*wire_cost+β*timing_cost+γ*density_cost+ω*contral_cost
[0041] Among them, cost is the evaluation value, wire_cost is the wire length cost, timing_cost is the timing cost, density_cost is the density cost, control_cost is the control signal cost, α, β, γ, ω are parameters representing their corresponding costs;
[0042] In one embodiment, the control signal cost is determined based on the first control signal and the second control signal. Specifically, if the second control signal at the current position contains the same set of control signals as the first control signal, the control signal cost is 1, otherwise it is 0.
[0043] For example, there are a certain number of REGs that need to find legal positions. Suppose there are three REGs whose layout order is REG1, REG3, and REG4, and their control signals are different. Currently, the position of REG1 is being searched. In a certain area, the final result of whether REG1 can be placed in the first search range is Figure 5 , Figure 5 A schematic diagram of the REG1 layout provided in an embodiment of the present invention is shown in the figure. The first search range is a rectangle with a side length of 4, which contains a total of 16 PLBs. Gray indicates that there is no legal position for REG1 in this PLB, white and black indicate that there is a legal position in this area, and black indicates that the same control signal as RE1G at this time exists in this area. For ease of explanation, all feasible PLBs are numbered; the original cost function is:
[0044] cost=α*wire_cost+β*timing_cost+γ*density_cost
[0045] Here, cost is the evaluation value, wire_cost is the wire length cost, timing_cost is the timing cost, and density_cost is the density cost. α, β, and γ are parameters representing their respective costs. Under its control, REG1 selects a location within PLBs 1-9. PLBs 1, 3, and 7, which share the same control signal, are not prioritized, so they may be placed in a PLB other than those. Assume that after the comparison control function, REG1 is ultimately placed in PLB 4. Subsequently, for other idle REG positions in PLB4, there are two situations. One is that there were other REGs in PLB4 before, and their control signals are inconsistent with REG1. For the subsequently laid out REG, assuming it is REG3, only if the control signal of REG3 is the same as that of REG1 or other REG control signals in PLB4, REG3 can be placed in PLB4. Otherwise, even if there is an idle position in PLB4, REG3 cannot be placed. The second is that there is no REG in PLB4 when REG1 is laid out. After REG1 is placed in PLB4, if REG3 with a control signal different from REG1 is also in PLB4, then the idle position in PLB4 can no longer be used to place REG4 with a control signal different from REG1 and REG3.
[0046] The cost function with the control signal cost added is:
[0047] cost=α*wire_cost+β*timing_cost+γ*density_cost+ω*contral_cost
[0048] Where cost is the evaluation value, wire_cost is the wire length cost, timing_cost is the timing cost, density_cost is the density cost, and control_cost is the control signal cost. α, β, γ, and ω are parameters representing their respective costs. control_cost is a Boolean variable. If the PLB at the current location has the same control signal as the REG to be placed, control_cost is 1; otherwise, control_cost is 0. When control signal costs are factored in, REG1 is more likely to be placed in PLBs 1, 3, and 7. Assuming REG1 is placed in PLB3 instead of PLB4, for PLB4, if REG3 is placed in PLB4, PLB4 can either accommodate a REG with the same control signal as REG3 or REG4, which has different control signals from both REG1 and REG3. Placing REG1 in PLB4 will be much less likely, and any subsequent placement will not be worse than the previous cost function choice. Therefore, when more identical control signals are placed in the same PLB, the resource utilization of the REG positions in the PLB will be higher.
[0049] In different embodiments, the first search range may be different. In a specific embodiment, the first search range may be adjusted according to actual conditions.
[0050] For example, during the detailed layout process, the initial search range of each REG is limited. For some projects with too many control signals and high resource utilization, sometimes REGs with the same signal cannot be placed in the same PLB. Figure 6A The first search range diagram of the registers provided by the present invention shows that the overlap between registers REG1, REG2, and REG3 is minimal, and REG2 and REG3 do not share the same area. If the control signals of these three registers are the same, then at best, two PLBs will be occupied. To improve the layout pass rate, the first search range can be expanded so that more REGs with the same control signals are placed in the same PLB, thereby improving the pass rate of detailed layout. Figure 6B This is a schematic diagram of the first search range of the register provided by the present invention after expansion. At this time, the registers REG1, REG2, and REG3 have more overlapping parts and have the same area. In the best case, only one PLB is occupied. Figure 6A There will be more cases of successful layout.
[0051] Based on the method in the above embodiment, the present invention further provides a layout device that takes control signal costs into consideration. Figure 7 A structural diagram of a layout device with a control signal cost provided by an embodiment of the present invention is shown as follows: Figure 7 As shown, the apparatus 700 includes:
[0052] An acquisition unit 701 is configured to read a layout file after global layout, and acquire first control signals of a plurality of registers, a first search range, and second control signals of a plurality of programmable logic blocks; the first control signals and the second control signals are composed of an enable signal, a reset signal, and a clock signal; and the first search range is obtained according to a global algorithm;
[0053] The layout unit 702 is configured to obtain multiple positions of registers in multiple programmable logic blocks within the first search range, evaluate each position using a cost function to obtain an evaluation value, wherein the cost function includes a control signal cost based on the values of the first control signal and the second control signal; and layout the registers based on the evaluation value.
[0054] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0055] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A layout method considering control signal costs, comprising: Reading a layout file after global layout, obtaining first control signals of a plurality of registers, a first search range, and second control signals of a plurality of programmable logic blocks; The first control signal and the second control signal include: an enable signal, a reset signal, and a clock signal, and the first search range is obtained according to a global algorithm; Acquire multiple positions of registers in multiple programmable logic blocks within the first search range, evaluate each position using a cost function to obtain multiple evaluation values, the cost function including control signal costs based on the values of the first control signal and the second control signal; and layout the registers based on the multiple evaluation values.
2. The method according to claim 1, wherein The first control signal is a group of control signals including an enable signal, a reset signal, and a clock signal, and the second control signal has at most two groups of control signals including an enable signal, a reset signal, and a clock signal; the cost function also includes line length cost, timing cost, and density cost.
3. The method according to claim 2, wherein: The calculation formula of the cost function is expressed as: cost=α*wire_cost+β*timing_cost+γ*density_cost+ω*contral_cost Among them, cost is the evaluation value, wire_cost is the wire length cost, timing_cost is the timing cost, density_cost is the density cost, control_cost is the control signal cost, α, β, γ, ω are parameters representing their corresponding costs; The control signal cost is determined according to the first control signal and the second control signal.
4. The method according to claim 3, wherein: The control signal cost is determined based on the first control signal and the second control signal, including: if the second control signal at the current position includes a group of control signals identical to the first control signal, the control signal cost is 1, otherwise it is 0.
5. The method according to claim 1, wherein The layout of registers according to the evaluation values includes: comparing multiple evaluation values and selecting positions corresponding to high evaluation values as layout positions.
6. The method according to claim 1, wherein The first search range is adjusted according to actual conditions.
7. A layout method considering control signal costs, comprising: an acquisition unit configured to read a layout file after global layout, and acquire first control signals of a plurality of registers, a first search range, and second control signals of a plurality of programmable logic blocks; The first control signal and the second control signal include: an enable signal, a reset signal, and a clock signal, and the first search range is obtained according to a global algorithm; The layout unit is configured to obtain multiple positions of registers in multiple programmable logic blocks within the first search range, evaluate each position using a cost function to obtain an evaluation value, wherein the cost function includes a control signal cost based on the values of the first control signal and the second control signal; and layout the registers based on the evaluation value.
8. An electronic device comprising: A processor, a memory, and computer program instructions stored in the memory and executable on the processor, wherein the processor is configured to implement the method according to any one of claims 1 to 6 when executing the computer program instructions.
9. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.