Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps. A plurality of passive elements are formed in a substrate, wherein the plurality of passive elements are arranged in an array in the substrate. A plurality of contacts are formed on the plurality of passive elements, the plurality of contacts and the plurality of passive elements corresponding to each other. A redistribution layer is formed over the substrate, wherein the redistribution layer is electrically connected to a portion of the plurality of passive elements through a portion of the plurality of contacts.

Description

Technical Field

[0001] The present invention relates to a structure and a manufacturing method thereof, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the advancement of technology and market demand, more and more components (such as memory, logic chips, etc.) need to be packaged together to achieve the needs of high-performance computing. When making large-sized grains, the single exposure area of ​​a general photomask may not be sufficient to produce large-sized grains, and multiple photolithography processes need to be performed through splicing to produce large-sized grains. For interposers, as the size increases, the number of photomasks required for each layer such as redistribution layers, through-holes, and passive components also increases. In addition, for different products, the photomasks for each layer are also different, which increases manufacturing costs. Summary of the Invention

[0003] The present invention provides a semiconductor structure and a manufacturing method thereof, which can reduce manufacturing costs.

[0004] The method for manufacturing a semiconductor structure of the present invention includes the following steps: forming a plurality of passive components in a substrate, wherein the plurality of passive components are arranged in an array in the substrate; forming a plurality of contacts on the plurality of passive components, wherein the plurality of contacts correspond to the plurality of passive components; and forming a redistribution wiring layer on the substrate, wherein the redistribution wiring layer is electrically connected to a portion of the plurality of passive components via a portion of the plurality of contacts.

[0005] In one embodiment of the present invention, forming a plurality of passive components in the substrate includes exposing different regions of the substrate separately through a passive component photomask.

[0006] In one embodiment of the present invention, forming a plurality of contacts on the plurality of passive components includes exposing different regions of the substrate through a contact photomask.

[0007] In one embodiment of the present invention, the above-mentioned formation of the redistribution wiring layer on the substrate includes making the first photomask correspond to the first sub-area, and forming the first feature of the redistribution wiring layer in the first sub-area of ​​the substrate through the first photomask; and making the second photomask correspond to the second sub-area, and forming the second feature of the redistribution wiring layer in the second sub-area of ​​the substrate through the second photomask, wherein the pattern of the first photomask is different from the pattern of the second photomask.

[0008] In one embodiment of the present invention, the first feature and the second feature are connected transversely.

[0009] In one embodiment of the present invention, the substrate includes a plurality of crystal grain regions, and an area of ​​each of the plurality of crystal grain regions is larger than a single maximum exposure area of ​​the first photomask.

[0010] In one embodiment of the present invention, the size of the passive device photomask is smaller than the size of the first photomask.

[0011] In one embodiment of the present invention, some of the plurality of passive components are dummy passive components.

[0012] In one embodiment of the present invention, the manufacturing method further includes forming a through-substrate via in the substrate.

[0013] The semiconductor structure of the present invention includes a plurality of passive components, a plurality of contacts, and a redistribution wiring layer. The plurality of passive components are arrayed in a substrate. The plurality of contacts are correspondingly disposed on the plurality of passive components and in direct contact with the plurality of passive components, wherein the plurality of contacts include a first contact and a second contact. The redistribution wiring layer is disposed on the substrate, wherein the redistribution wiring layer is electrically connected to the corresponding passive components via the first contact, and the second contact is not electrically connected to the redistribution wiring layer.

[0014] In one embodiment of the present invention, the semiconductor structure further includes a dielectric layer disposed on the substrate and laterally surrounding the plurality of contacts and the redistribution wiring layer, wherein a top surface of the second contact is encapsulated by the dielectric layer.

[0015] In one embodiment of the present invention, the semiconductor structure further includes a through-substrate via (TSV) disposed in the substrate, wherein top surfaces of the plurality of contacts are flush with a top surface of the TSV.

[0016] Based on the above, the present invention utilizes the same photomask to form multiple arrays of passive components within a substrate, and utilizes the wiring design of the redistribution layer to select the desired passive components for electrical connection. This reduces the burden of passive component layout design within the substrate and increases customization flexibility. Furthermore, the need for photomasks to manufacture passive components can be reduced, thereby lowering manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figures 10 to 12is a schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present invention;

[0018] Figure 13 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0019] Explanation of symbols

[0020] 10,20:Semiconductor structure

[0021] 100: Grain area

[0022] 102: Base

[0023] 110: Passive components

[0024] 120: dielectric layer

[0025] 122: first dielectric layer

[0026] 124: second dielectric layer

[0027] 130: Contact

[0028] 132: first contact

[0029] 134: Second contact

[0030] 140:Through substrate through hole

[0031] 150,152,154,156,158: Rerouting layer

[0032] 154a: First feature

[0033] 154b: Second feature

[0034] 154v, 156v, 158v: through hole

[0035] 162,164,166: Chip

[0036] 202: first photoresist layer

[0037] 204: second photoresist layer

[0038] 206: third photoresist layer

[0039] 208: fourth photoresist layer

[0040] 202', 204', 208': Exposure area

[0041] M1: Passive component photomask

[0042] M2: Contact photomask

[0043] M3: Through-substrate via photomask

[0044] M4a: First photomask

[0045] M4b: Second photomask

[0046] M4c: Third photomask

[0047] M4d: fourth photomask

[0048] R11, R21: first sub-area

[0049] R12, R22: Second sub-area

[0050] R13, R23: The third sub-area

[0051] R24: The fourth sub-area

[0052] p1: pattern

[0053] s1,s3: blank pattern

[0054] s2: area DETAILED DESCRIPTION

[0055] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. Identical or similar reference numerals denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0056] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

[0057] In addition, directional terms mentioned herein, such as “upper” and “lower”, are only used to refer to the directions of the drawings and are not intended to limit the present invention.

[0058] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A、 Figure 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figures 10 to 12 FIG. 4 is a schematic diagram of a manufacturing process of a semiconductor structure according to an embodiment of the present invention. Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10 It is a schematic diagram viewed from above. Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 11 and Figure 12 It is a partial cross-sectional schematic diagram. Figure 1B yes Figure 1A Schematic diagram of a partial cross-section. Figure 1C FIG. 4 is a top view schematic diagram of the passive component photomask M1. Figure 2B yes Figure 2A Schematic diagram of a partial cross-section. Figure 3B yes Figure 3A Schematic diagram of a partial cross-section. Figure 4B yes Figure 4A Schematic diagram of a partial cross-section. Figure 5B yes Figure 5A A partial cross-sectional diagram of . Figure 7B yes Figure 7A A partial cross-sectional diagram of . Figure 8B yes Figure 8A Schematic diagram of a partial cross-section. Figure 9B yes Figure 9A For the sake of clarity, Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10 Some components (such as photoresist layer, contact, dielectric layer, redistribution wiring layer, etc.) are omitted in the figure, and the omitted parts can be understood by referring to their corresponding cross-sectional views.

[0059] Please refer to Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B , a plurality of passive devices 110 are formed in a substrate 102, wherein the plurality of passive devices 110 are arranged in an array in the substrate 102. Specifically, first, a substrate 102 is provided. The substrate 102 includes a semiconductor substrate (e.g., silicon, silicon germanium, or other suitable semiconductor materials), a silicon-on-insulator (SOI) substrate, or a combination thereof. In some embodiments, a hard mask layer (not shown) may be formed on the substrate 102, but the present invention is not limited thereto. In some embodiments, the substrate 102 may be divided into a plurality of die regions 100, so that the substrate 102 can be cut into a plurality of dies according to the die regions 100 in subsequent fabrication processes. In some embodiments, the area of ​​a single die region 100 is larger than the maximum single exposure area of ​​a typical photomask, for example, larger than 26 mm x 33 mm. In some embodiments, the area of ​​a single die region 100 is approximately four times the maximum single exposure area of ​​a typical photomask. Here, the maximum single exposure area refers to the maximum range that can be exposed by the photomask in a single exposure, regardless of the pattern on the photomask.

[0060] Then, using a patchwork lithography process, different areas of the substrate 102 are exposed through the passive device photomask M1 to define the locations where the passive devices will be subsequently formed. The pattern layout of the multiple passive devices 110 is essentially an array arrangement, with the exception of areas where the passive device pattern overlaps with the predetermined through-substrate vias.

[0061] For example, if Figure 1A and Figure 1B As shown, a first photoresist layer 202 is formed on the substrate 102. Using the passive device photomask M1 as a mask, the passive device photomask M1 is first aligned with the first sub-region R11 to expose the first photoresist layer 202 in the first sub-region R11, thereby forming an exposed region 202' in the first photoresist layer 202 in the first sub-region R11. Then, as shown in FIG. Figure 2A and Figure 2B As shown, the passive device photomask M1 is aligned with the second sub-region R12 to expose the first photoresist layer 202 in the second sub-region R12, thereby forming an exposed region 202' in the first photoresist layer 202 in the second sub-region R12. The above steps are repeated so that each sub-region of the die region 100 is exposed through the passive device photomask M1, thereby transferring the pattern of the passive device photomask M1 to different locations in the die region 100. In other words, each sub-region of the die region 100 has the same pattern after being exposed through the passive device photomask M1.

[0062] It should be noted that Figure 1A For the sake of convenience, the single die area 100 is divided into 9 sub-areas (including the first sub-area R11, the second sub-area R12, the third sub-area R13 and other unnumbered sub-areas) by dotted lines, and the range of each sub-area corresponds to the single maximum exposure range of the passive device photomask M1. That is, Figure 1A In the embodiment, the single maximum exposure area of ​​the passive component photomask M1 is 1 / 9 of the die area 100. In other words, the area of ​​a single die area 100 is approximately 9 times the single maximum exposure area of ​​the passive component photomask M1. However, the single maximum exposure area of ​​the passive component photomask M1 (i.e., the size of the passive component photomask M1) can be adjusted according to actual needs, and the present invention is not limited thereto. As the single maximum exposure range of the passive component photomask M1 changes, the number of sub-areas of a single die area 100 will also vary depending on the single maximum exposure range of the passive component photomask M1. In some embodiments, the entire substrate 102, i.e., including the die area 100 and the area outside the die area 100, is exposed through the passive component photomask M1, so that the passive components formed subsequently can roughly cover the entire substrate 102.

[0063] In some embodiments, as Figure 1C As shown, the patterns p1 of the passive device mask M1 can be arranged in an array in the passive device mask M1. The passive device mask M1 may have some spaces without patterns (such as blank patterns s1) to reserve some space for subsequent through-substrate vias in the substrate 102. Figure 1C The pattern p1 and the blank pattern s1 of the passive device photomask M1 are only schematically illustrated, which is not intended to limit the present invention. The arrangement and coverage of the pattern p1 and the blank pattern s1 of the passive device photomask M1 can be adjusted according to actual needs.

[0064] Because the area of ​​a single die region 100 is larger than the maximum exposure area achievable by a single exposure of a typical photomask, and each of the passive components 110 has the same pattern, the pattern layout of multiple passive components 110 can be obtained by splicing together the same photomask without using different photomasks. Different sub-regions of the die region 100 are exposed using the same photomask to transfer the pattern layout of the multiple passive components 110 to the die region 100. This reduces the number of photomasks required for the passive components 110, thereby lowering manufacturing costs and reducing the number of photomask quality tests.

[0065] In some embodiments, the size of the passive device photomask M1 may be smaller than or equal to the size of a general photomask, for example, may be 0.1 to 1 times the size of a general photomask.

[0066] Please refer to Figure 3A and Figure 3B , after exposing different areas of the substrate 102 respectively through the passive component photomask M1, the first photoresist layer 202 is developed (for example, the display area 202' of the first photoresist layer 202 is removed) to obtain a patterned first photoresist layer (not shown). The passive component 110 can then be formed in the substrate 102 by any known method. For example, taking the passive component 110 as a capacitor, the patterned first photoresist layer can be used as a mask to etch the substrate 102 to form a groove (not shown), remove the patterned first photoresist layer, and then form a conductive layer, an insulating layer, and a conductive layer (not shown) in sequence in the groove to form a capacitor embedded in the substrate 102. However, the present invention is not limited to this, and other methods for forming capacitors are also applicable to this embodiment. In addition, the passive component 110 can be other passive components, such as resistors, inductors, etc., and the present invention is not limited to this.

[0067] Due to space constraints, Figure 3A Schematically, eight passive components 110 are shown in each sub-region of the die region 100. However, it should be understood that each sub-region of the die region 100 should be as follows. Figure 3A As shown in the partial enlarged view, the passive element 110 has a position corresponding to the pattern of the passive element photomask M1. It can be seen that the number of passive elements 110 in a single sub-area can adjust the pattern layout of the passive element photomask M1 according to actual needs. In addition, since the passive element photomask M1 has a blank pattern s1, each sub-area of ​​the die area 100 also has an area s2 corresponding to the blank pattern s1. This area s2 can be used as a space for the subsequent through-substrate via setting. In addition, the Figure 4A 、 Figure 5A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10 Also due to space constraints Figure 3A The number of components shown in each sub-area is generally simplified.

[0068] Please refer to Figure 4A and Figure 4B 、 Figure 5A 、 Figure 5B and Figure 6, a plurality of contacts 130 are formed on the plurality of passive components 110, and the plurality of contacts 130 correspond to each other. For example, a patchwork photolithography process can be used through the contact photomask M2 to expose different areas of the substrate 102 to define the locations where the contacts 130 will be subsequently formed. The pattern layout of the plurality of contacts 130 is basically arranged in the same manner as the passive components 110, except that the contact pattern is not arranged at the locations overlapping with the predetermined through-substrate vias. The contact pattern is arranged in all other areas corresponding to the passive components 110.

[0069] Specifically, if Figure 4A and Figure 4B As shown, a first dielectric layer 122 is formed on the substrate 102, and then a second photoresist layer 204 is formed on the first dielectric layer 122. Then, using the contact photomask M2 as a mask, the contact photomask M2 is first aligned with the first sub-region R11 to expose the second photoresist layer 204 in the first sub-region R11, thereby forming an exposed region 204' in the second photoresist layer 202 in the first sub-region R11. Then, as shown in FIG. Figure 5A and Figure 5B As shown, the contact photomask M2 is aligned with the second sub-region R12 to expose the second photoresist layer 204 in the second sub-region R12, thereby forming an exposed region 204' in the second photoresist layer 204 in the second sub-region R12. The above steps are repeated to expose each sub-region of the die region 100 through the contact photomask M2, thereby transferring the pattern of the contact photomask M2 to different locations in the die region 100. In some embodiments, the maximum single exposure area of ​​the contact photomask M2 is substantially the same as the maximum single exposure area of ​​the passive device photomask M1. Therefore, the size of the contact photomask M2 is substantially the same as that of the passive device photomask M1.

[0070] In some embodiments, the pattern of the contact photomask M2 may correspond to the pattern of the passive device photomask M1, so that the subsequently formed contacts are connected to the passive device 110. The contact photomask M2 may have a portion of space without a pattern (e.g., blank pattern s3). The blank pattern s3 substantially corresponds to the blank pattern s1 of the passive device photomask M1 or the region s2 of the die region 100, thereby reserving a portion of space in the substrate 102 for subsequent through-substrate vias.

[0071] The pattern layout of the multiple contacts 130 can be obtained by splicing different sub-regions of the die region 100 using the same photomask, so that the different sub-regions of the die region 100 can be exposed using the same photomask to transfer the pattern layout of the multiple contacts 130 to the die region 100. In this way, the number of photomasks required for the contacts 130 can be reduced, thereby lowering manufacturing costs and reducing the number of photomask quality tests.

[0072] Please refer to Figure 6 After exposing different areas of the substrate 102 through the contact photomask M2, the second photoresist layer 204 is developed (e.g., the display area 204' of the second photoresist layer 204 is removed) to obtain a patterned second photoresist layer (not shown). The patterned second photoresist layer can then be used as a mask to etch the first dielectric layer 122 to form openings (not shown). The patterned second photoresist layer is removed, and the openings are then filled with a conductive material to form contacts 130. The contacts 130 are electrically connected to the corresponding passive components 110. Figure 6 The schematic diagram shows a contact 130 connected to a passive component 110, but this is not intended to limit the present invention. The number of contacts 130 can be adjusted based on actual needs. Furthermore, because the contact mask M2 includes a blank pattern s3, each sub-region of the die region 100 also has an area corresponding to the blank pattern s3. In other words, each sub-region of the die region 100 has reserved space for subsequent through-substrate vias.

[0073] In some embodiments, a corresponding contact 130 is formed on each of the plurality of passive components 110 , so that subsequent wiring design can freely select the required passive components 110 and electrically connect them through the corresponding contact 130 .

[0074] Please refer to Figure 7A and Figure 7B , forming a through-substrate via 140 in the substrate 102. For example, the second sub-region R12 and the third sub-region R13 of the die region 100 may include a through-substrate via 140. Specifically, a third photoresist layer 206 may be formed on the first dielectric layer 122. Then, using a through-substrate via photomask M3 as a mask, the through-substrate via photomask M3 is aligned with a portion of the second sub-region R12 and the third sub-region R13 to expose and develop the third photoresist layer 206 located in a portion of the second sub-region R12 and the third sub-region R13 to form a patterned third photoresist layer 206. Thereafter, using the patterned third photoresist layer 206 as a mask, the first dielectric layer 122 and the substrate 102 are etched to form an opening (not shown), and then a conductive material is filled in the opening to form the through-substrate via 140. In some embodiments, the patterned third photoresist layer 206 is removed before the conductive material is filled into the opening. Since each sub-region of the die region 100 has a reserved space, the through-substrate vias 140 can be set in these spaces according to actual needs. It should be understood that the through-substrate vias 140 can be selectively formed in part of the reserved space instead of all of it. In other words, some of the reserved spaces may not be provided with the through-substrate vias 140, such as Figure 7AIn addition, the number and arrangement of the through-substrate vias 140 formed in the reserved space of each sub-region can be adjusted according to actual needs, and the present invention is not limited thereto.

[0075] In some embodiments, the dimensions of the TSV photomask M3 may be larger than the dimensions of the contact photomask M2 and the dimensions of the passive device photomask M1, but the present invention is not limited thereto. In other embodiments, the dimensions of the TSV photomask M3 may be equal to the dimensions of the contact photomask M2 and the dimensions of the passive device photomask M1. In some embodiments, the dimensions of the TSV photomask M3 may be the same as those of a typical photomask. In some embodiments, the area of ​​a single die region 100 is approximately four times the maximum single exposure area of ​​the TSV photomask M3.

[0076] Figure 7A Schematically illustrating the formation of a TSV 140 in portions of the second sub-region R12 and the third sub-region R13 using a TSV photomask M3. However, it should be understood that when the maximum exposure area of ​​a single TSV photomask M3 is insufficient to cover the pattern layout of the TSV 140, multiple TSV photomasks, each with a different pattern, must be stitched together to complete the TSV pattern layout. In this embodiment, a single die region 100 requires a maximum of four different TSV photomasks stitched together to complete the TSV pattern layout.

[0077] Please refer to Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10 and Figure 11 A redistribution layer 152 is formed on the substrate 102, wherein the redistribution layer 152 is electrically connected to a portion of the passive components 110 through a portion of the contacts 130. Because the area of ​​a single die region 100 is larger than the maximum exposure area of ​​a typical photomask, the pattern layout of the redistribution layer 152 must be transferred to the die region 100 through multiple exposures using different redistribution photomasks.

[0078] Specifically, if Figure 8A and Figure 8B As shown, a second dielectric layer 124 is formed on the first dielectric layer 122, and then a fourth photoresist layer 208 is formed on the second dielectric layer 124. Afterwards, the first photomask M4a is used as a mask, and the first photomask M4a is first aligned with the first sub-region R21 to expose the fourth photoresist layer 208 in the first sub-region R21, thereby forming an exposed region 208' in the fourth photoresist layer 208 in the first sub-region R21. Then, as shown in FIG. Figure 9A and Figure 9BAs shown, the second photomask M4b is aligned with the second sub-region R22 to expose the fourth photoresist layer 208 in the second sub-region R22, thereby forming an exposure region 208' in the fourth photoresist layer 208 in the second sub-region R22. Figure 10 As shown, the third sub-region R23 and the fourth sub-region R24 are exposed using the third photomask M4c and the fourth photomask M4d respectively. Figure 11 The fourth photoresist layer 208 is developed (e.g., the exposed areas 208' of the fourth photoresist layer 208 are removed) to form a patterned fourth photoresist layer (not shown). The patterned fourth photoresist layer is used as a mask to etch the second dielectric layer 124 to form an opening (not shown). The patterned fourth photoresist layer is removed, and then a conductive material is filled into the opening to form the redistribution wiring layer 152.

[0079] The first photomask M4a, the second photomask M4b, the third photomask M4c and the fourth photomask M4d are different photomasks of the same size, each having a different pattern. The patterns of the first photomask M4a, the second photomask M4b, the third photomask M4c and the fourth photomask M4d are combined to form the pattern layout of the redistribution circuit layer 152. In this way, the redistribution circuit layer 152 can be formed with a length or area that is larger than the feature size that can be produced by the single maximum exposure range of a general photomask.

[0080] It should be noted that Figure 8A 、 Figure 9A and Figure 10 For the sake of convenience, the single die region 100 is divided into four sub-regions (including the first sub-region R21, the second sub-region R22, the third sub-region R23 and the fourth sub-region R24) by dotted lines, and the range of each sub-region corresponds to the single maximum exposure range of the first photomask M4a (or the second photomask M4b or the third photomask M4c or the fourth photomask M4d). That is, Figure 8A In the example, the maximum single exposure area of ​​the first photomask M4a is 1 / 4 of the die region 100. In other words, the area of ​​a single die region 100 is approximately four times the maximum exposure area of ​​the first photomask M4a. However, the maximum single exposure range of the first photomask M4a (i.e., the size of the first photomask M4a) can be adjusted based on actual needs, and the present invention is not limited thereto. As the maximum single exposure range of the first photomask M4a changes, the number of sub-regions in a single die region 100 will also vary depending on the maximum single exposure range of the first photomask M4a.

[0081] In some embodiments, the size of the passive component photomask M1 is smaller than the size of the first photomask M4a, the size of the second photomask M4b, the size of the third photomask M4c, and the size of the fourth photomask M4d. For example, the size of the passive component photomask M1 may be between 0.1 and 1 times the size of the first photomask M4a. In other embodiments, the size of the passive component photomask M1 is equal to the size of the first photomask M4a, the size of the second photomask M4b, the size of the third photomask M4c, and the size of the fourth photomask M4d.

[0082] In some embodiments, portions of the redistribution layer 152 are electrically connected to portions of the passive components 110 via portions of the contacts 130. Because the substrate 102 includes multiple passive components 110 and corresponding contacts 130, the redistribution layer 152 can be electrically connected to selected passive components 110 based on their wiring requirements, facilitating customized design. Furthermore, this reduces the need to redesign the layout and quality test the passive components 110 and contacts 130 each time a new product is developed.

[0083] In some embodiments, the passive components 110 and the corresponding contacts 130 that are not electrically connected to the redistribution wiring layer 152 are dummy components.

[0084] Please refer to Figure 12 , redistribution wiring layers 154, 156, and 158 are formed on the redistribution wiring layer 152. For example, a dielectric layer (not separately numbered) can be first formed on the redistribution wiring layer 152, and then an opening (not shown) is formed in the dielectric layer through a via hole photomask (not shown). Thereafter, a conductive material layer (not shown) is formed on the dielectric layer and in the opening, and the conductive material layer is patterned through a redistribution wiring photomask (not shown) to form the redistribution wiring layer 154 and the via 154v. Similar steps are repeated to successively form the redistribution wiring layers 156 and 158 located in the dielectric layer 120, and the via 156v connected between the redistribution wiring layer 154 and the redistribution wiring layer 156, and the via 158v connected between the redistribution wiring layer 156 and the redistribution wiring layer 158. It should be understood that Figure 12 The dielectric layer 120 is formed by stacking multiple dielectric layers (including the aforementioned first dielectric layer 122 and second dielectric layer 124). The redistribution wiring layers 152, 154, 156, and 158 are collectively referred to as the redistribution wiring layer 150.

[0085] Since the area of ​​a single grain region 100 is larger than the maximum exposure area that can be achieved by a single exposure of a general photomask, the pattern layout of each via 154v, 156v, and 158v needs to be completed by splicing four different via photomasks, and the pattern layout of each redistribution circuit layer 152, 154, 156, and 158 needs to be completed by splicing four different redistribution circuit photomasks.

[0086] In some embodiments, first features 154a of the redistribution wiring layer 154 in the first sub-region R21 can be formed using a first redistribution wiring photomask (not shown), while second features 154b of the redistribution wiring layer 154 in the second sub-region R22 can be formed using a second redistribution wiring photomask (not shown), with the first features 154a and the second features 154b being laterally connected. Thus, by splicing the photomasks, the redistribution wiring layer 154 can be formed with feature sizes that exceed the maximum single exposure range of conventional photomasks.

[0087] Figure 12 Schematically depicting four layers of redistribution circuit layers, but this is not intended to limit the present invention. The number of layers and wiring design of the redistribution circuit layers can be adjusted according to actual needs.

[0088] In some embodiments, during the layout design stage of the die area 100, the number and position of the through-substrate via pattern in the die area 100 can be determined first, and then the passive component pattern can be arranged in an array in the remaining substrates 102 of the die area 100 and its space can be reserved according to the layout of the through-substrate via pattern. On the other hand, the redistribution wiring layer 150 can perform wiring design of each layer based on the connection requirements, and then select the passive component 110 at the appropriate position for electrical connection based on the wiring design of its bottom redistribution wiring layer 150 (such as the redistribution wiring layer 152). In this way, when a new product is developed, the wiring design of the redistribution wiring layer can be adjusted without redesigning the layout of the passive component 110 and the contact 130, thereby reducing the burden on designers and reducing development costs.

[0089] In some embodiments, the bottom surface of the substrate 102 may be planarized to expose the bottom surface of the TSV 102. A conductive connector (not shown) may then be formed on the bottom surface of the TSV 102 for electrical connection to the outside world.

[0090] In some embodiments, a singulation process may be performed to separate the substrate 102 and the structures thereon into a plurality of semiconductor structures 10 according to the die region 100 .

[0091] The manufacturing method of the semiconductor structure 10 can be substantially completed through the above manufacturing processes.

[0092] The semiconductor structure 10 includes a plurality of passive components 110, a plurality of contacts 130, and a redistribution wiring layer 150 (including a redistribution wiring layer 152, a redistribution wiring layer 154, a redistribution wiring layer 156, and a redistribution wiring layer 158). The plurality of passive components 110 are arranged in an array in the substrate 102. The plurality of contacts 130 are correspondingly arranged on the plurality of passive components 110 and are in direct contact with the plurality of passive components 110, wherein the plurality of contacts 130 include a first contact 132 and a second contact 134. The redistribution wiring layer 150 is arranged on the substrate 102, wherein the redistribution wiring layer 150 is electrically connected to the corresponding passive component 110 through the first contact 132, and the second contact 134 is not electrically connected to the redistribution wiring layer 150.

[0093] In some embodiments, the vias 154v, 156v, and 158v are connected between adjacent redistribution wiring layers 150 to provide electrical connections in a vertical direction of the redistribution wiring layers 150.

[0094] In some embodiments, the passive component 110 that is in direct contact with the second contact 134 is a dummy passive component.

[0095] In some embodiments, the semiconductor structure 10 further includes a dielectric layer 120. The dielectric layer 120 is disposed on the substrate 102 and laterally surrounds the plurality of contacts 130 and the redistribution layer 150. The top surface of the second contact 134 is encapsulated by the dielectric layer 120. In other words, the second contact 134 is a dummy contact.

[0096] In some embodiments, the semiconductor structure 10 further includes a through-substrate via 140 disposed in the substrate 102 to provide electrical connection between two sides of the substrate 102 .

[0097] In some embodiments, the through-substrate via 140 is further embedded in a portion of the dielectric layer 120. The top surface of the contact 130 may be flush with the top surface of the through-substrate via 140.

[0098] In some embodiments, the semiconductor structure 10 may serve as an interposer to connect between a chip and a circuit board.

[0099] Figure 13 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. It must be noted that Figure 13 The implementation examples follow Figure 12 The component numbers and partial contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0100] Please refer to Figure 13The semiconductor structure 20 includes a plurality of passive components 110, a plurality of contacts 130, and a redistribution wiring layer 150. The plurality of passive components 110 are arranged in an array in the substrate 102. The plurality of contacts 130 are correspondingly arranged on the plurality of passive components 110 and in direct contact with the plurality of passive components 110, wherein the plurality of contacts 130 include a first contact 132 and a second contact 134. The redistribution wiring layer 150 is arranged on the substrate 102, wherein the redistribution wiring layer 150 is electrically connected to the corresponding passive component 110 through the first contact 132, and the second contact 134 is not electrically connected to the redistribution wiring layer 150.

[0101] The semiconductor structure 20 is substantially similar to the semiconductor structure 10. The semiconductor structure 20 differs from the semiconductor structure 10 in that the semiconductor structure 20 further includes a plurality of chips 162, 164, and 166 disposed on the dielectric layer 120. The chips 162, 164, and 166 can be electrically connected to the redistribution layer 150 via conductive connectors (not numbered).

[0102] In some embodiments, chip 162 is located between chip 164 and chip 166. In some embodiments, chip 162 may be a system on chip (SOC), and chips 164 and 166 may be high-bandwidth memories, but the invention is not limited thereto.

[0103] In summary, the present invention utilizes the same photomask to form multiple arrays of passive components within a substrate, and utilizes the wiring design of the redistribution layer to select the desired passive components for electrical connection. This reduces the burden of passive component layout design within the substrate and increases customization flexibility. Furthermore, the need for photomasks to fabricate the passive components can be reduced, thereby lowering manufacturing costs.

[0104] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a plurality of passive components in a substrate, wherein the plurality of passive components are arranged in an array in the substrate; forming a plurality of contact members on the plurality of passive components, wherein the plurality of contact members correspond to the plurality of passive components; as well as A redistribution circuit layer is formed on the substrate, wherein the redistribution circuit layer is electrically connected to some of the plurality of passive components through some of the plurality of contacts.

2. The method for manufacturing a semiconductor structure according to claim 1 , wherein forming the plurality of passive components in the substrate comprises: Different areas of the substrate are exposed through a passive device photomask.

3. The method for manufacturing a semiconductor structure according to claim 1 , wherein forming the plurality of contacts on the plurality of passive components comprises: Different regions of the substrate are exposed separately through a contact photomask.

4. The method for manufacturing a semiconductor structure according to claim 2, wherein forming the redistribution wiring layer on the substrate comprises: Aligning a first photomask with the first sub-region, and forming a first feature of the redistribution wiring layer in the first sub-region of the substrate through the first photomask; as well as A second photomask is made to correspond to the second sub-region, and a second feature of the redistribution wiring layer is formed in the second sub-region of the substrate through the second photomask, wherein the pattern of the first photomask is different from the pattern of the second photomask. The method for fabricating a semiconductor structure according to claim 4 , wherein the first feature is laterally connected to the second feature. 6 . The method for manufacturing a semiconductor structure according to claim 4 , wherein the substrate comprises a plurality of crystal grain regions, and an area of ​​each of the plurality of crystal grain regions is larger than a single maximum exposure area of ​​the first photomask. 7 . The method for manufacturing a semiconductor structure according to claim 6 , wherein a size of the passive device photomask is smaller than a size of the first photomask. 8 . The method for manufacturing a semiconductor structure as claimed in claim 1 , wherein some of the passive components are dummy passive components.

9. The method for manufacturing a semiconductor structure according to claim 1 , further comprising: A through-substrate via is formed in the substrate.

10. A semiconductor structure comprising: A plurality of passive components are arrayed in a substrate; a plurality of contact members, correspondingly disposed on the plurality of passive components and in direct contact with the plurality of passive components, wherein the plurality of contact members include a first contact member and a second contact member; as well as A redistribution circuit layer is disposed on the substrate, wherein the redistribution circuit layer is electrically connected to the corresponding passive component through the first contact piece, and the second contact piece is not electrically connected to the redistribution circuit layer.

11. The semiconductor structure of claim 10, further comprising: A dielectric layer is disposed on the substrate and laterally surrounds the plurality of contacts and the redistribution wiring layer, wherein a top surface of the second contact is encapsulated by the dielectric layer.

12. The semiconductor structure of claim 10, further comprising: A through-substrate via is disposed in the substrate, wherein top surfaces of the plurality of contacts are flush with a top surface of the through-substrate via.

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