Manufacturing method for deep groove dielectric isolation
By introducing rounded corner etching and optimized filling processes in the deep-trough dielectric isolation manufacturing process, the Fence defect problem when the DTI structure is integrated with STI is solved, and the process stability and device reliability of the integrated circuit are improved.
Patent Information
- Application Number
- CN202510649892.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-08-29
AI Technical Summary
In the prior art, when the deep-trough dielectric isolation structure is integrated with the shallow-trough isolation process, it is prone to fence defects, resulting in process window shrinkage and device reliability risks.
The rounded corner etching step is introduced in the deep-trough media isolation manufacturing process, combining optimized deep-trough filling and chemical mechanical grinding, and by precisely controlling the removal of the etch stop layer and the liner oxide layer, avoiding the generation of Fence defects and ensuring high-quality filling of the DTI structure.
It significantly improves the DTI process window and improves the performance and reliability of integrated circuits, especially the manufacturing yield and reliability of high-voltage or high-density devices.
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing deep trench dielectric isolation. Background Art
[0002] With the rapid development of integrated circuit (IC) technology, device integration continues to increase while feature sizes continue to shrink. As feature sizes reach 0.18 micron and smaller, the requirements for electrical isolation between devices become increasingly stringent. Traditional isolation technologies, such as local oxide semiconductor (LOCOS) isolation and PN junction isolation, are gradually showing limitations in terms of isolation performance and footprint, making it difficult to meet the demands of high-performance, high-density integrated circuits.
[0003] To overcome the shortcomings of traditional isolation technologies, deep trench isolation (DTI) technology has emerged and is widely used in process platforms such as BCD (Bipolar-CMOS-DMOS) that require high-voltage devices or high isolation. A typical DTI structure fabrication method generally includes the following steps: First, a trench with a large aspect ratio is etched into a semiconductor substrate (e.g., a silicon substrate). The depth typically needs to reach 20 to 30 microns or even deeper to ensure sufficient vertical isolation capability. Next, a high-quality insulating dielectric layer, such as silicon dioxide, is grown on the inner walls (sidewalls and bottom) of the deep trench through methods such as thermal oxidation. The deep trench is then completely filled with a fill material such as polysilicon or silicon dioxide (e.g., using a high-aspect-ratio fill process, HARP). Finally, excess fill material is removed from the substrate surface through chemical mechanical polishing (CMP), aligning the top surface of the fill material with the surrounding area, thereby forming a DTI structure embedded in the substrate.
[0004] Compared to technologies like PN junction isolation, the DTI structure offers several advantages. First, DTI provides excellent electrical isolation, effectively suppressing latch-up and parasitic leakage between devices, thereby increasing device isolation voltage. Second, the DTI structure typically has smaller lateral dimensions, significantly reducing the area required for isolation, thereby reducing chip size and increasing integrated circuit integration density. Furthermore, a well-functioning DTI structure also helps improve overall device reliability.
[0005] However, in the existing semiconductor integration process flow, the formation of the DTI structure is usually located before the shallow trench isolation (STI) process step. STI is the mainstream technology used to isolate adjacent active areas (AA) on the same chip. In the subsequent manufacturing process, the patterned area of STI often needs to overlap with the previously formed DTI structure, that is, the edge of the STI trench will fall on the DTI area. This process integration method brings a severe technical challenge: when performing STI etching, especially in the edge area of the DTI structure, a process defect called "fence" is easily generated. This fence defect usually manifests as a protrusion or an abnormally steep step morphology remaining at the edge of the DTI filling medium after STI etching.
[0006] Fence defects are primarily caused by factors such as the differential selectivity of the etching gas for the DTI filler material and the surrounding substrate material (or capping layer) during the STI etch process, as well as inaccurate etch profile control. Fence defects can have a range of negative consequences: they significantly narrow the process window for STI etch and subsequent processes (such as gate formation), increasing the difficulty of process control. Fence structures can cause poor coverage of subsequently deposited thin films (such as gate dielectric and gate electrode materials) at the step, leading to device reliability issues. Furthermore, fence defects themselves can damage the edge integrity of the DTI structure, impacting its long-term isolation performance and reliability.
[0007] Therefore, the existing method of overlaying STI on traditional DTI structures faces problems such as a narrow process window and high reliability risks caused by fence defects. There is an urgent need to develop an improved DTI manufacturing method that can effectively avoid the generation of fence defects while integrating with STI, thereby improving overall process stability and device reliability. Summary of the Invention
[0008] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a manufacturing method for deep trench dielectric isolation, which is used to solve the problem in the prior art that a process defect called "fence" is easily generated during STI etching, especially in the edge area of the DTI structure.
[0009] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a deep trench dielectric isolation, comprising:
[0010] Step 1: forming a first pad oxide layer, a first etch stop layer and a hard mask layer in sequence on a semiconductor substrate;
[0011] Step 2: patterning the hard mask layer, the first etch stop layer, and the first pad oxide layer to form a deep trench isolation pattern opening to expose a predetermined area of the semiconductor substrate;
[0012] Step 3: performing fillet etching on the semiconductor substrate at the opening edge of the deep trench isolation pattern;
[0013] Step 4: etching the semiconductor substrate through the deep trench isolation pattern opening to form a deep trench;
[0014] Step 5: forming a sidewall oxide layer on the inner surface of the deep trench;
[0015] Step 6: Pre-cleaning the deep trench, forming a first dielectric material layer in the deep trench, and then filling the deep trench with a second dielectric material;
[0016] Step 7: grinding the second dielectric material until the first etch stop layer is exposed;
[0017] Step eight, removing the first etch stop layer, the first liner oxide layer, and a portion of the second dielectric material in the deep trench, so that a top surface of the second dielectric material filling the deep trench is lower than a top surface of the semiconductor substrate;
[0018] Step nine: forming a shallow trench isolation structure above the deep trench filled with the second dielectric material.
[0019] Preferably, in step 1, the first etch stop layer is a silicon nitride layer.
[0020] Preferably, in step 1, the hard mask layer is a silicon oxide hard mask layer.
[0021] Preferably, in step three, the fillet etching is used to adjust the angle of the opening edge of the deep trench isolation pattern to prevent fence defects from being generated at the junction of the shallow trench isolation structure formed in step nine and the deep trench.
[0022] Preferably, in step 4, the depth of the deep groove is greater than 20 microns.
[0023] Preferably, in step five, the sidewall oxide layer is formed by low-temperature wet oxygen thermal oxidation.
[0024] Preferably, in step five, the thickness of the sidewall oxide layer is greater than 5000 angstroms.
[0025] Preferably, in step six, the pre-cleaning treatment is SiCoNi treatment.
[0026] Preferably, in step six, the first dielectric material layer is formed by atomic layer deposition.
[0027] Preferably, in step six, the second dielectric material is oxide.
[0028] Preferably, in step six, the deposition of the first dielectric material layer forms an air gap in the deep trench.
[0029] Preferably, in step seven, the polishing is chemical mechanical polishing.
[0030] Preferably, in step eight, a portion of the second dielectric material in the deep trench is removed by wet etching.
[0031] In step eight, the first pad oxide layer and the first etch stop layer are removed by wet etching.
[0032] Preferably, step nine includes: depositing a second pad oxide layer and a second etch stop layer in sequence; patterning the second etch stop layer to form a shallow trench opening, wherein the shallow trench opening is adjacent to or partially overlaps with the deep trench; etching the semiconductor substrate to form a shallow trench; filling the shallow trench with a high-density plasma oxide layer; and chemically mechanically polishing the high-density plasma oxide layer until the hard mask material or the second etch stop layer is exposed.
[0033] Preferably, the method further comprises step ten, removing the second etch stop layer by a wet process.
[0034] As described above, the method for manufacturing deep trench dielectric isolation of the present invention has the following beneficial effects:
[0035] The deep trench dielectric isolation structure manufactured by the method of the present invention has high reliability, effectively improves the DTI process window, and can significantly improve the performance, reliability and manufacturing yield of integrated circuits, especially high-voltage or high-density devices such as BCD. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 Shown is a schematic diagram of the process flow of the present invention;
[0037] Figure 2 It is a schematic diagram showing the sequential formation of a first pad oxide layer, a first etch stop layer and a hard mask layer on a semiconductor substrate according to the present invention;
[0038] Figure 3 Shown is a schematic diagram of forming a deep trench isolation pattern opening according to the present invention;
[0039] Figure 4 It is a schematic diagram showing the rounded corner etching of the semiconductor substrate at the opening edge of the deep trench isolation pattern according to the present invention;
[0040] Figure 5Shown is a schematic diagram of forming a deep groove according to the present invention;
[0041] Figure 6 Schematic diagram showing the formation of a sidewall oxide layer on the inner surface of a deep trench according to the present invention;
[0042] Figure 7 Schematic diagram showing the formation of a first dielectric material layer in a deep trench according to the present invention;
[0043] Figure 8 Schematic diagram of filling the deep trench with a second dielectric material according to the present invention;
[0044] Figure 9 Shown is a schematic diagram of grinding the second dielectric material according to the present invention;
[0045] Figure 10 Schematic diagram showing the removal of the first etch stop layer, the first liner oxide layer and a portion of the second dielectric material in the deep trench according to the present invention;
[0046] Figure 11 It is a schematic diagram showing the sequential deposition of a second liner oxide layer and a second etch stop layer according to the present invention;
[0047] Figure 12 Shown is a schematic diagram of forming a shallow groove according to the present invention;
[0048] Figure 13 Schematic diagram of filling a high density plasma (HDP) oxide layer in a shallow trench according to the present invention;
[0049] Figure 14 Schematic diagram of chemical mechanical polishing of a high-density plasma oxide layer according to the present invention;
[0050] Figure 15 It is a schematic diagram showing the removal of the second etch stop layer according to the present invention. DETAILED DESCRIPTION
[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0052] See also Figure 1 The present invention provides a method for manufacturing a deep trench dielectric isolation, comprising:
[0053] Step 1: Form a first pad oxide layer 102, a first etch stop layer 103 and a hard mask layer 104 on the semiconductor substrate 101 in sequence to form a Figure 2The structure shown.
[0054] In some embodiments, in step 1, the first etch stop layer 103 is a silicon nitride layer. The silicon nitride layer has good etching selectivity, can serve as a reliable stop layer in the subsequent polishing step, and is easy to control during the subsequent selective removal.
[0055] In some embodiments, in step 1, the hard mask layer 104 is a silicon oxide hard mask layer 104. The silicon oxide hard mask layer 104 is easily patterned by photolithography and etching processes, and the pattern is accurately transferred to the underlying first etch stop layer 103. The first pad oxide layer 102 is typically a thin layer of silicon dioxide, which is used to buffer the stress between the first etch stop layer 103 and the semiconductor substrate 101 and protect the surface of the substrate 101.
[0056] Step 2: Patterning the hard mask layer 104, the first etch stop layer 103 and the first liner oxide layer 102 to form a deep trench isolation pattern opening, forming Figure 3 The structure shown exposes a predetermined area of the semiconductor substrate 101. This patterning process typically involves standard photoresist coating, exposure, and development processes to form a photoresist pattern. Subsequently, through dry etching or other methods, using the photoresist pattern as a mask, the hard mask layer 104, the first etch stop layer 103, and the first pad oxide layer 102 are sequentially etched until the bottom of the opening exposes the semiconductor substrate 101, thereby defining the location and shape of the deep trench to be subsequently formed.
[0057] Step 3: perform fillet etching on the semiconductor substrate 101 at the edge of the deep trench isolation pattern opening to form Figure 4 The structure shown.
[0058] In some embodiments, in step three, rounded corner etching is used to adjust the angle of the edge of the deep trench isolation pattern opening to prevent fence defects from forming at the junction of the shallow trench isolation structure and the deep trench formed in step nine. By introducing this rounded corner etching step, the sharp edge at the top of the deep trench opening can be smoothed to form a gentle transition profile. This optimization process can significantly reduce the risk of fence defects when the subsequent STI process is overetched in this area, because the steep steps or sharp corners that cause fence formation are eliminated, thereby greatly widening the window of subsequent STI etching and other processes, improving the stability of the process and the reliability of the final device.
[0059] Step 4: Etch the semiconductor substrate 101 through the deep trench isolation pattern opening to form a deep trench. Figure 5 The structure shown.
[0060] In some embodiments, in step 4, the trench depth is greater than 20 microns. For example, the trench depth can be 20-30 microns or deeper, with the specific depth determined based on design requirements such as device isolation voltage. A sufficiently deep trench is essential for achieving high-voltage isolation capabilities, effectively blocking lateral leakage paths within substrate 101 and ensuring effective isolation between devices.
[0061] Step 5: forming a sidewall oxide layer 105 on the inner surface of the deep trench, forming a Figure 6 The structure shown.
[0062] In some embodiments, in step five, the sidewall oxide layer 105 is formed by low-temperature wet oxygen thermal oxidation. Thermal oxidation using a low-temperature wet oxygen furnace can grow a high-quality silicon dioxide layer on the sidewalls and bottom of the deep trench. The low temperature helps reduce the impact on the thermal budget of other device components, while the wet oxygen environment allows for a relatively fast oxidation rate.
[0063] In some embodiments, in step five, the thickness of the sidewall oxide layer 105 is greater than 5,000 angstroms. For example, the thickness can be 5,000-10,000 angstroms. This oxide layer not only serves as the primary dielectric isolation layer, but its growth process also repairs silicon surface damage that may be caused by deep trench etching (thermal repair), improving interface quality. A sufficiently thick sidewall oxide layer 105 is crucial to ensuring high breakdown voltage and long-term reliability of DTI.
[0064] Step 6: Pre-clean the deep trench and form a first dielectric material layer 106 in the deep trench. Figure 7 The structure shown in FIG. 1 is then filled with a second dielectric material 108 to form a deep trench. Figure 8 The structure shown.
[0065] In some embodiments, in step 6, the pre-cleaning treatment is SiCoNi treatment. SiCoNi treatment is an advanced dry cleaning technology that can effectively remove contaminants such as the natural oxide layer and polymer residues on the surface of deep trenches, providing a clean and ideal starting surface for the subsequent deposition of high-quality dielectric layers.
[0066] In some embodiments, in step six, the first dielectric material layer 106 is formed by atomic layer deposition (ALD). ALD technology has excellent step coverage and precise thickness control capabilities, and is particularly suitable for forming uniform, dense, and conformal films in deep trenches with high aspect ratios. Depositing a layer of dielectric material (such as oxide) by ALD ensures good initial coverage in all corners of the deep trench, especially in the top area after fillet etching. This helps improve the quality of subsequent filling processes and avoids filling defects or voids in these complex topography areas. The first dielectric material layer 106 does not completely fill the deep trench.
[0067] In some embodiments, in step six, the deposition of the first dielectric material layer 106 may form an air gap 107 within the deep trench. Depending on the specific process parameters and trench topography, the deposition of the first dielectric material layer 106 may also form an air gap 107 within the deep trench, such as top closure in high aspect ratio regions. The presence of this air gap 107 can sometimes be used to reduce the effective dielectric constant of the isolation structure, further improving isolation performance.
[0068] In some embodiments, in step six, the second dielectric material 108 is an oxide. After forming the first dielectric material layer 106, the remaining space in the deep trench is completely filled with the second dielectric material 108 (e.g., an oxide deposited using a high aspect ratio process, HARP). Technologies such as HARP are specifically designed for filling high aspect ratio structures, achieving dense filling without voids, ensuring the integrity of the DTI structure and excellent isolation performance.
[0069] Step 7: Grind the second dielectric material 108 until the first etch stop layer 103 is exposed to form a Figure 9 The structure shown.
[0070] In some embodiments, in step seven, the polishing is performed by chemical mechanical polishing (CMP). An oxide CMP (OX CMP) process is employed, utilizing the chemical and mechanical effects of a slurry to polish away excess second dielectric material 108 (oxide) on the wafer surface until it reaches the underlying first etch stop layer 103. The first etch stop layer 103 (e.g., silicon nitride) has a high polishing selectivity relative to oxide and can serve as a precise stop layer, ensuring a globally planarized surface after CMP and well-controlled DTI fill height.
[0071] Step eight, remove the first etch stop layer 103, the first liner oxide layer 102 and part of the second dielectric material 108 in the deep trench, so that the top surface of the second dielectric material 108 filling the deep trench is lower than the top surface of the semiconductor substrate 101, forming Figure 10The structure shown. This key step integrates multiple removal actions. First, outside the DTI area, the first etch stop layer 103, which originally served as the CMP stop layer, and the first liner oxide layer 102 thereunder are removed. At the same time, the second dielectric material 108 filled in the deep trench is etched back to lower its top surface. The final effect is that not only is the top surface of the DTI filling dielectric recessed, but the depth of this recess is sufficient to make it lower than the surface level of the surrounding semiconductor substrate 101. In addition, the first etch stop layer 103 and the first liner oxide layer 102 originally covering the future active area are also removed, directly exposing the semiconductor substrate 101.
[0072] In some embodiments, in step eight, a portion of the second dielectric material 108 in the deep trench is removed by wet etching. For example, a wet etchant such as dilute hydrofluoric acid (DHF) that has selective etching capability for oxides can be used to etch back the oxide inside the DTI to a target depth.
[0073] In some embodiments, step eight further includes removing the first liner oxide layer 102 and the first etch stop layer 103 by wet etching. This can be accomplished through one or more wet etching steps, for example, first using hot phosphoric acid to remove silicon nitride (the first etch stop layer 103), followed by using dilute hydrofluoric acid to remove silicon dioxide (the first liner oxide layer 102 and to etch back a portion of the second dielectric material 108). By precisely controlling the etching time and chemicals, the top surface of the DTI filler can be precisely controlled to a predetermined depth below the surface of the semiconductor substrate 101, while completely removing the old overlying layer, creating clean and morphologically suitable conditions for subsequent STI formation directly on the substrate 101.
[0074] Step 9: Form a shallow trench isolation structure above the deep trench filled with the second dielectric material 108. At this point, since the first etch stop layer 103 and the first liner oxide layer 102 have been removed, the STI structure will be directly formed on the semiconductor substrate 101 and will be adjacent to or overlay the recessed DTI structure.
[0075] In some embodiments, step nine includes: sequentially depositing a second liner oxide layer 109 and a second etch stop layer 110 to form a Figure 11 the second etch stop layer 110 is patterned to form a shallow trench opening, wherein the shallow trench opening is adjacent to or partially overlaps the deep trench; etching the semiconductor substrate 101 to form a shallow trench, forming a Figure 12 The structure shown in FIG. 1 is filled with a high density plasma (HDP) oxide layer in the shallow trench to form a Figure 13The structure shown in FIG14 is formed by chemically mechanically polishing the high-density plasma oxide layer until the second etch stop layer 110 is exposed, thereby forming the structure shown in FIG14 . This is a specific step in forming the STI structure. First, a new liner oxide layer (second liner oxide layer 109) and a new etch stop layer (second etch stop layer 110, such as silicon nitride) are deposited over the entire wafer surface (including the recessed DTI region and the region of the semiconductor substrate 101 exposed in step 8). The second etch stop layer 110 is then patterned using photolithography and etching techniques to define shallow trench isolation (STI) regions, which are typically used to isolate adjacent active areas (AA). Shallow trench openings are formed in the previously exposed semiconductor substrate 101, and their edges may be adjacent to or partially overlap (overlay) the previously formed deep trenches. Next, using the patterned second etch stop layer 110 as a mask, the underlying second liner oxide layer 109 and semiconductor substrate 101 are etched to form shallow trenches of the desired depth. Subsequently, the shallow trench is filled with oxide 111 (HDP oxide layer) by using methods such as high-density plasma chemical vapor deposition (HDP-CVD). The HDP process has good gap filling ability and is suitable for filling shallow trenches with a certain aspect ratio. Finally, the excess HDP oxide layer 111 on the wafer surface is removed by a chemical mechanical polishing (CMP) process to achieve flattening of the STI area, and the polishing usually stops on the second etch stop layer 110. Since in the method of the present invention, the fence defects at the edge of the deep trench have been effectively prevented by the fillet etching in step three, and the processing in step eight makes the top of the DTI lower than the surface of the substrate 101, even if the STI pattern is overlaid on the DTI area, the etching and filling of the STI can be successfully completed to obtain an STI-DTI structure with good morphology and no fence defects, thereby ensuring the integrity and reliability of device isolation.
[0076] In some embodiments, the method further includes step 10, removing the second etch stop layer 110 by a wet process to form a Figure 15 The structure shown. After the STI structure is formed and planarized, the second etch stop layer 110 (e.g., silicon nitride), which serves as a CMP stop layer and hard mask, is typically removed to expose the underlying active area (typically covered by the second liner oxide layer 109). This can be accomplished by selective wet etching (e.g., using hot phosphoric acid). Removal of the second etch stop layer 110 completes the integrated fabrication of high-reliability deep trench dielectric isolation and shallow trench isolation.
[0077] In summary, the present invention successfully solves the problem of fence defects that are easily generated when STI overlays DTI in traditional processes by introducing a rounded corner etching step at the deep trench opening, combining optimized deep trench filling, precisely controlled CMP flattening, and the key etch stop layer / liner oxide layer removal and DTI dielectric etch back step (step eight), and finally integrating the STI process. This method not only optimizes the bonding interface between DTI and STI, avoiding the resulting process window reduction and reliability risks, but also ensures the high-quality filling and excellent isolation performance of the DTI itself. The deep trench dielectric isolation structure manufactured by the method of the present invention has high reliability, effectively improves the DTI process window, and can significantly improve the performance, reliability and manufacturing yield of integrated circuits, especially high-voltage or high-density devices such as BCD.
[0078] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for manufacturing a deep trench dielectric isolation, characterized in that: At least: Step 1: forming a first pad oxide layer, a first etch stop layer and a hard mask layer in sequence on a semiconductor substrate; Step 2: patterning the hard mask layer, the first etch stop layer, and the first pad oxide layer to form a deep trench isolation pattern opening to expose a predetermined area of the semiconductor substrate; Step 3: performing fillet etching on the semiconductor substrate at the opening edge of the deep trench isolation pattern; Step 4: etching the semiconductor substrate through the deep trench isolation pattern opening to form a deep trench; Step 5: forming a sidewall oxide layer on the inner surface of the deep trench; Step 6: Pre-cleaning the deep trench, forming a first dielectric material layer in the deep trench, and then filling the deep trench with a second dielectric material; Step 7: grinding the second dielectric material until the first etch stop layer is exposed; Step eight, removing the first etch stop layer, the first liner oxide layer, and a portion of the second dielectric material in the deep trench, so that a top surface of the second dielectric material filling the deep trench is lower than a top surface of the semiconductor substrate; Step nine: forming a shallow trench isolation structure above the deep trench filled with the second dielectric material.
2. The method for manufacturing a deep trench dielectric isolation according to claim 1, wherein: In step 1, the first etch stop layer is a silicon nitride layer.
3. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step 1, the hard mask layer is a silicon oxide hard mask layer.
4. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step three, the fillet etching is used to adjust the angle of the edge of the opening of the deep trench isolation pattern to prevent fence defects from being generated at the junction of the shallow trench isolation structure formed in step nine and the deep trench.
5. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step 4, the depth of the deep groove is greater than 20 microns.
6. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step five, the sidewall oxide layer is formed by low-temperature wet oxygen thermal oxidation.
7. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step five, the thickness of the sidewall oxide layer is greater than 5000 angstroms.
8. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step six, the pre-cleaning treatment is SiCoNi treatment.
9. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step six, the first dielectric material layer is formed by atomic layer deposition.
10. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step six, the second dielectric material is oxide.
11. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step six, the first dielectric material layer is deposited to form an air gap in the deep trench.
12. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step seven, the polishing is chemical mechanical polishing.
13. The method for manufacturing deep trench dielectric isolation according to claim 1, wherein: In step eight, a portion of the second dielectric material in the deep trench is removed by wet etching.
14. The method for manufacturing deep trench dielectric isolation according to claim 13, wherein: In step eight, the first pad oxide layer and the first etch stop layer are removed by wet etching.
15. The method for manufacturing deep trench dielectric isolation according to claim 14, wherein: Step nine includes: depositing a second liner oxide layer and a second etch stop layer in sequence; patterning the second etch stop layer to form a shallow trench opening, wherein the shallow trench opening is adjacent to or partially overlaps the deep trench; etching the semiconductor substrate to form a shallow trench; filling the shallow trench with a high-density plasma oxide layer; and chemically mechanically polishing the high-density plasma oxide layer until the hard mask material or the second etch stop layer is exposed.
16. The method for manufacturing deep trench dielectric isolation according to claim 15, wherein: The method further includes step ten of removing the second etch stop layer by a wet process.