Data processing method and data processing device

Abstract

The invention discloses a data processing method and a data processing device. And performing first data processing on the plurality of first data streams subjected to the first FEC coding to obtain m second data streams. Wherein each second data stream is subjected to second FEC coding, each code word after second FEC coding comprises N bits, N = K + S, K represents the number of information bits, and S represents the number of check bits. And performing second data processing on the m second data streams to obtain m third data streams. Wherein each third data stream comprises at least one bit sequence, each bit sequence comprises P + W bits, P bits in each bit sequence are from the second data stream, W bits in each bit sequence are added alignment identifiers, and P = N * b. Third data processing is carried out on the m third data streams to obtain Y modulation symbol streams, each modulation symbol stream is modulated, and the Baud rate value of each modulation symbol stream is integer multiples of the typical reference clock frequency value of the Ethernet.

Description

[0001] This application is a divisional application. The application number of the original application is 202480001044.8, and the original application date is July 21, 2023. The entire contents of the original application are incorporated into this application by reference. This application claims priority to the Chinese patent application with application number 202211307290.5, filed on October 24, 2022, entitled “A data processing method and data processing device”, the Chinese patent application with application number 202211559068.4, filed on December 6, 2022, entitled “A data processing method and data processing device”, and the Chinese patent application with application number 202310631032.0, filed on May 30, 2023, entitled “A data processing method and data processing device”, all of which are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communications, and in particular to a data processing method and a data processing device. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, Ethernet networks are developing toward greater capacity, higher speeds, and lower latency. Using forward error correction (FEC) to correct transmitted data errors can resolve transmission errors and recover the original data from the received data.

[0004] A cascaded FEC transmission scheme has been proposed. The transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the data after the first FEC encoding to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the data after the first FEC encoding, modulates and maps the bit sequence after the second FEC encoding to generate a corresponding modulation symbol sequence, and finally transmits the generated modulation symbol sequence via optical fiber to the receiving end. The data stream received by the receiving end is asynchronous and noisy. Clock and Data Recovery (CDR) based on a phase-locked loop (PLL) is typically used. This method extracts the clock from the data and "retimes" the data to remove jitter during transmission. Demodulation and decoding are then performed to recover the original data sent by the transmitting end. However, the PLL circuit used by the receiving end for CDR in existing schemes is complex to implement and exhibits high PLL jitter. Summary of the Invention

[0005] The embodiments of the present application provide a data processing method and a data processing device. On the one hand, they simplify the way the receiving end performs clock extraction and synchronization, and can perform fast phase locking, with low PLL complexity and small jitter. On the other hand, they simplify operations such as frame synchronization and inner code word synchronization at the receiving end, and achieve low complexity.

[0006] In a first aspect, an embodiment of the present application provides a data processing method, which is applied to a transmitting end and includes the following steps. First, a plurality of first data streams that have undergone first FEC encoding are subjected to first data processing to obtain m second data streams. Wherein, m is an integer greater than 1, each second data stream has undergone second FEC encoding, and each codeword after the second FEC encoding includes N bits, N=K+S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. Next, the m second data streams are subjected to second data processing to obtain m third data streams. Wherein, each third data stream includes at least one bit sequence, each bit sequence includes P+W bits, P bits in each bit sequence come from the second data stream, W bits in each bit sequence are added alignment markers, P=N×b, and b is an integer greater than or equal to 1. Furthermore, the m third data streams are subjected to third data processing to obtain Y modulation symbol streams, where Y is an integer greater than or equal to 1, each modulation symbol stream is modulated, and the baud rate value of each modulation symbol stream is an integer multiple of the reference clock frequency value.

[0007] In this implementation, P bits are periodically extracted from the data stream after concatenated FEC encoding, and an alignment marker of W bits is inserted, so that a W-bit alignment marker exists for every P+W bits in the data stream. By selecting positive integers P and W, the baud rate of the modulated symbol data stream can be an integer multiple of the Ethernet common reference clock frequency. This simplifies clock extraction and synchronization at the receiving end, enabling fast phase lock, low PLL complexity, and low jitter. Furthermore, P is required to be a multiple of the inner code length N, i.e., P = N × b. After the receiving end performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also known as marker locking), inner code word synchronization is guaranteed. This simplifies frame synchronization and inner code word synchronization operations at the receiving end, reducing implementation complexity.

[0008] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0009] In some possible implementations, each second data stream undergoes convolutional interleaving before undergoing the second FEC encoding. Convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, and each storage unit is used to store d bits. Bits in the input data stream are sequentially input into the r delay lines according to the sequence of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the consecutive r*d bits in the output data stream include the d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0010] In some possible implementations, for every f bits output after convolutional interleaving, the input and output switches corresponding to the convolutional interleaver are located on the 0th delay line, and K×b is divisible by f. It is required that the input and output switches of the convolutional deinterleaver corresponding to the starting position of each frame (W+P bits) are located at the starting position of the switch, typically the topmost position. More specifically, for every f bits output by the convolutional interleaver and convolutional deinterleaver, their input and output switches are located at the topmost position, ensuring synchronization of the convolutional deinterleaver during frame synchronization.

[0011] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and the convolutional deinterleaver can output K×b bits per polling c times, and at this time, the input and output switch positions are at the starting positions of the switches, so that the convolutional deinterleaver synchronization can be guaranteed during frame synchronization.

[0012] In some possible implementations, the rate of the first data stream is 850 Gbps. a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

[0013] In some possible implementations, N=128, K=120,

[0014] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud;

[0015] Alternatively, W = 48, P = 52224, a = 726, b = 408, baud rate = 113.4375 Gbaud;

[0016] Alternatively, W = 56, P = 15232, a = 728, b = 119, baud rate = 113.75 Gbaud;

[0017] Alternatively, W = 56, P = 60928, a = 726, b = 476, baud rate = 113.4375 Gbaud;

[0018] Alternatively, W = 64, P = 13056, a = 728, b = 102, baud rate = 113.75 Gbaud;

[0019] Alternatively, W = 64, P = 69632, a = 726, b = 544, baud rate = 113.4375 Gbaud;

[0020] Alternatively, W = 120, P = 32640, a = 728, b = 255, baud rate = 113.75 Gbaud;

[0021] Alternatively, W = 120, P = 52224, a = 727, b = 408, baud rate = 113.5938 Gbaud;

[0022] Alternatively, W = 120, P = 130560, a = 726, b = 1020, baud rate = 113.4375 Gbaud;

[0023] Alternatively, W = 128, P = 34816, a = 728, b = 272, baud rate = 113.75 Gbaud;

[0024] Alternatively, W=128, P=139264, a=726, b=1088, and baud rate=113.4375 Gbaud.

[0025] In some possible implementations, N=170, K=160,

[0026] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud;

[0027] Alternatively, W = 48, P = 69360, a = 723, b = 408, baud rate = 112.9688 Gbaud;

[0028] Alternatively, W = 56, P = 11560, a = 726, b = 68, baud rate = 113.4375 Gbaud;

[0029] Alternatively, W = 56, P = 80920, a = 723, b = 476, baud rate = 112.9688 Gbaud;

[0030] Alternatively, W = 64, P = 92480, a = 723, b = 544, baud rate = 112.9688 Gbaud;

[0031] Alternatively, W = 120, P = 34680, a = 725, b = 204, baud rate = 113.2813 Gbaud;

[0032] Alternatively, W = 120, P = 57800, a = 724, b = 340, baud rate = 113.125 Gbaud;

[0033] Or, W = 120, P = 173400, a = 723, b = 1020, baud rate = 112.9688 Gbaud;

[0034] Alternatively, W = 170, P = 49130, a = 725, b = 289, baud rate = 113.2813 Gbaud;

[0035] Alternatively, W=170, P=245650, a=723, b=1445, and baud rate=112.9688 Gbaud.

[0036] In some possible implementations, N=144, K=136,

[0037] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud;

[0038] Alternatively, W = 48, P = 8640, a = 724, b = 60, baud rate = 113.125 Gbaud;

[0039] Or, W = 48, P = 11520, a = 723, b = 80, baud rate = 112.9688 Gbaud;

[0040] Alternatively, W = 48, P = 17280, a = 722, b = 120, baud rate = 112.8125 Gbaud;

[0041] Alternatively, W = 48, P = 34560, a = 721, b = 240, baud rate = 112.6563 Gbaud;

[0042] Or, W = 56, P = 5760, a = 727, b = 40, baud rate = 113.5938 Gbaud;

[0043] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0044] Alternatively, W = 56, P = 40320, a = 721, b = 280, baud rate = 112.6563 Gbaud;

[0045] Alternatively, W = 64, P = 5760, a = 728, b = 40, baud rate = 113.75 Gbaud;

[0046] Alternatively, W = 64, P = 11520, a = 724, b = 80, baud rate = 113.125 Gbaud;

[0047] Alternatively, W = 64, P = 23040, a = 722, b = 160, baud rate = 112.8125 Gbaud;

[0048] Alternatively, W = 64, P = 46080, a = 721, b = 320, baud rate = 112.6563 Gbaud;

[0049] Or, W = 120, P = 14400, a = 726, b = 100, baud rate = 113.4375 Gbaud;

[0050] Or, W = 120, P = 17280, a = 725, b = 120, baud rate = 113.2813 Gbaud;

[0051] Or, W = 120, P = 28800, a = 723, b = 200, baud rate = 112.9688 Gbaud;

[0052] Or, W = 120, P = 43200, a = 722, b = 300, baud rate = 112.8125 Gbaud;

[0053] Alternatively, W = 120, P = 86400, a = 721, b = 600, baud rate = 112.6563 Gbaud;

[0054] Or, W = 144, P = 11520, a = 729, b = 80, baud rate = 113.9063 Gbaud;

[0055] Alternatively, W = 144, P = 17280, a = 726, b = 120, baud rate = 113.4375 Gbaud;

[0056] Alternatively, W = 144, P = 25920, a = 724, b = 180, baud rate = 113.125 Gbaud;

[0057] Or, W = 144, P = 34560, a = 723, b = 240, baud rate = 112.9688 Gbaud;

[0058] Or, W = 144, P = 51840, a = 723, b = 360, baud rate = 112.8125 Gbaud;

[0059] Alternatively, W=144, P=103680, a=721, b=720, and baud rate=112.6563 Gbaud.

[0060] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud;

[0061] Alternatively, W = 56, P = 10080, a = 724, b = 70, baud rate = 113.125 Gbaud;

[0062] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0063] Alternatively, W=56, P=40320, a=721, b=280, and baud rate=112.6563 Gbaud.

[0064] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0065] In some possible implementations, N=128, K=120, and the baud rate of the modulation symbol stream is 113.4375 Gbaud.

[0066] In some possible implementations, P=1088×W.

[0067] In some possible implementations, the alignment marker includes at least one frame synchronization sequence with a length of 48 bits.

[0068] In some possible implementations, the 48 bits of the frame synchronization sequence are continuous in the alignment marker.

[0069] In some possible implementations, the values ​​of the 48 bits of the frame synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0070] In some possible implementations, the frame synchronization sequence includes two frame synchronization subsequences, each frame synchronization subsequence has a bit length of 24 bits, and the two frame synchronization subsequences are separated by 8 bits in the alignment identifier.

[0071] In some possible implementations, the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other of the two frame synchronization subsequences include 0x65, 0xB5, and 0xD9.

[0072] In some possible implementations, the alignment indicator includes padding bits and / or a status field.

[0073] In some possible implementations, W is divisible by N.

[0074] In some possible implementations, each second data stream undergoes at least one of identification locking, channel deskew processing, and channel reordering before undergoing the second FEC encoding. And / or, each second data stream undergoes at least one of channel interleaving and scrambling after undergoing the second FEC encoding.

[0075] In some possible implementations, performing first data processing on the plurality of first data streams to obtain m second data streams includes: performing second FEC encoding on each group of eight first data streams in the plurality of first data streams to obtain each group of eight encoded data streams; and performing channel interleaving on each group of eight encoded data streams to obtain one second data stream, thereby obtaining the m second data streams.

[0076] In some possible implementations, N=128, K=120, and channel interleaving each group of eight coded data streams to obtain a second data stream includes: obtaining an inner codeword of 128 bits from each coded data stream in each group of eight coded data streams to obtain a total of eight inner codewords. Polling to obtain two bits from each of the eight inner codewords to obtain 1024 consecutive bits in the second data stream.

[0077] In some possible implementations, each second data stream is further cyclically shifted before being subjected to the second FEC encoding.

[0078] In some possible implementations, performing the first data processing on the multiple first data streams includes: performing convolution interleaving on each of the 8×m first data streams, performing cyclic shifting on each of the 8×m first data streams after the convolution interleaving, and performing second FEC encoding on each of the 8×m first data streams after the cyclic shifting.

[0079] In some possible implementations, performing first data processing on the multiple first data streams includes: performing convolution interleaving on each of the 2×m first data streams; distributing each of the convolution interleaved first data streams to obtain four distributed first data streams, for a total of 8×m distributed first data streams; performing cyclic shifting on each of the distributed 8×m first data streams; and performing second FEC encoding on each of the 8×m cyclically shifted first data streams.

[0080] In some possible implementations, performing first data processing on the multiple first data streams includes: performing convolution interleaving on each of the m first data streams; distributing each of the convolution interleaved first data streams to obtain eight distributed first data streams, for a total of 8×m distributed first data streams; performing cyclic shifting on each of the 8×m distributed first data streams; and performing second FEC encoding on each of the 8×m cyclically shifted first data streams.

[0081] In some possible implementations, in order to achieve lower latency, lower complexity and power consumption, the cyclic shift operation and / or channel interleaving operation may also be bypassed. Specifically, performing first data processing on multiple first data streams to obtain m second data streams includes: first, distributing each of the m first data streams to obtain 8 distributed first data streams, so as to obtain a total of 8×m distributed first data streams. Afterwards, performing second FEC encoding on the distributed 8×m first data streams respectively to obtain 8×m coded data streams. Furthermore, codeword merging is performed on every 8 coded data streams in the 8×m coded data streams to obtain 1 second data stream, so as to obtain a total of m second data streams. It should be understood that codeword merging on the 8 coded data streams is equivalent to performing one-way Hamming codeword interleaver on the 8 coded data streams.

[0082] In some possible implementations, the alignment identifier includes at least one target codeword, and the target codeword includes N bits.

[0083] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. It should be understood that the target codeword may also be referred to as an inner codeword, and selecting the alignment marker pattern as one or more inner codewords facilitates low-complexity frame and codeword synchronization at the receiving end.

[0084] In some possible implementations, the alignment marker is obtained by codeword interleaving of multiple target codewords. For example, each alignment marker is obtained by interleaving 8 target codewords through 8-way codewords. The codeword interleaving herein may also be referred to as channel interleaving. It should be understood that the alignment marker obtained by codeword interleaving of multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by codeword merging of multiple target codewords. For example, each alignment marker is obtained by codeword merging of 8 target codewords. The codeword merging herein may also be referred to as 1-way codeword interleaving.

[0085] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to a receiving end and includes the following steps. First, fourth data processing is performed on Y received modulation symbol streams to obtain m fourth data streams. Each fourth data stream is demodulated, and the Y modulation symbol streams are obtained by performing third data processing on m third data streams. Each modulation symbol stream is modulated, and the m third data streams are obtained by performing second data processing on m second data streams respectively. The m second data streams are obtained by performing first data processing on multiple first data streams that have undergone first FEC encoding. Y is an integer greater than or equal to 1, and m is an integer greater than 1. Each second data stream is subjected to second FEC encoding. Each codeword after the second FEC encoding includes N bits, where N = K + S, where K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. Each third data stream includes at least one bit sequence, and each bit sequence includes P + W bits. The P bits in each bit sequence come from the second data stream, and the W bits in each bit sequence are added alignment markers. P=N×b, where b is an integer greater than or equal to 1, and the baud rate value of each modulation symbol stream is an integer multiple of the reference clock frequency value. Furthermore, frame synchronization is performed on each fourth data stream according to the alignment identifier in each fourth data stream.

[0086] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0087] In some possible implementations, each second data stream undergoes convolutional interleaving before undergoing the second FEC encoding. Convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, and each storage unit is used to store d bits. Bits in the input data stream are sequentially input into the r delay lines according to the sequence of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the consecutive r*d bits in the output data stream include the d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0088] In some possible implementations, for every f bits output after convolutional interleaving, the input and output switches corresponding to the convolutional interleaver are located on the 0th delay line, and K×b is divisible by f. It is required that the input and output switches of the convolutional deinterleaver corresponding to the starting position of each frame (W+P bits) are located at the starting position of the switch, typically the topmost position. More specifically, for every f bits output by the convolutional interleaver and convolutional deinterleaver, their input and output switches are located at the topmost position, ensuring synchronization of the convolutional deinterleaver during frame synchronization.

[0089] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and the convolutional deinterleaver can output K×b bits per polling c times, and at this time, the input and output switch positions are at the starting positions of the switches, so that the convolutional deinterleaver synchronization can be guaranteed during frame synchronization.

[0090] In some possible implementations, the rate of the first data stream is 850 Gbps. a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

[0091] In some possible implementations, N=128, K=120,

[0092] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud;

[0093] Alternatively, W = 48, P = 52224, a = 726, b = 408, baud rate = 113.4375 Gbaud;

[0094] Alternatively, W = 56, P = 15232, a = 728, b = 119, baud rate = 113.75 Gbaud;

[0095] Alternatively, W = 56, P = 60928, a = 726, b = 476, baud rate = 113.4375 Gbaud;

[0096] Alternatively, W = 64, P = 13056, a = 728, b = 102, baud rate = 113.75 Gbaud;

[0097] Alternatively, W = 64, P = 69632, a = 726, b = 544, baud rate = 113.4375 Gbaud;

[0098] Alternatively, W = 120, P = 32640, a = 728, b = 255, baud rate = 113.75 Gbaud;

[0099] Alternatively, W = 120, P = 52224, a = 727, b = 408, baud rate = 113.5938 Gbaud;

[0100] Alternatively, W = 120, P = 130560, a = 726, b = 1020, baud rate = 113.4375 Gbaud;

[0101] Alternatively, W = 128, P = 34816, a = 728, b = 272, baud rate = 113.75 Gbaud;

[0102] Alternatively, W=128, P=139264, a=726, b=1088, and baud rate=113.4375 Gbaud.

[0103] In some possible implementations, N=170, K=160,

[0104] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud;

[0105] Alternatively, W = 48, P = 69360, a = 723, b = 408, baud rate = 112.9688 Gbaud;

[0106] Alternatively, W = 56, P = 11560, a = 726, b = 68, baud rate = 113.4375 Gbaud;

[0107] Alternatively, W = 56, P = 80920, a = 723, b = 476, baud rate = 112.9688 Gbaud;

[0108] Alternatively, W = 64, P = 92480, a = 723, b = 544, baud rate = 112.9688 Gbaud;

[0109] Alternatively, W = 120, P = 34680, a = 725, b = 204, baud rate = 113.2813 Gbaud;

[0110] Alternatively, W = 120, P = 57800, a = 724, b = 340, baud rate = 113.125 Gbaud;

[0111] Or, W = 120, P = 173400, a = 723, b = 1020, baud rate = 112.9688 Gbaud;

[0112] Alternatively, W = 170, P = 49130, a = 725, b = 289, baud rate = 113.2813 Gbaud;

[0113] Alternatively, W=170, P=245650, a=723, b=1445, and baud rate=112.9688 Gbaud.

[0114] In some possible implementations, N=144, K=136,

[0115] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud;

[0116] Alternatively, W = 48, P = 8640, a = 724, b = 60, baud rate = 113.125 Gbaud;

[0117] Or, W = 48, P = 11520, a = 723, b = 80, baud rate = 112.9688 Gbaud;

[0118] Alternatively, W = 48, P = 17280, a = 722, b = 120, baud rate = 112.8125 Gbaud;

[0119] Alternatively, W = 48, P = 34560, a = 721, b = 240, baud rate = 112.6563 Gbaud;

[0120] Or, W = 56, P = 5760, a = 727, b = 40, baud rate = 113.5938 Gbaud;

[0121] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0122] Alternatively, W = 56, P = 40320, a = 721, b = 280, baud rate = 112.6563 Gbaud;

[0123] Alternatively, W = 64, P = 5760, a = 728, b = 40, baud rate = 113.75 Gbaud;

[0124] Alternatively, W = 64, P = 11520, a = 724, b = 80, baud rate = 113.125 Gbaud;

[0125] Alternatively, W = 64, P = 23040, a = 722, b = 160, baud rate = 112.8125 Gbaud;

[0126] Alternatively, W = 64, P = 46080, a = 721, b = 320, baud rate = 112.6563 Gbaud;

[0127] Or, W = 120, P = 14400, a = 726, b = 100, baud rate = 113.4375 Gbaud;

[0128] Or, W = 120, P = 17280, a = 725, b = 120, baud rate = 113.2813 Gbaud;

[0129] Or, W = 120, P = 28800, a = 723, b = 200, baud rate = 112.9688 Gbaud;

[0130] Or, W = 120, P = 43200, a = 722, b = 300, baud rate = 112.8125 Gbaud;

[0131] Alternatively, W = 120, P = 86400, a = 721, b = 600, baud rate = 112.6563 Gbaud;

[0132] Or, W = 144, P = 11520, a = 729, b = 80, baud rate = 113.9063 Gbaud;

[0133] Alternatively, W = 144, P = 17280, a = 726, b = 120, baud rate = 113.4375 Gbaud;

[0134] Alternatively, W = 144, P = 25920, a = 724, b = 180, baud rate = 113.125 Gbaud;

[0135] Or, W = 144, P = 34560, a = 723, b = 240, baud rate = 112.9688 Gbaud;

[0136] Or, W = 144, P = 51840, a = 723, b = 360, baud rate = 112.8125 Gbaud;

[0137] Alternatively, W=144, P=103680, a=721, b=720, and baud rate=112.6563 Gbaud.

[0138] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud;

[0139] Alternatively, W = 56, P = 10080, a = 724, b = 70, baud rate = 113.125 Gbaud;

[0140] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0141] Alternatively, W=56, P=40320, a=721, b=280, and baud rate=112.6563 Gbaud.

[0142] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0143] In some possible implementations, the alignment indicator includes padding bits and / or a status field.

[0144] In some possible implementations, W is divisible by N.

[0145] In some possible implementations, the alignment identifier includes at least one target codeword, and the target codeword includes N bits.

[0146] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. It should be understood that the target codeword may also be referred to as an inner codeword, and selecting the alignment marker pattern as one or more inner codewords facilitates low-complexity frame and codeword synchronization at the receiving end.

[0147] In some possible implementations, the alignment marker is obtained by codeword interleaving of multiple target codewords. For example, each alignment marker is obtained by interleaving 8 target codewords through 8-way codewords. The codeword interleaving herein may also be referred to as channel interleaving. It should be understood that the alignment marker obtained by codeword interleaving of multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by codeword merging of multiple target codewords. For example, each alignment marker is obtained by codeword merging of 8 target codewords. The codeword merging herein may also be referred to as 1-way codeword interleaving.

[0148] In a third aspect, embodiments of the present application provide a data processing device, which is applied to a transmitting end and includes: a first data processing unit, a second data processing unit, and a third data processing unit. The first data processing unit is configured to perform first data processing on multiple first data streams that have undergone first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1. Each second data stream has undergone second FEC encoding, and each codeword after the second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. The second data processing unit is configured to perform second data processing on each of the m second data streams to obtain m third data streams, each third data stream including at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data stream, and W bits in each bit sequence are added alignment markers, where P = N × b, and b is an integer greater than or equal to 1. The third data processing unit is used to perform third data processing on m third data streams to obtain Y modulation symbol streams, where Y is an integer greater than or equal to 1, each modulation symbol stream is modulated, and the baud rate value of each modulation symbol stream is an integer multiple of the reference clock frequency value.

[0149] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0150] In some possible implementations, each second data stream undergoes convolutional interleaving before undergoing the second FEC encoding. Convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, and each storage unit is used to store d bits. Bits in the input data stream are sequentially input into the r delay lines according to the sequence of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the consecutive r*d bits in the output data stream include the d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0151] In some possible implementations, for every f bits output after convolutional interleaving, the input and output switches corresponding to the convolutional interleaver are located on the 0th delay line, and K×b is divisible by f. It is required that the input and output switches of the convolutional deinterleaver corresponding to the starting position of each frame (W+P bits) are located at the starting position of the switch, typically the topmost position. More specifically, for every f bits output by the convolutional interleaver and convolutional deinterleaver, their input and output switches are located at the topmost position, ensuring synchronization of the convolutional deinterleaver during frame synchronization.

[0152] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and the convolutional deinterleaver can output K×b bits per polling c times, and at this time, the input and output switch positions are at the starting positions of the switches, so that the convolutional deinterleaver synchronization can be guaranteed during frame synchronization.

[0153] In some possible implementations, the rate of the first data stream is 850 Gbps. a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

[0154] In some possible implementations, N=128, K=120, In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud; or, W=48, P=52224, a=726, b=408, baud rate=113.4375 Gbaud;

[0155] Alternatively, W = 56, P = 15232, a = 728, b = 119, baud rate = 113.75 Gbaud;

[0156] Alternatively, W = 56, P = 60928, a = 726, b = 476, baud rate = 113.4375 Gbaud;

[0157] Alternatively, W = 64, P = 13056, a = 728, b = 102, baud rate = 113.75 Gbaud;

[0158] Alternatively, W = 64, P = 69632, a = 726, b = 544, baud rate = 113.4375 Gbaud;

[0159] Alternatively, W = 120, P = 32640, a = 728, b = 255, baud rate = 113.75 Gbaud;

[0160] Alternatively, W = 120, P = 52224, a = 727, b = 408, baud rate = 113.5938 Gbaud;

[0161] Alternatively, W = 120, P = 130560, a = 726, b = 1020, baud rate = 113.4375 Gbaud;

[0162] Alternatively, W = 128, P = 34816, a = 728, b = 272, baud rate = 113.75 Gbaud;

[0163] Alternatively, W=128, P=139264, a=726, b=1088, and baud rate=113.4375 Gbaud.

[0164] In some possible implementations, N=170, K=160, In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud; or, W=48, P=69360, a=723, b=408, baud rate=112.9688 Gbaud;

[0165] Alternatively, W = 56, P = 11560, a = 726, b = 68, baud rate = 113.4375 Gbaud;

[0166] Alternatively, W = 56, P = 80920, a = 723, b = 476, baud rate = 112.9688 Gbaud;

[0167] Alternatively, W = 64, P = 92480, a = 723, b = 544, baud rate = 112.9688 Gbaud;

[0168] Alternatively, W = 120, P = 34680, a = 725, b = 204, baud rate = 113.2813 Gbaud;

[0169] Alternatively, W = 120, P = 57800, a = 724, b = 340, baud rate = 113.125 Gbaud;

[0170] Or, W = 120, P = 173400, a = 723, b = 1020, baud rate = 112.9688 Gbaud;

[0171] Alternatively, W = 170, P = 49130, a = 725, b = 289, baud rate = 113.2813 Gbaud;

[0172] Alternatively, W=170, P=245650, a=723, b=1445, and baud rate=112.9688 Gbaud.

[0173] In some possible implementations, N=144, K=136, In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud; or, W=48, P=8640, a=724, b=60, baud rate=113.125 Gbaud;

[0174] Or, W = 48, P = 11520, a = 723, b = 80, baud rate = 112.9688 Gbaud;

[0175] Alternatively, W = 48, P = 17280, a = 722, b = 120, baud rate = 112.8125 Gbaud;

[0176] Alternatively, W = 48, P = 34560, a = 721, b = 240, baud rate = 112.6563 Gbaud;

[0177] Or, W = 56, P = 5760, a = 727, b = 40, baud rate = 113.5938 Gbaud;

[0178] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0179] Alternatively, W = 56, P = 40320, a = 721, b = 280, baud rate = 112.6563 Gbaud;

[0180] Alternatively, W = 64, P = 5760, a = 728, b = 40, baud rate = 113.75 Gbaud;

[0181] Alternatively, W = 64, P = 11520, a = 724, b = 80, baud rate = 113.125 Gbaud;

[0182] Alternatively, W = 64, P = 23040, a = 722, b = 160, baud rate = 112.8125 Gbaud;

[0183] Alternatively, W = 64, P = 46080, a = 721, b = 320, baud rate = 112.6563 Gbaud;

[0184] Or, W = 120, P = 14400, a = 726, b = 100, baud rate = 113.4375 Gbaud;

[0185] Or, W = 120, P = 17280, a = 725, b = 120, baud rate = 113.2813 Gbaud;

[0186] Or, W = 120, P = 28800, a = 723, b = 200, baud rate = 112.9688 Gbaud;

[0187] Or, W = 120, P = 43200, a = 722, b = 300, baud rate = 112.8125 Gbaud;

[0188] Alternatively, W = 120, P = 86400, a = 721, b = 600, baud rate = 112.6563 Gbaud;

[0189] Or, W = 144, P = 11520, a = 729, b = 80, baud rate = 113.9063 Gbaud;

[0190] Alternatively, W = 144, P = 17280, a = 726, b = 120, baud rate = 113.4375 Gbaud;

[0191] Alternatively, W = 144, P = 25920, a = 724, b = 180, baud rate = 113.125 Gbaud;

[0192] Or, W = 144, P = 34560, a = 723, b = 240, baud rate = 112.9688 Gbaud;

[0193] Or, W = 144, P = 51840, a = 723, b = 360, baud rate = 112.8125 Gbaud;

[0194] Alternatively, W=144, P=103680, a=721, b=720, and baud rate=112.6563 Gbaud.

[0195] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud;

[0196] Alternatively, W = 56, P = 10080, a = 724, b = 70, baud rate = 113.125 Gbaud;

[0197] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0198] Alternatively, W=56, P=40320, a=721, b=280, and baud rate=112.6563 Gbaud.

[0199] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0200] In some possible implementations, N=128, K=120, and the baud rate of the modulation symbol stream is 113.4375 Gbaud.

[0201] In some possible implementations, P=1088×W.

[0202] In some possible implementations, the alignment marker includes at least one frame synchronization sequence with a length of 48 bits.

[0203] In some possible implementations, the 48 bits of the frame synchronization sequence are continuous in the alignment marker.

[0204] In some possible implementations, the values ​​of the 48 bits of the frame synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0205] In some possible implementations, the frame synchronization sequence includes two frame synchronization subsequences, each frame synchronization subsequence has a bit length of 24 bits, and the two frame synchronization subsequences are separated by 8 bits in the alignment identifier.

[0206] In some possible implementations, the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other of the two frame synchronization subsequences include 0x65, 0xB5, and 0xD9.

[0207] In some possible implementations, the alignment indicator includes padding bits and / or a status field.

[0208] In some possible implementations, W is divisible by N. In some possible implementations, each second data stream undergoes at least one of identification locking, channel deskew processing, and channel reordering before undergoing the second FEC encoding. And / or, each second data stream undergoes at least one of channel interleaving and scrambling after undergoing the second FEC encoding.

[0209] In some possible implementations, the first data processing unit is specifically configured to: perform second FEC encoding on each group of eight first data streams in the plurality of first data streams to obtain each group of eight encoded data streams, and perform channel interleaving on each group of eight encoded data streams to obtain one second data stream, thereby obtaining m second data streams.

[0210] In some possible implementations, N=128, K=120, and the first data processing unit is specifically configured to: obtain one inner codeword of 128 bits from each coded data stream in each group of eight coded data streams to obtain a total of eight inner codewords; and poll to obtain two bits from each of the eight inner codewords to obtain 1024 consecutive bits in the second data stream.

[0211] In some possible implementations, each second data stream is further cyclically shifted before being subjected to the second FEC encoding.

[0212] In some possible implementations, the first data processing unit is specifically configured to: perform convolution interleaving on each of the 8×m first data streams, perform cyclic shifting on each of the 8×m first data streams after the convolution interleaving, and perform second FEC encoding on each of the 8×m first data streams after the cyclic shifting.

[0213] In some possible implementations, the first data processing unit is specifically configured to: perform convolution interleaving on each of the 2×m first data streams; distribute each of the convolution interleaved first data streams to obtain four distributed first data streams, for a total of 8×m distributed first data streams; perform cyclic shifting on each of the 8×m distributed first data streams; and perform second FEC encoding on each of the 8×m cyclically shifted first data streams.

[0214] In some possible implementations, the first data processing unit is specifically configured to: perform convolution interleaving on each of the m first data streams; distribute each of the convolution interleaved first data streams to obtain eight distributed first data streams, for a total of 8×m distributed first data streams; perform cyclic shifting on each of the 8×m distributed first data streams; and perform second FEC encoding on each of the 8×m cyclically shifted first data streams.

[0215] In some possible implementations, the first data processing unit is specifically configured to: distribute each of the m first data streams to obtain eight distributed first data streams, for a total of 8×m distributed first data streams. Perform second FEC encoding on each of the 8×m distributed first data streams to obtain 8×m coded data streams. Perform codeword merging on each of the eight coded data streams in the 8×m coded data streams to obtain one second data stream, for a total of m second data streams. It should be understood that codeword merging on the eight coded data streams is equivalent to performing one-way Hamming codeword interleaver on the eight coded data streams.

[0216] In some possible implementations, the alignment identifier includes at least one target codeword, and the target codeword includes N bits.

[0217] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. It should be understood that the target codeword may also be referred to as an inner codeword, and selecting the alignment marker pattern as one or more inner codewords facilitates low-complexity frame and codeword synchronization at the receiving end.

[0218] In some possible implementations, the alignment marker is obtained by codeword interleaving of multiple target codewords. For example, each alignment marker is obtained by interleaving 8 target codewords through 8-way codewords. The codeword interleaving herein may also be referred to as channel interleaving. It should be understood that the alignment marker obtained by codeword interleaving of multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by codeword merging of multiple target codewords. For example, each alignment marker is obtained by codeword merging of 8 target codewords. The codeword merging herein may also be referred to as 1-way codeword interleaving.

[0219] In a fourth aspect, an embodiment of the present application provides a data processing device, which is applied to a receiving end and includes: a data processing unit and a synchronization unit; the data processing unit is configured to perform a fourth data processing on Y received modulation symbol streams to obtain m fourth data streams. Each fourth data stream is demodulated, and the Y modulation symbol streams are obtained by performing a third data processing on m third data streams. Each modulation symbol stream is modulated, and the m third data streams are obtained by performing a second data processing on m second data streams, respectively. The m second data streams are obtained by performing a first data processing on multiple first data streams that have undergone a first forward error correction (FEC) encoding. Y is an integer greater than or equal to 1, and m is an integer greater than 1. Each second data stream is second FEC-encoded, and each codeword after the second FEC encoding includes N bits, where N = K + S, where K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. Each third data stream includes at least one bit sequence, each bit sequence comprising P+W bits. The P bits in each bit sequence come from the second data stream, and the W bits in each bit sequence are added alignment markers. P = N × b, where b is an integer greater than or equal to 1. The baud rate of each modulation symbol stream is an integer multiple of the reference clock frequency. The synchronization unit is configured to perform frame synchronization on each fourth data stream based on the alignment marker in each fourth data stream.

[0220] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0221] In some possible implementations, each second data stream undergoes convolutional interleaving before undergoing the second FEC encoding. Convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, and each storage unit is used to store d bits. Bits in the input data stream are sequentially input into the r delay lines according to the sequence of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the consecutive r*d bits in the output data stream include the d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0222] In some possible implementations, for every f bits output after convolutional interleaving, the input and output switches corresponding to the convolutional interleaver are located on the 0th delay line, and K×b is divisible by f. It is required that the input and output switches of the convolutional deinterleaver corresponding to the starting position of each frame (W+P bits) are located at the starting position of the switch, typically the topmost position. More specifically, for every f bits output by the convolutional interleaver and convolutional deinterleaver, their input and output switches are located at the topmost position, ensuring synchronization of the convolutional deinterleaver during frame synchronization.

[0223] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and the convolutional deinterleaver can output K×b bits per polling c times, and at this time, the input and output switch positions are at the starting positions of the switches, so that the convolutional deinterleaver synchronization can be guaranteed during frame synchronization.

[0224] In some possible implementations, the rate of the first data stream is 850 Gbps. a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

[0225] In some possible implementations, N=128, K=120,

[0226] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud;

[0227] Alternatively, W = 48, P = 52224, a = 726, b = 408, baud rate = 113.4375 Gbaud;

[0228] Alternatively, W = 56, P = 15232, a = 728, b = 119, baud rate = 113.75 Gbaud;

[0229] Alternatively, W = 56, P = 60928, a = 726, b = 476, baud rate = 113.4375 Gbaud;

[0230] Alternatively, W = 64, P = 13056, a = 728, b = 102, baud rate = 113.75 Gbaud;

[0231] Alternatively, W = 64, P = 69632, a = 726, b = 544, baud rate = 113.4375 Gbaud;

[0232] Alternatively, W = 120, P = 32640, a = 728, b = 255, baud rate = 113.75 Gbaud;

[0233] Alternatively, W = 120, P = 52224, a = 727, b = 408, baud rate = 113.5938 Gbaud;

[0234] Alternatively, W = 120, P = 130560, a = 726, b = 1020, baud rate = 113.4375 Gbaud;

[0235] Alternatively, W = 128, P = 34816, a = 728, b = 272, baud rate = 113.75 Gbaud;

[0236] Alternatively, W=128, P=139264, a=726, b=1088, and baud rate=113.4375 Gbaud.

[0237] In some possible implementations, N=170, K=160,

[0238] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud;

[0239] Alternatively, W = 48, P = 69360, a = 723, b = 408, baud rate = 112.9688 Gbaud;

[0240] Alternatively, W = 56, P = 11560, a = 726, b = 68, baud rate = 113.4375 Gbaud;

[0241] Alternatively, W = 56, P = 80920, a = 723, b = 476, baud rate = 112.9688 Gbaud;

[0242] Alternatively, W = 64, P = 92480, a = 723, b = 544, baud rate = 112.9688 Gbaud;

[0243] Alternatively, W = 120, P = 34680, a = 725, b = 204, baud rate = 113.2813 Gbaud;

[0244] Alternatively, W = 120, P = 57800, a = 724, b = 340, baud rate = 113.125 Gbaud;

[0245] Or, W = 120, P = 173400, a = 723, b = 1020, baud rate = 112.9688 Gbaud;

[0246] Alternatively, W = 170, P = 49130, a = 725, b = 289, baud rate = 113.2813 Gbaud;

[0247] Alternatively, W=170, P=245650, a=723, b=1445, and baud rate=112.9688 Gbaud.

[0248] In some possible implementations, N=144, K=136,

[0249] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud;

[0250] Alternatively, W = 48, P = 8640, a = 724, b = 60, baud rate = 113.125 Gbaud;

[0251] Or, W = 48, P = 11520, a = 723, b = 80, baud rate = 112.9688 Gbaud;

[0252] Alternatively, W = 48, P = 17280, a = 722, b = 120, baud rate = 112.8125 Gbaud;

[0253] Alternatively, W = 48, P = 34560, a = 721, b = 240, baud rate = 112.6563 Gbaud;

[0254] Or, W = 56, P = 5760, a = 727, b = 40, baud rate = 113.5938 Gbaud;

[0255] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0256] Alternatively, W = 56, P = 40320, a = 721, b = 280, baud rate = 112.6563 Gbaud;

[0257] Alternatively, W = 64, P = 5760, a = 728, b = 40, baud rate = 113.75 Gbaud;

[0258] Alternatively, W = 64, P = 11520, a = 724, b = 80, baud rate = 113.125 Gbaud;

[0259] Alternatively, W = 64, P = 23040, a = 722, b = 160, baud rate = 112.8125 Gbaud;

[0260] Alternatively, W = 64, P = 46080, a = 721, b = 320, baud rate = 112.6563 Gbaud;

[0261] Or, W = 120, P = 14400, a = 726, b = 100, baud rate = 113.4375 Gbaud;

[0262] Or, W = 120, P = 17280, a = 725, b = 120, baud rate = 113.2813 Gbaud;

[0263] Or, W = 120, P = 28800, a = 723, b = 200, baud rate = 112.9688 Gbaud;

[0264] Or, W = 120, P = 43200, a = 722, b = 300, baud rate = 112.8125 Gbaud;

[0265] Alternatively, W = 120, P = 86400, a = 721, b = 600, baud rate = 112.6563 Gbaud;

[0266] Or, W = 144, P = 11520, a = 729, b = 80, baud rate = 113.9063 Gbaud;

[0267] Alternatively, W = 144, P = 17280, a = 726, b = 120, baud rate = 113.4375 Gbaud;

[0268] Alternatively, W = 144, P = 25920, a = 724, b = 180, baud rate = 113.125 Gbaud;

[0269] Or, W = 144, P = 34560, a = 723, b = 240, baud rate = 112.9688 Gbaud;

[0270] Or, W = 144, P = 51840, a = 723, b = 360, baud rate = 112.8125 Gbaud;

[0271] Alternatively, W=144, P=103680, a=721, b=720, and baud rate=112.6563 Gbaud.

[0272] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud;

[0273] Alternatively, W = 56, P = 10080, a = 724, b = 70, baud rate = 113.125 Gbaud;

[0274] Alternatively, W = 56, P = 20160, a = 722, b = 140, baud rate = 112.8125 Gbaud;

[0275] Alternatively, W=56, P=40320, a=721, b=280, and baud rate=112.6563 Gbaud.

[0276] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0277] In some possible implementations, the alignment indicator includes padding bits and / or a status field.

[0278] In some possible implementations, W is divisible by N.

[0279] In some possible implementations, the alignment identifier includes at least one target codeword, and the target codeword includes N bits.

[0280] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. It should be understood that the target codeword may also be referred to as an inner codeword, and selecting the alignment marker pattern as one or more inner codewords facilitates low-complexity frame and codeword synchronization at the receiving end.

[0281] In some possible implementations, the alignment marker is obtained by codeword interleaving of multiple target codewords. For example, each alignment marker is obtained by interleaving 8 target codewords through 8-way codewords. The codeword interleaving herein may also be referred to as channel interleaving. It should be understood that the alignment marker obtained by codeword interleaving of multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by codeword merging of multiple target codewords. For example, each alignment marker is obtained by codeword merging of 8 target codewords. The codeword merging herein may also be referred to as 1-way codeword interleaving.

[0282] In a fifth aspect, an embodiment of the present application provides a data processing method, which is applied to a transmitting end and includes the following steps. First, m first data streams encoded with a first forward error correction (FEC) are subjected to first data processing to obtain m second data streams. Wherein, m is an integer greater than 1, each second data stream includes at least one first bit sequence, and each first bit sequence includes bits, each first bit in the sequence bits come from the first data stream, and each of the first bit sequences bits are added as the first identifier. Next, the second data processing is performed on the m second data streams to obtain m third data streams. The second data processing includes a second FEC encoding. Each codeword after the second FEC encoding includes N bits, N = K + S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. Furthermore, third data processing is performed on the m third data streams to obtain Y modulation symbol streams. Y is an integer greater than or equal to 1, each modulation symbol stream is modulated, and the baud rate of each modulation symbol stream is an integer multiple of the reference clock frequency.

[0283] In the embodiment of the present application, the data stream after the outer code is periodically inserted into the first identifier and then the inner code is encoded. Specifically, the periodic acquisition of the first identifier from the data stream after the outer code is obtained bits and insert The first identifier of the bit length makes each bits exist The first identifier of the length of bits. This application selects a positive integer and The baud rate of the modulated symbol data stream can be made an integer multiple of the reference clock frequency (referenceclock), making it easier to implement clock extraction and clock synchronization at the receiving end, enabling fast phase locking, low PLL complexity and small jitter. Further selecting a positive integer and can be divided by the inner code information length K, so that the frame synchronization and code word synchronization operations of the receiving end processing module have lower hardware implementation complexity. At the same time, further select the positive integer The synchronization of the inner codewords can ensure the synchronization of the cascade deinterleaving. In other words, the data processing method provided by the present application material reduces the complexity of the receiving end processing module in performing frame synchronization, inner codeword synchronization and cascade deinterleaving synchronization.

[0284] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of bits are obtained through the second FEC encoding, the W bits in each second bit sequence are the second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

[0285] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0286] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0287] In some possible embodiments, each first data stream is further subjected to convolution interleaving, and the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the bits in the input data stream are input into the r delay lines in sequence according to the sequence numbers of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the consecutive r*d bits in the data stream output include d bits output by each delay line, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0288] In some possible implementations, after convolution interleaving, every time f bits are output, the input and output switches corresponding to the convolution interleaving are located in the 0th delay line, and K×b is divisible by f.

[0289] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0290] In some possible implementations,

[0291] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and Divisible by 7.

[0292] In some possible implementations, b=629×e.

[0293] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (148, 140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 140 information bits to obtain 70 bits, and then performs Hamming (78, 70) encoding on the 70 bits to obtain S = 8 parity bits. The codeword with a length of 148 bits obtained by the second FEC encoding includes K = 140 information bits and S = 8 parity bits.

[0294] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and Divisible by 3.

[0295] In some possible implementations, b=2159×e.

[0296] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (127, 120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 120 information bits to obtain 60 bits, and then performs Hamming (67, 60) encoding on the 60 bits to obtain S = 7 parity bits. The codeword with a length of 127 bits obtained by the second FEC encoding includes K = 120 information bits and S = 7 parity bits.

[0297] In some possible implementations, the first data processing further includes scrambling.

[0298] In some possible implementations, the third data processing further includes codeword interleaving, wherein t codewords are interleaved to obtain an interleaved sequence comprising t×N bits, wherein the i-th codeword among the t codewords comprises a K-bit information sequence B i and a check sequence P of S bits i , 0≤i≤t-1, the interleaved sequence contains a first subsequence of consecutive t×K bits and a second subsequence of consecutive t×S bits, the first subsequence contains B0, B1, B2, ..., B t；1 There are t information sequences in total, and the second subsequence contains P0, P1, P2, ..., P t；1 There are t check sequences in total.

[0299] In some possible implementations, the baud rate of the modulation symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

[0300] In some possible implementations, N=128, K=120, and the baud rate of the modulation symbol stream is 113.4375 Gbaud.

[0301] In some possible implementations,

[0302] In some possible implementations, performing third data processing on the m third data streams to obtain Y modulation symbol streams includes: performing channel interleaving on each group of eight third data streams in the m third data streams to obtain one fourth data stream, thereby obtaining a total of Y fourth data streams. And modulating the Y fourth data streams to obtain the Y modulation symbol streams.

[0303] In some possible implementations, the first identifier in each second data stream includes a length of The synchronization subsequence is located in the first mark starting from the starting position. bits.

[0304] In some possible implementations, A group of 8 third data streams among the m third data streams are obtained by a group of 8 second data streams among the m second data streams through second FEC encoding, and a fourth data stream obtained by channel interleaving of the group of 8 third data streams includes a synchronization sequence with a length of 48 bits. The synchronization sequence with a length of 48 bits is continuous in the 1 fourth data stream. The synchronization sequence with a length of 48 bits includes 1 synchronization subsequence included in each of the group of 8 second data streams, totaling 8 synchronization subsequences.

[0305] In some possible implementations, the values ​​of the 48 bits of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0306] In some possible implementations, the synchronization subsequence 0 included in the 0th second data stream in a group of 8 second data streams is 010110;

[0307] The synchronization subsequence 1 included in the first second data stream in a group of eight second data streams is 011010;

[0308] The synchronization subsequence 2 included in the second second data stream in a group of 8 second data streams is 100111;

[0309] The synchronization subsequence 3 included in the third second data stream in a group of eight second data streams is 010001;

[0310] The synchronization subsequence 4 included in the fourth second data stream in a group of eight second data streams is 011010;

[0311] The synchronization subsequence 5 included in the fifth second data stream in a group of eight second data streams is 011001;

[0312] The synchronization subsequence 6 included in the sixth second data stream in a group of eight second data streams is 000110;

[0313] The synchronization subsequence 7 included in the seventh second data stream in a group of eight second data streams is 101011.

[0314] In some possible implementations, a group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on a group of eight second data streams among the m second data streams. The 0th second data stream, the 1st second data stream, the 2nd second data stream, and the 3rd second data stream among the group of eight second data streams each include a synchronization subsequence of 8 bits in length. The 4th second data stream, the 5th second data stream, the 6th second data stream, and the 7th second data stream among the group of eight second data streams each include a synchronization subsequence of 4 bits in length, wherein the first two bits and the last two bits of the 4-bit synchronization subsequence are separated by 2 bits.

[0315] In some possible embodiments, a fourth data stream obtained by channel interleaving of a group of 8 third data streams includes a synchronization sequence with a length of 48 bits, and the synchronization sequence with a length of 48 bits includes a synchronization subsequence included in each of a group of 8 second data streams, totaling 8 synchronization subsequences, and there is an interval of 8 bits between the first 24 bits and the last 24 bits in the synchronization sequence with a length of 48 bits.

[0316] In some possible implementations, the values ​​of the first 24 bits in the 48-bit synchronization sequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit synchronization sequence include 0x65, 0xB5, and 0xD9.

[0317] In some possible implementations, the synchronization subsequence 0 included in the 0th second data stream in a group of 8 second data streams is 01011010;

[0318] The synchronization subsequence 1 included in the first second data stream in a group of 8 second data streams is 01101001;

[0319] The synchronization subsequence 2 included in the second second data stream in a group of 8 second data streams is 10010110;

[0320] The synchronization subsequence 3 included in the third second data stream in a group of eight second data streams is 01001011;

[0321] The synchronization subsequence 4 included in the fourth second data stream in a group of eight second data streams is 0110;

[0322] The synchronization subsequence 5 included in the fifth second data stream in a group of eight second data streams is 0110;

[0323] The synchronization subsequence 6 included in the sixth second data stream in a group of eight second data streams is 0011;

[0324] The synchronization subsequence 7 included in the seventh second data stream in a group of eight second data streams is 1001.

[0325] In some possible implementations, the first identifier in each second data stream includes a synchronization subsequence with a length of 48 bits, wherein the interval between the first 24 bits and the last 24 bits in the synchronization subsequence is 8 bits.

[0326] In some possible implementations, the values ​​of the first 24 bits in the 48-bit synchronization subsequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit synchronization subsequence include 0x65, 0xB5, and 0xD9.

[0327] In some possible implementations, N=128, K=120, and performing channel interleaving on each group of eight third data streams to obtain one fourth data stream includes: obtaining one inner codeword of 128 bits from each third data stream in each group of eight third data streams to obtain a total of eight inner codewords. Polling to obtain two bits from each of the eight inner codewords to obtain 1024 consecutive bits in the fourth data stream.

[0328] In some possible implementations, performing the first data processing on the m first data streams includes: performing cyclic shift on each of the m first data streams.

[0329] In some possible implementations, before performing cyclic shift on the m first data streams, performing first data processing on the m first data streams includes: performing convolution interleaving on the m first data streams.

[0330] In some possible implementations, before cyclically shifting the m first data streams, the method further includes: performing convolution interleaving on the m / 4 input data streams, distributing each of the convolution interleaved input data streams to obtain four first data streams, thereby obtaining a total of m first data streams.

[0331] In some possible implementations, before cyclically shifting the m first data streams, the method further includes: performing convolution interleaving on the m / 8 input data streams, distributing each of the convolution interleaved input data streams to obtain 8 first data streams, thereby obtaining a total of m first data streams.

[0332] In a sixth aspect, an embodiment of the present application provides a data processing method, which is applied to a receiving end and includes the following steps. First, the fourth data processing is performed on the received Y modulation symbol streams to obtain m fourth data streams. Wherein, Y is an integer greater than or equal to 1, each fourth data stream is demodulated, the baud rate value of each modulation symbol stream is an integer multiple of the reference clock frequency value, and the Y modulation symbol streams are obtained by performing the third data processing on the m third data streams, and each modulation symbol stream is modulated. The m third data streams are obtained by performing the second data processing on the m second data streams, and the m second data streams are obtained by performing the first data processing on the m first data streams that have been encoded by the first forward error correction FEC. m is an integer greater than 1, and each second data stream includes at least one first bit sequence, and each first bit sequence includes bits, each first bit in the sequence bits come from the first data stream, and each of the first bit sequences bits are added as the first identifier, the second data processing includes a second FEC encoding, each codeword after the second FEC encoding includes N bits, N=K+S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. Furthermore, codeword synchronization and / or frame synchronization are performed on each fourth data stream.

[0333] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of bits are obtained through the second FEC encoding, the W bits in each second bit sequence are the second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

[0334] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0335] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0336] In some possible embodiments, each first data stream is further subjected to convolution interleaving, and the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the bits in the input data stream are input into the r delay lines in sequence according to the sequence numbers of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the consecutive r*d bits in the data stream output include d bits output by each delay line, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0337] In some possible implementations, after convolution interleaving, every time f bits are output, the input and output switches corresponding to the convolution interleaving are located in the 0th delay line, and K×b is divisible by f.

[0338] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0339] In some possible implementations,

[0340] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and Divisible by 7.

[0341] In some possible implementations, b=629×e.

[0342] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (148, 140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 140 information bits to obtain 70 bits, and then performs Hamming (78, 70) encoding on the 70 bits to obtain S = 8 parity bits. The codeword with a length of 148 bits obtained by the second FEC encoding includes K = 140 information bits and S = 8 parity bits.

[0343] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and Divisible by 3.

[0344] In some possible implementations, b=2159×e.

[0345] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (127, 120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 120 information bits to obtain 60 bits, and then performs Hamming (67, 60) encoding on the 60 bits to obtain S = 7 parity bits. The codeword with a length of 127 bits obtained by the second FEC encoding includes K = 120 information bits and S = 7 parity bits.

[0346] In some possible implementations, the first data processing further includes scrambling.

[0347] In some possible implementations, the third data processing further includes codeword interleaving, wherein t codewords are interleaved to obtain an interleaved sequence comprising t×N bits, wherein the i-th codeword among the t codewords comprises a K-bit information sequence B i and a check sequence P of S bits i , 0≤i≤t-1, the interleaved sequence contains a first subsequence of consecutive t×K bits and a second subsequence of consecutive t×S bits, the first subsequence contains B0, B1, B2, ..., B t；1 There are t information sequences in total, and the second subsequence contains P0, P1, P2, ..., P t；1 There are t check sequences in total.

[0348] In a seventh aspect, an embodiment of the present application provides a data processing device. The data processing device includes: a first data processing unit, a second data processing unit, and a third data processing unit. The first data processing unit is used to: perform first data processing on m first data streams that have been encoded by the first forward error correction (FEC) to obtain m second data streams, where m is an integer greater than 1, and each second data stream includes at least one first bit sequence, and each first bit sequence includes bits, each first bit in the sequence bits come from the first data stream, and each of the first bit sequences bits are added as the first identifier. The second data processing unit is used to: perform second data processing on the m second data streams to obtain m third data streams, the second data processing includes second FEC encoding, each codeword after the second FEC encoding includes N bits, N = K + S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, S is an integer greater than or equal to 1, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. The third data processing unit is configured to perform third data processing on the m third data streams to obtain Y modulation symbol streams, where Y is an integer greater than or equal to 1, each modulation symbol stream is modulated, and a baud rate value of each modulation symbol stream is an integer multiple of a reference clock frequency value.

[0349] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of bits are obtained through the second FEC encoding, the W bits in each second bit sequence are the second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

[0350] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0351] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0352] In some possible embodiments, each first data stream is further subjected to convolution interleaving, and the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the bits in the input data stream are input into the r delay lines in sequence according to the sequence numbers of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the consecutive r*d bits in the data stream output include d bits output by each delay line, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0353] In some possible implementations, after convolution interleaving, every time f bits are output, the input and output switches corresponding to the convolution interleaving are located in the 0th delay line, and K×b is divisible by f.

[0354] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0355] In some possible implementations,

[0356] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and Divisible by 7.

[0357] In some possible implementations, b=629×e.

[0358] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (148, 140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 140 information bits to obtain 70 bits, and then performs Hamming (78, 70) encoding on the 70 bits to obtain S = 8 parity bits. The codeword with a length of 148 bits obtained by the second FEC encoding includes K = 140 information bits and S = 8 parity bits.

[0359] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and Divisible by 3.

[0360] In some possible implementations, b=2159×e.

[0361] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (127, 120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 120 information bits to obtain 60 bits, and then performs Hamming (67, 60) encoding on the 60 bits to obtain S = 7 parity bits. The codeword with a length of 127 bits obtained by the second FEC encoding includes K = 120 information bits and S = 7 parity bits.

[0362] In some possible implementations, the first data processing further includes scrambling.

[0363] In some possible implementations, the third data processing further includes codeword interleaving, wherein t codewords are interleaved to obtain an interleaved sequence comprising t×N bits, wherein the i-th codeword among the t codewords comprises a K-bit information sequence B i and a check sequence P of S bits i , 0≤i≤t-1, the interleaved sequence contains a first subsequence of consecutive t×K bits and a second subsequence of consecutive t×S bits, the first subsequence contains B0, B1, B2, ..., B t；1 There are t information sequences in total, and the second subsequence contains P0, P1, P2, ..., P t；1 There are t check sequences in total.

[0364] In some possible implementations, the baud rate of the modulation symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

[0365] In some possible implementations, N=128, K=120, and the baud rate of the modulation symbol stream is 113.4375 Gbaud.

[0366] In some possible implementations,

[0367] In some possible implementations, the third data processing unit is specifically configured to: perform channel interleaving on each group of eight third data streams in the m third data streams to obtain one fourth data stream, thereby obtaining a total of Y fourth data streams. And perform modulation on the Y fourth data streams to obtain Y modulation symbol streams.

[0368] In some possible implementations, the first identifier in each second data stream includes a length of The synchronization subsequence is located in the first mark starting from the starting position. bits.

[0369] In some possible implementations, A group of 8 third data streams among the m third data streams are obtained by a group of 8 second data streams among the m second data streams through second FEC encoding, and a fourth data stream obtained by channel interleaving of the group of 8 third data streams includes a synchronization sequence with a length of 48 bits. The synchronization sequence with a length of 48 bits is continuous in the 1 fourth data stream. The synchronization sequence with a length of 48 bits includes 1 synchronization subsequence included in each of the group of 8 second data streams, totaling 8 synchronization subsequences.

[0370] In some possible implementations, the values ​​of the 48 bits of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0371] In some possible implementations, the synchronization subsequence 0 included in the 0th second data stream in a group of 8 second data streams is 010110;

[0372] The synchronization subsequence 1 included in the first second data stream in a group of eight second data streams is 011010;

[0373] The synchronization subsequence 2 included in the second second data stream in a group of 8 second data streams is 100111;

[0374] The synchronization subsequence 3 included in the third second data stream in a group of eight second data streams is 010001;

[0375] The synchronization subsequence 4 included in the fourth second data stream in a group of eight second data streams is 011010;

[0376] The synchronization subsequence 5 included in the fifth second data stream in a group of eight second data streams is 011001;

[0377] The synchronization subsequence 6 included in the sixth second data stream in a group of eight second data streams is 000110;

[0378] The synchronization subsequence 7 included in the seventh second data stream in a group of eight second data streams is 101011.

[0379] In some possible implementations, a group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on a group of eight second data streams among the m second data streams. The 0th second data stream, the 1st second data stream, the 2nd second data stream, and the 3rd second data stream among the group of eight second data streams each include a synchronization subsequence of 8 bits in length. The 4th second data stream, the 5th second data stream, the 6th second data stream, and the 7th second data stream among the group of eight second data streams each include a synchronization subsequence of 4 bits in length, wherein the first two bits and the last two bits of the 4-bit synchronization subsequence are separated by 2 bits.

[0380] In some possible embodiments, a fourth data stream obtained by channel interleaving of a group of 8 third data streams includes a synchronization sequence with a length of 48 bits, and the synchronization sequence with a length of 48 bits includes a synchronization subsequence included in each of a group of 8 second data streams, totaling 8 synchronization subsequences, and there is an interval of 8 bits between the first 24 bits and the last 24 bits in the synchronization sequence with a length of 48 bits.

[0381] In some possible implementations, the values ​​of the first 24 bits in the 48-bit synchronization sequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit synchronization sequence include 0x65, 0xB5, and 0xD9.

[0382] In some possible implementations, the synchronization subsequence 0 included in the 0th second data stream in a group of 8 second data streams is 01011010;

[0383] The synchronization subsequence 1 included in the first second data stream in a group of 8 second data streams is 01101001;

[0384] The synchronization subsequence 2 included in the second second data stream in a group of 8 second data streams is 10010110;

[0385] The synchronization subsequence 3 included in the third second data stream in a group of eight second data streams is 01001011;

[0386] The synchronization subsequence 4 included in the fourth second data stream in a group of eight second data streams is 0110;

[0387] The synchronization subsequence 5 included in the fifth second data stream in a group of eight second data streams is 0110;

[0388] The synchronization subsequence 6 included in the sixth second data stream in a group of eight second data streams is 0011;

[0389] The synchronization subsequence 7 included in the seventh second data stream in a group of eight second data streams is 1001.

[0390] In some possible implementations, the first identifier in each second data stream includes a synchronization subsequence with a length of 48 bits, wherein the interval between the first 24 bits and the last 24 bits in the synchronization subsequence is 8 bits.

[0391] In some possible implementations, the values ​​of the first 24 bits in the 48-bit synchronization subsequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit synchronization subsequence include 0x65, 0xB5, and 0xD9.

[0392] In some possible implementations, N=128, K=120, and the third data processing unit is specifically configured to: obtain one inner codeword of 128 bits from each third data stream in each group of eight third data streams to obtain a total of eight inner codewords; and poll to obtain two bits from each of the eight inner codewords to obtain 1024 consecutive bits in the fourth data stream.

[0393] In some possible implementations, the first data processing unit is specifically configured to perform cyclic shift on each of the m first data streams.

[0394] In some possible implementations, before performing cyclic shift on the m first data streams respectively, the first data processing unit is specifically configured to: perform convolution interleaving on the m first data streams respectively.

[0395] In some possible implementations, the data processing apparatus further includes a convolutional interleaving unit and a distribution unit. The convolutional interleaving unit is configured to perform convolutional interleaving on each of the m / 4 input data streams before cyclically shifting each of the m first data streams. The distribution unit is configured to distribute each of the convolutionally interleaved input data streams to obtain four first data streams, resulting in a total of m first data streams.

[0396] In some possible implementations, the data processing apparatus further includes a convolutional interleaving unit and a distribution unit. The convolutional interleaving unit is configured to perform convolutional interleaving on each of the m / 8 input data streams before cyclically shifting each of the m first data streams. The distribution unit is configured to distribute each of the convolutionally interleaved input data streams to obtain eight first data streams, resulting in a total of m first data streams.

[0397] In an eighth aspect, an embodiment of the present application provides a data processing device. The data processing device includes: a data processing unit and a synchronization unit;

[0398] The data processing unit is used to: perform fourth data processing on the received Y modulation symbol streams to obtain m fourth data streams, wherein Y is an integer greater than or equal to 1, each fourth data stream is demodulated, the baud rate value of each modulation symbol stream is an integer multiple of the reference clock frequency value, the Y modulation symbol streams are obtained by performing third data processing on m third data streams, each modulation symbol stream is modulated, the m third data streams are obtained by performing second data processing on m second data streams, the m second data streams are obtained by performing first data processing on m first data streams that have been encoded by the first forward error correction FEC, m is an integer greater than 1, each second data stream includes at least one first bit sequence, and each first bit sequence includes bits, each first bit in the sequence bits come from the first data stream, and each of the first bit sequences bits are added as the first identifier, the second data processing includes a second FEC encoding, each codeword after the second FEC encoding includes N bits, N=K+S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. The synchronization unit is configured to perform codeword synchronization and / or frame synchronization on each fourth data stream.

[0399] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of bits are obtained through the second FEC encoding, the W bits in each second bit sequence are the second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

[0400] In some possible implementations, the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

[0401] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0402] In some possible embodiments, each first data stream is further subjected to convolution interleaving, and the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the bits in the input data stream are input into the r delay lines in sequence according to the sequence numbers of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the consecutive r*d bits in the data stream output include d bits output by each delay line, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0403] In some possible implementations, after convolution interleaving, every time f bits are output, the input and output switches corresponding to the convolution interleaving are located in the 0th delay line, and K×b is divisible by f.

[0404] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0405] In some possible implementations,

[0406] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and Divisible by 7.

[0407] In some possible implementations, b=629×e.

[0408] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (148, 140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 140 information bits to obtain 70 bits, and then performs Hamming (78, 70) encoding on the 70 bits to obtain S = 8 parity bits. The codeword with a length of 148 bits obtained by the second FEC encoding includes K = 140 information bits and S = 8 parity bits.

[0409] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and Divisible by 3.

[0410] In some possible implementations, b=2159×e.

[0411] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming (127, 120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs bit-wise exclusive-OR on every two consecutive information bits of K = 120 information bits to obtain 60 bits, and then performs Hamming (67, 60) encoding on the 60 bits to obtain S = 7 parity bits. The codeword with a length of 127 bits obtained by the second FEC encoding includes K = 120 information bits and S = 7 parity bits.

[0412] In some possible implementations, the first data processing further includes scrambling.

[0413] In some possible implementations, the third data processing further includes codeword interleaving, wherein t codewords are interleaved to obtain an interleaved sequence comprising t×N bits, wherein the i-th codeword among the t codewords comprises a K-bit information sequence B i and a check sequence P of S bits i , 0≤i≤t-1, the interleaved sequence contains a first subsequence of consecutive t×K bits and a second subsequence of consecutive t×S bits, the first subsequence contains B0, B1, B2, ..., B t；1 There are t information sequences in total, and the second subsequence contains P0, P1, P2, ..., P t；1 There are t check sequences in total.

[0414] In an embodiment of the present application, an alignment marker is periodically inserted into the data stream after cascade FEC encoding. Specifically, P bits are periodically extracted from the data stream after cascade FEC encoding, and an alignment marker of W bits in length is inserted, so that there is a W-bit alignment marker for every P+W bits in the data stream. By selecting positive integers P and W, the baud rate of the modulated symbol data stream can be an integer multiple of the Ethernet common reference clock frequency. This simplifies the clock extraction and synchronization method at the receiving end, allowing for fast phase lock, low PLL complexity, and low jitter. Furthermore, P is required to be a multiple of the inner code length N, that is, P = N × b. After the receiving end performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also known as marker locking operation), the inner code codeword synchronization can be guaranteed, simplifying the frame synchronization and inner codeword synchronization operations at the receiving end and achieving low implementation complexity. In addition, the convolution interleaver and convolution deinterleaver output f bits each time, and their input and output switch positions are located at the top, and K×b can be divided by f, so that the convolution deinterleaver synchronization can be guaranteed during frame synchronization.

[0415] The present application also provides another embodiment, in which the data stream after the outer code is periodically inserted into the first identifier and then the inner code is encoded. Specifically, the periodic acquisition of the first identifier from the data stream after the outer code is encoded is performed. bits and insert The first identifier of the bit length makes each bits exist The first identifier of the length of bits. This application selects a positive integer and The baud rate of the modulated symbol data stream can be made an integer multiple of the reference clock frequency, making it easier for the receiver to extract and synchronize the clock, and enabling fast phase locking, low PLL complexity, and low jitter. and can be divided by the inner code information length K, so that the frame synchronization and code word synchronization operations of the receiving end processing module have lower hardware implementation complexity. At the same time, further select the positive integer The synchronization of the inner codewords can ensure the synchronization of the cascade deinterleaving. In other words, the data processing method provided by the present application material reduces the complexity of the receiving end processing module in performing frame synchronization, inner codeword synchronization and cascade deinterleaving synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0416] Figure 1 A schematic diagram of a communication system used in an embodiment of the present application;

[0417] Figure 2(a) shows Figure 1 A schematic diagram of a data transmission process in the communication system shown;

[0418] FIG2( b ) is a schematic diagram of another communication system used in an embodiment of the present application;

[0419] Figure 3 A flowchart of a data processing method provided in an embodiment of the present application;

[0420] FIG4( a ) is a schematic diagram of a first structure of a convolutional interleaver in an embodiment of the present application;

[0421] FIG4( b ) is a schematic diagram of a second structure of a convolutional interleaver in an embodiment of the present application;

[0422] FIG5( a ) is a schematic diagram of a structure of a third data stream in an embodiment of the present application;

[0423] FIG5( b ) is another schematic diagram of the structure of the third data stream in an embodiment of the present application;

[0424] Figure 6Another flowchart of the data processing method provided in the embodiment of the present application;

[0425] Figure 7 A schematic diagram of another flow chart of the data processing method provided in an embodiment of the present application;

[0426] Figure 8 This is a structural diagram of the second data stream in an embodiment of the present application;

[0427] Figure 9 This is a structural diagram of the third data stream in an embodiment of the present application;

[0428] Figure 10 This is a schematic diagram of an implementation method of internal code encoding in an embodiment of the present application;

[0429] Figure 11 This is a schematic diagram of another implementation of internal code encoding in the embodiment of the present application;

[0430] Figure 12 Schematic diagram of the structure of a codeword;

[0431] Figure 13 Schematic diagram of the structure of another codeword;

[0432] Figure 14 This is a schematic diagram of an implementation method of data processing in the embodiments of this application;

[0433] Figure 15 A schematic diagram of the structure of an alignment mark in an embodiment of the present application;

[0434] Figure 16 A schematic diagram of a computer architecture for synchronization;

[0435] Figure 17 This is another structural diagram of the alignment mark in the embodiment of the present application;

[0436] Figure 18 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0437] Figure 19 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0438] Figure 20 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0439] Figure 21 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0440] FIG22( a ) is a schematic diagram of another embodiment of data processing in the present application;

[0441] FIG22( b ) is a schematic diagram of another implementation of data processing in an embodiment of the present application;

[0442] FIG22( c ) is a schematic diagram of another implementation method of data processing in an embodiment of the present application;

[0443] FIG22( d ) is a schematic diagram of an implementation method for generating an alignment mark in an embodiment of the present application;

[0444] Figure 23 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0445] Figure 24 A schematic diagram of the structure of the first identifier in the embodiment of the present application;

[0446] Figure 25 A schematic diagram of the structure of a synchronization sequence after channel interleaving in an embodiment of the present application;

[0447] Figure 26 This is another structural diagram of the first identifier in the embodiment of the present application;

[0448] Figure 27 This is another structural diagram of a synchronization sequence after channel interleaving in an embodiment of the present application;

[0449] Figure 28 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0450] Figure 29 This is another structural diagram of the first identifier in the embodiment of the present application;

[0451] Figure 30 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0452] Figure 31 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0453] Figure 32 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0454] Figure 33 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application;

[0455] Figure 34 This is a structural diagram of a data processing device applied to a sending end in an embodiment of the present application;

[0456] Figure 35 This is a structural diagram of a data processing device applied to a receiving end in an embodiment of the present application;

[0457] Figure 36 This is another structural diagram of the data processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0458] The embodiments of the present application provide a data processing method and a data processing device. On the one hand, they simplify the way the receiving end performs clock extraction and synchronization, enabling fast phase locking, low PLL complexity and low jitter. On the other hand, they simplify operations such as frame synchronization and inner codeword synchronization at the receiving end, achieving low implementation complexity. It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects, rather than to define a specific order or precedence. It should be understood that the above terms are interchangeable where appropriate, so that the embodiments described in this application can be implemented in an order other than that described in this application. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0459] Figure 1 This is a schematic diagram of a communication system used in the embodiment of this application. Figure 1 As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, transmitting device 01 and receiving device 05 can be devices such as switches or routers. Transmitting device 01 is also called a host chip at the transmitting end, while receiving device 05 is also called a host chip at the receiving end. Channel transmission medium 03 can be an optical fiber. The host chip is sometimes also called a host device. Transmitting device 01 and transmitting processing module 02 can be connected via an attachment unit interface (AUI), and receiving device 05 and receiving processing module 04 can be connected via an AUI. Transmitting processing module 02 and receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during transmission. For example, the processing module can be an 800LR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04 and receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not specifically limited here.

[0460] Figure 2(a) shows Figure 1 A schematic diagram of a data transmission process in a communication system is shown. As shown in Figure 2(a), during data transmission from a transmitting device 01 to a receiving device 05, the transmitting device 01 is configured to perform outer code encoding on the data and then transmit the outer code-encoded data to the transmitting processing module 02. The transmitting processing module 02 is configured to perform inner code encoding on the outer code-encoded data to obtain outer code-encoded and inner code-encoded data, and then transmit the outer code-encoded and inner code-encoded data to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer code-encoded and inner code-encoded data to the receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the outer code-encoded and inner code-encoded data and transmit the inner code-decoded data to the receiving device 05. The receiving device 05 is configured to perform outer code decoding on the inner code-decoded data.

[0461] It should be understood that the distinction between "inner" in inner code and "outer" in outer code is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity performing the inner code operation is closer to the channel transmission medium, while the entity performing the outer code operation is farther away. In the embodiment of the present application, after data is transmitted from transmitting device 01, it passes through transmitting processing module 02 to channel transmission medium 03, and then from channel transmission medium 03 to receiving device 05 via receiving processing module 04. The data encoded by transmitting device 01 is farther from channel transmission medium 03 than the data encoded by transmitting processing module 02, and the data decoded by receiving device 05 is farther from channel transmission medium 03 than the data decoded by receiving processing module 04. Therefore, data encoded by transmitting device 01 is referred to as data encoded with an outer code, data encoded by transmitting processing module 02 is referred to as data encoded with an inner code, data decoded by receiving device 05 is referred to as data decoded with an outer code, and data decoded by receiving processing module 04 is referred to as data decoded with an inner code. In one possible implementation, both the inner and outer code encoding described above employ FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the transmitting device 01 may employ Reed-Solomon (RS) code for outer code encoding, and the transmitting processing module 02 may employ Hamming code for inner code encoding. For another example, the transmitting device 01 may employ RS code for outer code encoding, and the transmitting processing module 02 may employ Bose-Chaudhuri-Hocquenghem (BCH) code for inner code encoding. The BCH code, which corrects single errors, is equivalent to the Hamming code. For another example, the transmitting device 01 may employ RS code for outer code encoding, and the transmitting processing module 02 may employ Polar code for inner code encoding.

[0462] Figure 2(b) is a schematic diagram of another communication system used in an embodiment of the present application. As shown in Figure 2(b), the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. Transmitting device 01 performs outer and inner coding on data, and then transmits the outer and inner coded data to transmission medium 03. Receiving device 05 then performs inner and outer decoding on the data received from transmission medium 03. Taking the communication system as a data center network as an example, transmitting device 01 and receiving device 05 can be devices such as switches or routers. Transmitting device 01 is also referred to as a client-side chip (host chip) at the transmitting end, and receiving device 05 is also referred to as a client-side chip (host chip) at the receiving end. Channel transmission medium 03 can be an optical fiber. The client-side chip is sometimes also referred to as a client-side device (host device). Transmitting device 01, channel transmission medium 03, and receiving device 05 in this communication system can all support bidirectional or unidirectional transmission, the specific details of which are not limited here.

[0463] It should be noted that the above content is an illustrative description of the application scenarios of the data processing method provided in the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data processing method. A person skilled in the art will know that as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one.

[0464] Figure 3 This is a flow chart of a data processing method provided in an embodiment of the present application. It should be understood that the data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in FIG2(a).

[0465] 301. Perform first data processing on multiple first data streams to obtain m second data streams.

[0466] In this embodiment, the multiple first data streams are all data streams that have undergone first FEC encoding, that is, the data streams that have undergone outer code encoding as described above. The outer code encoding can use Reed-Solomon (RS) code, and the data stream after outer code encoding can include multiple RS code words. In practical applications, other encoding methods can also be used for outer code encoding. For ease of description, RS code words are uniformly used below to represent the code words generated after outer code encoding. It should be noted that in this application, the outer code length value is calculated in units of outer code symbols, where an outer code symbol can include one or more bits. For example, the outer code uses a KP4 RS (544,514) code with a code length of 544 symbols, and one outer code RS symbol contains 10 bits.

[0467] It should be understood that the operation of the first data processing includes but is not limited to performing a second FEC encoding on each first data stream, and the second FEC encoding can be understood as the inner code encoding introduced above. That is, the m second data streams are all subjected to the second FEC encoding, where m is an integer greater than 1. Typically, m is 4, 8, 16, 32, or 64. As an example, an inner code encoder is used to perform inner code encoding on each K information bits in each first data stream, that is, after adding S check bits, a total of N bits of inner code codewords are obtained, that is, N = K + S, where K ≥ 1 and S ≥ 1. In some scenarios, K is a multiple of 10, and these K bits correspond to K / 10 outer code symbols, and the corresponding K / 10 outer code symbols come from K / 10 different outer code codewords.

[0468] In some possible implementations, the first data processing operation may further include at least one of alignment lock, lane de-skew, lane reorder, concatenated interleaving, channel interleaving, and scrambling. For example, before each second data stream undergoes the second FEC encoding, it also undergoes at least one of alignment lock, lane de-skew, lane reorder, and concatenated interleaving. For another example, after each second data stream undergoes the second FEC encoding, it also undergoes at least one of channel interleaving and scrambling.

[0469] It should be noted that each second data stream is also channel interleaved after the second FEC coding, and the channel interleaving is performed from the input n HM After the second FEC encoding (inner code encoding), the data streams each obtain an inner code word of length N bits, for a total of n HM The inner code words include n HM ×N bits, and poll (Round-Robin) to obtain 2 bits from each inner code word as the bits on the second data stream to obtain n consecutive bits on the second data stream. HM ×N bits. That is, the channel interleaving HM The second FEC coded (inner code coded) data stream is processed to obtain a second data stream. The channel interleaving is also called n HM - Intra-path code word interleaving (n HM-wayinnercodewordinterleaver), also known as inner codeword interleaver.

[0470] It should be noted that, considering the AWGN channel, the error bits of the inner code decoding input obey random distribution, while the error bits of the decoding output no longer obey random distribution. Adding a cascade interleaver between the inner code and the outer code can make the performance of the entire cascade FEC scheme better. Among them, the cascade interleaving operation usually includes convolution interleaving to achieve lower latency. A specific implementation method of cascade interleaving is to include channel permutation and convolution interleaving, wherein the channel permutation performs data permutation on the input g data streams to obtain g data-permuted data streams, and then performs convolution interleaving on each of them to obtain g convolution interleaved data streams. Another specific implementation method of cascade interleaving is to include channel multiplexing and convolution interleaving, wherein the channel multiplexing performs symbol multiplexing (symbol mux) on the input g data streams to obtain g1 symbol-multiplexed data streams, wherein g is divisible by g1, and then the above g1 data streams are convolution interleaved to obtain g1 convolution interleaved data streams, and at this time g1 is not equal to g. That is, the number of the first data stream and the second data stream obtained after the first data processing may be the same or different, depending on the actual application scenario and is not limited here.

[0471] The following introduces possible implementation methods of the above convolution interleaving.

[0472] A convolution interleaver for performing convolution interleaving includes r delay lines, each delay line including a different number of storage cells. The delay line with the smallest number of storage cells includes zero storage cells, and the difference in the number of storage cells between two adjacent delay lines is Q, where r is an integer greater than 1. Each storage cell is used to store d bits. The bits in each channel data stream are input into the r delay lines in sequence according to the sequence of the r delay lines, with each delay line inputting d bits at a time and outputting d bits at a time. The continuous r*d bits in the data stream output after convolution interleaving include the d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, r delay lines include 0 storage units, Q storage units, 2Q storage units, ..., (r-1)Q storage units, and each storage unit is used to store d bits. Then, the r delay lines correspond to r delay values, and the delay values ​​include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits the delay value of the delay line includes, the longer the delay (also called time delay) of this delay line to the data stream. It should be understood that when the delay line does not include a storage unit, the delay of the delay line is 0 bits, that is, there is no delay transmission.

[0473] The specific structure of the convolution interleaver is introduced below with reference to the accompanying drawings. Figure 4(a) is a schematic diagram of the first structure of the convolution interleaver in an embodiment of the present application. As shown in Figure 4(a), the number of storage units in the r delay lines decreases in sequence according to the sequence numbers of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases in sequence by Q storage units, and delay line r-1 has 0 storage units. Figure 4(b) is a schematic diagram of the second structure of the convolution interleaver in an embodiment of the present application. As shown in Figure 4(b), the number of storage units in the r delay lines increases in sequence according to the sequence numbers of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases in sequence by Q storage units, and delay line r-1 has (r-1)Q storage units.

[0474] It should be noted that at the same moment, the switches for the input and output of the convolution interleaver are located on the same delay line. After the current delay line inputs d bits and outputs d bits at a time, the switch is switched to the next delay line to ensure that the bits in each channel data stream are input to the r delay lines in sequence according to the sequence of the r delay lines, and the continuous r*d bits in the first data stream include the d bits output by each delay line. The specific data reading and writing operations are as follows: read d bits from the storage unit closest to the output port of the current delay line. Transfer the d bits stored in each storage unit in the current delay line to the next storage unit. Then write d bits to the storage unit closest to the input port in the current delay line. After that, switch to the next delay line and repeat the above operations, and so on.

[0475] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 4(a) and the convolutional interleaving process in Figure 4(b) are inverse operations of each other. That is, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 4(a), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 4(b). Similarly, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 4(b), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 4(a).

[0476] It should be noted that, in some specific applications, the inner code encoder also performs a cyclic shift operation before performing inner code encoding on each K information bits in each first data stream. The cyclic shift operation cyclically shifts each K information bits to the left or to the right to improve the overall anti-burst performance of the cascade code.

[0477] 302. Perform second data processing on the m second data streams to obtain m third data streams.

[0478] In this embodiment, an alignment marker is periodically inserted into each second data stream to obtain a third data stream. Specifically, P bits are periodically obtained from each second data stream, and an alignment marker of W bits in length is inserted, so that an alignment marker of W bits in length exists in every P+W bits in each third data stream. It should be understood that the present application does not limit the specific form of the alignment marker. For example, the alignment marker added here may be the same as the alignment marker used by the above-mentioned alignment lock. For another example, the alignment marker added here may be a part of the alignment marker used by the above-mentioned alignment lock. It should be noted that if the alignment marker added here includes a part of the alignment marker used by the above-mentioned alignment lock, the operation of the first data processing generally includes scrambling.

[0479] Figure 5(a) is a structural diagram of the third data stream in an embodiment of the present application. As shown in Figure 5(a), the third data stream includes at least one bit sequence, each bit sequence includes P+W bits, the P bits in each bit sequence come from the second data stream, and the W bits in each bit sequence are added alignment identifiers. It should be noted that each of the above P+W bits can be called a frame, wherein the W-bit alignment identifier is usually located at the front W consecutive bits of the frame. In some specific application scenarios, the above W-bit alignment identifier is also called a frame header, and may also be called a frame alignment signal (FAS), or may be called other names. It should be noted that the alignment identifier may contain bits with multiple functions, that is, only some of the W bits are used for synchronization of the receiving end.

[0480] It should be noted that, among the P+W bits of each frame, the alignment marker of the W bits can be located at the first W consecutive bits of the frame, or the alignment marker of the W bits can be located at the last W consecutive bits of the frame.

[0481] Figure 5(b) is another structural diagram of the third data stream in an embodiment of the present application. As shown in Figure 5(b), the alignment identifier includes a pad bit and / or a status field. For example, W0 bits out of W bits are used for receiving end synchronization, and W1 bits are pad bits (Padbit), and the pad bits can be preset bits, such as W1 bits are all 0, or W1 bits are random bits, where W0+W1≤W. For another example, W0 bits out of W bits are used for receiving end synchronization, W1 bits are pad bits (Padbit) reserved for future development or innovative use, and W2 bits are status fields (status field) used to indicate the status of FEC, where W0+W1+W2≤W.

[0482] In other scenarios, the W-bit alignment marker may not be arranged continuously. For example, the alignment marker may be split into multiple sub-identifier blocks distributed in P+W bits. Specifically, the W-bit alignment marker is divided into h sub-identifier blocks distributed in P+W bits. The lengths of the h sub-identifier blocks are represented by W0, W1, ..., W respectively. h；1 If they are expressed as W0+W1+…+W h；1 = W. There is no specific restriction on the position of the W-bit alignment marker in a frame of P+W bits.

[0483] 303. Perform third data processing on the m third data streams to obtain Y modulation symbol streams.

[0484] In this embodiment, after performing third data processing including modulation on the m third data streams, Y modulation symbol streams are obtained, where Y is an integer greater than or equal to 1.

[0485] It should be noted that, by selecting positive integers P and W, the present application can make the baud rate value of the modulated symbol data stream an integer multiple of the reference clock frequency (reference clock), making it simpler to implement clock extraction and clock synchronization at the receiving end, and can perform fast phase locking, with low PLL complexity and small jitter. It should be understood that the present application does not limit the specific value of the reference clock frequency. For example, it can be the Ethernet common reference clock frequency (Ethernet common reference clock). As an example, the baud rate value of the modulated symbol data stream is an integer multiple of 156.25M. It should also be understood that in actual applications, a certain error range can also be accepted, for example, the baud rate value of the modulated symbol data stream is an integer multiple of 156.25M ±V (ppm), where V can be 20, 50 or 100.

[0486] Furthermore, selecting a positive integer P allows the receiving end processing module to perform frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier lock operation). Once frame synchronization is achieved, the synchronization of the inner codewords and the synchronization of the cascaded deinterleaving can be guaranteed. In other words, the data processing method provided by the present application materials allows the receiving end processing module to achieve synchronization of the inner codewords and the cascaded deinterleaving after performing the frame synchronization operation without having to design other operations to perform synchronization of the inner codewords and the cascaded deinterleaving, thus simplifying the implementation. The value requirements for P and W are described in detail below.

[0487] Considering the 800GbE scenario, the transmitting device performs KP4 RS (544,514) outer code encoding on the 800GbE service data stream to be transmitted, obtaining a data stream with a total rate of 850Gbps. After PMA processing, it is sent to the transmitting end processing module through the connection unit interface 800GAUI. The transmitting end processing module performs first data processing including inner code encoding on multiple first data streams to obtain m second data streams, whose total rate is Insert the alignment marks into the m second data streams periodically, that is, perform the second data processing to obtain m third data streams, whose total rate is After the third data stream is processed by the third data including PAM4 modulation, 4 modulation symbol streams are obtained, whose baud rate is Here baud represents the modulation symbol rate transmitted per second.

[0488] It should be noted that for the 1.6TbE scenario, the transmitting device performs KP4RS (544,514) outer code encoding on the 1.6TbE service data stream to be transmitted to obtain a data stream with a total rate of 1.7Tbps, and after PMA processing, it is sent to the transmitting end processing module through the connection unit interface AUI. After the first data processing, the second data processing and the third data processing, the transmitting end processing module obtains 8 PAM4 modulation symbol streams with a baud rate of It should be noted that when the modulation in the third data stream processing is not PAM4 modulation, for example, PAM8 modulation is used, then 8 PAM8 modulation symbol streams are obtained, and the baud rate is

[0489] Assume the reference clock frequency is The following describes the 800GBE scenario as an example. The baud rate of the PAM4 modulation symbol stream is an integer multiple of the typical Ethernet reference clock frequency. Where N is the code length of the inner code, K is the information bit length of the inner code, and a is a positive integer. G represents 10^9, and M represents 10^6. In this case, the clock extraction and clock synchronization at the receiving end are simple to implement, and fast phase locking can be performed. The PLL complexity is low and the jitter is small. A typical Ethernet reference clock frequency is 156.25MHz. In some 800GbE scenarios, considering the 112.5G baud rate, there is

[0490] It should be noted that the parameter combination N, K, P, and W used in the above 800GbE scenario can be used in higher-speed scenarios, such as 1.6TbE. For example, when 1.6TbE uses PAM4 modulation, The integer used in 1.6TbE It is twice the integer a in the 800GbE scenario. In some 1.6TbE scenarios, considering the 225G baud rate, there is

[0491] Furthermore, when P is a multiple of the inner code length N, that is, P = N × b, where b is a positive integer. After the receiving end processing module performs frame synchronization on the received data (that is, frame synchronization of P + W bits, also called identifier locking operation), the inner code word synchronization can be guaranteed. In other words, the receiving end processing module can determine the boundary of the frame (boundary) according to the alignment identifier, thereby completing the frame synchronization, and then, since P is a multiple of the inner code length N, the boundary of the inner code code word can be obtained after completing the frame synchronization, thereby completing the inner code code word synchronization. In some 800GbE scenarios using PAM4 modulation and 112.5G baud rate or 1.6TbE scenarios considering 225G baud rate, there are Combined with P=N×b, we have

[0492] Furthermore, for the transmitting processing module, cascade interleaving including convolutional interleaving is employed. To ensure synchronization of convolutional deinterleaving during frame synchronization, the receiving processing module must ensure that the starting position of each frame (W+P bits) corresponds to the convolutional deinterleaver's input and output switches located at the starting positions of the switches, typically at the topmost positions, such as the position of delay line 0 shown in Figures 4(a) and 4(b). More specifically, for every f bits output by the convolutional interleaver and convolutional deinterleaver, their input and output switches are located at the topmost positions, and K×b is divisible by f. This ensures synchronization of the convolutional deinterleaver during frame synchronization. A specific approach is: r*d*c=K×b, where r is the number of delay lines in the convolutional interleaver and convolutional deinterleaver, d is the number of bits stored in the storage units in the convolutional interleaver and convolutional deinterleaver, and c is a positive integer.

[0493] In this way, based on the improvement of the transmitting end processing module in this application, as long as the receiving end processing module realizes the frame synchronization of the received data according to the alignment identifier added by the transmitting end processing module, it is equivalent to realizing the inner code word synchronization and convolution deinterleaving synchronization at the same time, simplifying the receiving end frame synchronization, inner code word synchronization, cascade interleaving synchronization and other operations, and the implementation complexity is relatively low.

[0494] Figure 6 This is another flow chart of the data processing method provided in the embodiment of the present application. It should be understood that the data processing method is applied to the receiving end, for example, it can be implemented by the receiving end processing module 04 shown in FIG2(a).

[0495] 601. Perform fourth data processing on the received Y modulation symbol streams to obtain m fourth data streams.

[0496] It should be understood that the Y modulation symbol streams come from the transmitting end processing module 02. For the characteristics and generation method of the modulation symbol stream, please refer to the above Figure 3 The receiving end processing module 04 performs a fourth data processing including demodulation on the Y modulated symbol streams to obtain m fourth data streams, wherein the fourth data processing performed by the receiving end processing module 04 is the inverse operation of the third data processing performed by the transmitting end processing module 02.

[0497] 602. Perform frame synchronization on each fourth data stream according to the alignment identifier in each fourth data stream.

[0498] The receiving end processing module 04 can lock the identifier of each fourth data stream according to the alignment identifier added by the transmitting end processing module 02 to determine the boundary of each frame (P+W bits) in the fourth data stream, thereby achieving frame synchronization.

[0499] It should be understood that after completing frame synchronization, the receiving processing module 04 will also perform fifth data processing on the m fourth data streams, wherein the fifth data processing can be understood as the inverse operation of the first data processing performed by the transmitting processing module 02. For example, the fifth data processing includes but is not limited to inner code decoding and cascade deinterleaving, wherein cascade deinterleaving includes convolutional deinterleaving, which will not be described one by one here.

[0500] The following describes the operations of the sending end processing module 02 and the receiving end processing module 04 by taking a specific application scenario as an example.

[0501] The transmitting end processing module 02 performs a first data processing including cascade interleaving and inner code encoding on the first data stream after outer code encoding to obtain m second data streams, wherein the cascade interleaving includes convolution interleaving. Then, the m second data streams are respectively inserted with alignment marks of W bits at a period of P bits to obtain P+W bits, that is, a second data processing is performed to obtain m third data streams. After the third data stream undergoes a third data processing including PAM4 modulation, Y modulation symbol streams are obtained, where Y is a positive integer. For the 800GbE business scenario, Y=4, and for the 1.6TbE business scenario, Y=8. This application material describes the data processing method using the 800GbE business scenario as an example, which can be simply extended to the 1.6TbE business scenario. Its specific implementation method is known to ordinary technicians in this field and will not be repeated here.

[0502] The receiving end processing module 04 performs a fourth data processing on the Y received modulated symbol streams to obtain m fourth data streams. The fourth data processing is the inverse of the third data processing and includes PAM4 demodulation. Each fourth data stream is then identifier-locked based on the W-bit alignment marker inserted by the transmitting end processing module 02 to obtain the P+W-bit frame boundary in the fourth data stream, i.e., frame synchronization. The m fourth data streams are then subjected to a fifth data processing, which includes inner code decoding and concatenated deinterleaving, where concatenated deinterleaving includes convolutional deinterleaving. It should be understood that the receiving end processing module 04 may also identifier-lock each received modulated symbol stream based on the W-bit alignment marker inserted by the transmitting end processing module 02 and the characteristics of the third data processing to further achieve frame synchronization.

[0503] It should be noted that before performing inner code decoding, the receiving end processing module 04 needs to determine the inner code word boundaries, also known as the need for inner code code word synchronization. It should also be noted that before performing convolutional deinterleaving, the receiving end processing module 04 needs to determine the positions of the input and output switches in the convolutional deinterleaving, also known as the need for convolutional deinterleaving synchronization. Based on the above description, as long as the receiving end processing module 04 achieves frame synchronization of the received data based on the alignment marker added by the transmitting end processing module 02, it is equivalent to achieving both inner code word synchronization and convolutional deinterleaving synchronization. There is no need to design additional operations for inner code word synchronization and cascade deinterleaving synchronization, simplifying the receiving end's operations such as receiving end frame synchronization, inner code word synchronization, and convolutional deinterleaving, and reducing implementation complexity.

[0504] The following provides several embodiments based on different inner code encoding methods to introduce the possible values ​​of P and W.

[0505] Example 1: The inner code is encoded using Hamming (128, 120).

[0506] Consider a block code with an inner code length of K = 120 bits and a codeword length of N = 128 bits, such as Hamming (128, 120). The baud rate of the PAM4 modulation symbol stream is Assuming the above baud rate value It is an integer multiple of the Ethernet typical reference clock frequency 156.25MHz, that is, Where a is a positive integer, G represents 10^9, and M represents 10^6. The clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and low jitter.

[0507] When P is a multiple of the inner code length N, that is, P = 128 × b, the receiving end processing module performs frame synchronization of the received data (that is, frame synchronization of P + W bits, also known as the identification lock operation), which can ensure the synchronization of the inner code word and obtain the boundary of the inner code word, where b is a positive integer. At this time, The positive integer 17×W is divisible by the positive integer b, and the positive integer Divisible by 3.

[0508] Consider some commonly used alignment marker bit lengths W of 48, 56, 64, 120, N = 128, and the corresponding optional positive integers a, b, P combinations and their corresponding baud rates are shown in Table 1 below:

[0509] Table 1

[0510]

[0511]

[0512] For higher baud rates, optical modules typically consume more power. Considering baud rates below 114GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 2 below:

[0513] Table 2

[0514] W P a b Baud rate (Gbaud) 48 13056 728 102 113.75 48 52224 726 408 113.4375 56 15232 728 119 113.75 56 60928 726 476 113.4375 64 17408 728 136 113.75 64 69632 726 544 113.4375 120 32640 728 255 113.75 120 52224 727 408 113.5938 120 130560 726 1020 113.4375 128 34816 728 272 113.75 128 139264 726 1088 113.4375

[0515] The inner code information length is K = 120 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer code encoding, there is a convolutional interleaver whose input and output switches are located at the top for every 120 bits it outputs. For example, if the number of delay lines in the convolutional interleaver is r = 3, each storage unit of the convolutional interleaver stores d = 40 bits. Another example is if the number of delay lines in the convolutional interleaver is r = 6, each storage unit of the convolutional interleaver stores d = 20 bits. At this point, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P + W bits, also known as the identifier lock operation), which ensures inner codeword synchronization, i.e., obtains the boundaries of the inner codewords. It also ensures convolutional deinterleaving synchronization, i.e., obtains the positions of the input and output switches of the convolutional deinterleaving, simplifying the implementation of the receiving end processing module.

[0516] It should be noted that the above embodiment considers the 800GbE scenario and can be easily extended to the 1.6TbE scenario. For example, the parameter combinations of W, P, and b in Table 1 can be directly applied to the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and the baud rate it uses is twice that of the 800GbE scenario.

[0517] Example 2: Inner code encoding adopts Hamming (170,160).

[0518] Consider a block code with an inner code length of K = 160 bits and a codeword length of N = 170 bits, such as Hamming (170, 160). The baud rate of the PAM4 modulation symbol stream is Assuming the above baud rate value It is an integer multiple of the Ethernet typical reference clock frequency 156.25MHz, that is, Where a is a positive integer, G represents 10^9, and M represents 10^6. The clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and low jitter.

[0519] When P is a multiple of the inner code length N, that is, P = 170 × b, the receiving end processing module performs frame synchronization of the received data (that is, frame synchronization of P + W bits, also known as the identification lock operation), which can ensure the synchronization of the inner code word and obtain the boundary of the inner code word, where b is a positive integer. At this time, The positive integer 17×W is divisible by the positive integer b, and the positive integer Divisible by 4.

[0520] Consider some commonly used alignment marker bit lengths W of 48, 56, 64, 120, N = 170, and the corresponding optional positive integers a, b, P combinations and their corresponding baud rates are shown in Table 3 below:

[0521] Table 3

[0522] W P a b Baud rate (Gbaud) 48 1360 748 8 116.875 48 4080 731 24 114.2188 48 23120 724 136 113.125 56 680 782 4 122.1875 56 4760 731 28 114.2188 56 11560 726 68 113.4375 56 80920 723 476 112.9688 48 69360 723 408 112.9688 64 5440 731 32 114.2188 64 92480 723 544 112.9688 120 680 850 4 132.8125 120 2040 765 12 119.5313 120 3400 748 20 116.875 120 10200 731 60 114.2188 120 11560 730 68 114.0625 120 34680 725 204 113.2813 120 57800 724 340 113.125 120 173400 723 1020 112.9688 170 170 1445 1 225.7813 170 850 867 5 135.4688 170 2890 765 17 119.5313 170 14450 731 85 114.2188 170 49130 725 289 113.2813 170 245650 723 1445 112.9688

[0523] For higher baud rates, optical modules typically consume more power. Considering baud rates below 114GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 4 below:

[0524] Table 4

[0525]

[0526]

[0527] The inner code information length is K = 160 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer codes, there is a convolutional interleaver in which the input and output switches are located at the top for every 160 bits it outputs. For example, if the convolutional interleaver has r = 4 delay lines, each storage unit of the convolutional interleaver stores d = 40 bits. Another example is if the convolutional interleaver has r = 8 delay lines, each storage unit of the convolutional interleaver stores d = 20 bits. At this point, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P + W bits, also known as the identifier lock operation), which ensures the synchronization of the inner code codewords, i.e., the determination of the boundaries of the inner code codewords. It also ensures the synchronization of the convolutional deinterleaving, i.e., the determination of the positions of the input and output switches of the convolutional deinterleaving, simplifying the implementation of the receiving end processing module.

[0528] It should be noted that the above embodiment considers the 800GbE scenario and can be easily extended to the 1.6TbE scenario. For example, the parameter combination W, P, and b in Table 3 can be directly applied to the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and its baud rate is twice that of the 800GbE scenario.

[0529] Example 3: Inner code encoding adopts Hamming (144,136).

[0530] Consider a block code with an inner code length of K = 136 bits and a codeword length of N = 144 bits, such as Hamming (144, 136). The baud rate of the PAM4 modulation symbol stream is Assuming the above baud rate value It is an integer multiple of the Ethernet typical reference clock frequency 156.25MHz, that is, Where a is a positive integer, G represents 10^9, and M represents 10^6. The clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and low jitter.

[0531] When P is a multiple of the inner code length N, that is, P = 144 × b, the receiving end processing module performs frame synchronization of the received data (that is, frame synchronization of P + W bits, also known as the identification lock operation), which can ensure the synchronization of the inner code word and obtain the boundary of the inner code word, where b is a positive integer. At this time, The positive integer 5×W is divisible by the positive integer b.

[0532] Consider some commonly used alignment marker bit lengths W of 48, 56, 64, 120, N = 144, and the corresponding optional positive integers a, b, P combinations and their corresponding baud rates are shown in Table 5 below:

[0533] Table 5

[0534]

[0535]

[0536]

[0537] For higher baud rates, optical modules typically consume more power. Considering baud rates below 114GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 6 below:

[0538] Table 6

[0539]

[0540]

[0541] It should be noted that the inner code information length is K = 136 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer codes, there exists a convolutional interleaver that outputs r*d = 160 bits per bit, with its input and output switches located at the top. For example, if the convolutional interleaver has r = 4 delay lines, each storage unit of the convolutional interleaver stores d = 40 bits. Another example is if the convolutional interleaver has r = 8 delay lines, each storage unit of the convolutional interleaver stores d = 20 bits. Considering that the inner code information length K = 136 and the lowest common multiple of 160 are 2720 = 136 × 20, the convolutional interleaver outputs 2720 = 17 × 160 bits per bit, with its input and output switches located at the top, and the 2720 bits output serve as the information bits of the 20 inner codes. That is, when b is a multiple of 20, 2720 = r*d*c = K × b, where c is a positive integer. At this point, the receiving processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier lock operation). This ensures inner codeword synchronization, i.e., determines the boundaries of the inner codewords. It also ensures convolutional deinterleaving synchronization, i.e., determines the positions of the input and output switches for convolutional deinterleaving. The corresponding combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 7 below:

[0542] Table 7

[0543]

[0544]

[0545] It should be noted that the inner code information length is K = 136 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner code and the outer code, there is a convolutional interleaver that outputs r*d = 140 bits per bit, with its input and output switches located at the top. For example, the number of delay lines of the convolutional interleaver is r = 7, and each storage unit of the convolutional interleaver stores d = 20 bits. Considering that the inner code information length K = 136 and the lowest common multiple of the above 140 is 4760 = 136 × 35, the above convolutional interleaver outputs 4760 = 34 * 140 bits per bit, with its input and output switches located at the top, and the output 4760 bits serve as the information bits of the 35 inner codes. That is, when b is a multiple of 35, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier lock operation), which ensures inner codeword synchronization, i.e., obtains the boundaries of the inner codewords; it also ensures convolutional deinterleaving synchronization, i.e., obtains the positions of the input and output switches of the convolutional deinterleaving. The corresponding positive integer combinations a, b, and P, and their corresponding baud rates, are shown in Table 8 below:

[0546] Table 8

[0547] W P a b Baud rate (Gbaud) 56 5040 728 35 113.75 56 10080 724 70 113.125 56 20160 722 140 112.8125 56 40320 721 280 112.6563

[0548] It should be noted that the above embodiment considers the 800GbE scenario and can be easily extended to the 1.6TbE scenario. For example, the parameter combination W, P, and b in Table 5 can be directly applied to the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and its baud rate is twice that of the 800GbE scenario.

[0549] Embodiment 4: The inner code encoding adopts an FEC code with an information length K=140 bits and a codeword length N=148 bits.

[0550] Consider an FEC code with an information length of K = 140 bits and a codeword length of N = 148 bits, such as the Hamming (148, 140) code. Figure 10In the encoding scheme shown, the 140-bit data to be encoded is represented as B[139:0]. Each consecutive 2 bits are bit-wise XORed to obtain 1-bit data C[i], resulting in a total of 70 bits of data, represented as C[69:0], where C[i] = B[2*i]^B[2*i+1], 0≤i≤69. C[69:0] is then used as the information data and Hamming (78,70) encoded to obtain 8 bits of parity data, represented as P[7:0]. Finally, B[139:0] and P[7:0], a total of 148 bits, are concatenated to form the output of the inner code, represented as D[147:0]. D[139:0] comes from B[139:0], and D[147:140] comes from P[7:0].

[0551] The baud rate of the PAM4 modulation symbol stream is Assuming the above baud rate value It is an integer multiple of the Ethernet typical reference clock frequency 156.25MHz, that is, Where a is a positive integer, G represents 10^9, and M represents 10^6. The clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and low jitter.

[0552] When P is a multiple of the inner code length N, that is, P = 148 × b, the receiving end processing module performs frame synchronization of the received data (that is, frame synchronization of P + W bits, also known as the identification lock operation), which can ensure the synchronization of the inner code word and obtain the boundary of the inner code word, where b is a positive integer. At this time, The positive integer 34×W is divisible by the positive integer b, and the positive integer Divisible by 7.

[0553] Consider some commonly used alignment marker bit lengths W of 48, 56, 64, 120, N = 148, and the corresponding optional positive integers a, b, P combinations and their corresponding baud rates are shown in Table 9 below:

[0554] Table 9

[0555] W P a b Baud rate (Gbaud) 48 148 952 1 148.75 48 1184 748 8 116.875 48 30192 720 204 112.5 48 241536 719 1632 112.3438 56 35224 720 238 112.5 56 281792 719 1904 112.3438 64 5032 728 34 113.75 64 40256 720 272 112.5 64 322048 719 2176 112.3438 120 888 816 6 127.5 120 2960 748 20 116.875 120 5032 736 34 115 120 7104 731 48 114.2188 120 40256 721 272 112.6563 120 75480 720 510 112.5 120 603840 719 4080 112.3438 148 5032 740 34 115.625 148 93092 720 629 112.5 148 744736 719 5032 112.3438

[0556] For higher baud rates, optical modules typically consume more power. Considering baud rates below 114 GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 10 below:

[0557] Table 10

[0558]

[0559]

[0560] The inner code information length is K = 140 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer codes, there is a convolutional interleaver whose input and output switches are located at the top for every 140 bits it outputs. For example, the convolutional interleaver has r = 7 delay lines, and each storage unit of the convolutional interleaver stores d = 20 bits. At this point, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P + W bits, also known as the identifier lock operation), which ensures the synchronization of the inner code codewords, that is, the determination of the boundaries of the inner code codewords. It also ensures the synchronization of the convolutional deinterleaving, that is, the determination of the positions of the input and output switches of the convolutional deinterleaving, making the implementation of the receiving end processing module simple.

[0561] It should be noted that the above embodiment considers the 800GbE scenario and can be easily extended to the 1.6TbE scenario. For example, the parameter combination W, P, and b in Table 9 can be directly applied to the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and its baud rate is twice that of the 800GbE scenario.

[0562] In some 800GbE scenarios using PAM4 modulation and 112.5G baud rate or 1.6TbE scenarios considering 225G baud rate, there are Combined with P=N×b, we have Since N = 148 and K = 140, 17W = 4b. Considering b as an integer, the integer W is a multiple of 4, and the integer b is a multiple of 17.

[0563] Embodiment 5: The inner code encoding adopts an FEC code with an information length K=120 bits and a codeword length N=128 bits.

[0564] Consider an inner code using an FEC code with an information length of K = 120 bits and a codeword length of N = 128 bits, such as a Hamming (128, 120) code. For another example, the 120-bit data to be encoded is represented as B[119:0]. Each consecutive 2 bits are bitwise XORed to obtain 1-bit data C[i], resulting in a total of 60 bits of data, represented as C[59:0]. Here, C[i] = B[2*i]^B[2*i+1], where 0≤i≤59. C[59:0] is then encoded using the Hamming (68, 60) method as the information data to obtain 8 bits of parity data, represented as P[7:0]. Finally, the 128 bits, B[119:0] and P[7:0], are concatenated to form the inner code output, represented as D[127:0]. Among them, D[119:0] comes from B[119:0], and D[127:120] comes from P[7:0].

[0565] Considering the 800GE scenario and using PAM4 modulation, data processing generates four PAM modulation symbol streams. Without considering the alignment mark of W bits inserted into the period, the baud rate of the PAM4 modulation symbol stream is Its baud rate value is approximately 725.3333 times the reference clock frequency value of 156.25M. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering that the baud rate of the PAM4 modulation symbol stream under the alignment marker with a length of W bits inserted every P bits is 113.4375 Gbaud, its baud rate value is 726 times the reference clock frequency value of 156.25M.

[0566] Combined with Example 1 have In this case, P = 1088 × W. Considering W to be an integer multiple of the inner codeword length N = 128, the corresponding value of P is also an integer multiple of 128, allowing the receiver to perform low-complexity frame synchronization and codeword synchronization. Table 13 shows several typical values ​​of W and P.

[0567] Table 13

[0568] W P 128 139264 256 278528 384 417792 512 557056 640 696320 768 835584 896 974848 1024 1114112

[0569] Figure 14 This is a schematic diagram of an implementation method of data processing in the embodiment of this application. Figure 14 , the specific data processing process is introduced below:

[0570] The 32 data streams that have undergone the first FEC encoding are inner-coded to obtain 32 inner-coded data streams. Specifically, inner-coded is performed on every K=120 information bits in each of the data streams, that is, after adding S=8 check bits, a total of N=128 bits of inner code codewords are obtained.

[0571] Channel interleaving is performed on every 8 coded data streams in the 32 inner code coded data streams to obtain 1 second data stream, and a total of m=4 second data streams are obtained. Figure 14 ,For 800GE scenario, data processing includes four data sub-processing, namely Figure 14 The data sub-processing 0, data sub-processing 1, data sub-processing 2, and data sub-processing 3 in each data sub-processing include 1 channel interleaving. The channel interleaving is performed from the input n HM= 8 coded data streams each receive a 128-bit inner codeword, for a total of 8 inner codewords. Two bits are round-robin-ed from each inner codeword to serve as bits for the second data stream, resulting in 1024 consecutive bits for the second data stream. Channel interleaving is also known as 8-way Hamming codeword interleaver, or inner codeword interleaving.

[0572] An alignment marker is periodically inserted into each of the m=4 second data streams to obtain m=4 third data streams. Specifically, P bits are periodically obtained from each second data stream and an alignment marker of W bits is inserted, so that an alignment marker of W bits is present in every P+W bits in each third data stream.

[0573] A third data processing including PAM4 modulation is performed on the m=4 third data streams to obtain Y=4 modulation symbol streams.

[0574] Figure 15 This is a structural diagram of an alignment marker in an embodiment of the present application. This embodiment takes W=3×128=384, P=1088×W=417792 as an example to introduce the specific structure of the alignment marker with a length of W=384 bits inserted periodically. Figure 15 As shown in (a), the 1024-bit alignment identifier contains at least one frame synchronization sequence (Frame Synchronization Sequence) for receiving end synchronization. The frame synchronization sequence contains a total of 48 bits, which are distributed as 2 frame synchronization subsequences in the alignment identifier, namely Figure 15 Frame synchronization subsequence 1 and frame synchronization subsequence 2 in (b). Each frame synchronization subsequence contains 24 bits. The two frame synchronization subsequences are not continuous in the 1024-bit alignment identifier and are separated by 8 bits (one byte). The specific structure is as follows: Figure 15 Here, the interval between two consecutive bits is defined as 0 bits.

[0575] In some specific applications, the 24-bit frame synchronization subsequence 1 specifically takes the following values: 0x9A, 0x4A, 0x26, and the 24-bit frame synchronization subsequence 2 specifically takes the following values: 0x65, 0xB5, 0xD9. It should be noted that the frame synchronization subsequence 1 (or frame synchronization subsequence 2) is transmitted in the order of 0x9A, 0x4A, 0x26 (or 0x65, 0xB5, 0xD9). More specifically, corresponding to frame synchronization subsequence 1, 0x9A is the first byte transmitted, and 0x26 is the last byte transmitted. Furthermore, for the 8 bits of a byte, the LSB is transmitted first, and the MSB is transmitted last. For example, the 8 bits corresponding to 0x9A are transmitted from left to right according to the bit sequence 01011100.

[0576] Figure 16 Schematic diagram of the computer architecture for synchronization. It should be noted that the two frame synchronization subsequences in the set of frame synchronization sequences are separated by 8 bits (one byte) in the 1024-bit alignment identifier, which allows the receiving end to reuse the synchronization hardware implementation architecture in the existing 100GE 802.3bj and 400GE 802.3bs standards when performing frame synchronization. Figure 16 (a) shows the architecture of the related calculator used for alignment marker synchronization in the 100GE 802.3bj standard. Figure 16 (b) shows the architecture of the related calculator used for alignment marker synchronization in the 400GE 802.3bs standard. Figure 16 (c) shows the architecture of the relevant calculator used for the frame synchronization in the present invention. It can be seen that the proposed frame synchronization sequence structure can reuse the synchronization hardware implementation architecture in the existing 100GE 802.3bj and 400GE 802.3bs standards, which is easy to implement.

[0577] Example 6:

[0578] Figure 17 This is another structural diagram of the alignment mark in the embodiment of the present application. Based on Example 5, consider W = 8 × 128 = 1024, P = 1088 × W = 1114112. In the data processing operation, P bits are periodically obtained from each second data stream, and an alignment mark of W bits in length is inserted. The alignment mark contains multiple groups of frame synchronization sequences for receiving end synchronization. Figure 17 (a) and Figure 17 As shown in (b), the alignment mark includes 3 groups of frame synchronization sequences for receiving end synchronization. Figure 17 As shown in (c), the alignment identifier includes two groups of frame synchronization sequences for receiving end synchronization.

[0579] It should be noted that there may be or may not be an interval between each set of frame synchronization sequences. Figure 17 As shown in (a), there is no gap between the three sets of frame synchronization sequences in the alignment mark of W=1024 bits in length. Figure 17 As shown in (b), two adjacent frame synchronization sequences in the three sets of frame synchronization sequences are separated by 8 bits in the alignment identifier of the length of W = 1024 bits. It should be noted that the number of bits separating two adjacent frame synchronization sequences in the three sets of frame synchronization sequences in the alignment identifier of the length of W = 1024 bits can be another positive integer that is an integer multiple of 8.

[0580] It should be noted that the specific values ​​of the multiple sets of frame synchronization sequences can be the same or different. Figure 17 As shown in (a), the values ​​of the three frame synchronization sequences are the same, and the values ​​of the 48 bits in each frame synchronization sequence are: 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9. Figure 17 As shown in (b), among the three groups of frame synchronization sequences, the values ​​of the first group of frame synchronization sequences and the second group of frame synchronization sequences are the same, and the 48 bits in each group of frame synchronization sequences are: 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9; the values ​​of the third group of frame synchronization sequences are different from the values ​​of the first and second groups of frame synchronization sequences, and the 48 bits are: 0x01, 0x71, 0xF3, 0xFE, 0x8E, 0x0C. Figure 17 As shown in (c), the values ​​of the two sets of frame synchronization sequences are different. The 48 bits in the first frame synchronization sequence are: 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9; the 48 bits in the second frame synchronization sequence are: 0x01, 0x71, 0xF3, 0xFE, 0x8E, 0x0C.

[0581] Example 7:

[0582] Figure 18 This is another embodiment of data processing in the present application. Based on Example 5, considering the 1.6TE scenario and using PAM4 modulation, the data processing obtains 8 PAM modulation symbol streams. Without considering the alignment mark of W bits inserted in the period, the baud rate of the PAM4 modulation symbol stream is Its baud rate value is approximately 725.3333 times the reference clock frequency value of 156.25M. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering that the baud rate of the PAM4 modulation symbol stream under the alignment marker with a length of W bits is inserted periodically, it is 113.4375Gbaud, and its baud rate value is 726 times the reference clock frequency value of 156.25M.

[0583] Combined with Example 1 have At this time, P = 1088 × W. Considering that W is an integer multiple of the inner codeword length N = 128, the corresponding value of P is also an integer multiple of 128, so that the receiving end can perform low-complexity frame synchronization and codeword synchronization. Several typical values ​​of W and P are shown in Table 13 of Example 5. For the specific data processing flow, please refer to Figure 18 For understanding, the data processing includes 8 data sub-processings, namely data sub-processings 0 to 7. The specific operation of each data sub-processing can be understood by referring to Example 5.

[0584] Example 8:

[0585] Figure 19 FIG1 is another schematic diagram of another embodiment of data processing in the embodiment of the present application. Based on embodiment 5, the inner code encoder further performs a cyclic shift operation before performing inner code encoding on each K=120 information bits in each first data stream. Figure 19 As shown, the cyclic shift operation cyclically shifts every K=120 information bits to the right to improve the overall anti-burst performance of the concatenated code.

[0586] Example 9:

[0587] Figure 20 This is another schematic diagram of data processing in the embodiment of the present application. Based on Example 5, the inner code encoder further performs a convolution interleaving operation before performing inner code encoding on each K=120 information bits in each first data stream. Figure 20 As shown, eight of the 32 first data streams are first convolutionally interleaved, then cyclically shifted by K = 120 bits, then inner-coded, and finally channel-interleaved (inner-codeword interleaving) to produce one second data stream, for a total of four second data streams. Convolutional interleaving is also performed before inner-code coding, improving the performance of the overall concatenated code under AWGN conditions.

[0588] Example 10:

[0589] Figure 21 This is a schematic diagram of another implementation method of data processing in the embodiments of the present application. Based on Example 9, every two first data streams in the eight first data streams are grouped as two input data streams for data sub-processing. In each data sub-processing, each of the two first data streams is subjected to convolution interleaving processing to obtain two convolution interleaved data streams. Each convolution interleaved data stream is subjected to data distribution to obtain four distributed data streams, and a total of eight distributed data streams are obtained. The data distribution is based on a 0 bit granularity. Figure 21As shown, in the convolutionally interleaved data stream, with α0 bits as a group, for four consecutive groups of 4×α0 bits, the 0th group of α0 bits is sent to the 0th data stream of the four distributed data streams, the 1st group of α0 bits is sent to the 1st data stream of the four distributed data streams, the 2nd group of α0 bits is sent to the 2nd data stream of the four distributed data streams, and the 3rd group of α0 bits is sent to the 3rd data stream of the four distributed data streams. Typically, the distributed bit granularity is α0 = 120.

[0590] It should be noted that for 800GE scenarios, data processing includes four data sub-processing steps, such as Figure 21 As shown, the data stream input for each data sub-process is two first data streams. The two first data streams correspond to a bit rate of approximately 200 Gbps, that is, each first data stream corresponds to a bit rate of approximately 100 Gbps. Correspondingly, the distributed data stream corresponds to a bit rate of approximately 25 Gbps.

[0591] It should also be noted that when the distribution bit granularity is α0=120, Figure 21 The data processing shown can be described as performing convolution interleaving on the two first data streams, resulting in a total of two convolution interleaved data streams. Four bit blocks are obtained from each convolution interleaved data stream, each of which is 120 bits long. Each bit block is cyclically shifted and inner-coded to obtain four inner-code codewords. A total of eight bit blocks are obtained from the two convolution interleaved data streams, which are then cyclically shifted and inner-coded to obtain a total of eight inner-code codewords. These blocks are then channel-interleaved to obtain 1024 bits on the second data stream.

[0592] It should be noted that in some specific application scenarios with low latency requirements, the Figure 21 The convolution interleaving in is removed and the convolution interleaving operation is not performed (bypass).

[0593] It should be noted that for the 1.6TE scenario, data processing includes eight data sub-processes, with each sub-processing receiving two first data streams as input. These two first data streams correspond to a bit rate of approximately 200 Gbps, meaning each first data stream corresponds to a bit rate of approximately 100 Gbps. Accordingly, the distributed data streams correspond to a bit rate of approximately 25 Gbps.

[0594] Example 11:

[0595] Figure 22(a) is a schematic diagram of another implementation method of data processing in an embodiment of the present application. Based on Example 9, each of the four first data streams serves as the input data stream for the data sub-processing. In each data sub-processing, the one first data stream undergoes convolution interleaving processing to obtain one convolution interleaved data stream. The one convolution interleaved data stream undergoes data distribution to obtain eight distributed data streams. The data distribution uses α0 bits as the granularity. As shown in Figure 22(a), when the convolution interleaved data stream is grouped with α0 bits, for 8 consecutive groups of a total of 8×α0 bits, the 0th group of α0 bits is sent to the 0th data stream of the 8 distributed data streams, the 1st group of α0 bits is sent to the 1st data stream of the 8 distributed data streams, ..., the 7th group of α0 bits is sent to the 7th data stream of the 8 distributed data streams. Typically, the distribution bit granularity is α0=120.

[0596] It should be noted that for 800GE scenarios, data processing includes four data sub-processes, as shown in Figure 22(a). The data stream input for each data sub-process is a first data stream, corresponding to a bit rate of approximately 200 Gbps. Correspondingly, the distributed data stream corresponds to a bit rate of approximately 25 Gbps.

[0597] It should also be noted that when the distribution bit granularity is α0 = 120, the data processing shown in Figure 22(a) can be described as performing convolution interleaving on each first data stream to obtain a convolution interleaved data stream. Eight bit groups are obtained from the convolution interleaved data stream, each with a length of 120 bits. Each bit group is cyclically shifted and inner-coded to obtain eight inner-code codewords, which are then channel-interleaved to obtain 1024 bits on the second data stream.

[0598] It should be noted that in some specific application scenarios with low latency requirements, the convolution interleaving in Figure 22 can be removed and the convolution interleaving operation can be bypassed. Furthermore, in order to achieve lower latency, lower complexity and power consumption, in some possible scenarios, the cyclic shift operation and / or the channel interleaving (inner codeword interleaving) operation can also be bypassed. If the channel interleaving (inner codeword interleaving) operation is not performed (bypassed), a one-way Hamming codeword interleaver can be performed on the 8 encoded data streams, which is equivalent to codeword merging (codeword merge) on the 8 encoded data streams.

[0599] Figure 22(b) is a schematic diagram of another implementation method of data processing in an embodiment of the present application. Each of the four first data streams serves as an input data stream for data sub-processing. Different from the implementation method shown in Figure 22(a), as shown in Figure 22(b), in each data sub-processing, convolution interleaving is not performed on one first data stream, but data distribution is directly performed to obtain 8 distributed data streams. Among them, the data distribution is based on the granularity of α0 bits, that is, when the first data stream before data distribution is a group of α0 bits, for 8 consecutive groups of a total of 8×α0 bits, the 0th group of α0 bits is sent to the 0th data stream after distribution, the 1st group of α0 bits is sent to the 1st data stream after distribution, ..., the 7th group of α0 bits is sent to the 7th data stream after distribution. Typically, the distribution bit granularity is α0=120.

[0600] Figure 22(c) is a schematic diagram of another embodiment of data processing in an embodiment of the present application. In one possible embodiment, the embodiment of Figure 22(b) is simplified to obtain an embodiment as shown in Figure 22(c) that is equivalent to Figure 22(b). Specifically, as shown in Figure 22(c), in each data sub-processing, the first data stream is inner-coded to obtain the second data stream, and an alignment marker is inserted into the second data stream period to obtain the third data stream, which is then PAM4 modulated to obtain a modulation symbol stream.

[0601] It should be noted that the modulated symbol stream obtained by the data processing shown in Figure 22(b) or Figure 22(c) is transmitted through the actual channel to obtain a received symbol stream at the receiving end, and PAM4 demodulation is performed to obtain a demodulated data stream. As an example, the data processing method at the receiving end is to use the frame synchronization sequence in the alignment marker to perform frame synchronization to obtain the starting position of each frame and the inner code boundary. Then, soft decision decoding of the inner code is performed to obtain the inner code decoded data stream, which is then sent to the client-side device for outer code KP4 decoding. The entire cascaded system can achieve a pre-correction bit error rate of approximately 3.3E-3.

[0602] As another example, the receiving end processes data using the frame synchronization sequence in the alignment marker to determine the start position of each frame and the inner code boundary. Hard-decision decoding of the inner code is then performed to obtain a decoded inner code data stream, which is then sent to the client-side device for outer code KP4 decoding. The entire cascaded system can achieve a bit error rate before correction of approximately 6E-4. It should be understood that hard-decision decoding of the inner code reduces decoding complexity.

[0603] As another example, in some scenarios with good link quality, the receiver can use the frame synchronization sequence in the alignment marker for frame synchronization to obtain the starting position of each frame and the inner code boundary. It then bypasses inner code decoding, directly removing the parity bits from each received inner code word in the data stream, retaining only the information bits. It then uses the frame synchronization sequence in the alignment marker for frame synchronization to obtain the starting position of each frame, removes the alignment marker, and then sends the data to the client device for outer code KP4 decoding. This achieves minimal latency and complexity at the receiver.

[0604] In some possible implementations, the length W of the alignment marker is an integer multiple of the length N of the inner code word, and the specific pattern of the alignment marker is one or more inner code words. As an example, the inner code word constituting the alignment marker is obtained by inner code encoding the alignment marker information, and the inner code encoding is the above-mentioned second FEC encoding. The length of the inner code word obtained after the alignment marker information is inner code encoded is the same as the length of the inner code word obtained by the second FEC encoding in the above-mentioned second data stream. For the convenience of description, the inner code word constituting the alignment marker can also be referred to as a target code word, that is, the length of the target code word is the same as the length of the inner code code word in the above-mentioned second data stream. Specifically, each target code word is obtained by inner code encoding the alignment marker information including K target bits, the target code word includes N bits, and the N bits include K target bits and S check bits obtained by encoding.

[0605] Figure 22(d) is a schematic diagram of an implementation method for generating an alignment mark in an embodiment of the present application. As shown in Figure 22(d), two possible methods for generating the alignment mark are provided.

[0606] Taking the generation method 0 of the alignment marker as an example, the length W of the alignment marker is an integer multiple of the target codeword length N, that is, W = b0×N. Among them, b0 is an integer multiple of 8, for example, W = 8×128 = 1024. At this time, the specific pattern of the alignment marker can be selected as one or more target codewords. Optionally, the alignment marker is obtained by codeword interleaving of multiple target codewords. Specifically, the alignment marker information including b0×K target bits is encoded through inner code to obtain b0 target codewords, and the b0 target codewords are then interleaved through 8-way codewords to obtain the alignment marker. It should be understood that the alignment marker obtained by codeword interleaving of multiple target codewords should also be considered to include multiple target codewords.

[0607] Taking the generation method 1 of the alignment marker as an example, the length W of the alignment marker is an integer multiple of the target codeword length N, that is, W = b1×N. For example, W = 3×128 = 384, and for another example, W = 8×128 = 1024. At this time, the specific pattern of the alignment marker can be selected as one or more target codewords. Optionally, the alignment marker is obtained by merging multiple target codewords. Specifically, the alignment marker information including b1×K target bits is encoded through an inner code to obtain b1 target codewords, and the b1 target codewords are then merged to obtain the alignment marker.

[0608] It should be noted that for the implementation shown in Figure 22 (a), the generation method 0 of the alignment mark shown in Figure 22 (d) can be adopted, or the generation method 1 of the alignment mark shown in Figure 22 (d) can be adopted. At this time, the corresponding data processing method of the receiving end is to perform inner code word self-synchronization on the demodulated data stream after demodulation processing to obtain the inner code word boundary, then obtain the 8-way inner code codeword deinterleaved data stream and perform inner code decoding, and then use the frame synchronization sequence in the alignment mark information after inner code decoding to perform frame synchronization to obtain the starting position of each frame. It should be understood that since the reliability of the frame synchronization sequence and status field (status field) contained in the alignment mark information after inner code decoding is further improved, the time required for frame synchronization can be shortened.

[0609] It should be noted that for the implementation shown in Figure 22 (b) or Figure 22 (c), the generation method 0 of the alignment mark shown in Figure 22 (d) can be adopted, or the generation method 1 of the alignment mark shown in Figure 22 (d) can be adopted. At this time, the corresponding data processing method of the receiving end is to perform inner code word self-synchronization on the demodulated data stream after demodulation processing to obtain the inner code word boundary, and then perform inner code decoding, and then use the frame synchronization sequence in the alignment mark information after inner code decoding to perform frame synchronization to obtain the starting position of each frame. It should be understood that since the reliability of the frame synchronization sequence and status field (status field) contained in the alignment mark information after inner code decoding is further improved, the time required for frame synchronization can be shortened.

[0610] It should be noted that in the data processing methods shown in Figures 22(a), 22(b), and 22(c), the third data stream obtained after inserting the alignment marker contains W-bit alignment markers every P+W bit interval, and the synchronization sequence in the alignment marker is located at a fixed position. Therefore, for the data processing methods shown in Figures 22(a), 22(b), and 22(c), the corresponding receiving-end data processing can use the same operation to perform frame synchronization and obtain the frame start position, facilitating compatibility of a set of hardware with the receiving-end data processing corresponding to the transmitting-end data processing shown in Figures 22(a), 22(b), and 22(c).

[0611] It should be noted that for the 1.6TE scenario, data processing includes eight data sub-processes, where the data stream input of each data sub-process is one first data stream, corresponding to a bit rate of approximately 200G per second. Correspondingly, the distributed data stream corresponds to a bit rate of approximately 25G per second.

[0612] It should be noted that, in some specific applications, the length W of the alignment marker is an integer multiple of the length N of the second FEC code (also called inner code), and the P is an integer multiple of N. In this case, the alignment marker can be protected by the inner code, that is, the W-bit alignment marker contains W / N inner code words, where W / N×K bits correspond to the information bits of the inner code word, and W / N×(NK) corresponds to the check bits of the W / N inner code word. Typically, the W / N×K bits The bits are used as the frame synchronization sequence, and the other part is used to transmit link information and / or control information, including the receiving end status, FEC status, etc., which is also called the status field. Specifically, in order to improve the accuracy of the transmitted link information and / or control information, the W / N×K bits are excluding the remaining bits of the frame synchronization sequence. bits, of which bits are used to indicate the type of link information and / or control information, bits are used to indicate the specific content of the indication link information and / or control information, bits are used for cyclic redundancy check CRC (Cyclic Redundancy Check). Typically, The value of is 8, 16 or 32. In other specific applications, it is necessary to use multiple frames to collaboratively transmit the link indication information and / or control information to further improve the accuracy of the transmitted information. In this case, the W / N×K bits are bits are used to refer to the multiple frames, the bits are also called multi-frame synchronization signals. Typically,

[0613] In some specific applications, such as Figure 15 The frame synchronization sequence contains 48 bits, which are distributed into 2 frame synchronization subsequences and the two frame synchronization subsequences are separated by 8 bits. At this time, the 8-bit intervals can be used for the 8 bits required for the CRC8 check, or for the 8 bits required to indicate the type of link information and / or control information, or 8 of the bit positions are used for the 8 bits required for the multi-frame synchronization signal.

[0614] In summary, in the embodiments of the present application, an alignment marker is periodically inserted into the data stream after concatenated FEC encoding. Specifically, P bits are periodically extracted from the data stream after concatenated FEC encoding, and a W-bit alignment marker (also known as a frame header, which may include padding bits or a status field) is inserted. This ensures that every P+W bits (referred to as a frame) in the data stream contains a W-bit alignment marker. By selecting positive integers P and W, the baud rate of the modulated symbol data stream can be an integer multiple of the Ethernet common reference clock frequency. This simplifies clock extraction and synchronization at the receiving end, enabling fast phase lock, low PLL complexity, and low jitter. Furthermore, P is required to be a multiple of the inner code length N, i.e., P = N × b. After the receiving end performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also known as marker locking), inner code word synchronization is guaranteed. This simplifies frame synchronization and inner code word synchronization operations at the receiving end, reducing implementation complexity. In addition, the convolution interleaver and convolution deinterleaver output f bits each time, and their input and output switch positions are located at the top, and K×b can be divided by f, so that the convolution deinterleaver synchronization can be guaranteed during frame synchronization.

[0615] When the receiving end uses the W-bit alignment marker (also known as the frame header, which may include padding bits or a status field) for frame synchronization, it is necessary to perform a bit-by-bit position identification marker. Considering that the value of the integer P is usually large, the complexity of the frame synchronization operation of the bit-by-bit position identification marker is greater than the complexity of the inner codeword synchronization operation. In some application scenarios, by selecting the length W of the alignment marker as an integer multiple of the codeword length N of the second FEC code (also known as the inner code code), and selecting the specific pattern of the alignment marker as one or more inner codewords, the receiving end can perform low-complexity frame synchronization and codeword synchronization. The above-mentioned operation method of first performing inner code encoding and then periodically inserting the alignment marker is equivalent to the following operation method of first periodically inserting the marker and then performing inner code encoding. That is, the inner code encoding scheme of "first performing inner code encoding and then periodically inserting the alignment marker" in the above embodiment can also be used for the inner code encoding scheme of "first periodically inserting the marker and then performing inner code encoding" in the following embodiment. For example, the block code with an information length K = 120 bits and a codeword length N = 128 bits used in Example 1 can also be used in the following specific embodiment. The specific implementation scheme of "inserting the identifier periodically before performing the inner code encoding" is introduced below.

[0616] Figure 7 This is another flow chart of the data processing method provided in the embodiment of the present application. It should be understood that the data processing method is applied to the sending end and includes the following steps.

[0617] 401. Perform first data processing on m first data streams to obtain m second data streams.

[0618] In this embodiment, the m first data streams are all data streams obtained by first FEC encoding, that is, the data streams obtained by outer code encoding as described above. Typically, m is 4, 8, 16, 32, or 64.

[0619] Specifically, a first identifier is periodically inserted into each of the m first data streams to obtain a total of m second data streams. Specifically, a first identifier is periodically obtained from each first data stream. bits and insert The first identifier of the bit length makes each second data stream bits exist The first identifier is bits long.

[0620] Figure 8 This is a structural diagram of the second data stream in the embodiment of the present application. Figure 8 As shown, the second data stream includes at least one first bit sequence, each of which includes bits, each first bit in the sequence bits come from the first data stream, and each first bit sequence bits are added as the first identifier. It should be noted that the first identifier may include pad bits and / or status fields. The pad bits may be preset bits, such as all 0s, or random bits; the status field is used to indicate the status of FEC. In other scenarios, the above The first identifier of the bits may not be arranged continuously. The alignment marker of the bits is The position in the bits is not specifically restricted here.

[0621] It should be noted that each bits, the The first identifier of the bits can be located in the The first bit consecutive bits, the The first identifier of the bit can also be located in the The last bit consecutive bits.

[0622] In some possible implementations, a cascaded interleaver is added between the inner code and the outer code to improve the performance of the entire cascaded FEC scheme. The cascaded interleaving operation typically includes convolutional interleaving to achieve lower latency. That is, the m first data streams are all data streams obtained through cascaded interleaving. One specific implementation of cascaded interleaving includes channel permutation and convolutional interleaving, wherein channel permutation performs data permutation on the g input data streams to obtain g data-permuted data streams, which are then convolutionally interleaved to obtain g convolutionally interleaved data streams. Another specific implementation of cascaded interleaving includes channel multiplexing and convolutional interleaving, wherein channel multiplexing performs symbol multiplexing (symbol muxing) on ​​the g input data streams to obtain g1 symbol-multiplexed data streams, where g is divisible by g1, and then convolutionally interleaving the g1 data streams to obtain g1 convolutionally interleaved data streams, where g1 is not equal to g. In other words, the number of first data streams and second data streams obtained after the first data processing may be the same or different, depending on the actual application scenario and is not limited here. Possible implementations of convolution interleaving may be understood with reference to step 301 .

[0623] In some possible implementations, the first data processing may further include at least one of alignment lock, lane de-skew, and lane reordering.

[0624] In some possible implementations, the first data processing operation may further include scrambling. For example, each first data stream is first scrambled and then periodically inserted with a first identifier. This can improve synchronization quality when the receiving end performs synchronization.

[0625] 402. Perform second data processing on the m second data streams to obtain m third data streams.

[0626] In this embodiment, the second data processing operation includes, but is not limited to, performing a second FEC encoding on each second data stream. This second FEC encoding can be understood as the inner code encoding described above. That is, each of the m third data streams is obtained by undergoing the second FEC encoding, where m is an integer greater than 1. Typically, m is 4, 8, 16, 32, or 64. As an example, an inner code encoder is used to perform inner code encoding on each K information bits in each second data stream. That is, after adding S check bits, a total inner code codeword of N bits is obtained, i.e., N = K + S, where K ≥ 1 and S ≥ 1.

[0627] Figure 9 This is a structural diagram of the third data stream in the embodiment of the present application. Figure 9As shown, each third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of the bits are obtained through the second FEC encoding, W bits in each second bit sequence are a second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

[0628] It should be noted that the length of the first identifier inserted into each first data stream in step 401 is is a multiple of the inner code information length K, The integer e is an integer greater than 0. Moreover, in step 401, the periodic acquisition bits The integer b is an integer greater than 0. The first identifier is encoded by the inner code to obtain a second identifier with a length of W=N×e. bits and add The first identifier of the bit is obtained bits, the The bits are encoded by the inner code to obtain a length of P+W bits, where P=N×b. In the data stream after each second data stream is encoded by the inner code, there are W bits of second identifiers in each P+W bits. Figure 9 by Take W=N×e=N×2 as an example. In some specific implementations, the P+W bits are called a frame, and the W-bit second identifier is called a frame header.

[0629] In some possible implementations, the second data processing operation may further include at least one of channel interleaving and scrambling. For example, after each second data stream undergoes the second FEC encoding, it also undergoes at least one of channel interleaving and scrambling.

[0630] It should be noted that Figure 9 The second identifier shown is the structure of the data stream after inner code encoding. The data stream after inner code encoding may also undergo other operations, such as channel interleaving to disrupt the order. At this time, the data stream of the second identifier after channel interleaving will be disrupted; but the channel interleaving method is fixed and preset. The receiving end can restore the specific position of the second identifier in the data stream when performing inner code synchronization according to the channel interleaving method.

[0631] 403. Perform third data processing on the m third data streams to obtain Y modulation symbol streams.

[0632] In this embodiment, after performing third data processing including modulation on m third data streams, Y modulation symbol streams are obtained, where Y is an integer greater than or equal to 1.

[0633] In some possible implementations, the third data processing operation may further include at least one of codeword interleaving and symbol interleaving. For example, each third data stream undergoes codeword interleaving before being modulated. Another example is that each third data stream undergoes symbol interleaving after modulation, also known as channel interleaving. This interleaving can disrupt the order of colored noise in channel transmission, thereby improving signal quality at the receiving end.

[0634] It should be noted that in some specific applications, each n HM The third data stream is first channel interleaved to obtain a channel interleaved data stream, a total of m / n HM The data stream after the channels are interleaved. HM After the channels are interleaved, the data stream is modulated to obtain m / n HM Modulation symbol data stream, where m / n HM =Y. The channel interleaving will n HM The third data stream obtains an inner code word of length N bits, a total of n HM inner code words, the n HM The inner code words include n HM ×N bits, and poll (Round-Robin) to obtain 2 bits from each inner code word as the bits on the second data stream to obtain n consecutive bits on the data stream after channel interleaving. HM ×N bits. The channel interleaving is also called n HM -way Hamming codeword interleaving (n HM -wayHammingcodeword interleaver), also known as inner codeword interleaving.

[0635] Consider each n of the m third data streams above HM The third data stream is first channel interleaved and then modulated, resulting in a total of m / n HM The corresponding n HM In each of the third data streams in the second data stream Bits, total After the bits are encoded by inner code and channel interleaved, the total bits. bits is called a frame, and the n HM The first identifier is obtained by interleaving the coded channel The bit is called a frame identifier. In some specific implementations, the frame identifier is also called a frame header.

[0636] It should be noted that the The first identifier of bits may include a synchronization subsequence for receiving end frame synchronization, and the length of the synchronization subsequence is less than Each of the m second data streams contains a periodically inserted synchronization subsequence, for a total of m synchronization subsequences. In some specific applications, the lengths of the m synchronization subsequences are the same. bits. Each n bits in the m synchronization subsequences HM The synchronization subsequence is encoded by inner code and channel interleaved (n HM - Intra-channel code word interleaving) to obtain the channel interleaved data stream bits. bits can be called a frame synchronization sequence, or simply a synchronization sequence. HM Channel interleaved data stream, corresponding to m / n HM It should be noted that, in some specific embodiments, the n HM The specific bit patterns of the synchronization subsequences are not exactly the same, but m / n HM The specific bit patterns of the synchronization sequences are the same.

[0637] It should be noted that, in some other specific applications, each of the m second data streams includes a periodically inserted synchronization subsequence, for a total of m synchronization subsequences, and the lengths of the m synchronization subsequences are not all the same.

[0638] It should be noted that in some specific applications, in order to further improve the overall anti-burst performance of the cascade code, a period is inserted in the cycle. Before the first identifier of the bits, a cyclic shift operation is performed on the data in the data stream. The cyclic shift operation cyclically shifts every K information bits in the data stream to the left or to the right.

[0639] It should be noted that this application selects positive integers and The baud rate value of the modulated symbol data stream can be made an integer multiple of the reference clock frequency (reference clock), so that the implementation of clock extraction and clock synchronization at the receiving end is simpler, and fast phase locking can be performed, and the PLL complexity is low and the jitter is small. It should be understood that the present application does not limit the specific value of the reference clock frequency. For example, it can be the Ethernet common reference clock frequency (Ethernet common reference clock). As an example, the baud rate value of the modulated symbol data stream is an integer multiple of 156.25M. It should also be understood that in actual applications, a certain error range can also be accepted, for example, the baud rate value of the modulated symbol data stream is an integer multiple of 156.25M ±V (ppm), where V can be 20, 50 or 100.

[0640] Further select positive integers and can be divided by the inner code information length K, which enables the receiving end processing module to perform frame synchronization of received data (i.e., frame synchronization of P+W bits or Bit frame synchronization (also called identification lock operation) and codeword synchronization have low hardware implementation complexity. At the same time, further select positive integer The synchronization of the inner codewords can ensure the synchronization of the cascade deinterleaving. In other words, the data processing method provided by the present application material reduces the complexity of the receiving end processing module in performing frame synchronization, inner codeword synchronization and cascade deinterleaving synchronization.

[0641] It should be noted that the receiving end may first perform codeword synchronization and then frame synchronization, or may directly use the first identifier or the second identifier to perform frame synchronization bit by bit, which can ensure synchronization of codeword synchronization and cascade deinterleaving.

[0642] Below and The value requirements are introduced in detail.

[0643] Considering the 800GbE scenario, the transmitting device performs KP4 RS (544,514) outer code encoding on the 800GbE service data stream to be transmitted, obtaining a data stream with a total rate of 850Gbps. After PMA processing, it is sent to the transmitting processing module through the connection unit interface 800GAUI. The transmitting processing module periodically inserts the first identifier into each of the m first data streams, that is, after performing the first data processing, m second data streams are obtained, whose total rate is After the m second data streams are processed with the second data including the inner code, m third data streams are obtained, and their total rate is After the third data stream is processed by the third data including PAM4 modulation, four modulation symbol streams are obtained, whose baud rate is Here baud represents the modulation symbol rate transmitted per second. Assuming the reference clock frequency is PAM4 modulation

[0644] The baud rate of the symbol stream is an integer multiple of the Ethernet typical reference clock frequency. Where N is the code length of the inner code, K is the information bit length of the inner code, and a is a positive integer. G represents 10^9, and M represents 10^6. In this case, the clock extraction and clock synchronization at the receiving end are simple to implement, and fast phase locking can be performed. The PLL complexity is low and the jitter is small. A typical Ethernet reference clock frequency is 156.25MHz. In some 800GbE scenarios, considering the 112.5G baud rate, there is The overall PLL implementation is now simpler.

[0645] Further, when is a multiple of the inner code information length K and When it is a multiple of the inner code information length K, that is, Where b and e are positive integers. In the data stream after the second FEC encoding of the second data stream, the W bits at a fixed position in every P+W bits are the second identifier, which corresponds to The first identifier of the bit, where P=N×b, W=N×e; and every N bits of the P+W bits are an inner code word. In some specific embodiments, the P+W bits are called a frame, and the second identifier of the W bits is called a frame header. The receiving end can first perform inner code word synchronization on the received data stream and identify the inner code word boundary. Combined with the fixed position of the first bit position of the first identifier or the second identifier in the inner code code word, the above-mentioned first identifier or second identifier can be used to perform simple frame synchronization to identify the first identifier or the second identifier. When the receiving end processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called identifier locking operation), there is no need to perform complex bit-by-bit position identification.

[0646] It should be noted that, considering the m third data streams, each n HM The third data stream is first channel interleaved and then modulated, resulting in a total of m / n HM At this time, each channel on the data stream after channel interleaving Fixed position in bits bits are the frame synchronization sequence, which corresponds to n bits HM A first identification.

[0647] Furthermore, for the transmitting end processing module, the cascade interleaving including convolution interleaving is adopted. In order to ensure the synchronization of convolution deinterleaving during frame synchronization, the receiving end processing module should meet the requirement of (W+P bits or The starting position of the convolutional deinterleaver (frame synchronization of bits) corresponds to the input and output switches of the convolutional deinterleaver being located at the starting position of the switch, usually at the topmost position, such as the position of delay line 0 shown in Figures 4(a) and 4(b). More specifically, for every f bits output by the convolutional interleaver and convolutional deinterleaver, the input and output switches are located at the topmost position, and K×b is divisible by f, so that the synchronization of the convolutional deinterleaver can be guaranteed during frame synchronization. A specific method is: r*d*c=K×b, where r is the number of delay lines of the convolutional interleaver and convolutional deinterleaver, d is the number of bits stored in the storage units of the convolutional interleaver and convolutional deinterleaver, and c is a positive integer. In this way, based on the improvement of the transmitting end processing module of the present application, the receiving end processing module can achieve frame synchronization and codeword synchronization with low complexity. At the same time, the frame synchronization of the received data ensures the synchronization of the convolutional deinterleaver, simplifies the operations such as frame synchronization, inner codeword synchronization, and cascade interleaving synchronization at the receiving end, and achieves low complexity.

[0648] It should be noted that, in the data processing operation of this embodiment, the data stream is first periodically inserted For the first embodiment of this application, the data stream is firstly encoded with an inner code, and then the alignment mark of W bits is periodically inserted into the data stream after the inner code encoding. The first identifier of the bit is inner-coded to obtain the second identifier of W bits. When the second identifier is the same as the alignment identifier of W bits in the first embodiment, the effects achieved by the two embodiments are the same, that is, the two embodiments are equivalent at this time.

[0649] The following provides several implementation methods based on different inner code encoding methods to introduce the above and The possible values ​​of .

[0650] Implementation method 1: Inner code encoding uses an FEC code with an information length K=140 bits and a codeword length N=148 bits.

[0651] Consider an FEC code with an information length K=140 bits and a codeword length N=148 bits as the inner code, for example, Hamming (148, 140).

[0652] Figure 10 This is a schematic diagram of an implementation method of the internal code encoding in the embodiment of this application. For example, using Figure 10In the encoding scheme shown, the 140-bit data to be encoded is represented as B[139:0]. Each consecutive 2 bits are bit-wise XORed to obtain 1-bit data C[i], resulting in a total of 70 bits of data, represented as C[69:0], where C[i] = B[2*i]^B[2*i+1], 0≤i≤69. C[69:0] is then used as the information data and Hamming (78,70) encoded to obtain 8 bits of parity data, represented as P[7:0]. Finally, B[139:0] and P[7:0], a total of 148 bits, are concatenated to form the output of the inner code, represented as D[147:0]. D[139:0] comes from B[139:0], and D[147:140] comes from P[7:0].

[0653] Considering the 800GbE scenario, the baud rate of the PAM4 modulation symbol stream is Assuming the above baud rate value It is an integer multiple of the Ethernet typical reference clock frequency 156.25MHz, that is, Where a is a positive integer, G represents 10^9, and M represents 10^6. The clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and low jitter.

[0654] when and is a multiple of the inner code information length K, that is, The frame synchronization and inner code word synchronization operations at the receiving end have low complexity. The positive integer 5032×e is divisible by the positive integer b, and the positive integer It is divisible by 7. Table 11 below gives some parameter combinations and their corresponding baud rates.

[0655] Table 11

[0656]

[0657] Parameter combinations in Table X1 b, e can also be used in 1.6TbE scenarios; for 1.6TbE using PAM4 modulation, the corresponding parameter a and the corresponding baud rate are twice that of 800GbE. In some 800GbE scenarios using PAM4 modulation and 112.5G baud rate or 1.6TbE scenarios considering 225G baud rate, So b=629×e.

[0658] The inner code information length is K = 140 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner code and the outer code, there is a convolutional interleaver that outputs 140 bits with its input and output switches positioned at the top. For example, the convolutional interleaver has r = 7 delay lines, and each storage unit of the convolutional interleaver stores d = 20 bits. In this case, the receiving end processing module can achieve frame synchronization and codeword synchronization with low complexity. At the same time, the frame synchronization of the received data can ensure the synchronization of the convolutional deinterleaving, that is, obtain the input and output switch positions of the convolutional deinterleaving, simplifying the operations of the receiving end frame synchronization, inner codeword synchronization, and cascade interleaving synchronization, and achieving low complexity.

[0659] Implementation method 2: Inner code encoding uses an FEC code with an information length K = 120 bits and a codeword length N = 127 bits.

[0660] Consider an FEC code with an information length K=120 bits and a codeword length N=127 bits as the inner code, for example, Hamming (127, 120).

[0661] Figure 11 This is another schematic diagram of the implementation of the internal code encoding in the embodiment of this application. Figure 11 In the encoding method shown, the 120-bit data to be encoded is represented as B[119:0]. Each consecutive 2 bits are bit-wise XORed to obtain 1-bit data C[i], resulting in a total of 60 bits of data, represented as C[59:0], where C[i] = B[2*i]^B[2*i+1], 0≤i≤59. C[59:0] is then used as the information data and Hamming (67,60) encoded to obtain 7 bits of parity data, represented as P[6:0]. Finally, B[119:0] and P[6:0], a total of 127 bits, are concatenated to form the output of the inner code, represented as D[126:0]. D[119:0] comes from B[119:0], and D[126:120] comes from P[6:0].

[0662] Considering the 800GbE scenario, the baud rate of the PAM4 modulation symbol stream is Assuming the above baud rate value It is an integer multiple of the Ethernet typical reference clock frequency 156.25MHz, that is, Where a is a positive integer, G represents 10^9, and M represents 10^6. The clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and low jitter.

[0663] when and is a multiple of the inner code information length K, that is, The frame synchronization and inner code word synchronization operations at the receiving end have low complexity. The positive integer 2159×e is divisible by the positive integer b, and the positive integer It is divisible by 3. Table 12 below shows some parameter combinations and their corresponding baud rates.

[0664] Table 12

[0665]

[0666] In some 800GbE scenarios using PAM4 modulation and 112.5G baud rate or 1.6TbE scenarios considering 225G baud rate, So b = 2159 × e. In this case, the overall PLL implementation is simpler.

[0667] The above inner code information length is K = 120 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolution interleaver between the inner code encoding and the outer code encoding, there is a convolution interleaver whose input and output switch positions are located at the top for every 120 bits it outputs. For example, the number of delay lines of the convolution interleaver is r = 3, and each storage unit of the convolution interleaver stores d = 40 bits. For another example, the number of delay lines of the convolution interleaver is r = 6, and each storage unit of the convolution interleaver stores d = 20 bits. At this time, the receiving end processing module can achieve frame synchronization and codeword synchronization with low complexity. At the same time, the frame synchronization of the received data can ensure the synchronization of the convolution deinterleaving, that is, obtaining the input and output switch positions of the convolution deinterleaving, simplifying the operations of the receiving end frame synchronization, inner codeword synchronization, cascade interleaving synchronization, etc., and achieving low complexity.

[0668] It should be noted that when PAM4 modulation is used, each PAM4 symbol corresponds to 2 bits, where the MSB (Most Significant Bit) and LSB (Least Significant Bit) have different bit error rates. When the codeword bit length N is an odd number (such as the 127-bit FEC code length used in Implementation 2), two consecutive inner codewords will be generated. Figure 12 This is a schematic diagram of the structure of a codeword. Figure 12 As shown, the first bit of the K-bit information sequence (also referred to as information bit) of one codeword is the MSB, and the first bit of the K-bit information sequence of another codeword is the LSB, which is not conducive to the hardware implementation of inner code decoding at the receiving end.

[0669] To overcome the above problem, in some possible application scenarios, the t inner codewords after inner code encoding may be subjected to inner codeword interleaving, where t is an even number, such as 2, 4, 8, or 16. The inner codeword interleaving process is described in detail below.

[0670] Figure 13 This is a schematic diagram of the structure of another codeword. Figure 13 As shown, consider t inner code words D0, D1, D2, ..., D t；1 , where codeword D i (0≤i≤t-1) contains K bits of information sequence B i and a check sequence P of length S bits i More specifically, there are t information sequences B0, B1, B2, ..., B t；1 , t check sequences are P0, P1, P2, ..., P t；1 The inner code interleaving process interleaves the t inner code codewords with a total of t×N bits to obtain an interleaved sequence with a length of t×N bits. The interleaved sequence includes two consecutive bit subsequences, a first subsequence with a length of t×K bits and a second subsequence with a length of t×S bits. The first consecutive bit subsequence includes the t information sequences B0, B1, B2, ..., B t；1 The second subsequence of consecutive bits includes the t check sequences P0, P1, P2, ..., P t；1 . Please refer to Figure 13 The above codeword interleaving is also called a specific implementation scheme of channel interleaving.

[0671] It should be noted that the above information sequences of length t×K bits are B0, B1, B2, ..., B t；1 Perform inner code encoding to obtain t inner code words D0, D1, D2, ..., D t；1 Then, the inner codeword is interleaved to obtain the t×N bit interleaved sequence B0, B1, B2, ..., B t；1 ,P0,P1,P2,…,P t；1 In some possible scenarios, the inner code (N, K) encoding and the interleaving of t inner code codewords are combined to form an inner code (t×N, t×K) encoding. Those skilled in the art can distinguish between the (N, K) encoding and the (t×N, t×K) encoding based on the context, and this will not be repeated here.

[0672] It should be noted that the above t codewords D0, D1, D2, ..., D t；1, which is obtained by inner coding t×K bits in the same second data stream; it can also be obtained by inner coding from multiple second data streams, for example, t / 2 inner code words are obtained by inner coding from t / 2×K bits in one second data stream, and another t / 2 inner code words are obtained by inner coding from t / 2×K bits in another second data stream. The specific implementation method is known to ordinary technicians in this field and will not be repeated here.

[0673] Implementation method 3: Inner code encoding uses an FEC code with an information length K = 120 bits and a codeword length N = 128 bits.

[0674] Consider an inner code using an FEC code with an information length of K = 120 bits and a codeword length of N = 128 bits, such as a Hamming (128, 120) code. For another example, the 120-bit data to be encoded is represented as B[119:0]. Each consecutive 2 bits are bitwise XORed to obtain 1-bit data C[i], resulting in a total of 60 bits of data, represented as C[59:0]. Here, C[i] = B[2*i]^B[2*i+1], where 0≤i≤59. C[59:0] is then encoded using the Hamming (68, 60) method as the information data to obtain 8 bits of parity data, represented as P[7:0]. Finally, the 128 bits, B[119:0] and P[7:0], are concatenated to form the inner code output, represented as D[127:0]. Among them, D[119:0] comes from B[119:0], and D[127:120] comes from P[7:0].

[0675] Considering the 800GE scenario and using PAM4 modulation, data processing obtains 4 PAM modulation symbol streams. Under the first indicator of bit length, the baud rate of the PAM4 modulation symbol stream is The baud rate value is about 725.3333 times the reference clock frequency value 156.25M. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering each Bit insertion The baud rate of the PAM4 modulation symbol stream under the first identifier of bit length is 113.4375Gbaud, and its baud rate value is 726 times the reference clock frequency value of 156.25M.

[0676] Considering the 800GbE scenario, the baud rate of the PAM4 modulation symbol stream is have 113.4375, at this time consider and It is an integer multiple of the inner code information length K, and the frame synchronization and inner code word synchronization operations at the receiving end have low complexity.

[0677] Figure 23 This is another schematic diagram of data processing in the embodiment of this application. Figure 23 , the specific data processing process is introduced below:

[0678] A first identifier is periodically inserted into each of the m=32 first FEC-encoded data streams to obtain a total of m=32 second data streams. Specifically, a first identifier is periodically obtained from each of the data streams. bits and insert The first identifier of the bit length makes each second data stream bits exist The first identifier is bits long.

[0679] Each of the m=32 second data streams is inner-coded to obtain m=32 third data streams. Specifically, each K=120 information bits in each second data stream are inner-coded, i.e., S=8 check bits are added to obtain a total of N=128 bits of inner codewords.

[0680] For each n of m=32 third data streams HM = 8 third data streams are processed with the third data including PAM4 modulation to obtain a total of Y = m / n HM = 4 modulation symbol streams. More specifically, channel interleaving is first performed on each of the 32 third data streams to obtain one channel-interleaved data stream, resulting in a total of 4 channel-interleaved data streams. Figure 23 ,For 800GE scenario, data processing includes four data sub-processing, namely Figure 23 Data sub-processing 0, data sub-processing 1, data sub-processing 2, and data sub-processing 3 in the data stream. Each data sub-processing includes 1 channel interleaving. The channel interleaving obtains 1 inner codeword of length 128 bits from each of the 8 input third data streams, a total of 8 inner codewords, and polls (Round-Robin) to obtain 2 bits from each inner codeword as the bits on the data stream after the channel interleaving to obtain 1024 consecutive bits on the data stream after the channel interleaving. The channel interleaving is also called 8-way Hamming codeword interleaver, or inner codeword interleaving. Then, PAM4 modulation is performed on the 4 channel interleaved data streams to obtain Y=4 modulation symbol streams.

[0681] Figure 24This is a structural diagram of the first identifier in the embodiment of this application. For example, insert the cycle The specific structure of the first identifier with a bit length is introduced below. Figure 24 As shown, a periodic insertion is performed on each of the m=32 data streams encoded by the first FEC. The first identifier of the bit results in a total of m=32 second data streams. The first bit identifier contains the bit length The synchronization subsequence of the 8 first identifiers in the 8 second data streams corresponding to each data sub-processing, that is, Figure 24 Synchronous subsequence 0, synchronous subsequence 1, ..., synchronous subsequence 7 in the total bits can be used for frame synchronization at the receiving end.

[0682] In some specific applications, the The synchronization subsequence of the bit is located in the second data stream The first consecutive bit positions. Figure 24 As shown, this embodiment uses The specific bit patterns of the 8 synchronization subsequences are shown in Table 14.

[0683] Table 14

[0684]

[0685] Figure 25 This is a structural diagram of a synchronization sequence after channel interleaving in an embodiment of the present application. It should be noted that the specific bit patterns of the 8 synchronization subsequences are not exactly the same. Figure 25 , the 8 synchronization subsequences are After the inner code encoding and inner code codeword interleaving, the bits are located in 48 consecutive bits in the corresponding channel interleaved data stream, and the specific bit pattern is 01011001010100100110010010100110101010110011011 (transmitted from left to right). The 48 bits can be used for frame synchronization at the receiving end, also known as the frame synchronization sequence, or simply referred to as the synchronization sequence. The leftmost bit in the bit pattern here is sent first in actual transmission. The synchronization sequence of 48 consecutive bits in the corresponding channel interleaved data stream can be expressed in hexadecimal, which is 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9 (wherein the 8 bits within a byte have their LSB transmitted first). It should be noted that although the specific bit patterns of the 8 synchronization subsequences are not exactly the same, the specific bit patterns of the 4 synchronization sequences corresponding to the data streams after the 4 channels are interleaved are the same, namely 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0686] Implementation 4:

[0687] Figure 26 This is another structural diagram of the first identifier in the embodiment of the present application. Based on the implementation method 3, each of the m=32 data streams encoded by the first FEC is periodically inserted into The first identifier of the bit results in a total of m=32 second data streams. The lengths of the synchronization subsequences contained in the first identifiers periodically inserted in the m=32 second data streams are not completely equal. Figure 26 The specific structure of 8 synchronization subsequences in each data sub-process is given.

[0688] The specific bit patterns of the eight synchronization subsequences are shown in Table 15. The lengths of the eight synchronization subsequences are not all the same. Specifically, the bit length of synchronization subsequence 0, synchronization subsequence 1, synchronization subsequence 2, and synchronization subsequence 3 is 8, and the bit length of synchronization subsequence 4, synchronization subsequence 5, synchronization subsequence 6, and synchronization subsequence 7 is 4.

[0689] Table 15

[0690]

[0691]

[0692] Figure 27 This is another structural diagram of the synchronization sequence after channel interleaving in the embodiment of the present application. Figure 27, the 8 synchronization subsequences, totaling 48 bits, correspond to 48 bits in the corresponding channel interleaved data stream after inner code encoding and inner code codeword interleaving. The 48 bits can be used for frame synchronization at the receiving end, also known as a frame synchronization sequence, or simply a synchronization sequence. The 48-bit synchronization sequence is not arranged continuously in the channel interleaved data stream, and it contains 2 partial bit sequences, the first partial bit sequence contains 24 bits, and the second partial bit sequence contains 24 bits. The first partial bit sequence and the second partial bit sequence are separated by 8 bits (i.e., one byte). Here, the interval between two consecutive bits is defined as 0 bit.

[0693] In some specific applications, the specific value of the first part of the 24-bit bit sequence is 0101100101010010 01100100 (transmitted from left to right), and the specific value of the second part of the 24-bit bit sequence is 10100110 10101101 10011011 (transmitted from left to right). Here, the leftmost bit in the bit pattern is sent first in the actual transmission. The first part of the bit sequence and the second part of the bit sequence can be represented in hexadecimal, the first part of the bit sequence is 0x9A, 0x4A, 0x26, and the second part of the bit sequence is 0x65, 0xB5, 0xD9. It should be noted that the specific bit patterns of the four synchronization sequences corresponding to the data streams after the four channels are interleaved are the same, all of which are 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9.

[0694] It should be noted that, in the 48-bit synchronization sequence, the first part of the bit sequence contains 24 bits, the second part of the bit sequence contains 24 bits, and the first part of the bit sequence and the second part of the bit sequence are separated by 8 bits (one byte). Figure 16 It can be seen that by adopting the data processing method of this embodiment, the relevant calculator architecture for receiving end synchronization can reuse the synchronization hardware implementation architecture in the existing 100GE 802.3bj and 400GE 802.3bs standards, which is easy to implement.

[0695] Implementation 5:

[0696] Figure 28 This is another embodiment of data processing in the present application. Based on the third embodiment, considering the 1.6TE scenario and using PAM4 modulation, the data processing obtains 8 PAM modulation symbol streams. Under the first indicator of bit length, the baud rate of the PAM4 modulation symbol stream is The baud rate value is about 725.3333 times the reference clock frequency value 156.25M. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering the period insertion The baud rate of the PAM4 modulation symbol stream under the first identifier of bit length is 113.4375Gbaud, and its baud rate value is 726 times the reference clock frequency value of 156.25M.

[0697] Considering the 1.6TE scenario, the baud rate of the PAM4 modulation symbol stream is have at this time consider and It is an integer multiple of the inner code information length K, and the frame synchronization and inner code word synchronization operations at the receiving end have low complexity. For the specific data processing process, please refer to Figure 28 For understanding, the data processing includes 8 data sub-processings, namely data sub-processings 0 to 7. The specific operation of each data sub-processing can be understood by referring to Implementation 3.

[0698] Implementation 6:

[0699] Figure 29 This is another structural diagram of the first identifier in the embodiment of the present application. Based on the implementation method 3, each of the m=32 data streams encoded by the first FEC is periodically inserted into The first identifier of the bit results in a total of m=32 second data streams. Figure 29 As shown, each second data stream The first bit identifier contains the bit length Each data sub-processing corresponds to 8 second data streams The first bit identifier contains the bit length The synchronization subsequence of Figure 29 The synchronization subsequences 0, 1, ..., 7 in the embodiment are identical. It should be noted that, based on Implementation 6, channel interleaving is not necessarily required during data processing. That is, Implementation 6 is decoupled from channel interleaving.

[0700] More specifically, the bit length of each synchronization subsequence is They are not all arranged continuously in the first identifier. Each of the synchronization subsequences includes two partial bit sequences, the first partial bit sequence includes 24 bits, and the second partial bit sequence includes 24 bits, and the first partial bit sequence and the second partial bit sequence are separated by 8 bits. Here, the interval between two consecutive bits is defined as 0 bits.

[0701] In some specific applications, the first part of the bit sequence with a length of 24 bits has specific values: 0x9A, 0x4A, 0x26, and the second part of the bit sequence with a length of 24 bits has specific values: 0x65, 0xB5, 0xD9.

[0702] In some specific applications, the specific data processing scheme of the present invention is adopted, and the receiving end can perform frame synchronization based on the 8 synchronization subsequences totaling 384 bits, that is, the receiving end performs frame synchronization based on the received data stream at a rate of about 200G. In other specific applications, the receiving end can first perform channel deinterleaving on the received data stream at a rate of about 200G according to the channel interleaving rules to obtain 8 channel deinterleaved data streams, where each channel deinterleaved data stream has a rate of about 25G, and then synchronize each channel deinterleaved data stream according to the known synchronization subsequence. It should be noted that when the receiving end adopts the above-mentioned synchronization scheme based on the 25G rate, the 8 channel deinterleaved data streams are not completely aligned. The order of the channel deinterleaved data streams in the 8 channel deinterleaved data streams can be determined based on the position of the synchronization subsequence obtained after the synchronization of each channel deinterleaved data stream, so as to achieve the correct recovery of the order of the data streams and the synchronization alignment.

[0703] Implementation 7:

[0704] Figure 30 This is another embodiment of the data processing in the present application. Based on the third embodiment, insert Before the first identifier of the bit, a cyclic shift operation is performed on the data in the data stream. Figure 30 As shown, the cyclic shift operation cyclically shifts every K=120 bits to the right to improve the anti-burst performance of the overall concatenated code.

[0705] Implementation 8:

[0706] Figure 31 This is another embodiment of the data processing in the present application. Based on the third embodiment, insert Before the first identifier of the bits, a convolution interleaving operation is performed on the data in the data stream. Figure 31As shown, for each of the 32 first data streams, eight first data streams are first convolutionally interleaved to obtain eight convolutionally interleaved data streams. Cyclic shifts are then performed every K = 120 bits, followed by periodic insertion of a first identifier to obtain eight second data streams. Inner code encoding is then performed to obtain eight third data streams, which are then channel interleaved (inner codeword interleaving) to obtain one channel-interleaved data stream. Convolutional interleaving is also performed before inner code encoding, improving the performance of the overall concatenated code under AWGN conditions.

[0707] Implementation 9:

[0708] Figure 32 This is another schematic diagram of the data processing in the embodiment of the present application. Based on the eighth embodiment, in each data sub-processing, the two input data streams are respectively subjected to convolution interleaving processing to obtain two convolution interleaved data streams. Each convolution interleaved data stream is subjected to data distribution (distribution) to obtain four distributed first data streams, and a total of eight distributed first data streams are obtained. The data distribution is based on the granularity of α0 bits. Figure 32 As shown, after convolutional interleaving, when α0 bits are grouped together in the data stream, for four consecutive groups of 4×α0 bits, the 0th group of α0 bits is sent to the 0th data stream of the four distributed first data streams, the 1st group of α0 bits is sent to the 1st data stream of the four distributed first data streams, the 2nd group of α0 bits is sent to the 2nd data stream of the four distributed first data streams, and the 3rd group of α0 bits is sent to the 3rd data stream of the four distributed first data streams. Typically, the distribution bit granularity is α0 = 120.

[0709] It should be noted that for 800GE scenarios, data processing includes four data sub-processing steps, such as Figure 32 Each data sub-process corresponds to two input data streams. The two input data streams correspond to a bit rate of approximately 200 Gbps, that is, each input data stream corresponds to a bit rate of approximately 100 Gbps. Correspondingly, the first data stream after distribution corresponds to a bit rate of approximately 25 Gbps.

[0710] It should also be noted that when the distribution bit granularity is α0=120, Figure 32The data processing shown can be described as performing convolution interleaving on two input data streams, resulting in a total of two convolution interleaved data streams. Four bit blocks are obtained from each convolution interleaved data stream, each of which is 120 bits long. Each bit block is cyclically shifted and inner-coded to obtain four inner-code codewords. A total of eight bit blocks are obtained from the two convolution interleaved data streams, which are then cyclically shifted and inner-coded to obtain a total of eight inner-code codewords. Channel interleaving is then performed to obtain 1024 bits on the channel-interleaved data stream.

[0711] It should be noted that for the 1.6TE scenario, data processing includes eight data sub-processes, each of which corresponds to two input data streams. These two input data streams correspond to a bit rate of approximately 200 Gbps, meaning each input data stream corresponds to a bit rate of approximately 100 Gbps. Correspondingly, the first data stream after distribution corresponds to a bit rate of approximately 25 Gbps.

[0712] Implementation 10:

[0713] Figure 33 This is another schematic diagram of the data processing in the embodiment of the present application. Based on the eighth embodiment, the data processing includes four input data streams, and each data sub-processing includes one input data stream. Each input data stream is subjected to convolution interleaving processing to obtain one convolution interleaved data stream. The one convolution interleaved data stream is subjected to data distribution to obtain eight distributed first data streams. The data distribution is based on a 0 bit granularity. Figure 33 As shown, in the first data stream after convolutional interleaving, with α0 bits as a group, for eight consecutive groups totaling 8×α0 bits, the 0th group of α0 bits is sent to the 0th data stream of the eight distributed first data streams, the 1st group of α0 bits is sent to the 1st data stream of the eight distributed first data streams, ..., and the 7th group of α0 bits is sent to the 7th data stream of the eight distributed first data streams. Typically, the distribution bit granularity is α0 = 120.

[0714] It should be noted that for 800GE scenarios, data processing includes four data sub-processing steps, such as Figure 33 As shown, the data stream input of each data sub-process is one data stream, corresponding to a bit rate of approximately 200G per second. Correspondingly, the first data stream after distribution corresponds to a bit rate of approximately 25G per second.

[0715] It should be noted that for the 1.6TE scenario, data processing includes eight data sub-processes, where the data stream input of each data sub-process is one data stream, corresponding to a bit rate of approximately 200G per second. Correspondingly, the first data stream after distribution corresponds to a bit rate of approximately 25G per second.

[0716] It should be noted that if Figure 32 The input data stream shown in FIG is distributed after convolution interleaving to obtain four first data streams, as shown in FIG. Figure 33 The input data stream shown is distributed after convolution interleaving to obtain 8 first data streams, which can be understood as each first data stream has undergone convolution interleaving.

[0717] It should be noted that, in Embodiments 3 to 10, each of the eight second data streams includes a periodically inserted Bit first identifier, total length is Bit. Part of the bits are used for frame synchronization at the receiving end, that is, as the above-mentioned frame synchronization sequence, and the remaining bits can be used to transmit link information and / or control information, including the receiving end status, FEC status, etc., also known as the status field. Specifically, in order to improve the accuracy of the transmitted link information and / or control information, the Of the remaining bits excluding the frame synchronization sequence, bits are used to indicate the type of link information and / or control information, bits are used to indicate the specific content of the indication link information and / or control information, bits are used for cyclic redundancy check CRC (Cyclic Redundancy Check). Typically, The value of is 8, 16 or 32. In other specific applications, it is necessary to use multiple frames to collaboratively transmit the indication link information and / or control information to further improve the accuracy of the transmitted information. Bit bits are used to refer to the multiple frames, the bits are also called multi-frame synchronization signals. Typically,

[0718] In some specific applications, such as Figure 26 The 8 synchronization subsequences in the frame synchronization sequence have a total of 48 bits as the frame synchronization sequence, which are distributed in the 8 second data streams, wherein each of the 4 second data streams contains 8 bits in the frame synchronization sequence (i.e., synchronization subsequences 0-3), and each of the other 4 second data streams contains 4 bits in the frame synchronization sequence (i.e., synchronization subsequences 4-7). The 4 bits of each synchronization subsequence in the synchronization subsequences 4-7 are located in the The 0th, 1st, 4th and 5th bit positions in the bit first identifier (i.e., the first identifier 4, the first identifier 5, the first identifier 6, and the first identifier 7) can be understood with reference to Table 15. The 2nd, 3rd, 6th and 7th bit positions in the first identifier 4, the first identifier 5, the first identifier 6, and the first identifier 7 are a total of 16 bit positions, of which 8 bit positions are used for the 8 bits required for the CRC8 check, or 8 bit positions are used for the 8 bits required to indicate the type of link information and / or control information, or 8 bit positions are used for the 8 bits required for the multi-frame synchronization signal.

[0719] It should be noted that based on the above Figure 7 The data processing method applied to the transmitting end is shown in FIG. 1 . Correspondingly, the data processing method applied to the receiving end includes the following steps. First, the received Y modulation symbol streams are subjected to the fourth data processing to obtain m fourth data streams. For the characteristics and generation method of the modulation symbol stream, please refer to the above Figure 7 The relevant description of the illustrated embodiment will not be repeated here. After performing a fourth data processing including demodulation on the Y modulated symbol streams, m fourth data streams are obtained. The fourth data processing performed by the receiving end is the inverse of the third data processing performed by the transmitting end. Furthermore, frame synchronization is performed on each fourth data stream. It should be understood that the receiving end performs identifier lock based on the identifier added to the data stream by the transmitting end to determine the boundary of each frame (P + W bits) in the fourth data stream, thereby achieving codeword synchronization and / or frame synchronization.

[0720] It should be understood that after the receiving end completes codeword synchronization and / or frame synchronization, it will also perform the fifth data processing on the m fourth data streams, wherein the fifth data processing can be understood as the inverse operation of the second data processing performed by the sending end. For example, the fifth data processing includes but is not limited to inner code decoding and cascade deinterleaving, wherein cascade deinterleaving includes convolutional deinterleaving, which will not be described one by one here.

[0721] The following describes a data processing device provided in an embodiment of the present application.

[0722] Figure 34 FIG. 1 is a structural diagram of a data processing device applied to a sending end in an embodiment of the present application. Figure 34 As shown, the data processing device includes a first data processing unit 701, a second data processing unit 702 and a third data processing unit 703. The first data processing unit 701 is used to perform the above Figure 3 The operation of step 301 in the embodiment shown or the above Figure 7 The second data processing unit 702 is used to perform the operation of step 401 in the embodiment shown. Figure 3 The operation of step 302 in the embodiment shown or the above Figure 7The operation of step 402 in the embodiment shown. The third data processing unit 703 is used to perform the above Figure 3 The operation of step 303 in the embodiment shown or the above Figure 7 The operation of step 403 in the embodiment shown. For specific operations, please refer to the above Figure 3 and Figure 7 The relevant introduction of the illustrated embodiment will not be repeated here.

[0723] Figure 35 FIG. 1 is a structural diagram of a data processing device applied to a receiving end in an embodiment of the present application. Figure 35 As shown, the data processing device includes a data processing unit 801 and a synchronization unit 802. The data processing unit 801 is used to perform the above Figure 6 The operation of step 601 in the embodiment shown. The synchronization unit 802 is used to perform the above Figure 6 The operation of step 602 in the embodiment shown in the figure can be referred to above for specific operation. Figure 6 The relevant introduction of the illustrated embodiment will not be repeated here.

[0724] It should be understood that the device provided in this application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0725] Figure 36 FIG. 1 is another structural diagram of the data processing device in the embodiment of the present application. Figure 36 As shown, the data processing device includes a processor 901, a memory 902 and a transceiver 903. The processor 901, the memory 902 and the transceiver 903 are interconnected via a line. Among them, the memory 902 is used to store program instructions and data. Specifically, the processor 901 is used to perform data processing operations, and the transceiver 903 is used to perform data transmission and reception operations. In a possible embodiment, the processor 901 may include the above Figure 34 The first data processing unit 701, the second data processing unit 702 and the third data processing unit 703 are shown. In another possible implementation, the processor 901 may include the above Figure 35 The data processing unit 801 and the synchronization unit 802 are shown.

[0726] It should be noted that the above Figure 36The processor shown in the figure may be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. Figure 36 The memory shown in can store an operating system and other application programs. When the technical solutions provided in the embodiments of the present application are implemented by software or firmware, the program code for implementing the technical solutions provided in the embodiments of the present application is stored in the memory and executed by the processor. In one embodiment, the processor may include a memory. In another embodiment, the processor and the memory are two independent structures.

[0727] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0728] Those skilled in the art will appreciate that all or part of the steps in the above embodiments can be implemented by hardware or by programs instructing the relevant hardware to perform the steps. The programs can be stored in a computer-readable storage medium, which can be a read-only memory, a random access memory, or the like. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0729] When software is used for implementation, the method steps described in the above embodiment can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

Claims

1. A data processing method, characterized in that: include: A first data stream that has been encoded by the first forward error correction (FEC) is subjected to a first data processing to obtain a second data stream, wherein the second data stream includes at least one first bit sequence, and each first bit sequence includes bits, each of the first bit sequences bits come from the first data stream, each of the first bit sequences bits are the first identifier added; performing second data processing on the second data stream to obtain a third data stream, the second data processing including second FEC encoding, each codeword after the second FEC encoding includes N bits, N=K+S, where K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1; The third data stream is subjected to third data processing to obtain Y modulation symbol streams, where Y is an integer greater than or equal to 1, each modulation symbol stream is modulated, and the baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

2. The method according to claim 1, characterized in that The third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of bits are obtained through the second FEC encoding, W bits in each second bit sequence are a second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

3. The method according to claim 1 or 2, characterized in that 4. The method according to any one of claims 1 to 3, characterized in that The performing first data processing on the first data stream after the first FEC encoding to obtain the second data stream includes: Performing first data processing on m FEC-encoded first data streams to obtain m second data streams, where m is an integer greater than 1, and each second data stream includes at least one first bit sequence; The performing second data processing on the second data stream to obtain a third data stream includes: Performing second data processing on the m second data streams to obtain m third data streams; The performing third data processing on the third data stream to obtain Y modulation symbol streams includes: Perform third data processing on the m third data streams to obtain Y modulation symbol streams.

5. The method according to any one of claims 1 to 4, characterized in that The first data stream has also undergone convolution interleaving, and the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between two adjacent delay lines is Q, and each storage unit is used to store d bits. The bits in the input data stream are input into the r delay lines in sequence according to the sequence numbers of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the continuous r*d bits in the data stream output include d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

6. The method according to claim 5, characterized in that After convolution interleaving, every time f bits are output, the input and output switches corresponding to the convolution interleaving are located in the 0th delay line, and the K×b can be divided by f.

7. The method according to claim 5 or 6, characterized in that r×d×c=K×b, where c is an integer greater than or equal to 1.

8. The method according to any one of claims 1 to 7, characterized in that The baud rate of the modulation symbol stream is And the baud rate value is Wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

9. The method according to any one of claims 1 to 8, characterized in that N=128, K=120.

10. The method according to any one of claims 1 to 9, characterized in that The baud rate of the modulation symbol stream is 113.4375 Gbaud.

11. The method according to any one of claims 1 to 10, characterized in that Performing third data processing on the m third data streams to obtain Y modulation symbol streams includes: performing channel interleaving on each group of eight third data streams in the m third data streams to obtain one fourth data stream, so as to obtain a total of Y fourth data streams; The Y fourth data streams are modulated respectively to obtain the Y modulation symbol streams.

12. The method according to claim 11, characterized in that The first identifier in each of the second data streams includes a length of bits of synchronization subsequence, wherein the synchronization subsequence is located in the first identifier starting from the starting position bits.

13. The method according to claim 12, characterized in that A group of 8 third data streams among the m third data streams are obtained by a group of 8 second data streams among the m second data streams through the second FEC encoding, and a fourth data stream obtained by channel interleaving of the group of 8 third data streams includes a synchronization sequence with a length of 48 bits, and the synchronization sequence with a length of 48 bits is continuous in the 1 fourth data stream. The synchronization sequence with a length of 48 bits includes 1 synchronization subsequence included in each of the group of 8 second data streams, a total of 8 synchronization subsequences.

14. The method according to claim 13, characterized in that The values ​​of the 48 bits of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5 and 0xD9.

15. The method according to claim 13 or 14, characterized in that The synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 010110; The synchronization subsequence 1 included in the first second data stream of the group of 8 second data streams is 011010; The synchronization subsequence 2 included in the second second data stream in the group of 8 second data streams is 100111; The synchronization subsequence 3 included in the third second data stream in the group of 8 second data streams is 010001; The synchronization subsequence 4 included in the fourth second data stream in the group of eight second data streams is 011010; The synchronization subsequence 5 included in the fifth second data stream in the group of eight second data streams is 011001; The synchronization subsequence 6 included in the sixth second data stream in the group of eight second data streams is 000110; The synchronization subsequence 7 included in the seventh second data stream in the group of eight second data streams is 101011.

16. The method according to any one of claims 11 to 15, characterized in that N=128, K=120, performing channel interleaving on each group of eight third data streams to obtain one fourth data stream includes: Obtaining one inner code word with a length of 128 bits from each third data stream of each group of eight third data streams to obtain a total of eight inner code words; Polling obtains 2 bits from each of the 8 inner code words to obtain 1024 consecutive bits in the fourth data stream.

17. The method according to any one of claims 1 to 16, characterized in that Performing first data processing on the m first data streams includes: Perform cyclic shift on the m first data streams respectively.

18. The method according to claim 17, characterized in that Before cyclically shifting the m first data streams respectively, performing first data processing on the m first data streams includes: Convolution interleaving is performed on the m first data streams respectively.

19. The method according to claim 17, wherein Before cyclically shifting the m first data streams respectively, the method further includes: Perform convolution interleaving on each of the m / 8 input data streams; Each input data stream after convolution interleaving is distributed to obtain 8 first data streams, so as to obtain a total of m first data streams.

20. A data processing method, characterized in that: include: Performing a fourth data processing on the received Y modulation symbol streams to obtain m fourth data streams, wherein Y is an integer greater than or equal to 1, each of the fourth data streams is demodulated, and the baud rate value of each modulation symbol stream is an integer multiple of 156.25M. The Y modulation symbol streams are obtained by performing a third data processing on m third data streams, each of the modulation symbol streams is modulated, and the m third data streams are obtained by performing a second data processing on m second data streams, and the m second data streams are obtained by performing a first data processing on m first data streams that have undergone first forward error correction (FEC) encoding, and m is an integer greater than 1. Each of the second data streams includes at least one first bit sequence, and each of the first bit sequences includes bits, each of the first bit sequences bits come from the first data stream, each of the first bit sequences bits are added as a first identifier, the second data processing includes a second FEC encoding, each codeword after the second FEC encoding includes N bits, N=K+S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1; Codeword synchronization and / or frame synchronization are performed on each of the fourth data streams.

21. The method according to claim 20, characterized in that 22. The method according to claim 20 or 21, characterized in that The baud rate of the modulation symbol stream is And the baud rate value is Wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

23. The method according to any one of claims 20 to 22, characterized in that N=128, K=120.

24. The method according to any one of claims 20 to 23, characterized in that The baud rate of the modulation symbol stream is 113.4375 Gbaud.

25. The method according to any one of claims 20 to 24, characterized in that Y=4, or Y=8.

26. A data processing method, characterized in that: include: A first data stream that has been encoded by the first forward error correction (FEC) is subjected to a first data processing to obtain a second data stream, wherein the second data stream includes at least one first bit sequence, and each first bit sequence includes bits, each of the first bit sequences bits come from the first data stream, each of the first bit sequences bits are the first identifier added; performing second data processing on the second data stream to obtain a third data stream, the second data processing including second FEC encoding, each codeword after the second FEC encoding includes N bits, N=K+S, where K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1; A third data processing is performed on the third data stream to obtain Y modulation symbol streams, where Y is an integer greater than or equal to 1, and each modulation symbol stream is modulated.

27. The method according to claim 26, characterized in that The third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of bits are obtained through the second FEC encoding, W bits in each second bit sequence are a second identifier, and the second identifier is obtained by the first identifier through the second FEC encoding, P=N×b, W=N×e.

28. The method according to claim 26 or 27, characterized in that The baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

29. The method according to any one of claims 26 to 28, characterized in that The performing first data processing on the first data stream after the first forward error correction (FEC) encoding to obtain the second data stream includes: Performing first data processing on m first data streams that have undergone first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, and each second data stream includes at least one first bit sequence; The performing second data processing on the second data stream to obtain a third data stream includes: Performing second data processing on the m second data streams to obtain m third data streams; The performing third data processing on the third data stream to obtain Y modulation symbol streams includes: Perform third data processing on the m third data streams to obtain Y modulation symbol streams.

30. The method according to any one of claims 26 to 29, characterized in that The first data stream has also undergone convolution interleaving, and the convolution interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between two adjacent delay lines is Q, and each storage unit is used to store d bits. The bits in the input data stream are input into the r delay lines in sequence according to the sequence numbers of the r delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the continuous r*d bits in the data stream output include d bits output by each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

31. The method according to claim 30, characterized in that After convolution interleaving, every time f bits are output, the input and output switches corresponding to the convolution interleaving are located in the 0th delay line, and the K×b can be divided by f.

32. The method according to claim 30 or 31, characterized in that r×d×c=K×b, where c is an integer greater than or equal to 1.

33. The method according to any one of claims 26 to 32, characterized in that The baud rate of the modulation symbol stream is And the baud rate value is Wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

34. The method according to any one of claims 26 to 33, wherein: N=128, K=120.

35. The method according to any one of claims 26 to 34, characterized in that The baud rate of the modulation symbol stream is 113.4375 Gbaud.

36. The method according to any one of claims 26 to 35, characterized in that Performing third data processing on the m third data streams to obtain Y modulation symbol streams includes: performing channel interleaving on each group of eight third data streams in the m third data streams to obtain one fourth data stream, so as to obtain a total of Y fourth data streams; The Y fourth data streams are modulated respectively to obtain the Y modulation symbol streams.

37. The method according to claim 36, wherein The first identifier in each of the second data streams includes a length of bits of synchronization subsequence, wherein the synchronization subsequence is located in the first identifier starting from the starting position bits.

38. The method according to claim 37, wherein A group of 8 third data streams among the m third data streams are obtained by a group of 8 second data streams among the m second data streams through the second FEC encoding, and a fourth data stream obtained by channel interleaving of the group of 8 third data streams includes a synchronization sequence with a length of 48 bits, and the synchronization sequence with a length of 48 bits is continuous in the 1 fourth data stream. The synchronization sequence with a length of 48 bits includes 1 synchronization subsequence included in each of the group of 8 second data streams, a total of 8 synchronization subsequences.

39. The method according to claim 38, characterized in that The values ​​of the 48 bits of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5 and 0xD9.

40. The method according to claim 38 or 39, characterized in that The synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 010110; The synchronization subsequence 1 included in the first second data stream of the group of 8 second data streams is 011010; The synchronization subsequence 2 included in the second second data stream in the group of 8 second data streams is 100111; The synchronization subsequence 3 included in the third second data stream in the group of 8 second data streams is 010001; The synchronization subsequence 4 included in the fourth second data stream in the group of eight second data streams is 011010; The synchronization subsequence 5 included in the fifth second data stream in the group of eight second data streams is 011001; The synchronization subsequence 6 included in the sixth second data stream in the group of eight second data streams is 000110; The synchronization subsequence 7 included in the seventh second data stream in the group of eight second data streams is 101011.

41. The method according to any one of claims 26 to 40, wherein: N=128, K=120, performing channel interleaving on each group of eight third data streams to obtain one fourth data stream includes: Obtaining one inner code word with a length of 128 bits from each third data stream of each group of eight third data streams to obtain a total of eight inner code words; Polling obtains 2 bits from each of the 8 inner code words to obtain 1024 consecutive bits in the fourth data stream.

42. The method according to any one of claims 26 to 41, wherein: Performing first data processing on the m first data streams includes: Perform cyclic shift on the m first data streams respectively.

43. The method according to claim 42, characterized in that Before cyclically shifting the m first data streams respectively, performing first data processing on the m first data streams includes: Convolution interleaving is performed on the m first data streams respectively.

44. The method according to claim 42, wherein Before cyclically shifting the m first data streams respectively, the method further includes: Perform convolution interleaving on each of the m / 8 input data streams; Each input data stream after convolution interleaving is distributed to obtain 8 first data streams, so as to obtain a total of m first data streams.

45. A data processing method, characterized in that: include: Performing a fourth data processing on the received Y modulation symbol streams to obtain m fourth data streams, wherein Y is an integer greater than or equal to 1, each of the fourth data streams is demodulated, and the Y modulation symbol streams are obtained by performing a third data processing on m third data streams, each of the modulation symbol streams is modulated, and the m third data streams are obtained by performing a second data processing on m second data streams, and the m second data streams are obtained by performing a first data processing on m first data streams that have undergone first forward error correction (FEC) encoding, and m is an integer greater than 1, and each of the second data streams includes at least one first bit sequence, and each of the first bit sequences includes bits, each of the first bit sequences bits come from the first data stream, each of the first bit sequences bits are added as a first identifier, the second data processing includes a second FEC encoding, each codeword after the second FEC encoding includes N bits, N=K+S, K represents the number of information bits, S represents the number of check bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1; Codeword synchronization and / or frame synchronization are performed on each of the fourth data streams.

46. ​​The method according to claim 45, characterized in that The baud rate value of each modulation symbol stream is an integer multiple of 156.25M.

47. The method according to claim 45 or 46, characterized in that The baud rate of the modulation symbol stream is And the baud rate value is Wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

48. The method according to any one of claims 45 to 47, wherein: N=128, K=120.

49. The method according to any one of claims 45 to 48, wherein The baud rate of the modulation symbol stream is 113.4375 Gbaud.

50. The method according to any one of claims 45 to 49, wherein Y=4, or Y=8.

51. A data processing device, characterized in that: The device includes a processor and a transceiver, the transceiver is used to perform data transmission and reception operations, and the processor is used to execute the method according to any one of claims 1 to 50.

52. A chip, characterized in that: The chip includes a processor and a transceiver, the transceiver is used to perform data transmission and reception operations, and the processor is used to execute the method according to any one of claims 1 to 50.

53. An optical module, characterized in that The optical module includes a processor and a transceiver, the transceiver is used to perform data transmission and reception operations, and the processor is used to execute the method according to any one of claims 1 to 50.

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