Vector operation mapping optimization system, method, equipment and program product

Abstract

The invention discloses a vector operation mapping optimization system, method, equipment and program product, and the system comprises a mapping configuration module which is used for determining the multiplication of a plurality of groups of vectors and scalar quantities corresponding to a vector operation batch processing instruction when the vector operation batch processing instruction is received, and obtaining the length of the vector in the multiplication; when the length of the vector is smaller than a preset vector length threshold value, determining a mapping numerical value of each processing unit based on a preset parallel mapping strategy, generating parallel mapping configuration information and sending the parallel mapping configuration information to the reconfigurable computing array module; and the reconfigurable computing array module is used for mapping a plurality of vector values and scalar values in the at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array. According to the method, the parallel optimization of the vector and scalar multiplication operation can be realized based on the coarse-grained reconfigurable computing architecture, the operation execution efficiency can be improved, and the group delay of the operation execution can be optimized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a vector operation mapping optimization system, method, terminal equipment and computer program product. Background Art

[0002] The physical layer signal processing process on the wireless base station side usually involves a large number of vector and scalar multiplication operations. The large amount of computing power required leads to low execution efficiency of vector and scalar multiplication operations, resulting in a large group delay in the execution of the operations.

[0003] Currently, coarse-grained reconfigurable computing architectures combine the advantages of general-purpose processors and application-specific integrated circuits, offering both flexible programming and high computing speeds. Therefore, existing technologies exist that use coarse-grained reconfigurable computing architectures to accelerate parallel computing in specific areas. For example, coarse-grained reconfigurable computing architectures enable efficient computation of the SKINNY-128-128 and PRESENT encryption algorithms. However, existing technologies do not yet exist that optimize vector operation mapping based on coarse-grained reconfigurable computing architectures. Therefore, existing technologies are not suitable for parallel optimization of vector and scalar multiplication operations in 5G physical layer signal processing. Summary of the Invention

[0004] The present invention provides a vector operation mapping optimization system, method, device and program product, which can perform parallel mapping configuration on several groups of vector and scalar multiplication operations based on a coarse-grained reconfigurable computing architecture, thereby realizing parallel optimization of vector and scalar multiplication operations, helping to improve the execution efficiency of vector and scalar multiplication operations and optimize the group delay of vector and scalar multiplication operations.

[0005] In order to solve the above technical problems, a first aspect of an embodiment of the present invention provides a vector operation mapping optimization system, including a mapping configuration module and a reconfigurable computing array module, wherein the reconfigurable computing array module includes a plurality of processing unit arrays, each of the processing unit arrays includes a plurality of processing units;

[0006] The mapping configuration module is used to:

[0007] When a vector operation batch processing instruction is received, determining a plurality of vector and scalar multiplication operations corresponding to the vector operation batch processing instruction, and obtaining the length of the vector in the multiplication operation;

[0008] When the length of the vector in the multiplication operation is less than a preset vector length threshold, determining a mapping value for each of the processing units based on a preset parallel mapping strategy, generating parallel mapping configuration information, and sending the information to the reconfigurable computing array module; wherein the vector length threshold is set based on the number of processing units in the processing unit array;

[0009] The reconfigurable computing array module is used for:

[0010] Based on the parallel mapping configuration information, several vector values ​​and scalar values ​​in at least two groups of multiplication operations are mapped to the processing unit array, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array; wherein the mapped values ​​are the vector values, the scalar values ​​or null values.

[0011] As a preferred solution, each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, the mapping configuration module is used to determine the mapping value of each processing unit based on a preset parallel mapping strategy, generate parallel mapping configuration information, and send it to the reconfigurable computing array module, specifically including:

[0012] Selecting a first processing unit and a second processing unit from a plurality of the processing units in the processing unit array;

[0013] Mapping and configuring the first processing unit and the second processing unit respectively based on scalar values ​​in any two groups of multiplication operations;

[0014] Based on the vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit;

[0015] When the current number of processing units to be mapped is greater than or equal to N+1, mapping and configuring any one of the processing units to be mapped based on the scalar value in the new multiplication operation, and mapping and configuring a number of processing units to be mapped that are within the preset relative unit distance from the any one of the processing units to be mapped based on a number of vector values ​​in the new multiplication operation; repeating this step until the current number of processing units to be mapped is less than N+1; where N represents the length of the vector in the multiplication operation;

[0016] Determining a mapping value of each processing unit in the processing unit array based on a number of processing units that have currently completed mapping configuration;

[0017] The parallel mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array and sent to the reconfigurable computing array module.

[0018] As a preferred solution, the mapping configuration module is used to select a first processing unit and a second processing unit from a plurality of processing units in the processing unit array, specifically including:

[0019] Select any one processing unit from the processing unit array as the first processing unit;

[0020] According to a selection strategy with the least shared processing units, the second processing unit is selected from the remaining processing units in the processing unit array except the first processing unit; wherein the shared processing unit is a processing unit whose relative distance from the first processing unit and the second processing unit is within the preset relative unit distance.

[0021] As a preferred solution, the mapping configuration module is configured to perform mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit based on a plurality of vector values ​​in the arbitrary two sets of multiplication operations, specifically including:

[0022] Based on the several vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on several to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit, and the sum of the distances between the remaining to-be-mapped processing units after the mapping configuration is minimized.

[0023] As a preferred solution, the system further includes a main control module and a data cache module;

[0024] The main control module is used for:

[0025] Generate the vector operation batch processing instruction according to the vector operation batch processing task and send it to the mapping configuration module;

[0026] Sending all vector values ​​and scalar values ​​in the plurality of groups of multiplication operations corresponding to the vector operation batch processing instructions to the data cache module;

[0027] The data cache module is used for:

[0028] All vector values ​​and scalar values ​​in received sets of multiplication operations are stored.

[0029] As a preferred solution, the mapping configuration module is further used to:

[0030] When the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to a preset abnormal length threshold, determining a mapping value for each of the processing units based on a preset serial mapping strategy, generating serial mapping configuration information, and sending the information to the reconfigurable computing array module;

[0031] The reconfigurable computing array module is also used for:

[0032] The scalar values ​​and the vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information are mapped to the processing unit array, so as to perform the set of multiplication operations corresponding to the serial mapping configuration information based on the mapped processing unit array.

[0033] As a preferred solution, each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, the mapping configuration module is used to determine the mapping value of each processing unit based on a preset serial mapping strategy, generate serial mapping configuration information, and send it to the reconfigurable computing array module, specifically including:

[0034] Select any one processing unit from the processing unit array as the third processing unit;

[0035] mapping the third processing unit based on a scalar value in any set of multiplication operations;

[0036] Performing mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the third processing unit based on a plurality of vector values ​​in the arbitrary set of multiplication operations;

[0037] Determining a mapping value of each processing unit in the processing unit array according to a number of processing units that have currently completed mapping configuration;

[0038] The serial mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array and sent to the reconfigurable computing array module.

[0039] As a preferred solution, the mapping configuration module is further used to:

[0040] When the length of the vector in the multiplication operation is greater than the abnormal length threshold, an abnormal signal is sent to the main control module.

[0041] As a preferred solution, the reconfigurable computing array module further includes a control unit and a data reading and writing unit; then, the reconfigurable computing array module is used to map a number of vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information, specifically including:

[0042] receiving the parallel mapping configuration information through the control unit, and determining a mapping value of each of the processing units in the processing unit array based on the parallel mapping configuration information;

[0043] Reading, from the data cache module, a plurality of vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the parallel mapping configuration information, through the data read / write unit, according to the mapping value of each processing unit in the processing unit array; wherein any one of the read vector values ​​or scalar values ​​has a corresponding relationship with the mapping value of any one of the processing units;

[0044] According to the mapping value of each of the processing units in the processing unit array, the vector values ​​and scalar values ​​in the read sets of multiplication operations are mapped to the processing unit array.

[0045] As a preferred solution, the reconfigurable computing array module further includes a control unit and a data reading and writing unit; then, the reconfigurable computing array module is used to map a scalar value and a plurality of vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information to the processing unit array, specifically including:

[0046] receiving the serial mapping configuration information through the control unit, and determining a mapping value of each of the processing units in the processing unit array based on the serial mapping configuration information;

[0047] According to the mapping value of each processing unit in the processing unit array, read, from the data cache module, via the data read / write unit, a scalar value and a plurality of vector values ​​in a group of multiplication operations corresponding to the serial mapping configuration information; wherein any one of the read vector values ​​or scalar values ​​has a corresponding relationship with the mapping value of any one of the processing units;

[0048] According to the mapping value of each of the processing units in the processing unit array, a scalar value and a plurality of vector values ​​in a group of multiplication operations read are mapped to the processing unit array.

[0049] As a preferred solution, the reconfigurable computing array module is further used for:

[0050] In the process of executing the at least two groups of multiplication operations in parallel, the processing unit mapped with the vector value is controlled to access the processing unit mapped with the scalar value belonging to the same group of multiplication operations as the vector value, and perform the multiplication operation of the vector value and the accessed scalar value.

[0051] As a preferred solution, the reconfigurable computing array module includes 4 processing unit arrays, each of the processing unit arrays includes 16 processing units, and the 16 processing units form a 4×4 processing unit array.

[0052] A second aspect of an embodiment of the present invention provides a vector operation mapping optimization method, including:

[0053] When a vector operation batch processing instruction is received, determining a plurality of vector and scalar multiplication operations corresponding to the vector operation batch processing instruction, and obtaining the length of the vector in the multiplication operation;

[0054] When the length of the vector in the multiplication operation is less than a preset vector length threshold, determining a mapping value for each of the processing units based on a preset parallel mapping strategy, and generating parallel mapping configuration information; wherein the vector length threshold is set based on the number of processing units included in the processing unit array in the reconfigurable computing array module;

[0055] Based on the parallel mapping configuration information, several vector values ​​and scalar values ​​in at least two groups of multiplication operations are mapped to the processing unit array, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array; wherein the mapped values ​​are the vector values, the scalar values ​​or null values.

[0056] As a preferred solution, each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, determining a mapping value for each processing unit based on a preset parallel mapping strategy and generating parallel mapping configuration information specifically includes:

[0057] Selecting a first processing unit and a second processing unit from a plurality of the processing units in the processing unit array;

[0058] Mapping and configuring the first processing unit and the second processing unit respectively based on scalar values ​​in any two groups of multiplication operations;

[0059] Based on the vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit;

[0060] When the current number of processing units to be mapped is greater than or equal to N+1, mapping and configuring any one of the processing units to be mapped based on the scalar value in the new multiplication operation, and mapping and configuring a number of processing units to be mapped that are within the preset relative unit distance from the any one of the processing units to be mapped based on a number of vector values ​​in the new multiplication operation; repeating this step until the current number of processing units to be mapped is less than N+1; where N represents the length of the vector in the multiplication operation;

[0061] Determining a mapping value of each processing unit in the processing unit array based on a number of processing units that have currently completed mapping configuration;

[0062] The parallel mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array.

[0063] As a preferred solution, selecting the first processing unit and the second processing unit from a plurality of the processing units in the processing unit array specifically includes:

[0064] Select any one processing unit from the processing unit array as the first processing unit;

[0065] According to a selection strategy with the least shared processing units, the second processing unit is selected from the remaining processing units in the processing unit array except the first processing unit; wherein the shared processing unit is a processing unit whose relative distance from the first processing unit and the second processing unit is within the preset relative unit distance.

[0066] As a preferred solution, the mapping configuration of the plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit based on the plurality of vector values ​​in the arbitrary two sets of multiplication operations specifically includes:

[0067] Based on the several vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on several to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit, and the sum of the distances between the remaining to-be-mapped processing units after the mapping configuration is minimized.

[0068] As a preferred solution, it also includes:

[0069] When the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to a preset abnormal length threshold, determining a mapping value for each of the processing units based on a preset serial mapping strategy, and generating serial mapping configuration information;

[0070] The scalar values ​​and the vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information are mapped to the processing unit array, so as to perform the set of multiplication operations corresponding to the serial mapping configuration information based on the mapped processing unit array.

[0071] As a preferred solution, each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, determining a mapping value for each processing unit based on a preset serial mapping strategy and generating serial mapping configuration information specifically includes:

[0072] Select any one processing unit from the processing unit array as the third processing unit;

[0073] mapping the third processing unit based on a scalar value in any set of multiplication operations;

[0074] Performing mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the third processing unit based on a plurality of vector values ​​in the arbitrary set of multiplication operations;

[0075] Determining a mapping value of each processing unit in the processing unit array according to a number of processing units that have currently completed mapping configuration;

[0076] The serial mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array.

[0077] As a preferred solution, it also includes:

[0078] When the length of the vector in the multiplication operation is greater than the abnormal length threshold, an abnormal signal is sent to the main control module.

[0079] As a preferred solution, mapping the vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information specifically includes:

[0080] Determining a mapping value for each of the processing units in the processing unit array based on the parallel mapping configuration information;

[0081] Reading, from a data cache module, a plurality of vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the parallel mapping configuration information according to the mapping value of each processing unit in the processing unit array; wherein the data cache module stores all vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the vector operation batch instruction; and any read vector value or scalar value has a corresponding relationship with the mapping value of any processing unit;

[0082] According to the mapping value of each of the processing units in the processing unit array, the vector values ​​and scalar values ​​in the read sets of multiplication operations are mapped to the processing unit array.

[0083] As a preferred solution, mapping a set of scalar values ​​and a plurality of vector values ​​in the multiplication operation corresponding to the serial mapping configuration information to the processing unit array specifically includes:

[0084] Determining a mapping value of each of the processing units in the processing unit array based on the serial mapping configuration information;

[0085] Reading, from a data cache module, a scalar value and a plurality of vector values ​​in a group of multiplication operations corresponding to the serial mapping configuration information according to the mapping value of each processing unit in the processing unit array; wherein the data cache module stores all vector values ​​and scalar values ​​in the plurality of groups of multiplication operations corresponding to the vector operation batch instruction; and any read vector value or scalar value has a corresponding relationship with the mapping value of any processing unit;

[0086] According to the mapping value of each of the processing units in the processing unit array, a scalar value and a plurality of vector values ​​in a group of multiplication operations read are mapped to the processing unit array.

[0087] As a preferred solution, it also includes:

[0088] In the process of executing the at least two groups of multiplication operations in parallel, the processing unit mapped with the vector value is controlled to access the processing unit mapped with the scalar value belonging to the same group of multiplication operations as the vector value, and perform the multiplication operation of the vector value and the accessed scalar value.

[0089] A third aspect of an embodiment of the present invention provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the vector operation mapping optimization method described in any one of the second aspects when executing the computer program.

[0090] A fourth aspect of an embodiment of the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the vector operation mapping optimization method described in any one of the second aspects.

[0091] Compared with the existing technology, the beneficial effect of the embodiments of the present invention is that it can perform parallel mapping configuration on several groups of vector and scalar multiplication operations based on a coarse-grained reconfigurable computing architecture, thereby realizing parallel optimization of vector and scalar multiplication operations, helping to improve the execution efficiency of vector and scalar multiplication operations, and optimizing the group delay of vector and scalar multiplication operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] Figure 1 This is a schematic diagram of the architecture of a preferred embodiment of the vector operation mapping optimization system provided by the present invention;

[0093] Figure 2 is a structural diagram of a processing unit array provided by an embodiment of the present invention;

[0094] Figure 3 1 is a schematic diagram of the architecture of another preferred embodiment of the vector operation mapping optimization system provided by the present invention;

[0095] Figure 4 1 is a flow chart of a vector operation mapping optimization method provided by an embodiment of the present invention;

[0096] Figure 5 It is a structural diagram of a terminal device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0097] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0098] See also Figure 1 , is a schematic diagram of the architecture of a preferred embodiment of the vector operation mapping optimization system provided by the present invention. A first aspect of an embodiment of the present invention provides a vector operation mapping optimization system, comprising a mapping configuration module 100 and a reconfigurable computing array module 200, wherein the reconfigurable computing array module 200 comprises a plurality of processing unit arrays, each of which comprises a plurality of processing units 201;

[0099] The mapping configuration module 100 is used to:

[0100] When a vector operation batch processing instruction is received, determining a plurality of vector and scalar multiplication operations corresponding to the vector operation batch processing instruction, and obtaining the length of the vector in the multiplication operation;

[0101] When the length of the vector in the multiplication operation is less than a preset vector length threshold, determining a mapping value for each of the processing units 201 based on a preset parallel mapping strategy, generating parallel mapping configuration information, and sending the information to the reconfigurable computing array module 200; wherein the vector length threshold is set based on the number of the processing units 201 in the processing unit array;

[0102] The reconfigurable computing array module 200 is used for:

[0103] Based on the parallel mapping configuration information, several vector values ​​and scalar values ​​in at least two groups of multiplication operations are mapped to the processing unit array, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array; wherein the mapped values ​​are the vector values, the scalar values ​​or null values.

[0104] Specifically, since the vector operation batch instruction is a single instruction multiple data stream type batch instruction, the mapping configuration module 100 in this embodiment first needs to decompose the vector operation batch instruction, so as to determine several groups of vector and scalar multiplication operations corresponding to the vector operation batch instruction, and obtain the length of the vector in the multiplication operation, that is, the number of vector values ​​contained in the vector, in order to clarify the number of vector value and scalar value multiplication operations that need to be performed in a set of multiplication operations.

[0105] Furthermore, when the length of the vector in the multiplication operation is less than a preset vector length threshold, it is determined that the vector and scalar multiplication operations can be performed in parallel. Therefore, the mapping configuration module 100 in this embodiment determines the mapping value of each processing unit 201 based on the preset parallel mapping strategy. It can be understood that each processing unit 201 is responsible for performing the multiplication operation of the vector value and the scalar value. The purpose of the parallel mapping strategy is to map several vector values ​​and scalar values ​​in at least two groups of multiplication operations to several processing units 201 in the processing unit array respectively, so as to realize the simultaneous execution of at least two groups of vector and scalar multiplication operations, thereby achieving the purpose of parallel optimization. Among them, the vector length threshold is set based on the number of processing units 201 in the processing unit array. It can be understood that the number of processing units 201 in the processing unit array determines the computing power scale of the current coarse-grained reconfigurable computing architecture. Since each processing unit 201 is only responsible for performing multiplication operations of a single vector value and a scalar value, this embodiment needs to consider the length of the vector in the multiplication operation and the number of processing units 201 in the processing unit array before executing the parallel mapping strategy, so as to clarify whether the computing power scale of the current coarse-grained reconfigurable computing architecture can meet the parallel optimization conditions of at least two groups of multiplication operations.

[0106] Furthermore, the reconfigurable computing array module 200 maps the plurality of vector values ​​and scalar values ​​in the at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information sent by the mapping configuration module 100, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array. It is understood that the plurality of groups of multiplication operations mapped to the processing unit array are determined by the parallel mapping configuration information, and may be two groups of multiplication operations, three groups of multiplication operations, or four groups of multiplication operations, etc., and this embodiment will not be described in detail here. Among them, the mapped values ​​in this embodiment are vector values, scalar values, or null values. It is understood that the parallel mapping configuration information specifies any vector value or scalar value in any group of multiplication operations corresponding to the plurality of processing units 201 in the processing unit array, and there may be processing units 201 in the processing unit array that are not mapped, so the mapped values ​​of these processing units 201 are null values. In addition, since the processing units 201 in the coarse-grained reconfigurable computing architecture have the characteristics of interconnected access, several processing units 201 mapped with scalar values ​​or vector values ​​can complete the multiplication operations of each vector value and scalar value based on the characteristics of interconnected access, and then complete the multiplication operations of each group of vectors and scalars.

[0107] As an optional embodiment, the processing unit 201 in this embodiment includes an ALU (Arithmetic Logic Unit) capable of performing 16-bit addition / subtraction / multiplication / division.

[0108] As an optional embodiment, the mapping configuration module 100 in this embodiment transmits the parallel mapping configuration information to the reconfigurable computing array module 200 in the form of a configuration code.

[0109] The vector operation mapping optimization system provided by the embodiment of the present invention can perform parallel mapping configuration on several groups of vector and scalar multiplication operations based on a coarse-grained reconfigurable computing architecture, thereby realizing parallel optimization of vector and scalar multiplication operations, helping to improve the execution efficiency of vector and scalar multiplication operations, and optimizing the group delay of vector and scalar multiplication operations.

[0110] As a preferred solution, each processing unit 201 in the processing unit array supports interconnection access with the processing units 201 within a preset relative unit distance; then, the mapping configuration module 100 is used to determine the mapping value of each processing unit 201 based on a preset parallel mapping strategy, generate parallel mapping configuration information, and send it to the reconfigurable computing array module 200, specifically including:

[0111] Selecting a first processing unit and a second processing unit from the plurality of processing units 201 in the processing unit array;

[0112] Mapping and configuring the first processing unit and the second processing unit respectively based on scalar values ​​in any two groups of multiplication operations;

[0113] Based on the vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit;

[0114] When the current number of processing units to be mapped is greater than or equal to N+1, mapping and configuring any one of the processing units to be mapped based on the scalar value in the new multiplication operation, and mapping and configuring a number of processing units to be mapped that are within the preset relative unit distance from the any one of the processing units to be mapped based on a number of vector values ​​in the new multiplication operation; repeating this step until the current number of processing units to be mapped is less than N+1; where N represents the length of the vector in the multiplication operation;

[0115] Determine a mapping value of each processing unit 201 in the processing unit array based on a number of processing units 201 that have completed mapping configuration;

[0116] The parallel mapping configuration information is generated according to the mapping value of each processing unit 201 in the processing unit array and sent to the reconfigurable computing array module 200 .

[0117] Specifically, this embodiment assumes that each processing unit 201 in the processing unit array supports interconnection access with the processing units 201 within a relative unit distance. For example, any processing unit 201 supports interconnection access with the processing units 201 within a relative unit distance of 2, and follows a cyclic access mechanism, such as Figure 2 FIG. 2 is a schematic diagram of the structure of the processing unit array according to an embodiment of the present invention. Taking the processing unit 201 in the upper left corner as an example, its accessible range includes all processing units 201 within a relative unit distance of 2 on all sides. The processing unit 201 represented by the dotted box is folded into the 4×4 processing unit array due to the existence of the cyclic access mechanism. Therefore, Figure 2 The processing units 201 marked with “PE” are all processing units 201 that can be interconnected and accessed by the processing unit 201 in the upper left corner.

[0118] Furthermore, when it is determined that the length of the vector in the multiplication operation is less than the vector length threshold, it indicates that at least two groups of processing data of multiplication operations need to be mapped in the processing unit array. Therefore, the mapping configuration module 100 in this embodiment first selects the first processing unit and the second processing unit from the several processing units 201 in the processing unit array to map and configure the first processing unit and the second processing unit respectively based on the scalar values ​​in any two groups of multiplication operations. At this time, the mapping values ​​of the first processing unit and the second processing unit are the scalar values ​​in two different groups of multiplication operations. Furthermore, based on several vector values ​​in any two selected groups of multiplication operations, several processing units to be mapped that are within a preset relative unit distance from the first processing unit or the second processing unit are mapped and configured respectively. It can be understood that in order to achieve parallel optimization of any two selected groups of multiplication operations, for the multiplication operations corresponding to the scalar values ​​mapped and configured by the first processing unit, based on several vector values ​​in the group of multiplication operations, several processing units to be mapped that are within a preset relative unit distance from the first processing unit are mapped and configured; for the multiplication operations corresponding to the scalar values ​​mapped and configured by the second processing unit, based on several vector values ​​in the group of multiplication operations, several processing units to be mapped that are within a preset relative unit distance from the second processing unit are mapped and configured, and each processing unit to be mapped can only be mapped and configured with one vector value.

[0119] Furthermore, after completing the mapping configuration of any two selected groups of multiplication operations, if the current number of processing units to be mapped is greater than or equal to N+1, it indicates that another new group of multiplication operations is supported, that is, any one of the processing units to be mapped is mapped based on the scalar value in the new multiplication operation, and a number of processing units to be mapped that are within a preset relative unit distance from any selected processing unit to be mapped are mapped based on the number of vector values ​​in the new multiplication operation, and this step is repeated until the current number of processing units to be mapped is less than N+1. It can be understood that since the length N of the vector in a group of multiplication operations corresponds to the need to map N processing units to be mapped, and in addition, one processing unit to be mapped is required to complete the mapping configuration of the scalar value, the addition of another new group of multiplication operations can only be supported when the current number of processing units to be mapped is greater than or equal to N+1.

[0120] The vector operation mapping optimization system provided by the embodiment of the present invention can fully consider the computing power scale of the current coarse-grained reconfigurable computing architecture, and perform parallel mapping configuration on at least two groups of vector and scalar multiplication operations, which helps to achieve parallel optimization of vector and scalar multiplication operations, improve the execution efficiency of vector and scalar multiplication operations, and optimize the group delay of vector and scalar multiplication operations.

[0121] As a preferred solution, the mapping configuration module 100 is configured to select a first processing unit and a second processing unit from a plurality of the processing units 201 in the processing unit array, specifically including:

[0122] Select any one processing unit 201 from the processing unit array as the first processing unit;

[0123] According to the selection strategy of the least shared processing units, the second processing unit is selected from the remaining processing units 201 in the processing unit array except the first processing unit; wherein the shared processing unit is a processing unit 201 whose relative distances to the first processing unit and the second processing unit are within the preset relative unit distance.

[0124] It can be understood that the mapping configuration module 100 in this embodiment first selects any one processing unit 201 from the processing unit array as the first processing unit, and then traverses the remaining processing units 201. If there is any one processing unit 201 as the second processing unit, the number of shared processing units between the first processing unit and the second processing unit is the least, then the processing unit 201 is the second processing unit. It is worth noting that if there are many shared processing units between the first processing unit and the second processing unit, it indicates that the range of processing units 201 that the first processing unit and the second processing unit can interconnect and access has a large overlap, resulting in low utilization of the processing units 201 in the processing unit array. If there are many vector values ​​in any two selected groups of multiplication operations, there may be a problem that the vector values ​​cannot be fully mapped and configured, thereby failing to achieve parallel optimization of vector and scalar multiplication operations. Therefore, this embodiment determines the first processing unit and the second processing unit according to the selection strategy of the least shared processing unit, ensuring that at least two groups of vector and scalar multiplication operations can be achieved in the processing unit array. Parallel optimization.

[0125] As a preferred solution, the mapping configuration module 100 is configured to perform mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit based on a plurality of vector values ​​in the arbitrary two sets of multiplication operations, specifically including:

[0126] Based on the several vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on several to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit, and the sum of the distances between the remaining to-be-mapped processing units after the mapping configuration is minimized.

[0127] Specifically, this embodiment takes into account that each processing unit 201 can only access the remaining processing units 201 within a preset relative unit distance. If the spacing between the remaining processing units to be mapped after the current mapping configuration is large, it is possible that some of the processing units to be mapped cannot be interconnected and accessed. Even if the number of remaining processing units to be mapped is greater than or equal to N+1, another set of new multiplication operations may not be performed. Therefore, in the process of executing the mapping configuration of any two selected sets of vector and scalar multiplication operations, this embodiment calculates the sum of the spacing between the remaining processing units to be mapped after the mapping configuration, and executes it based on the mapping configuration method with the smallest sum of spacing. This ensures that the topological positions of the remaining processing units to be mapped after the mapping configuration are as concentrated as possible, thereby providing maximum feasibility for mapping another set of new multiplication operations.

[0128] See also Figure 3 , is a schematic diagram of the architecture of another preferred embodiment of the vector operation mapping optimization system provided by the present invention. As a preferred solution, the system further includes a main control module 300 and a data cache module 400;

[0129] The main control module 300 is used for:

[0130] Generate the vector operation batch processing instruction according to the vector operation batch processing task and send it to the mapping configuration module 100;

[0131] Sending all vector values ​​and scalar values ​​in the plurality of groups of multiplication operations corresponding to the vector operation batch processing instructions to the data cache module 400;

[0132] The data cache module 400 is used for:

[0133] All vector values ​​and scalar values ​​in received sets of multiplication operations are stored.

[0134] It is worth noting that when the main control module 300 in this embodiment needs to execute a vector operation batch processing task, it generates a vector operation batch processing instruction based on the processing task and sends it to the mapping configuration module 100 through the interconnection bus. At the same time, all vector values ​​and scalar values ​​in several groups of multiplication operations corresponding to the vector operation batch processing instruction are sent to the data cache module 400 for storage.

[0135] As a preferred solution, the mapping configuration module 100 is further configured to:

[0136] When the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to a preset abnormal length threshold, determining a mapping value for each of the processing units 201 based on a preset serial mapping strategy, generating serial mapping configuration information, and sending it to the reconfigurable computing array module 200;

[0137] The reconfigurable computing array module 200 is further configured to:

[0138] The scalar values ​​and the vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information are mapped to the processing unit array, so as to perform the set of multiplication operations corresponding to the serial mapping configuration information based on the mapped processing unit array.

[0139] Specifically, when the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to the preset abnormal length threshold, the mapping configuration module 100 in this embodiment indicates that the computing power scale of the current coarse-grained reconfigurable computing architecture does not support the parallel execution of at least two groups of vector and scalar multiplication operations, but can execute a group of vector and scalar multiplication operations. It can be understood that the abnormal length threshold is the maximum length of the vector in the vector and scalar multiplication operation that can be executed under the condition that each processing unit 201 can interconnect and access the other processing units 201 within a preset relative unit distance. In this case, the mapping value of each processing unit 201 is determined based on the preset serial mapping strategy, and the serial mapping configuration information is generated and sent to the reconfigurable computing array module 200. The purpose of the serial mapping strategy is to map the scalar value and several vector values ​​in any group of multiplication operations to several processing units 201 in the processing unit array to realize the execution of a group of vector and scalar multiplication operations.

[0140] The vector operation mapping optimization system provided by the embodiment of the present invention can dynamically map the multiplication operation based on the length of the vector in the vector and scalar multiplication operation, thereby being able to flexibly execute vector and scalar multiplication operations under different vector lengths.

[0141] As a preferred solution, each processing unit 201 in the processing unit array supports interconnection access with the processing units 201 within a preset relative unit distance; then, the mapping configuration module 100 is used to determine the mapping value of each processing unit 201 based on a preset serial mapping strategy, generate serial mapping configuration information, and send it to the reconfigurable computing array module 200, specifically including:

[0142] Select any one processing unit 201 from the processing unit array as the third processing unit;

[0143] mapping the third processing unit based on a scalar value in any set of multiplication operations;

[0144] Performing mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the third processing unit based on a plurality of vector values ​​in the arbitrary set of multiplication operations;

[0145] Determine a mapping value of each processing unit 201 in the processing unit array according to the processing units 201 that have currently completed mapping configuration;

[0146] The serial mapping configuration information is generated according to the mapping value of each processing unit 201 in the processing unit array and sent to the reconfigurable computing array module 200 .

[0147] Specifically, since it is determined that the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to the preset abnormal length threshold, it indicates that only one set of processing data of the multiplication operation can be mapped in the processing unit array. Therefore, the mapping configuration module 100 in this embodiment selects any one processing unit 201 from the processing unit array as the third processing unit to map and configure the third processing unit based on the scalar value in any one set of multiplication operations.

[0148] Furthermore, in order to ensure that the mapped processing units 201 can be interconnected and accessed to perform multiplication operations of various vector values ​​and scalar values, the mapping configuration module 100 in this embodiment maps and configures several processing units to be mapped that are within a preset relative unit distance from the third processing unit based on several vector values ​​in any set of multiplication operations, thereby completing the mapping configuration of the selected set of vector and scalar multiplication operations in the processing unit array.

[0149] As a preferred solution, the mapping configuration module 100 is further configured to:

[0150] When the length of the vector in the multiplication operation is greater than the abnormal length threshold, an abnormal signal is sent to the main control module 300.

[0151] It is worth noting that when the length of the vector in the multiplication operation is greater than the abnormal length threshold, it indicates that when the multiplication operation is fully mapped, some processing units 201 cannot be interconnected and accessed because they exceed the preset relative unit distance, and thus the multiplication operation cannot be effectively performed. Therefore, at this time, the mapping configuration module 100 sends an abnormal signal to the main control module 300.

[0152] As a preferred solution, the reconfigurable computing array module 200 further includes a control unit 202 and a data reading and writing unit 203. Then, the reconfigurable computing array module 200 is configured to map a plurality of vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information, specifically including:

[0153] receiving the parallel mapping configuration information through the control unit 202, and determining a mapping value of each of the processing units 201 in the processing unit array based on the parallel mapping configuration information;

[0154] According to the mapping value of each of the processing units 201 in the processing unit array, the data read / write unit 203 reads from the data cache module 400 a plurality of vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the parallel mapping configuration information; wherein any one of the read vector values ​​or scalar values ​​has a corresponding relationship with the mapping value of any one of the processing units 201;

[0155] According to the mapping value of each of the processing units 201 in the processing unit array, the vector values ​​and scalar values ​​in the read sets of multiplication operations are mapped to the processing unit array.

[0156] It is worth noting that the control unit 202 and the data read / write unit 203 included in the reconfigurable computing array module 200 in this embodiment are both first-input first-output storage structures, thereby ensuring that the mapping configuration information and mapping values ​​of the processing unit 201 are synchronously received by the corresponding processing unit 201 in the processing unit array.

[0157] In this embodiment, since the parallel mapping configuration information has recorded the mapping values ​​of each processing unit 201 in the processing unit array, based on the parallel mapping configuration information, the reconfigurable computing array module 200 can read the multiple vector values ​​and scalar values ​​in the multiple groups of multiplication operations corresponding to the parallel mapping configuration information from the data cache module 400 through the data read and write unit 203, and then map the multiple vector values ​​and scalar values ​​in the multiple groups of multiplication operations read to the corresponding processing units 201 in the processing unit array.

[0158] As a preferred solution, the reconfigurable computing array module 200 further includes a control unit 202 and a data reading and writing unit 203; then, the reconfigurable computing array module 200 is configured to map a scalar value and a plurality of vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information to the processing unit array, specifically including:

[0159] receiving the serial mapping configuration information through the control unit 202, and determining a mapping value of each of the processing units 201 in the processing unit array based on the serial mapping configuration information;

[0160] According to the mapping value of each of the processing units 201 in the processing unit array, the data read / write unit 203 reads a scalar value and a plurality of vector values ​​in a group of multiplication operations corresponding to the serial mapping configuration information from the data cache module 400; wherein any one of the read vector values ​​or scalar values ​​has a corresponding relationship with the mapping value of any one of the processing units 201;

[0161] According to the mapping value of each of the processing units 201 in the processing unit array, a scalar value and a plurality of vector values ​​in a group of multiplication operations read are mapped to the processing unit array.

[0162] In this embodiment, since the serial mapping configuration information has recorded the mapping values ​​of each processing unit 201 in the processing unit array, based on the serial mapping configuration information, the reconfigurable computing array module 200 can read the scalar values ​​and the plurality of vector values ​​in the set of multiplication operations corresponding to the serial mapping configuration information from the data cache module 400 via the data read / write unit 203, and then map the read scalar values ​​and the plurality of vector values ​​in the set of multiplication operations to the corresponding processing units 201 in the processing unit array.

[0163] As a preferred solution, the reconfigurable computing array module 200 is further used for:

[0164] In the process of executing the at least two groups of multiplication operations in parallel, the processing unit 201 mapped with the vector value is controlled to access the processing unit 201 mapped with the scalar value belonging to the same group of multiplication operations as the vector value, and perform the multiplication operation of the vector value and the accessed scalar value.

[0165] It is worth noting that, in this embodiment, several vector values ​​in the same group of multiplication operations share a processing unit 201 mapped with a scalar value, thereby making maximum use of the computing power scale of the coarse-grained reconfigurable computing architecture and mapping as many vector and scalar multiplication operations as possible to the same processing unit array for parallel processing.

[0166] As a preferred solution, the reconfigurable computing array module 200 includes four processing unit arrays, each of the processing unit arrays includes 16 processing units 201, and the 16 processing units 201 form a 4×4 processing unit array.

[0167] For example, based on the 4×4 processing unit array composed of 16 processing units 201 proposed in this embodiment, the vector length threshold is correspondingly set to 7, so that when the lengths of the vectors in any two groups of multiplication operations are less than 7, at least two groups of multiplication operations including these two groups of multiplication operations can be mapped to the above-mentioned 4×4 processing unit array to achieve parallel execution. It should be noted that, according to actual application requirements, the vector length threshold can also be set to 4, 5, 6, etc., as long as it is ensured that at least two groups of multiplication operations can be mapped in parallel when the length of the vector in the multiplication operation is less than the set vector length threshold. This embodiment does not make specific limitations here.

[0168] See also Figure 4, is a flow chart of a vector operation mapping optimization method provided by an embodiment of the present invention. A second aspect of an embodiment of the present invention provides a vector operation mapping optimization method, comprising the following steps S1 to S3:

[0169] Step S1, when a vector operation batch processing instruction is received, determining a plurality of vector and scalar multiplication operations corresponding to the vector operation batch processing instruction, and obtaining the length of the vector in the multiplication operation;

[0170] Step S2: When the length of the vector in the multiplication operation is less than a preset vector length threshold, determining a mapping value for each of the processing units based on a preset parallel mapping strategy, and generating parallel mapping configuration information; wherein the vector length threshold is set based on the number of processing units included in the processing unit array in the reconfigurable computing array module;

[0171] Step S3, based on the parallel mapping configuration information, mapping several vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array; wherein the mapped values ​​are the vector values, the scalar values ​​or null values.

[0172] As a preferred solution, each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, determining a mapping value for each processing unit based on a preset parallel mapping strategy and generating parallel mapping configuration information specifically includes:

[0173] Selecting a first processing unit and a second processing unit from a plurality of the processing units in the processing unit array;

[0174] Mapping and configuring the first processing unit and the second processing unit respectively based on scalar values ​​in any two groups of multiplication operations;

[0175] Based on the vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit;

[0176] When the current number of processing units to be mapped is greater than or equal to N+1, mapping and configuring any one of the processing units to be mapped based on the scalar value in the new multiplication operation, and mapping and configuring a number of processing units to be mapped that are within the preset relative unit distance from the any one of the processing units to be mapped based on a number of vector values ​​in the new multiplication operation; repeating this step until the current number of processing units to be mapped is less than N+1; where N represents the length of the vector in the multiplication operation;

[0177] Determining a mapping value of each processing unit in the processing unit array based on a number of processing units that have currently completed mapping configuration;

[0178] The parallel mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array.

[0179] As a preferred solution, selecting the first processing unit and the second processing unit from a plurality of the processing units in the processing unit array specifically includes:

[0180] Select any one processing unit from the processing unit array as the first processing unit;

[0181] According to a selection strategy with the least shared processing units, the second processing unit is selected from the remaining processing units in the processing unit array except the first processing unit; wherein the shared processing unit is a processing unit whose relative distance from the first processing unit and the second processing unit is within the preset relative unit distance.

[0182] As a preferred solution, the mapping configuration of the plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit based on the plurality of vector values ​​in the arbitrary two sets of multiplication operations specifically includes:

[0183] Based on the several vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on several to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit, and the sum of the distances between the remaining to-be-mapped processing units after the mapping configuration is minimized.

[0184] As a preferred solution, it also includes:

[0185] When the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to a preset abnormal length threshold, determining a mapping value for each of the processing units based on a preset serial mapping strategy, and generating serial mapping configuration information;

[0186] The scalar values ​​and the vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information are mapped to the processing unit array, so as to perform the set of multiplication operations corresponding to the serial mapping configuration information based on the mapped processing unit array.

[0187] As a preferred solution, each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, determining a mapping value for each processing unit based on a preset serial mapping strategy and generating serial mapping configuration information specifically includes:

[0188] Select any one processing unit from the processing unit array as the third processing unit;

[0189] mapping the third processing unit based on a scalar value in any set of multiplication operations;

[0190] Performing mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the third processing unit based on a plurality of vector values ​​in the arbitrary set of multiplication operations;

[0191] Determining a mapping value of each processing unit in the processing unit array according to a number of processing units that have currently completed mapping configuration;

[0192] The serial mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array.

[0193] As a preferred solution, it also includes:

[0194] When the length of the vector in the multiplication operation is greater than the abnormal length threshold, an abnormal signal is sent to the main control module.

[0195] As a preferred solution, mapping the vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information specifically includes:

[0196] Determining a mapping value for each of the processing units in the processing unit array based on the parallel mapping configuration information;

[0197] Reading, from a data cache module, a plurality of vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the parallel mapping configuration information according to the mapping value of each processing unit in the processing unit array; wherein the data cache module stores all vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the vector operation batch instruction; and any read vector value or scalar value has a corresponding relationship with the mapping value of any processing unit;

[0198] According to the mapping value of each of the processing units in the processing unit array, the vector values ​​and scalar values ​​in the read sets of multiplication operations are mapped to the processing unit array.

[0199] As a preferred solution, mapping a set of scalar values ​​and a plurality of vector values ​​in the multiplication operation corresponding to the serial mapping configuration information to the processing unit array specifically includes:

[0200] Determining a mapping value of each of the processing units in the processing unit array based on the serial mapping configuration information;

[0201] Reading, from a data cache module, a scalar value and a plurality of vector values ​​in a group of multiplication operations corresponding to the serial mapping configuration information according to the mapping value of each processing unit in the processing unit array; wherein the data cache module stores all vector values ​​and scalar values ​​in the plurality of groups of multiplication operations corresponding to the vector operation batch instruction; and any read vector value or scalar value has a corresponding relationship with the mapping value of any processing unit;

[0202] According to the mapping value of each of the processing units in the processing unit array, a scalar value and a plurality of vector values ​​in a group of multiplication operations read are mapped to the processing unit array.

[0203] As a preferred solution, it also includes:

[0204] In the process of executing the at least two groups of multiplication operations in parallel, the processing unit mapped with the vector value is controlled to access the processing unit mapped with the scalar value belonging to the same group of multiplication operations as the vector value, and perform the multiplication operation of the vector value and the accessed scalar value.

[0205] The vector operation mapping optimization method provided in an embodiment of the present invention can perform parallel mapping configuration on several groups of vector and scalar multiplication operations based on a coarse-grained reconfigurable computing architecture, thereby realizing parallel optimization of vector and scalar multiplication operations, helping to improve the execution efficiency of vector and scalar multiplication operations, and optimizing the group delay of vector and scalar multiplication operations.

[0206] See also Figure 5 , is a schematic diagram of the structure of a terminal device 500 provided in an embodiment of the present invention. A third aspect of an embodiment of the present invention provides a terminal device 500, comprising a memory 52, a processor 51, and a computer program stored in the memory 52 and executable on the processor 51. When the processor 51 executes the computer program, it implements the vector operation mapping optimization method described in any embodiment of the second aspect.

[0207] Exemplarily, the computer program may be divided into one or more modules / units, which are stored in the memory 52 and executed by the processor 51 to implement the present invention. The one or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device 500.

[0208] The terminal device 500 may include, but is not limited to, a processor 51 and a memory 52. ​​Those skilled in the art will appreciate that the schematic diagram is merely an example of the terminal device 500 and does not limit the terminal device 500. The terminal device 500 may include more or fewer components than shown, or may combine certain components or different components. For example, the terminal device 500 may further include input and output devices, network access devices, buses, and the like.

[0209] The processor 51 may be a central processing unit (CPU), or other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor. The processor 51 is the control center of the terminal device 500 and connects various parts of the entire terminal device 500 using various interfaces and lines.

[0210] The memory 52 can be used to store the computer programs and / or modules. The processor 51 implements the various functions of the terminal device 500 by running or executing the computer programs and / or modules stored in the memory 52 and accessing the data stored in the memory 52. ​​The memory 52 may mainly include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as a sound playback function, an image playback function, etc.); the data storage area may store data generated based on the use of the mobile phone (such as audio data, a phone book, etc.). In addition, the memory 52 may include high-speed random access memory and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0211] A fourth aspect of an embodiment of the present invention provides a computer program product, including a computer program / instruction, which, when executed by the processor 51, implements the vector operation mapping optimization method described in any embodiment of the second aspect.

[0212] Wherein, if the module / unit integrated in the terminal device 500 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor 51, it can implement the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0213] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A vector operation mapping optimization system, characterized in that: It includes a mapping configuration module and a reconfigurable computing array module, wherein the reconfigurable computing array module includes a plurality of processing unit arrays, and each of the processing unit arrays includes a plurality of processing units; The mapping configuration module is used to: When a vector operation batch processing instruction is received, determining a plurality of vector and scalar multiplication operations corresponding to the vector operation batch processing instruction, and obtaining the length of the vector in the multiplication operation; When the length of the vector in the multiplication operation is less than a preset vector length threshold, determining a mapping value for each of the processing units based on a preset parallel mapping strategy, generating parallel mapping configuration information, and sending the information to the reconfigurable computing array module; wherein the vector length threshold is set based on the number of processing units in the processing unit array; The reconfigurable computing array module is used for: Based on the parallel mapping configuration information, several vector values ​​and scalar values ​​in at least two groups of multiplication operations are mapped to the processing unit array, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array; wherein the mapped values ​​are the vector values, the scalar values ​​or null values.

2. The vector operation mapping optimization system according to claim 1, wherein: Each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, the mapping configuration module is used to determine a mapping value for each processing unit based on a preset parallel mapping strategy, generate parallel mapping configuration information, and send it to the reconfigurable computing array module, specifically including: Selecting a first processing unit and a second processing unit from a plurality of the processing units in the processing unit array; Mapping and configuring the first processing unit and the second processing unit respectively based on scalar values ​​in any two groups of multiplication operations; Based on the vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit; When the current number of processing units to be mapped is greater than or equal to N+1, mapping and configuring any one of the processing units to be mapped based on the scalar value in the new multiplication operation, and mapping and configuring a number of processing units to be mapped that are within the preset relative unit distance from the any one of the processing units to be mapped based on a number of vector values ​​in the new multiplication operation; repeating this step until the current number of processing units to be mapped is less than N+1; where N represents the length of the vector in the multiplication operation; Determining a mapping value of each processing unit in the processing unit array based on a number of processing units that have currently completed mapping configuration; The parallel mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array and sent to the reconfigurable computing array module.

3. The vector operation mapping optimization system according to claim 2, wherein: The mapping configuration module is used to select a first processing unit and a second processing unit from a plurality of processing units in the processing unit array, specifically including: Select any one processing unit from the processing unit array as the first processing unit; According to a selection strategy with the least shared processing units, the second processing unit is selected from the remaining processing units in the processing unit array except the first processing unit; wherein the shared processing unit is a processing unit whose relative distance from the first processing unit and the second processing unit is within the preset relative unit distance.

4. The vector operation mapping optimization system according to claim 2, wherein: The mapping configuration module is configured to perform mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit based on a plurality of vector values ​​in the arbitrary two groups of multiplication operations, specifically including: Based on the several vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on several to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit, and the sum of the distances between the remaining to-be-mapped processing units after the mapping configuration is minimized.

5. The vector operation mapping optimization system according to claim 1, wherein: The system also includes a main control module and a data cache module; The main control module is used for: Generate the vector operation batch processing instruction according to the vector operation batch processing task and send it to the mapping configuration module; Sending all vector values ​​and scalar values ​​in the plurality of groups of multiplication operations corresponding to the vector operation batch processing instructions to the data cache module; The data cache module is used for: All vector values ​​and scalar values ​​in received sets of multiplication operations are stored.

6. The vector operation mapping optimization system according to claim 5, characterized in that: The mapping configuration module is further configured to: When the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to a preset abnormal length threshold, determining a mapping value for each of the processing units based on a preset serial mapping strategy, generating serial mapping configuration information, and sending the information to the reconfigurable computing array module; The reconfigurable computing array module is also used for: The scalar values ​​and the vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information are mapped to the processing unit array, so as to perform the set of multiplication operations corresponding to the serial mapping configuration information based on the mapped processing unit array.

7. The vector operation mapping optimization system according to claim 6, characterized in that: Each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, the mapping configuration module is used to determine a mapping value for each processing unit based on a preset serial mapping strategy, generate serial mapping configuration information, and send it to the reconfigurable computing array module, specifically including: Select any one processing unit from the processing unit array as the third processing unit; mapping the third processing unit based on a scalar value in any set of multiplication operations; Performing mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the third processing unit based on a plurality of vector values ​​in the arbitrary set of multiplication operations; Determining a mapping value of each processing unit in the processing unit array according to a number of processing units that have currently completed mapping configuration; The serial mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array and sent to the reconfigurable computing array module.

8. The vector operation mapping optimization system according to claim 6, wherein: The mapping configuration module is further configured to: When the length of the vector in the multiplication operation is greater than the abnormal length threshold, an abnormal signal is sent to the main control module.

9. The vector operation mapping optimization system according to claim 5, characterized in that: The reconfigurable computing array module further includes a control unit and a data reading and writing unit; the reconfigurable computing array module is configured to map a plurality of vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information, specifically including: receiving the parallel mapping configuration information through the control unit, and determining a mapping value of each of the processing units in the processing unit array based on the parallel mapping configuration information; Reading, from the data cache module, a plurality of vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the parallel mapping configuration information, through the data read / write unit, according to the mapping value of each processing unit in the processing unit array; wherein any one of the read vector values ​​or scalar values ​​has a corresponding relationship with the mapping value of any one of the processing units; According to the mapping value of each of the processing units in the processing unit array, the vector values ​​and scalar values ​​in the read sets of multiplication operations are mapped to the processing unit array.

10. The vector operation mapping optimization system according to claim 6, wherein: The reconfigurable computing array module further includes a control unit and a data reading and writing unit; the reconfigurable computing array module is configured to map a scalar value and a plurality of vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information to the processing unit array, specifically including: receiving the serial mapping configuration information through the control unit, and determining a mapping value of each of the processing units in the processing unit array based on the serial mapping configuration information; According to the mapping value of each processing unit in the processing unit array, read, from the data cache module, via the data read / write unit, a scalar value and a plurality of vector values ​​in a group of multiplication operations corresponding to the serial mapping configuration information; wherein any one of the read vector values ​​or scalar values ​​has a corresponding relationship with the mapping value of any one of the processing units; According to the mapping value of each of the processing units in the processing unit array, a scalar value and a plurality of vector values ​​in a group of multiplication operations read are mapped to the processing unit array.

11. The vector operation mapping optimization system according to claim 2, wherein: The reconfigurable computing array module is also used for: In the process of executing the at least two groups of multiplication operations in parallel, the processing unit mapped with the vector value is controlled to access the processing unit mapped with the scalar value belonging to the same group of multiplication operations as the vector value, and perform the multiplication operation of the vector value and the accessed scalar value.

12. The vector operation mapping optimization system according to any one of claims 1 to 11, characterized in that: The reconfigurable computing array module includes four processing unit arrays, each of the processing unit arrays includes 16 processing units, and the 16 processing units form a 4×4 processing unit array.

13. A vector operation mapping optimization method, characterized in that: include: When a vector operation batch processing instruction is received, determining a plurality of vector and scalar multiplication operations corresponding to the vector operation batch processing instruction, and obtaining the length of the vector in the multiplication operation; When the length of the vector in the multiplication operation is less than a preset vector length threshold, determining a mapping value for each of the processing units based on a preset parallel mapping strategy, and generating parallel mapping configuration information; wherein the vector length threshold is set based on the number of processing units included in the processing unit array in the reconfigurable computing array module; Based on the parallel mapping configuration information, several vector values ​​and scalar values ​​in at least two groups of multiplication operations are mapped to the processing unit array, so as to execute the at least two groups of multiplication operations in parallel based on the mapped processing unit array; wherein the mapped values ​​are the vector values, the scalar values ​​or null values.

14. The vector operation mapping optimization method according to claim 13, wherein: Each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, determining a mapping value for each processing unit based on a preset parallel mapping strategy and generating parallel mapping configuration information specifically includes: Selecting a first processing unit and a second processing unit from a plurality of the processing units in the processing unit array; Mapping and configuring the first processing unit and the second processing unit respectively based on scalar values ​​in any two groups of multiplication operations; Based on the vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit; When the current number of processing units to be mapped is greater than or equal to N+1, mapping and configuring any one of the processing units to be mapped based on the scalar value in the new multiplication operation, and mapping and configuring a number of processing units to be mapped that are within the preset relative unit distance from the any one of the processing units to be mapped based on a number of vector values ​​in the new multiplication operation; repeating this step until the current number of processing units to be mapped is less than N+1; where N represents the length of the vector in the multiplication operation; Determining a mapping value of each processing unit in the processing unit array based on a number of processing units that have currently completed mapping configuration; The parallel mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array.

15. The vector operation mapping optimization method according to claim 14, wherein: The selecting a first processing unit and a second processing unit from a plurality of the processing units in the processing unit array specifically includes: Select any one processing unit from the processing unit array as the first processing unit; According to a selection strategy with the least shared processing units, the second processing unit is selected from the remaining processing units in the processing unit array except the first processing unit; wherein the shared processing unit is a processing unit whose relative distance from the first processing unit and the second processing unit is within the preset relative unit distance.

16. The vector operation mapping optimization method according to claim 14, wherein: The mapping configuration of the plurality of to-be-mapped processing units located within the preset relative unit distance from the first processing unit or the second processing unit based on the plurality of vector values ​​in the arbitrary two sets of multiplication operations specifically includes: Based on the several vector values ​​in the arbitrary two groups of multiplication operations, mapping configuration is performed on several to-be-mapped processing units that are within the preset relative unit distance from the first processing unit or the second processing unit, and the sum of the distances between the remaining to-be-mapped processing units after the mapping configuration is minimized.

17. The vector operation mapping optimization method according to claim 13, wherein: Also includes: When the length of the vector in the multiplication operation is greater than or equal to the vector length threshold and less than or equal to a preset abnormal length threshold, determining a mapping value for each of the processing units based on a preset serial mapping strategy, and generating serial mapping configuration information; The scalar values ​​and the vector values ​​in a set of multiplication operations corresponding to the serial mapping configuration information are mapped to the processing unit array, so as to perform the set of multiplication operations corresponding to the serial mapping configuration information based on the mapped processing unit array.

18. The vector operation mapping optimization method according to claim 17, wherein: Each processing unit in the processing unit array supports interconnection access with processing units within a preset relative unit distance; then, determining a mapping value for each processing unit based on a preset serial mapping strategy and generating serial mapping configuration information specifically includes: Select any one processing unit from the processing unit array as the third processing unit; mapping the third processing unit based on a scalar value in any set of multiplication operations; Performing mapping configuration on a plurality of to-be-mapped processing units that are within the preset relative unit distance from the third processing unit based on a plurality of vector values ​​in the arbitrary set of multiplication operations; Determining a mapping value of each processing unit in the processing unit array according to a number of processing units that have currently completed mapping configuration; The serial mapping configuration information is generated according to the mapping value of each processing unit in the processing unit array.

19. The vector operation mapping optimization method according to claim 17, wherein: Also includes: When the length of the vector in the multiplication operation is greater than the abnormal length threshold, an abnormal signal is sent to the main control module.

20. The vector operation mapping optimization method according to claim 13, wherein: Mapping the plurality of vector values ​​and scalar values ​​in at least two groups of multiplication operations to the processing unit array based on the parallel mapping configuration information specifically includes: Determining a mapping value for each of the processing units in the processing unit array based on the parallel mapping configuration information; Reading, from a data cache module, a plurality of vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the parallel mapping configuration information according to the mapping value of each processing unit in the processing unit array; wherein the data cache module stores all vector values ​​and scalar values ​​in a plurality of groups of multiplication operations corresponding to the vector operation batch instruction; and any read vector value or scalar value has a corresponding relationship with the mapping value of any processing unit; According to the mapping value of each of the processing units in the processing unit array, the vector values ​​and scalar values ​​in the read sets of multiplication operations are mapped to the processing unit array.

21. The vector operation mapping optimization method according to claim 17, wherein: Mapping a set of scalar values ​​and a plurality of vector values ​​in a multiplication operation corresponding to the serial mapping configuration information to the processing unit array specifically includes: Determining a mapping value of each of the processing units in the processing unit array based on the serial mapping configuration information; Reading, from a data cache module, a scalar value and a plurality of vector values ​​in a group of multiplication operations corresponding to the serial mapping configuration information according to the mapping value of each processing unit in the processing unit array; wherein the data cache module stores all vector values ​​and scalar values ​​in the plurality of groups of multiplication operations corresponding to the vector operation batch instruction; and any read vector value or scalar value has a corresponding relationship with the mapping value of any processing unit; According to the mapping value of each of the processing units in the processing unit array, a scalar value and a plurality of vector values ​​in a group of multiplication operations read are mapped to the processing unit array.

22. The vector operation mapping optimization method according to claim 14, wherein: Also includes: In the process of executing the at least two groups of multiplication operations in parallel, the processing unit mapped with the vector value is controlled to access the processing unit mapped with the scalar value belonging to the same group of multiplication operations as the vector value, and perform the multiplication operation of the vector value and the accessed scalar value.

23. A terminal device, characterized in that: It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the vector operation mapping optimization method according to any one of claims 13 to 22 when executing the computer program.

24. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the vector operation mapping optimization method according to any one of claims 13 to 22 is implemented.

Images