Source-drain contact interface optimization method, source-drain contact interface and semiconductor device
By doping and depositing antimony single atomic layer in the source and drain areas of the semiconductor substrate, the heat treatment process is optimized to generate metal silicide, which solves the problem of high contact resistivity caused by the pinning effect of Fermi level, and achieves lower contact resistance and higher carrier mobility, improving the performance and stability of semiconductor devices.
Patent Information
- Application Number
- CN202510639660.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-19
- Publication Date
- 2025-08-29
AI Technical Summary
In the prior art, the Fermi level pinning effect leads to the difficulty of effectively reducing the source-drain contact resistivity, which limits the improvement of semiconductor device performance.
Impurity doping is performed in the source and drain region of the semiconductor substrate, forming a source and drain doping layer, and depositing an antimony single atom layer, and then silicification occurs with the contact metal layer to generate metal silicides, and the interface quality is controlled by optimizing the heat treatment process.
It significantly reduces the source-drain ratio contact resistivity, improves the carrier mobility and current transmission efficiency, enhances the overall performance and stability of semiconductor devices, and meets the miniaturization needs of modern integrated circuits.
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Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a method for optimizing a source-drain contact interface, a source-drain contact interface, and a semiconductor device. Background Art
[0002] As CMOS (Complementary Metal-Oxide-Semiconductor) technology develops towards deep submicron and nanometer-scale processes, the continuous reduction in transistor size has led to an increasing proportion of source-drain contact resistance in the overall resistance, becoming a key factor limiting device performance.
[0003] In existing technologies, contact resistance is typically reduced by increasing the contact area or reducing the specific contact resistivity. However, given the decreasing contact area between the source and drain regions, increasing the contact area no longer has widespread application, and therefore, effectively reducing the source-drain specific contact resistivity has become a key concern. Ideally, the Schottky barrier height can be controlled by selecting metals with different work functions, thereby optimizing the contact resistance. However, due to the Fermi level pinning effect, the Schottky barrier height no longer depends on the work function of the metal used. Even changing the type of metal cannot effectively change the Schottky barrier height, further limiting the ability to reduce contact resistance.
[0004] Therefore, an optimization method for the source-drain contact interface that can effectively alleviate the Fermi level pinning effect and reduce the source-drain contact resistivity needs to be studied urgently. Summary of the Invention
[0005] In view of this, the present application provides a method for optimizing the source-drain contact interface, a source-drain doping layer and a semiconductor device, the main purpose of which is to solve the technical problem in the prior art that the Fermi level pinning effect cannot effectively reduce the contact resistance.
[0006] A first aspect of the present invention provides a method for optimizing a source-drain contact interface, comprising:
[0007] Doping impurities in the source and drain regions on the semiconductor substrate to form source and drain doped layers;
[0008] depositing an antimony single atomic layer on the source / drain doped layer;
[0009] depositing a contact metal layer on the semiconductor structure on which the antimony single atomic layer has been deposited;
[0010] The semiconductor structure is subjected to heat treatment so that the source-drain doping layer on which the antimony single atomic layer is deposited undergoes a silicidation reaction with the contact metal layer to generate silicide.
[0011] Optionally, depositing an antimony single atomic layer on the source / drain doping layer includes: depositing an antimony single atomic layer on the source / drain doping layer using an atomic layer deposition process.
[0012] Optionally, the source and drain regions on the semiconductor substrate are doped with impurities to form source and drain doped layers, including: providing a semiconductor substrate, wherein the semiconductor substrate has a gate structure; determining a target source and drain region based on the gate structure, and determining a target impurity type based on the type of semiconductor device to be manufactured; and doping the target source and drain region with impurities of the target impurity type.
[0013] Optionally, impurity doping is performed using an ion implantation process or an in-situ doping process.
[0014] Optionally, the contact metal layer is a titanium metal layer, or a stacked titanium metal layer and a titanium nitride metal layer, or a nickel metal layer, or a nickel-platinum alloy metal layer.
[0015] Optionally, when the contact metal layer is a titanium metal layer, the thickness of the titanium metal layer is 3-5 nm; when the contact metal layer is a stacked titanium metal layer and a titanium nitride metal layer, the thickness of the titanium metal layer and the titanium nitride metal layer are both 3-5 nm.
[0016] Optionally, the heat-treating the semiconductor structure includes: heat-treating the semiconductor structure using a rapid thermal annealing process, a dynamic surface annealing process, or a laser annealing process.
[0017] A second aspect of the present invention provides a source-drain contact interface, which is prepared based on any of the above-mentioned methods for optimizing the source-drain contact interface.
[0018] A third aspect of the present invention provides a semiconductor device comprising the source-drain contact interface as described above.
[0019] The present invention provides a method for optimizing the source-drain contact interface, a source-drain contact interface, and a semiconductor device. Considering that a large number of dangling bonds on the silicon surface will lead to additional surface states, increase the surface state density, and thus affect device performance, by depositing an antimony monoatomic layer, it is possible to provide electrons to fill the dangling bonds on the silicon surface, effectively reducing the surface state density, reducing the interference of the surface state on carrier transport, improving electron mobility, improving interface quality, and significantly reducing the Fermi level pinning effect; the presence of the antimony monoatomic layer reduces interface defect states and promotes the uniform formation of subsequent metal silicides, significantly reducing the source-drain contact resistivity; the antimony in the antimony monoatomic layer has a lower diffusion rate in silicon than other group V elements. In the subsequent silicide reaction, antimony will not easily diffuse into the depth of silicon, maintain its passivation effect at high temperatures, ensure that the interface quality is not affected by high temperatures, show higher thermal stability, and thus comprehensively improve the overall performance of the semiconductor. The above method reduces the source-drain contact resistivity, improves current transfer efficiency, and maintains interface quality in high-temperature processes, extending the life of semiconductor devices and improving working stability by depositing an antimony monoatomic layer.
[0020] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0022] Figure 1 A schematic flow chart of a method for optimizing a source-drain contact interface provided by an embodiment of the present invention is shown;
[0023] Figure 2 A schematic flow chart of another method for optimizing a source-drain contact interface provided by an embodiment of the present invention is shown;
[0024] Figure 3 A schematic diagram showing the deposition of an antimony single atomic layer on a source-drain doped layer in a method for optimizing a source-drain contact interface provided by an embodiment of the present invention is shown;
[0025] Figure 4 A schematic diagram showing the principle of depositing an antimony single atomic layer on a source-drain doped layer in a method for optimizing a source-drain contact interface provided by an embodiment of the present invention is shown;
[0026] Figure 5A schematic diagram showing a contact metal layer deposited on the surface of a semiconductor structure in a method for optimizing a source-drain contact interface provided by an embodiment of the present invention is shown;
[0027] Figure 6 A schematic diagram of forming silicide by heat treatment in a method for optimizing a source-drain contact interface provided by an embodiment of the present invention is shown.
[0028] In the picture:
[0029] 1. Antimony monoatomic layer; 2. Contact metal layer; 3. Silicide;
[0030] ILD, dielectric layer; MG HK, metal gate + high-K dielectric; STI, shallow trench isolation; Spacer, sidewall; n + -Si, source and drain doping layers. DETAILED DESCRIPTION
[0031] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.
[0032] The embodiment of the present application provides a method for optimizing the source-drain contact interface, such as Figure 1 As shown, the method includes the following steps:
[0033] 101. Doping impurities in the source and drain regions on the semiconductor substrate to form source and drain doped layers.
[0034] Specifically, the semiconductor substrate, as the basic material for manufacturing transistors, is usually silicon (Si), but may also be other semiconductor materials such as gallium arsenide (GaAs) or silicon carbide (SiC). In a transistor, it specifically includes three parts: source, gate, and drain. The source and drain in the drain-source region are where current enters and leaves the transistor. By introducing a small amount of impurity atoms into the semiconductor material, the electrical properties can be significantly changed. For example, adding phosphorus (P) or arsenic (As) to silicon will produce an n-type semiconductor. Conversely, adding boron (B) will form a p-type semiconductor.
[0035] In the embodiments of the present application, impurity doping increases the number of free electrons or holes in the source and drain regions, thereby improving the conductivity of these regions. By optimizing the doping concentration and distribution, the resistance can be effectively reduced, the current driving capability can be improved, and the operating speed and efficiency of the transistor can be improved. Appropriate doping can help set the threshold voltage of the transistor and reduce hot carrier injection and other potential reliability problems when the transistor is working, thereby extending the life of the device.
[0036] 102. Deposit an antimony single atomic layer on the source and drain doping layers.
[0037] In an embodiment of the present application, advanced thin film deposition technology is used to form a single atomic layer composed of antimony atoms on the surface of the source and drain doping layers. Antimony atoms can effectively fill the dangling bonds on the silicon surface. Considering that the dangling bonds on the silicon surface will cause additional charge traps and increase the surface state density if they are not passivated, thereby affecting the device performance, the antimony single atomic layer can provide electrons to fill these dangling bonds, reduce surface states, and improve carrier mobility; and the presence of the antimony single atomic layer helps to form an ohmic contact with lower resistance, which helps to improve the working efficiency of the transistor. Low resistance contact means that current can flow more efficiently between the source and drain, reducing energy loss and increasing circuit speed; and the diffusion rate of antimony in silicon is low, which means that even in the subsequent high-temperature treatment process, antimony can maintain its position and continue to play a passivation role. Therefore, the antimony single atomic layer deposited on the source and drain doping layers still maintains good interface quality under high temperature conditions.
[0038] 103. Depositing a contact metal layer on the semiconductor structure on which the antimony monoatomic layer has been deposited.
[0039] Specifically, a contact metal layer is further deposited on the semiconductor structure on which the antimony single atomic layer has been deposited. This is a key step in the manufacture of semiconductor devices and aims to optimize the electrical performance of the transistor. The specific selection of the contact metal layer depends on the specific application needs and process requirements. Commonly used contact metals include cobalt (Co), nickel (Ni), titanium (Ti), etc., which usually react with the silicon below to form a low-resistivity metal silicide to ensure good ohmic contact.
[0040] In an embodiment of the present application, by depositing a contact metal layer on the antimony single atomic layer, lower contact resistance can be achieved, and the switching speed, current driving capability and overall electrical performance of the transistor can be effectively improved while reducing energy loss.
[0041] 104. Performing heat treatment on the semiconductor structure to cause the source / drain doping layer where the antimony single atomic layer is deposited to react with the contact metal layer to generate silicide.
[0042] Specifically, through a precisely controlled heat treatment process, the contact metal layer and the silicon in the source and drain doping layers undergo a silicidation reaction to generate metal silicide. In this process, the presence of the antimony single atomic layer helps maintain the quality of the interface.
[0043] In the embodiments of the present application, the metal silicide generated by the silicidation reaction has a very low resistivity, which greatly reduces the contact resistance between the source and drain regions and the metal electrode and improves the current transmission efficiency; through optimized heat treatment conditions, it can be ensured that the formed silicide is uniform and stable, and considering that the diffusion rate of antimony in silicon is low, its passivation effect can be maintained during high-temperature treatment to protect the interface from damage.
[0044] The optimization method of the source-drain contact interface provided by the present invention takes into account that the presence of a large number of dangling bonds on the silicon surface will lead to additional surface states, increase the surface state density, and thus affect the device performance. Therefore, by depositing an antimony monoatomic layer, it is possible to provide electron-filled dangling bonds on the silicon surface, effectively reducing the surface state density, reducing the interference of the surface state on carrier transport, improving electron mobility, improving interface quality, and significantly reducing the Fermi level pinning effect; the presence of the antimony monoatomic layer reduces interface defect states and promotes the uniform formation of subsequent metal silicides, significantly reducing the source-drain contact resistivity; the antimony in the antimony monoatomic layer has a lower diffusion rate in silicon than other Group V elements. In the subsequent silicide reaction, antimony will not easily diffuse into the depth of silicon, maintaining its passivation effect at high temperatures, ensuring that the interface quality is not affected by high temperatures, showing higher thermal stability, and thus comprehensively improving the overall performance of the semiconductor. The above method reduces the source-drain contact resistivity by depositing an antimony monoatomic layer, improves current transfer efficiency, and maintains interface quality in high-temperature processes, extending the life of semiconductor devices and improving working stability.
[0045] The present invention provides another method for optimizing the source-drain contact interface, such as Figure 2 As shown, specifically taking an NMOS transistor as an example, the method includes the following steps:
[0046] 201. Doping impurities in the source and drain regions on the semiconductor substrate to form source and drain doped layers.
[0047] Specifically, a semiconductor substrate is first provided, which has a gate structure. Then, a target source and drain region is determined based on the gate structure, and a target impurity type is determined based on the type of semiconductor device to be manufactured. Then, the target source and drain region is doped with impurities of the target impurity type.
[0048] Specifically, impurity doping is performed using an ion implantation process or an in-situ doping process.
[0049] Among them, first, a semiconductor material is prepared as a basic substrate, usually silicon (Si), but it may also be other semiconductor materials, such as gallium arsenide (GaAs) or silicon carbide (SiC), as the basis for all subsequent process steps; then a gate structure is formed on the substrate, and the existing gate structure is used as a reference point to accurately mark the areas to be doped with impurities, that is, the positions of the source and drain; the target impurity type is determined based on the type of semiconductor device to be manufactured: the appropriate impurity type is selected according to the type of semiconductor device to be manufactured. For NMOS tubes, commonly used impurities include phosphorus (P) or arsenic (As), and then impurity doping is performed using an ion implantation process or an in-situ doping process. The ion implantation process is to use a high-energy ion beam to directly implant selected impurity atoms into the predetermined source and drain regions, allowing very precise control of the doping concentration and depth, while the in-situ doping process introduces impurities simultaneously during the growth of the semiconductor material.
[0050] In the embodiments of the present application, whether ion implantation or in-situ doping process is used, precise positioning of the doping area and fine control of the doping concentration can be achieved; by selecting the appropriate impurity type and concentration, the conductivity of the source and drain regions can be significantly improved, the resistance can be reduced, and the current driving capability of the device can be enhanced; appropriate doping helps to set the threshold voltage of the transistor, reduce unnecessary defects and non-uniformity, thereby improving the overall reliability and long-term stability of the device.
[0051] 202. Deposit an antimony single atomic layer 1 on the source / drain doping layer.
[0052] Specifically, if Figure 3 As shown, an antimony single atomic layer 1 is deposited on the source and drain doping layer using an atomic layer deposition process.
[0053] Among them, atomic layer deposition (ALD) is an advanced thin film deposition technology that can precisely control the thickness and uniformity of the film at the atomic level. By alternately exposing the substrate to gaseous precursors and reactants, only one layer of atoms is grown at a time, ensuring high consistency and coverage. Antimony (Sb) provides electrons to fill dangling bonds on the silicon (Si) surface, thereby reducing the surface state density. This is because when the silicon surface is exposed, unpaired chemical bonds, namely dangling bonds, are formed. Dangling bonds can act as charge traps, increasing the surface state density and thus affecting device performance. Antimony atoms can provide additional electrons to fill these dangling bonds, effectively passivating the dangling bonds, which means that the number or density of surface states is reduced, the surface quality is improved, and the negative impact of interface states on device performance is reduced. In addition, the diffusion rate of antimony in silicon is relatively low, which means that even if it experiences high temperatures during subsequent processing, antimony will not easily diffuse deep into the silicon interior. It maintains its position under high temperature conditions and continues to exert its passivation effect, ensuring that the interface quality is not affected by high-temperature treatment.
[0054] In the embodiments of this application, Figure 4 As shown, the antimony single atomic layer 1 significantly reduces the surface state density and improves the carrier mobility by filling the dangling bonds on the silicon surface; the presence of antimony helps to form a higher quality metal-semiconductor contact interface, reduces the interface state's obstruction to electron transmission, and optimizes the contact resistance; due to the low diffusion rate of antimony in silicon, antimony can maintain its passivation function even during high-temperature treatment, ensuring the consistency and long-term stability of the interface quality, which not only improves the basic electrical performance of the transistor, but also enhances its reliability and service life, and is particularly suitable for the requirements of miniaturization and high efficiency in the manufacture of high-performance integrated circuits.
[0055] 203. Deposit a contact metal layer 2 on the semiconductor structure on which the antimony monoatomic layer 1 has been deposited.
[0056] Specifically, if Figure 5 As shown, the contact metal layer 2 is a titanium metal layer, or a stacked titanium metal layer and a titanium nitride metal layer, or a nickel metal layer, or a nickel-platinum alloy metal layer.
[0057] Specifically, when the contact metal layer 2 is a titanium metal layer, the thickness of the titanium metal layer is 3-5 nm; when the contact metal layer 2 is a stacked titanium metal layer and a titanium nitride metal layer, the thickness of the titanium metal layer and the titanium nitride metal layer are both 3-5 nm.
[0058] Among them, the contact metal layer 2 can be selected as a titanium (Ti) metal layer, or a stacked titanium metal layer and a titanium nitride (TiN) metal layer, or a nickel (Ni) metal layer or a nickel platinum (NiCr) alloy metal layer; metal titanium can react with silicon to form a low-resistivity metal silicide 3, and has good adhesion and oxidation resistance. Currently, three-dimensional device processes generally use titanium metal layers and titanium nitride metal layers; when titanium is selected as the contact metal layer 2, its thickness should be controlled between 3-5nm, which can ensure sufficient conductivity without significantly increasing the physical size of the device. On this basis, the titanium nitride metal layer should also be maintained at 3-5nm. The titanium nitride metal layer acts as a barrier layer to prevent the titanium below from diffusing into the silicon substrate, while also enhancing the stability of the overall structure.
[0059] In the embodiments of the present application, metals such as titanium or nickel are used as contact layers, which can react with silicon to form metal silicides with low resistivity, thereby significantly reducing contact resistance and improving current transmission efficiency. When the titanium nitride metal layer is used as a barrier layer, it can effectively prevent excessive diffusion of titanium into the silicon substrate and maintain the stability and electrical properties of the interface. Both titanium and titanium nitride have good adhesion and can form a stable contact interface on the semiconductor surface, which is very important for long-term reliability and stability. Controlling the thickness of the metal layer within the range of 3-5nm helps to meet the miniaturization requirements of modern integrated circuits while ensuring that electrical performance is not affected.
[0060] 204 . Perform heat treatment on the semiconductor structure to cause a silicidation reaction between the source / drain doped layer and the contact metal layer 2 to generate silicide 3 .
[0061] Specifically, if Figure 6 As shown, the semiconductor structure is thermally treated by using a rapid thermal annealing process, a dynamic surface annealing process, or a laser annealing process to form a silicide 3 .
[0062] Among them, Rapid Thermal Annealing (RTP) uses high-power lamps to quickly heat the wafer to a set temperature, maintains it for a period of time, and then quickly cools it down. It can achieve the required silicidation reaction in a short time while reducing impurity diffusion and other adverse effects; Dynamic Surface Annealing (DSA) uses a laser beam to scan the wafer surface to provide extremely high local temperatures, but because the action time is very short, the overall heat-affected zone is small, which is suitable for occasions where fine control of surface layer properties is required; Laser Annealing uses laser as a heat source, which can very precisely control the energy input and heating area, and is particularly suitable for applications that require highly localized processing.
[0063] In the embodiments of the present application, optimized heat treatment conditions ensure that the formed silicide 3 is uniform and stable, which is very important for long-term reliability and stability. Good electrical contact characteristics can enhance the overall electrical performance of the device. Technologies such as rapid thermal annealing, dynamic surface annealing, and laser annealing can reach high temperatures in a shorter period of time, thereby reducing the total heat treatment time, reducing the impact on other material layers, and preventing unnecessary diffusion or other negative effects. The presence of the antimony monoatomic layer 1 still plays its passivation role during the heat treatment process, protecting the silicon surface from damage and maintaining a high-quality interface. This further enhances the reliability and performance of the device.
[0064] The present invention also provides a source-drain contact interface. By depositing an antimony single atomic layer 1 on the source-drain doped layer and further depositing an appropriate contact metal layer 2 thereon, the number of dangling bonds on the silicon surface can be effectively reduced, thereby reducing the contact resistance, helping to improve the current transmission efficiency, and enhancing the working performance of the transistor; the antimony single atomic layer 1 can passivate the silicon surface, reduce the surface state density, alleviate the Fermi level pinning effect, make electron transmission smoother, improve the carrier mobility, and thus improve the overall electrical performance; antimony has a low diffusion rate in silicon, and its passivation effect can be maintained even during high-temperature treatment, ensuring that the interface quality is not affected in subsequent processes and maintaining long-term stability and reliability; using advanced thin film deposition technology and controlling the appropriate thickness of the contact metal layer 2, precise control of the contact interface can be achieved.
[0065] The present invention also provides a semiconductor device, in which the optimized source-drain contact interface reduces contact resistance and energy loss. By reducing interface defects and optimizing the heat treatment process, the reliability and service life of the device can be significantly improved. As the size of transistors continues to shrink, traditional contact methods may not be able to meet performance requirements. Semiconductor devices with optimized contact interfaces can provide excellent electrical performance without significantly increasing the contact area, adapting to the trend of miniaturization of modern integrated circuits.
[0066] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0067] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.
Claims
1. A method for optimizing a source-drain contact interface, characterized in that: include: Doping impurities in the source and drain regions on the semiconductor substrate to form source and drain doped layers; depositing an antimony single atomic layer on the source / drain doped layer; depositing a contact metal layer on the semiconductor structure on which the antimony single atomic layer has been deposited; The semiconductor structure is subjected to heat treatment so that the source-drain doping layer on which the antimony single atomic layer is deposited undergoes a silicidation reaction with the contact metal layer to generate silicide.
2. The method according to claim 1, characterized in that The step of depositing an antimony single atomic layer on the source / drain doped layer comprises: An antimony single atomic layer is deposited on the source / drain doping layer using an atomic layer deposition process.
3. The method according to claim 1, characterized in that The step of doping the source and drain regions on the semiconductor substrate with impurities to form source and drain doped layers includes: Providing a semiconductor substrate, wherein the semiconductor substrate has a gate structure; Determining a target source / drain region based on the gate structure, and determining a target impurity type based on the type of semiconductor device to be manufactured; The target source and drain regions are doped with impurities of the target impurity type.
4. The method according to claim 1 or 3, characterized in that The impurity doping is performed using an ion implantation process or an in-situ doping process.
5. The method according to claim 1, wherein The contact metal layer is a titanium metal layer, or a stacked titanium metal layer and a titanium nitride metal layer, or a nickel metal layer, or a nickel-platinum alloy metal layer.
6. The method according to claim 1, characterized in that When the contact metal layer is a titanium metal layer, the thickness of the titanium metal layer is 3-5 nm; When the contact metal layer is a stacked titanium metal layer and a titanium nitride metal layer, the thickness of the titanium metal layer and the titanium nitride metal layer are both 3-5 nm.
7. The method according to claim 1, characterized in that The heat treatment of the semiconductor structure comprises: The semiconductor structure is thermally treated by using a rapid thermal annealing process, a dynamic surface annealing process, or a laser annealing process.
8. A source-drain contact interface, characterized in that: It is prepared based on the source-drain contact interface optimization method described in any one of claims 1 to 7.
9. A semiconductor device, characterized in that: Comprising the source-drain contact interface as claimed in claim 8.