Formation method of semiconductor structure
By adjusting the depth ratio and cleaning the channel, the problems caused by holes in the Wall-first solution are solved, the smoothness of the fin structure is improved, and the performance of semiconductor devices is enhanced.
Patent Information
- Application Number
- CN202410225176.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-28
- Publication Date
- 2025-08-29
AI Technical Summary
In semiconductor manufacturing, when using the Wall-first scheme to form a fin field effect transistor, holes are easily generated, resulting in leakage.
By performing one or more depth ratio adjustment treatments on the channel and performing a cleaning process, debris generated by the etching process are removed, the flatness of the side walls of the channel is improved, and after forming a dielectric layer, the mask layer, a stacked structure and a part of the substrate are etched to form a discrete fin structure, and an isolation structure surrounding the fin structure is formed on the substrate.
This reduces the chance of hole generation, improves the smoothness of the sidewall of the fin structure, and enhances the performance of semiconductor devices.
Smart Images
Figure CN120568831A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this specification relate to the field of semiconductor technology, and more particularly, to a method for forming a semiconductor structure. Background Art
[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (Fin Field Effect Transistors) and Gate-All-Around (GAA) transistors.
[0003] The structure of a FinFET typically consists of multiple discrete fins formed on a substrate. There are two technical approaches to forming FinFETs: the first is the Wall-first approach, which forms the dielectric layer first, followed by the isolation structure; the second is the Wall-last approach, which forms the isolation structure first, followed by the dielectric layer. However, using the Wall-first approach can easily create voids during the fin formation process, leading to leakage.
[0004] In this context, how to provide a technical solution to reduce the probability of hole generation has become a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention
[0005] In view of this, embodiments of the present disclosure provide a method for forming a semiconductor structure, which can reduce the probability of void generation and thereby reduce the probability of leakage.
[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a stacked structure and a mask layer located above the stacked structure are formed, the stacked structure comprising one or more channel stacks stacked in sequence from bottom to top, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a channel in the substrate, the stacked structure and the mask layer; performing one or more aspect ratio adjustment processes on the channel, the aspect ratio adjustment process comprising: etching the sidewalls of the channel using a free radical etching process, and removing impurities generated during the etching process using a cleaning process; forming a dielectric layer in the channel; after forming the dielectric layer, etching the mask layer, the stacked structure and a portion of the substrate to form a discrete fin structure; and forming an isolation structure surrounding the fin structure on the substrate, wherein the top of the isolation structure is lower than the top of the fin structure.
[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, by performing one or more aspect ratio adjustment processes on the channel and performing a cleaning process, impurities generated during the etching process can be removed, and the flatness of the channel sidewalls can be improved. Therefore, when the fin structure is subsequently formed, it is less likely to produce holes, so that the smoothness of the sidewalls of the fin structure can meet the design requirements, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the following briefly introduces the drawings required for use in the embodiments of this specification or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0010] Figure 1 A schematic diagram of a semiconductor structure is shown;
[0011] Figure 2 Shown Figure 1 Electron microscope image of the internal structure of a semiconductor;
[0012] Figures 3 to 22 A schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention is shown. DETAILED DESCRIPTION
[0013] As known from the background art, the current Wall-first solution is used, and holes are easily generated during the process of forming the fins, which leads to leakage.
[0014] Now we analyze the cause of leakage phenomenon by combining a semiconductor structure, see Figure 1 A schematic diagram of a semiconductor structure is shown in FIG. Figure 1 As shown, the semiconductor structure may include a substrate 10 , a plurality of dielectric layers 11 at least partially located on the substrate 10 , and sidewalls 12 at both ends of the dielectric layer 11 .
[0015] In adopting Figure 1 When the dielectric layer 11 is formed by the process shown in FIG. Figure 1 As shown, holes 13 are generated, which leads to leakage.
[0016] The inventors analyzed the reasons for the above situation and found that before forming the dielectric layer 11, a groove needs to be formed. When the groove is formed by the etching process, see Figure 2 shown Figure 1 Electron microscope images of the internal structure of semiconductors, such as Figure 2As shown in the dotted box B, the sidewalls 12 of the formed groove are relatively rough. In this way, when filling the material in the groove and forming the dielectric layer 11, holes 13 are easily generated, which makes it difficult for the sidewall smoothness of the subsequently formed fin to meet the design requirements, which easily leads to leakage.
[0017] It should be noted that Figure 1 The black parts in other areas are the background when the electron microscope image is formed, and are not the holes 13 formed in the trenches.
[0018] In order to solve the technical problem, an embodiment of the present specification provides a method for forming a semiconductor structure, including: providing a substrate, on which a stacked structure and a mask layer located above the stacked structure are formed, the stacked structure including one or more channel stacks stacked in sequence from bottom to top, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; forming a channel in the substrate, the stacked structure and the mask layer; performing one or more aspect ratio adjustment processes on the channel, the aspect ratio adjustment process including: etching the sidewalls of the channel using a free radical etching process, and using a cleaning process to remove impurities generated during the etching process; forming a dielectric layer in the channel; after forming the dielectric layer, etching the mask layer, the stacked structure and part of the substrate to form a discrete fin structure, the fin structure including: a mask layer, a stacked structure, and a dielectric layer; forming an isolation structure surrounding the fin structure on the substrate, the top of the isolation structure being lower than the top of the fin structure.
[0019] In the method for forming a semiconductor structure provided in the embodiments of this specification, by performing one or more aspect ratio adjustment processes on the channel and performing a cleaning process, impurities generated during the etching process can be removed, and the flatness of the channel sidewalls can be improved. As a result, when the fin structure is subsequently formed, holes are less likely to be generated, so that the smoothness of the sidewalls of the fin structure can meet the design requirements, thereby improving the performance of the semiconductor device.
[0020] In order to make the above-mentioned purposes, features and advantages of the embodiments of this specification more obvious and easy to understand, the specific embodiments of this specification are described in detail below with reference to the accompanying drawings.
[0021] It should be noted that the following drawings describe the embodiments of the present invention from two perspectives.
[0022] refer to Figures 3 to 22 , shows a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention, wherein, Figures 3 to 22 The sub-figure labeled (a) may be a cross-sectional view along the extending direction of the channel stack, and the sub-figure labeled (b) may be a cross-sectional view perpendicular to the extending direction of the channel stack.
[0023] refer to Figure 3, providing a substrate 100 , on which a stacked structure 101 and a mask layer 105 located above the stacked structure 101 are formed.
[0024] In some examples, in the step of providing a substrate, the substrate 100 may include a substrate ( Figure 3 Not shown), the stacked structure 101 may be located on top of the substrate.
[0025] In this embodiment, the substrate can be used to provide a process platform for forming a semiconductor structure.
[0026] In some optional examples, the substrate may be a silicon substrate, that is, the material forming the substrate may be single crystal silicon.
[0027] In other optional examples, the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, or the substrate can also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0028] In some embodiments, the stacked structure 101 may be a superlattice structure composed of alternating layers of different materials.
[0029] For example, Figure 3 As shown in Figures (a) and (b), the stacked structure 101 may include one or more channel stacks 104 stacked sequentially from bottom to top, and each channel stack 104 may include a sacrificial layer 102 and a channel layer 103 located on the sacrificial layer 102.
[0030] In some examples, the channel stack 104 may provide a process foundation for a subsequently formed channel layer 103 with a suspended spacing, wherein the channel layer 103 with a suspended spacing may provide a conductive channel of a field effect transistor.
[0031] Specifically, the sacrificial layer 102 can be used to support the channel layer 103 , thereby providing a process basis for subsequently implementing a spaced-apart suspended arrangement of the channel layer 103 .
[0032] In some examples, the sacrificial layer 102 may also be used to occupy a space for subsequently forming a gate structure.
[0033] In some embodiments, when different types of transistors are formed in different regions, the materials used for the sacrificial layer 102 and the channel layer 103 may be different.
[0034] For example, when forming an NMOS transistor, the material of the channel layer 103 can be Si, and the material of the sacrificial layer 102 can be SiGe. In the subsequent process of removing the sacrificial layer 102, the etching selectivity of SiGe and Si is relatively high, which can effectively reduce the impact of the sacrificial layer 102 removal process on the channel layer 103, thereby improving the quality of the channel layer 103 and further improving device performance.
[0035] In other embodiments, when forming a PMOS transistor, SiGe channel technology may be used to improve the performance of the PMOS transistor. In this case, the channel layer material may be SiGe, and the sacrificial layer material may be Si. In other embodiments, the channel layer material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
[0036] In some examples, a deposition process may be used to form a mask layer 105 on top of the stacked structure 101 .
[0037] As an optional example, the material forming the mask layer 105 and the material forming the sacrificial layer 102 may be the same, such as SiGe.
[0038] In some other optional examples, the material forming the mask layer 105 may also be silicon nitride, silicon oxynitride, etc.
[0039] It should be noted that Figure 3 The number of channel stacks shown is merely an example, and is used to indicate that channel stacks can be formed on a substrate and stacked sequentially from bottom to top, and should not be construed as limiting the present invention.
[0040] See also Figure 4 and Figure 5 , a trench 107 is formed in the substrate 100, the stacked structure 101 and the mask layer 105 (see Figure 5 ), specifically including:
[0041] like Figure 4 As shown, a first mask 106 is formed on the mask layer 105 .
[0042] In some examples, the method of forming the first mask 106 may include: sequentially forming a first mask material layer, an anti-reflective coating, and a photoresist layer on the mask layer 105, wherein the photoresist layer is formed with a graphic opening that exposes a portion of the anti-reflective coating, using the photoresist layer as a mask, sequentially etching the anti-reflective coating and the first mask material layer along the graphic opening, removing the first mask material layer exposed by the graphic opening, and using the remaining first mask material layer as the first mask 106.
[0043] In some optional examples, an atomic layer deposition (ALD) process may be used to form a first mask material layer on top of the mask layer 105 . Through multiple ALD cycles, the thickness uniformity of the obtained first mask 106 can be improved.
[0044] In some optional examples, the material of the first mask 106 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon boron nitride.
[0045] It should be noted that after forming the first mask 106 , the anti-reflective coating and the photoresist layer need to be removed.
[0046] See also Figure 5 Under the action of the first mask 106, a portion of the substrate 100, the stacked structure 101 and the mask layer 105 are patterned to form a channel 107, as shown in sub-figure (a).
[0047] Specifically, using the first mask 106 as a mask, photolithography and etching processes are performed to sequentially etch the mask layer 105 , the stacked structure 101 and a portion of the substrate 100 to form a trench 107 with its bottom located in the substrate 100 .
[0048] It should be noted that after forming the trench 107 , the first mask 106 needs to be removed.
[0049] See next Figure 5 Currently, when the trench 107 is formed by an etching process, an etching process with plasma is used. During the etching process, the sidewalls of the trench 107 are damaged. In addition, byproducts of the etching gas containing components such as F, Cl, and C will be deposited on the surface of the trench 107 and are not easy to clean. Therefore, the sidewalls of the formed trench 107 are relatively rough, which will affect the subsequently formed fin structure.
[0050] Based on this, see Figure 6 The trench 107 may be subjected to one or more depth-to-width ratio adjustment processes, wherein the depth-to-width ratio adjustment processes include: etching the sidewalls of the trench using a free radical etching process, and removing debris generated during the etching process using a cleaning process.
[0051] In some examples, process parameters of the free radical etching process include: etching gas includes at least two of NF3, HF, NH3, H2 and Ar; etching temperature range is -20 to 200°C; pressure range is 100 to 3000 mT; etching time is 5s to 10min.
[0052] The process parameters of the cleaning process include: a wet liquid cleaning process, wherein the liquid includes: at least one of SC1, HF, OZ and SC2; the mass fraction of the liquid ranges from 2 to 30wt%; the temperature ranges from 0 to 100°C; and the cleaning time is from 10s to 20min.
[0053] In short, by introducing a free radical etching process, the sidewalls of the channel can be modified to obtain a groove with smooth sidewalls. Then, through a cleaning process, the debris generated by the etching process can be removed, making the sidewalls of the trench hydrophobic, thereby avoiding the generation of holes when forming the dielectric layer.
[0054] Furthermore, by forming the channel first and then using the free radical etching process, different etching parameters can be selected, thereby controlling the etching selectivity to reduce the critical dimension difference between the formed structures. Figure 7 , a dielectric layer 108 is formed in the trench 107 .
[0055] In some examples, a deposition process (e.g., an atomic layer deposition process) can be used to form a dielectric material layer filling the trench 107 on the mask layer 105, and the mask layer 105 is used as a grinding stop layer. A planarization process is used to remove the dielectric material layer above the top of the mask layer 105, retaining the dielectric material layer located in the trench 107 and serving as the dielectric layer 108.
[0056] In some optional examples, the material of the dielectric layer 108 may include a low-k dielectric material, wherein the low-k dielectric material may include at least one of SiOF, SiOC, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.
[0057] After the dielectric layer is formed, the mask layer, the stacked structure and part of the substrate can be etched to form a discrete fin structure (such as Figure 10 fin structure 130 shown).
[0058] As an optional example, a self-aligned double patterning (SAPD) process may be used to etch the mask layer, the stacked structure, and a portion of the substrate to form a discrete fin structure.
[0059] As an example, the following steps may be used to form a discrete fin structure:
[0060] See also Figure 8 , a first hard mask material layer 109 , a second hard mask material layer 110 , a third hard mask material layer 111 and a first photoresist 112 are sequentially formed on the mask layer 105 .
[0061] See also Figure 9, the first photoresist 112 is processed to form a pattern opening ( Figure 9 not shown).
[0062] In some optional examples, such as Figure 9 As shown, the first photoresist 112 having pattern openings may appear in pairs. The paired first photoresist 112 (eg Figure 9 The dielectric layers 108 and 109 are arranged at a certain distance from each other and can be symmetrically distributed along the dielectric layer 108.
[0063] See also Figure 10 Using the first photoresist 112 as a mask, the third hard mask material layer 111, the second hard mask material layer 110 and the first hard mask material layer 109 are etched in sequence along the pattern opening, and the pattern on the mask is transferred to the second hard mask material layer 110 to obtain a plurality of discrete second hard mask material layers 110 and a plurality of first hard mask material layers 109 located below the second hard mask material layer 110, and the first hard mask material layer 109 exposes the top of the dielectric layer 108.
[0064] Afterwards, an etch-back process is performed to etch the mask layer 105 , the stacked structure 101 (ie, the stacked fin) and a portion of the substrate 100 to form a separate fin structure 130 .
[0065] In some examples, during the process of etching back and removing part of the substrate 100 , a substrate fin 120 protruding from the substrate can be obtained, that is, part of the substrate 100 can be converted into a substrate fin 120 , wherein the fin 120 can provide a process basis for the subsequent formation of an isolation layer.
[0066] In some examples of this specification, the material of the substrate fin 120 may be the same as that of the base 100 , that is, silicon.
[0067] In this case, the fin structure 130 in the example of this specification may include a mask layer 105 , a stacked structure 101 , a dielectric layer 108 , and a substrate fin 120 .
[0068] In some examples, such as Figure 10 As shown, two fin structures 130 are illustrated, and these two fin structures can be used to form different types of devices.
[0069] For example, one of the fin structures may be used to form an N-type device (eg, NMOS), and the other fin structure may be used to form a P-type device (eg, PMOS).
[0070] Continue to see Figure 10While forming the discrete fin structure 130 , a groove 121 can also be formed, wherein the groove 121 can be surrounded by the substrate fin 120 , the remaining mask layer 105 , the remaining stacked structure 101 , the remaining first hard mask material layer 109 , the remaining second hard mask material layer 110 and the remaining third hard mask material layer 111 .
[0071] In some examples, after forming the discrete fin structure 130, the first hard mask material layer 109, the second hard mask material layer 110 and the third hard mask material layer 111 can also be removed, so that the groove 121 can also be surrounded only by the substrate fin 120, the remaining mask layer 105 and the stacked structure 101, that is, the top height of the fin structure 130 is the same as the top height of the groove 121.
[0072] In some optional examples, considering that the subsequent process of forming the isolation structure may affect the top of the fin structure 130, Figure 10 In the illustrated steps, the first hard mask material layer 109 , the second hard mask material layer 110 and the third hard mask material layer 111 are not removed.
[0073] See e.g. 11 and Figure 12 After the fin structure 130 is formed, an isolation structure 124 surrounding the fin structure 130 may be formed on the substrate 100 .
[0074] More specifically, an isolation structure 124 surrounding the substrate fin 120 may be formed on the substrate 100 .
[0075] As an example, see Figure 11 An isolation material layer 122 is formed on the substrate 100 to conformally cover the fin structure 130 , the first hard mask material layer 109 , the second hard mask material layer 110 , and the third hard mask material layer 111 .
[0076] In some examples, the isolation material layer 122 also fills the groove 121 .
[0077] In some optional examples, the isolation material layer 122 may be formed by using at least one deposition process selected from chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
[0078] In some examples, the isolation material layer 122 may include an insulating material, such as silicon oxide, silicon oxynitride, or the like.
[0079] See also Figure 12 The top of the mask layer 105 is used as the grinding stop position, and a planarization process is used to remove the isolation material layer 122 higher than the mask layer 105, so that the top of the mask layer 105 and the isolation material layer 122 are flush with each other.
[0080] During this time, the first hard mask material layer 109 , the second hard mask material layer 110 , and the third hard mask material layer 111 are also removed.
[0081] Next, a dry etching process is used to etch back the isolation material layer 122 in the groove until the top of the isolation material layer 122 is lower than the top of the fin structure 130, so that the remaining isolation material layer 122 can be used as an isolation structure 124, which can be used to isolate adjacent devices.
[0082] Furthermore, if Figure 12 As shown, the top of the isolation structure 124 may be lower than the top of the substrate fin 120 .
[0083] In some other examples, the top of the isolation structure 124 may be flush with the top of the fin 120 .
[0084] In some examples, the isolation structure 124 may be a shallow trench isolation (STI) structure.
[0085] In some optional examples, before forming an isolation structure surrounding the fin structure on the substrate, such as Figure 11 As shown, the method for forming a semiconductor structure may further include: forming a liner material layer 123 on the substrate 100 to conformally cover the fin structure 130 .
[0086] In some examples, the liner material layer 123 may be formed by using at least one deposition process selected from chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
[0087] In some examples, the liner material layer 123 may be silicon oxide. In some other examples, the liner material layer 123 may be one or more of silicon carbide and silicon carbonitride.
[0088] It is understood that when the liner material layer 123 is formed on the substrate 100 to conformally cover the fin structure 130, as shown in FIG. Figure 11 As shown, the formed liner material layer 123 may cover the sidewalls and the top of the third hard mask material layer 111 .
[0089] See next Figure 12 In the process of forming the isolation structure 124 surrounding the fin structure 130 on the substrate 100, the method for forming the semiconductor structure may further include: removing part of the liner material layer 123 to expose the top and part of the sidewall of the fin structure 130, and using the remaining liner material layer as the liner layer 125, that is, the liner layer 125 is located between the substrate 100 and the isolation structure, and covers the bottom and sidewalls of the isolation structure 124.
[0090] After the above structure is formed, subsequent processing operations can be performed using the above structure as a processing platform to form a nanosheet.
[0091] As an example, see Figures 13 to 15 , forming a dummy gate structure 140 on the sidewalls and top of the isolation structure 124 where the fin structure 130 is exposed, specifically comprising:
[0092] See also Figure 13 , a dummy gate material layer 131 is formed on the substrate 100 to cover the fin structure 130 and the isolation structure 124 .
[0093] In some examples, the dummy gate material layer 131 may be formed using an atomic layer deposition process.
[0094] See also Figure 14 , a fourth hard mask material layer 133 , a fifth hard mask material layer 134 , a sixth hard mask material layer 135 and a second photoresist 136 are sequentially formed on top of the dummy gate material layer 131 .
[0095] See also Figure 15 , the second photoresist 136 is processed to form a pattern opening ( Figure 15 not shown).
[0096] Then, using the second photoresist 136 as a mask, the sixth hard mask material layer 135, the fifth hard mask material layer 134 and the fourth hard mask material layer 133 are etched in sequence along the pattern opening, and the pattern on the mask is transferred to the fourth hard mask material layer 133 to obtain multiple discrete fourth hard mask material layers 133, fifth hard mask material layers 134, and sixth hard mask material layers 135.
[0097] Afterwards, an etch-back process is performed to remove a portion of the dummy gate material layer 131 to expose the top of the mask layer 105 , and the remaining portion of the dummy gate material layer serves as the dummy gate structure 140 .
[0098] It should be noted that, during the process of removing the dummy gate material layer and forming the dummy gate structure 140 , part of the dummy gate structure 140 covers the sidewalls of the mask layer 105 and the stacked structure 101 , as well as part of the top of the isolation structure 124 .
[0099] In some examples, the dummy gate structure 140 may be used to pre-occupy a spatial position for subsequently forming a gate structure, wherein the dummy gate structure 140 may be a polysilicon gate structure or an amorphous silicon gate structure.
[0100] In some embodiments, the dummy gate structure may include a dummy gate oxide layer and a dummy gate layer, wherein the dummy gate oxide layer may be made of silicon oxide or silicon oxynitride, and the dummy gate layer may be made of polysilicon or amorphous silicon.
[0101] In some optional examples, before forming a dummy gate structure on the sidewall and top of the isolation structure where the fin structure is exposed, continue to refer to Figure 13 , the method for forming a semiconductor structure may further include:
[0102] A compensation sidewall material layer 132 is formed on the substrate 100 to cover the top of the isolation structure 124 , the sidewalls and the top of the fin structure.
[0103] By forming the compensation sidewall material layer 132 , the loss of the sidewall and top of the fin structure caused by subsequent processing can be reduced, thereby improving the performance of the formed semiconductor device.
[0104] In some examples of this specification, the material of the compensation sidewall material layer 132 may be silicon nitride. In other embodiments, the material of the compensation sidewall material layer may also be other insulating materials such as silicon oxide.
[0105] It should be noted that in the subsequent steps, Figure 15 As shown, the compensation sidewall material layer 132 may be removed to expose the top of the mask layer 105 .
[0106] In some examples of this specification, after the gate spacer 142 is formed, source and drain doping regions may be formed in the fin structure on both sides of the dummy gate structure.
[0107] As an example, see Figures 16 to 19 The process of forming the source-drain doped region 150 may include:
[0108] refer to Figure 16 , a portion of the fin structure is removed to form a first opening K1 exposing the top of the substrate 100 .
[0109] More specifically, the fourth hard mask material layer 133 may be used as a mask to remove portions of the mask layer 105 , the channel layer 103 , and the sacrificial layer 102 to form a first opening K1 exposing the top of the fin 120 .
[0110] In some optional examples, a portion of the fin 120 may be removed when forming the first opening K1 , that is, the bottom of the first opening K1 may be located within the substrate 100 .
[0111] See also Figure 17 , along the first opening K1, remove part of the sacrificial layer 102 in the fin structure, and form an inner groove ( Figure 17 not shown).
[0112] In some examples, the inner groove may be surrounded by the channel layer 103 and the remaining sacrificial layer 102 , or the inner groove may be surrounded by the fin 120 , the channel layer 103 adjacent to the fin 120 , and the remaining sacrificial layer 102 .
[0113] Among them, the inner groove can be used to provide a spatial position for the subsequent formation of the inner wall layer, so that after the source and drain doping regions are subsequently formed and the metal gate structure is formed at the sacrificial layer position, the inner wall layer can be located between the source and drain doping regions and the metal gate structure, which can isolate the source and drain doping regions and the metal gate structure, increase the distance between the source and drain doping regions and the metal gate structure, and thus reduce the parasitic capacitance between the source and drain doping regions and the metal gate structure.
[0114] In some examples, a wet etching process can be used to etch part of the sacrificial layer 102, wherein the wet etching process is an isotropic etching process, so that the sacrificial layer 102 can be etched along the length direction of the channel layer 103, and the wet etching process can easily achieve a larger etching selectivity ratio, which can reduce the difficulty of etching the sacrificial layer 102 and reduce the probability of damage to other film layer structures.
[0115] In some embodiments of the present specification, the material of the sacrificial layer 102 is SiGe, and the material of the channel layer 103 is Si. Therefore, the sacrificial layer 102 can be wet-etched by HCl vapor, and the etching rate of HCl vapor on SiGe material is much greater than the etching rate on Si material. Therefore, using HCl vapor to etch the sacrificial layer 102 can effectively reduce the probability of damage to the channel layer 103.
[0116] It should be noted that after removing a portion of the sacrificial layer 102 , a portion of the mask layer 105 is also removed, and the gate spacer formed subsequently is still located between the sacrificial layer 102 and the mask layer 105 .
[0117] See next Figure 18 An inner wall layer 141 is formed in the inner groove, and the outer side surface of the inner wall layer 141 can be vertically flush with the end surface of the fin structure.
[0118] In some examples, the inner wall layer 141 is used to support the channel layer 103 , thereby facilitating the subsequent replacement of the dummy gate structure 140 with a gate structure.
[0119] In some optional examples, the material of the inner wall layer 141 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride, and boron carbonitride.
[0120] As an example, the material of the inner wall layer 141 is silicon nitride.
[0121] In some examples, the step of forming the inner wall layer 141 in the inner groove may include:
[0122] An inner spacer material layer is formed on the sidewalls of the dummy gate structure 140 and the sidewalls of the inner groove. The inner spacer material layer is also filled in the inner groove. The inner spacer material layer filled in the inner groove can be used to subsequently form an inner wall layer 141 .
[0123] In some optional examples, an atomic layer deposition process may be used to form an inner spacer material layer on the sidewalls of the dummy gate structure 140 and the sidewalls of the inner groove, thereby obtaining an inner spacer material layer of higher quality and higher thickness uniformity.
[0124] Next, the inner sidewall material layer outside the inner groove is removed, and the remaining inner sidewall material layer inside the inner groove is retained as the inner wall layer 141 .
[0125] In some optional examples, the process of removing the inner sidewall material layer outside the inner groove includes a dry etching process. The dry etching process is conducive to improving the cross-sectional morphology quality of the inner sidewall layer, thereby facilitating precise control of the sidewall morphology of the inner sidewall layer.
[0126] In some optional examples, the method for forming the semiconductor structure may further include: removing a portion of the width of the inner wall layer 141 along an extension direction of the channel layer 103 .
[0127] By removing a portion of the width of the inner wall layer 141, more of the surface of the channel layer 103 can be exposed, thereby facilitating the removal of a portion of the length of the channel layer 103 along the extension direction of the channel layer 103. Moreover, by removing a portion of the width of the inner wall layer 141, it is also convenient to subsequently remove a portion of the length of the channel layer 103 using the sidewall of the inner wall layer 141 as a stop position.
[0128] In some examples, the process of removing a portion of the width of the inner wall layer 141 may include: an isotropic dry etching process or a wet etching process, wherein both the isotropic dry etching process and the wet etching process have the characteristics of isotropic etching, which is conducive to lateral etching of the inner wall layer 141.
[0129] Furthermore, after the inner wall layer 141 is formed, a portion of the length of the channel layer 103 can be removed along the extension direction of the channel layer 103. By removing a portion of the length of the channel layer 103, the arc-shaped protruding portion of the channel layer 103 at the end position due to the formation process of the inner wall layer 141 can be removed, thereby improving the flatness of the end of the channel layer 103, and then improving the flatness of the crystal surface of the subsequent source and drain doping layer growth, and improving the quality of the subsequently formed source and drain doping layer.
[0130] In some examples, while forming the inner wall layer 141 , a gate spacer 142 covering the sidewall of the dummy gate structure 140 may also be formed on the substrate 100 .
[0131] In some optional examples, when forming the gate spacer 142 , the gate spacer 142 may also cover the sidewalls of the fourth hard mask material layer 133 , the sidewalls of the fifth hard mask material layer 134 , and part of the sidewalls of the sixth hard mask material layer 135 .
[0132] In some examples, the materials forming the inner wall layer 141 and the gate sidewall 142 can be the same, for example, both can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride.
[0133] See also Figure 18 Based on the sidewall of the inner wall layer 141 , an epitaxial process is performed to form the source-drain doped region 150 .
[0134] In some examples, the step of forming the source / drain doped regions 150 may include: forming a stress layer in the first opening K1 using an epitaxial process, and forming the source / drain doped regions 150 in situ by self-doping ions during the process of forming the stress layer.
[0135] Among them, when the all-around gate transistor is a P-type MOS transistor, the material of the stress layer can be Si or SiGe, and the doping ions can be P-type ions; when the all-around gate transistor is an N-type MOS transistor, the material of the stress layer can be Si or SiC, and the doping ions can be N-type ions.
[0136] In some other examples, ion implantation may be performed on the stress layer after the stress layer is formed.
[0137] In some examples, the source / drain doping regions 150 cover sidewalls of the channel layer 103 and the inner wall layer 141 .
[0138] In some examples of the present disclosure, a top surface of the source / drain doped region 150 is lower than a top surface of the channel stack 104 .
[0139] In some other examples, the top surface of the source / drain doped region 150 may be higher than the top surface of the channel stack 104 , and the source / drain doped region 150 also covers part of the sidewall of the gate spacer 142 ; or, the top surface of the source / drain doped region 150 may also be flush with the top surface of the channel stack 104 .
[0140] After forming the source and drain doping regions, see Figure 19 The method for forming a semiconductor structure may further include: forming a conformal contact etch stop material layer 151 on the substrate 100, wherein the contact etch stop material layer 151 may serve as an etch stop layer when etching the zeroth metal layer.
[0141] In some examples, the contact etch stop material layer 151 may be formed using an atomic layer deposition process.
[0142] In some examples, the contact etch stop material layer 151 may include silicon nitride, silicon oxynitride, or the like.
[0143] In some examples, when the contact etch stop material layer 151 is formed, the contact etch stop material layer 151 is also filled into the gaps between the source and drain doped regions 150 .
[0144] After forming the source / drain doped regions 150 , subsequent process steps may further include:
[0145] See also Figure 20 , an interlayer dielectric layer 160 is formed on both sides of the dummy gate structure 140 .
[0146] In some examples, the interlayer dielectric layer 160 may be used to achieve electrical isolation between adjacent devices.
[0147] In some optional examples, the material of the interlayer dielectric layer 160 may be silicon oxide. In some other examples, the material of the interlayer dielectric layer 160 may be silicon nitride.
[0148] As an example, combining Figure 19 and Figure 20 , the step of forming the interlayer dielectric layer 160 may include:
[0149] The top of the dummy gate structure 140 is used as the grinding stop position, and a planarization process is used to remove the contact etch stop material layer 151 , the fourth hard mask material layer 133 , the fifth hard mask material layer 134 , and the sixth hard mask material layer 135 above the top of the dummy gate structure 140 .
[0150] Next, a dielectric material layer is formed on the substrate on the side of the dummy gate structure 140, and the dielectric material layer also covers the top of the dummy gate structure 140. The dielectric material layer above the top of the dummy gate structure 140 is removed, and the remaining dielectric material layer serves as the interlayer dielectric layer 160, wherein the top height of the interlayer dielectric layer 160 can be flush with the top height of the dummy gate structure 140.
[0151] See also Figure 21 After forming the interlayer dielectric layer 160, the method for forming the semiconductor structure may further include:
[0152] The dummy gate structure 140 is removed, and a gate opening K2 is formed in the interlayer dielectric layer 160 .
[0153] In some examples, the gate opening K2 may be used to provide a spatial location for forming a gate structure.
[0154] In some optional examples, the process of forming the gate opening K2 may include a dry etching process, which has high process controllability. In other embodiments, the process of forming the gate opening K2 may also be a wet etching process.
[0155] As an example, the step of forming the gate opening K2 may include: removing the dummy gate structure 140 by a dry etching process.
[0156] In some examples, the step of forming the gate opening K2 may also include: after removing the dummy gate structure 140, removing the compensation sidewall material layer 132 at the location of the dummy gate structure 140, so as to meet the performance requirements of the device (for example, operating voltage).
[0157] In some optional examples, the process of removing the compensation sidewall material layer 132 at the location of the dummy gate structure 140 may include: a dry etching process, which can improve process compatibility and reduce process costs by making the process of removing the compensation sidewall material layer 132 at the location of the dummy gate structure 140 the same as the process of removing the dummy gate structure 140.
[0158] In some other optional examples, the process of removing the compensation sidewall material layer 132 at the location of the dummy gate structure 140 may be a wet etching process.
[0159] See next Figure 22 The sacrificial layer 102 in the channel stack 104 is removed to form a through groove 161 . The through groove 161 may be surrounded by the fin 120 and the channel layer 103 , or the through groove 161 may be surrounded by the adjacent channel layer 103 and the source / drain doped region 150 .
[0160] In some examples, the through-slot 161 may communicate with the gate opening K2 .
[0161] In some optional examples, the sacrificial layer 102 may be removed by using a wet etching process.
[0162] Specifically, the material of the channel layer 103 may be Si, and the material of the sacrificial layer 102 may be SiGe. Therefore, the sacrificial layer 102 exposed by the gate opening is removed by HCl vapor, and the etching rate of the sacrificial layer 102 by the wet etching process is much greater than the etching rate of the channel layer 103 and the fin 120.
[0163] Furthermore, by removing the sacrificial layer 102 after forming the source / drain doped regions 150 , the channel layer 103 along the extension direction of the fin 120 can be connected to the source / drain doped regions 150 at both ends and suspended in the gate opening K2 , thereby providing a basis for the subsequent metal gate structure to surround the channel layer 103 .
[0164] In some examples, after the sacrificial layer 102 is removed, the channel layers 103 are spaced apart, and the remaining channel layers 103 may constitute a channel structure layer. The channel structure layer may be located on the fin 120 and spaced apart from the fin 120 .
[0165] In some optional examples, during the process of removing the sacrificial layer 102 , the mask layer 105 may also be removed.
[0166] In some optional examples, the subsequent process may further include: forming a metal gate structure in the gate opening and the through groove, the gate structure may surround the channel layer, wherein the metal gate structure may be used to control the opening and closing of the conductive channel when the device is operating.
[0167] In some examples, the gate opening is connected to the through-trench, so during the process of forming the metal gate structure in the gate opening, the metal gate structure is also filled in the through-trench.
[0168] As an example, the metal gate structure can span the channel structure layer and cover part of the top of the channel structure layer, and the metal gate structure can also surround the channel layer, wherein the metal gate structure located in the through groove is the first part and the metal gate structure located in the gate opening is the second part.
[0169] In some examples, the metal gate structure may include a high-k gate dielectric layer and a metal gate electrode layer located on the high-k gate dielectric layer.
[0170] As an example, the high-k gate dielectric layer may be located on the upper surface, the lower surface, and the side surfaces of the channel layer, and may also cover a portion of the top and a portion of the sidewalls of the fin.
[0171] In some examples, the material of the high-k gate dielectric layer may be HfO 2 , and the material of the metal gate electrode layer may be tungsten W.
[0172] In some optional examples, the metal gate structure may further include other functional layers, such as a work function layer.
[0173] Although the present invention is disclosed as above, it is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure and a mask layer located above the stacked structure are formed, wherein the stacked structure includes one or more channel stacks stacked sequentially from bottom to top, each of the channel stacks including a sacrificial layer and a channel layer located on the sacrificial layer; forming a trench in the substrate, the stacked structure, and the mask layer; Performing one or more aspect ratio adjustment processes on the trench, wherein the aspect ratio adjustment processes include: etching the sidewalls of the trench using a free radical etching process, and removing debris generated during the etching process using a cleaning process; forming a dielectric layer in the trench; After forming the dielectric layer, etching the mask layer, the stacked structure and a portion of the substrate to form a discrete fin structure; An isolation structure surrounding the fin structure is formed on the substrate, wherein a top portion of the isolation structure is lower than a top portion of the fin structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: The forming of a trench in the substrate, the stacked structure and the mask layer comprises: forming a first mask on the mask layer; Under the action of the first mask, a portion of the substrate, the stacked structure and the mask layer is patterned to form the channel.
3. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the free radical etching process include: etching gas includes at least two of NF3, HF, NH3, H2 and Ar; etching temperature range is -20 to 200°C; pressure range is 100 to 3000mT; etching time is 5s to 10min.
4. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the cleaning process include: a wet liquid cleaning process, wherein the liquid includes: at least one of SC1, HF, OZ and SC2; the mass fraction of the liquid is in the range of 2 to 30wt%; the temperature is in the range of 0 to 100°C; and the cleaning time is in the range of 10s to 20min.
5. The method for forming a semiconductor structure according to claim 1, wherein: The etching of the mask layer, the stacked structure, and a portion of the substrate to form a discrete fin structure includes: The mask layer, the stacked structure and a portion of the substrate are etched using a self-aligned double patterning process to form a discrete fin structure.
6. The method for forming a semiconductor structure according to claim 1, wherein: Before forming an isolation structure surrounding the fin structure on the substrate, the method further includes: forming a liner material layer on the substrate conformally covering the fin structure; The step of forming an isolation structure surrounding the fin structure on the substrate includes: A portion of the liner material layer is removed to expose the top and a portion of the sidewall of the fin structure, and the remaining liner material layer is used as a liner layer, which is located between the substrate and the isolation structure and covers the bottom and sidewalls of the isolation structure.
7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a dummy gate structure on the sidewalls and top of the isolation structure exposed from the fin structure; After the dummy gate structure is formed, source and drain doping regions are formed in the fin structure on both sides of the dummy gate structure.
8. The method for forming a semiconductor structure according to claim 7, wherein: The forming of a dummy gate structure on the sidewall and top of the isolation structure where the fin structure is exposed comprises: forming a dummy gate material layer on the substrate covering the fin structure and the isolation structure; A portion of the dummy gate material layer is removed, and the remaining portion of the dummy gate material layer serves as the dummy gate structure.
9. The method for forming a semiconductor structure according to claim 7, wherein: The forming of source-drain doped regions in the fin structure on both sides of the dummy gate structure includes: removing a portion of the fin structure to form a first opening exposing the top of the substrate; removing a portion of the sacrificial layer in the fin structure along the first opening to form a groove; forming an inner wall layer in the groove, wherein the outer side surface of the inner wall layer is vertically flush with the end surface of the fin structure; An epitaxial process is performed based on the sidewalls of the inner wall layer to form the source and drain doping regions.
10. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: At the same time as the inner wall layer is formed, a gate sidewall is formed on the substrate to cover the sidewall of the dummy gate structure.
11. The method for forming a semiconductor structure according to claim 7, wherein: After forming source and drain doping regions in the fin structures on both sides of the dummy gate structure, the method further includes: An interlayer dielectric layer is formed on both sides of the dummy gate structure, and the top height of the interlayer dielectric layer is flush with the top height of the dummy gate structure.
12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the interlayer dielectric layer on both sides of the dummy gate structure, the method further includes: removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer; After removing the dummy gate structure, the sacrificial layer in the fin structure is removed to form a channel layer with spaced distributions.
13. The method for forming a semiconductor structure according to claim 12, wherein: Before forming a dummy gate structure on the sidewall and top of the isolation structure where the fin structure is exposed, the method further includes: forming a compensation sidewall material layer on the substrate, covering the top of the isolation structure, the sidewalls and the top of the fin structure; When the dummy gate structure is removed and a gate opening is formed in the interlayer dielectric layer, the method further includes: The compensation sidewall material layer is removed to expose the sidewalls and the top of the fin structure.