Preparation method of solar cell grid line, solar cell grid line and solar cell

Abstract

The invention discloses a preparation method of a solar cell grid line, the solar cell grid line and a solar cell. The method comprises the following steps: forming a photoresist layer on the surface of a contact layer of a wafer; forming a plurality of first hollow parts with rectangular sections on the photoresist layer by adopting a photoetching process; etching the contact layer below the first hollow-out part downwards by adopting a wet etching process, forming a plurality of second hollow-out parts on the contact layer, gradually narrowing the section width of the second hollow-out parts from top to bottom, and forming a contact part between two adjacent second hollow-out parts; removing the residual photoresist of the photoresist layer; arranging a mask at the bottom of the second hollow part to obtain a pretreated wafer; metal is deposited on the surface of the pretreated wafer, so that a metal grid line layer is formed on the outer side of the contact part, the mask is removed, the solar cell grid line laid on other functional layers is obtained, the section width of the solar cell grid line is gradually narrowed from bottom to top, the light absorption efficiency is effectively improved, and therefore the photoelectric conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell grid line, a solar cell grid line, and a solar cell. Background Art

[0002] Gallium arsenide (GaAs) solar cells are widely used in high-end fields such as aerospace, concentrated photovoltaics, etc. due to their high photoelectric conversion efficiency, excellent high temperature resistance and radiation resistance, and have become the core photovoltaic devices in these fields.

[0003] The electrode grid lines of traditional GaAs batteries mostly adopt rectangular structures, such as Figure 1 As shown, a rectangular gridline 3 is disposed above the other functional layers 1 of the solar cell, with a rectangular contact layer 2 disposed between the gridlines 3 and the other functional layers 1. When light strikes the cell surface, the rectangular gridlines 3 cause vertical reflection. This vertical reflection causes a significant portion of the incident light to be directly reflected outward, preventing it from being absorbed and utilized again within the cell, resulting in significant light loss.

[0004] Furthermore, conventional screen printing processes, due to technical limitations, struggle to create complex gridline structures, resulting in excessively large light-shielding areas and significant resistance losses. While photolithography can create relatively fine patterns, the resulting patterns after metal evaporation are often rectangular in cross-section, which still fails to effectively address the issue of excessive light-shielding areas.

[0005] Therefore, there is an urgent need to develop a new method for preparing solar cell grid lines. Summary of the Invention

[0006] In view of this, the present invention provides a method for preparing a solar cell grid line, a solar cell grid line, and a solar cell, which are used to solve the problem of high incident light energy loss caused by the vertical reflection characteristics of the grid line in the prior art.

[0007] To achieve one, part, or all of the above objectives or other objectives, a first aspect of the present invention provides a method for preparing a solar cell grid line, the method comprising:

[0008] preparing a wafer, wherein the wafer includes a contact layer and other functional layers stacked from top to bottom;

[0009] coating a photoresist on the surface of the contact layer to form a photoresist layer;

[0010] Using a photolithography process, a preset stripe pattern is transferred to the photoresist layer through a preset mask, and the photoresist in a local area is removed by a development process, thereby forming a plurality of first hollow portions with a rectangular cross-section in the photoresist layer, exposing the contact layer below the first hollow portions;

[0011] The contact layer below the first hollow portion is etched downward using a wet etching process to form a plurality of second hollow portions in the contact layer, wherein the cross-sectional width of the second hollow portions gradually narrows from top to bottom, and contact portions are formed between two adjacent second hollow portions, wherein the cross-sectional width of the contact portions gradually narrows from bottom to top;

[0012] removing the remaining photoresist of the photoresist layer;

[0013] Disposing a mask at the bottom of the second hollow portion to obtain a pre-processed wafer;

[0014] Metal is deposited on the surface of the pre-processed wafer to form a metal grid line layer outside the contact portion, and the mask is removed to obtain the solar cell grid line laid on the other functional layers, wherein the cross-sectional width of the solar cell grid line gradually narrows from bottom to top.

[0015] Furthermore, the step of etching downward the contact layer below the first hollow portion using a wet etching process to form a plurality of second hollow portions in the contact layer includes:

[0016] Prepare an etching solution, the etching solution comprising a mixed acid and a surfactant, wherein the mixed acid comprises phosphoric acid and hydrochloric acid, the surfactant comprises at least one of Triton X-100, tetramethylammonium hydroxide, and ethylenediamine pyrocatechol, the volume ratio of phosphoric acid to hydrochloric acid ranges from 1:2 to 1:4, and the volume ratio of the surfactant to the mixed acid is from 0.1% to 0.5%;

[0017] The wafer with the photoresist removed from a local area is placed in the etching solution to start etching the contact layer below the first hollow portion downwards until the bottom of the contact layer is etched, forming a plurality of second hollow portions in the contact layer.

[0018] Furthermore, the step of placing the wafer after removing the photoresist from a local area into the etching solution to start etching the contact layer below the first hollow portion downward until etching reaches the bottom of the contact layer, thereby forming a plurality of second hollow portions in the contact layer, includes:

[0019] At room temperature, the wafer after removing the photoresist from a local area is placed in an etching solution preheated to 40-50° C., the etching solution is stopped from being heated, and the etching is continued for a first preset time at a stirring speed of 200-300 rpm;

[0020] The stirring speed is adjusted to 100-200 rpm, and etching is continued until the bottom of the contact layer is etched to form a plurality of second hollow portions in the contact layer.

[0021] Furthermore, the step of depositing metal on the surface of the pre-processed wafer to form a metal grid line layer outside the contact portion, removing the mask to obtain the solar cell grid line laid on the other functional layers, wherein the cross-sectional width of the solar cell grid line gradually narrows from bottom to top, includes:

[0022] Performing multi-layer evaporation on the surface of the pre-processed wafer to deposit metal on the outside of the contact portion to form a metal grid line layer with a triangular cross section;

[0023] annealing the metal gate line layer at a preset annealing temperature so that the metal gate line layer outside the contact portion has a smooth transition to form a metal gate line layer with a triangular cross section;

[0024] The mask is removed to obtain the solar cell grid lines laid on the other functional layers, wherein the cross-sectional width of the solar cell grid lines gradually narrows from bottom to top.

[0025] Furthermore, the step of performing multi-layer evaporation on the surface of the pre-processed wafer to deposit metal on the outside of the contact portion to form a metal grid line layer with a triangular cross-section includes:

[0026] Depositing a first metal layer on the outer side of the contact portion at a first evaporation rate and a second preset time on the surface of the pre-processed wafer, wherein the material of the first metal layer is at least one of Ti and Ni, and the deposition thickness of the first metal layer on the top surface of the contact portion is greater than the deposition thickness on the side surface of the contact portion;

[0027] Depositing a second metal layer on the surface of the first metal layer at a second evaporation rate for a third preset time to deposit a second metal layer outside the first metal layer, wherein a material of the second metal layer is at least one of Ag and Au, the second evaporation rate is less than the first evaporation rate, and a deposition thickness of the second metal layer on a top surface of the contact portion is greater than a deposition thickness on a side surface of the contact portion;

[0028] A fourth preset length of time is evaporated on the surface of the second metal layer at a third evaporation rate to deposit a third metal layer on the outside of the second metal layer, the material of the third metal layer is at least one of Ag and Au, the third evaporation rate is greater than the second evaporation rate, and the deposition thickness of the third metal layer on the top surface of the contact portion is greater than the deposition thickness on the side surface of the contact portion.

[0029] Furthermore, the first evaporation rate is The second evaporation rate is The third evaporation rate is

[0030] Furthermore, the thickness of the first metal layer is in the range of 0-50 nm, the thickness of the second metal layer is in the range of 50-300 nm, and the thickness of the third metal layer is in the range of 300-1000 nm.

[0031] Furthermore, the step of annealing the metal gate line layer at a preset annealing temperature includes:

[0032] The metal gate line layer is annealed at a preset annealing temperature of 250 to 350° C. in an inert gas atmosphere for 10 to 30 minutes.

[0033] A second aspect of the present invention provides a solar cell grid line, which is prepared using the above-mentioned method for preparing a solar cell grid line.

[0034] A third aspect of the present invention provides a solar cell comprising other functional layers and the aforementioned solar cell grid lines, wherein a plurality of parallel and spaced solar cell grid lines are arranged above the other functional layers.

[0035] Implementing the embodiments of the present invention will have at least the following beneficial effects:

[0036] The present invention provides a method for preparing a solar cell grid line, a solar cell grid line, and a solar cell. The method comprises the following steps: forming a plurality of first hollow portions with rectangular cross sections on a photoresist layer by a photolithography process, exposing a contact layer below the first hollow portions; then etching the contact layer below the first hollow portions downward by a wet etching process, forming a plurality of second hollow portions in the contact layer, wherein the cross-sectional width of the second hollow portions gradually narrows from top to bottom, forming a contact portion between two adjacent second hollow portions, and the cross-sectional width of the contact portion gradually narrows from bottom to top; then removing the remaining photoresist in the photoresist layer, and A mask is set at the bottom of the second hollow part to obtain a pre-processed wafer; finally, metal is deposited on the surface of the pre-processed wafer to form a metal grid line layer on the outside of the contact part, and the mask is removed to obtain a solar cell grid line laid on other functional layers. The cross-sectional width of the solar cell grid line gradually narrows from bottom to top; the grid line structure finally formed can reflect more incident light into the interior of the battery, reduce the loss of light due to vertical reflection, increase the propagation path and absorption opportunity of light in the solar cell, effectively improve the light absorption efficiency, and thus improve the photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] in:

[0039] Figure 1 A schematic diagram of light reflection of rectangular grid lines in the prior art;

[0040] Figure 2 A flow chart of a method for preparing a solar cell grid line according to an embodiment;

[0041] Figure 3 Schematic diagrams of the various stages of the preparation process of solar cell grid lines in one embodiment; (a) is a schematic diagram of the wafer structure after coating with photoresist, (b) is a schematic diagram of the structure after photolithography of the photoresist layer, (c) is a schematic diagram of the structure after etching the contact layer, (d) is a schematic diagram of the structure after removing the photoresist layer, (e) is a schematic diagram of the structure after setting a mask at the bottom of the second hollow portion, and (f) is a schematic diagram of the structure after evaporation to form a metal grid line layer;

[0042] Figure 4 FIG. 1 is a schematic diagram of light reflection of a solar cell grid line according to an embodiment. DETAILED DESCRIPTION

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this invention belongs. The terms used in the description of the invention herein are for the purpose of describing specific embodiments only and are not intended to limit the invention. The terms "including" and "having" and any variations thereof in the description and claims of the invention and the accompanying drawings are intended to cover non-exclusive inclusions. The terms "first" and "second" in the description and claims of the invention and the accompanying drawings are used to distinguish different objects, not to describe a specific order.

[0044] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0046] Reference Figure 2 , an embodiment of the present invention shows a method for preparing a solar cell grid line, comprising:

[0047] S1: preparing a wafer, wherein the wafer includes a contact layer and other functional layers stacked from top to bottom;

[0048] S2: coating a photoresist on the surface of the contact layer to form a photoresist layer;

[0049] S3: using a photolithography process to transfer a predetermined stripe pattern to the photoresist layer through a predetermined mask, removing the photoresist in a local area through a development process, and forming a plurality of first hollow portions with a rectangular cross-section in the photoresist layer, exposing the contact layer below the first hollow portions;

[0050] S4: etching downward the contact layer below the first hollow portion using a wet etching process to form a plurality of second hollow portions in the contact layer, wherein the cross-sectional width of the second hollow portions gradually narrows from top to bottom, and contact portions are formed between two adjacent second hollow portions, wherein the cross-sectional width of the contact portions gradually narrows from bottom to top;

[0051] S5: removing the remaining photoresist of the photoresist layer;

[0052] S6: Setting a mask at the bottom of the second hollow portion to obtain a pre-processed wafer;

[0053] S7: depositing metal on the surface of the pre-processed wafer to form a metal grid line layer outside the contact portion, removing the mask, and obtaining the solar cell grid line laid on the other functional layers, wherein the cross-sectional width of the solar cell grid line gradually narrows from bottom to top.

[0054] In this embodiment, in the above step S1, the above wafer is a GaAs wafer for solar cell manufacturing, having a multi-layer stacked structure. The top layer is the contact layer 4, which is usually made of a material with good conductivity to form a good ohmic contact between the gate line and the GaAs wafer, reduce the contact resistance, and ensure that the current is efficiently transmitted from the other functional layers 1 to the metal gate line, and then to the battery. Usually, a material with good lattice matching with GaAs and capable of forming a low resistance contact is used, such as a doped GaAs layer, Ga x (InP) 1-x Below the contact layer are other functional layers, including an absorption layer and a buffer layer, which are used to achieve the photovoltaic conversion function of the solar cell. Those skilled in the art can design the materials and thicknesses of each functional layer based on the specific type and performance requirements of the solar cell, and this is not detailed here. After selecting the wafer, it is cleaned using a conventional cleaning process and blown dry in a nitrogen atmosphere to ensure a clean wafer surface.

[0055] In the above step S2, before the photoresist coating is performed, a tackifier such as hexamethyldisilazane (HMDS) is first used to pre-treat the wafer by liquid phase spin coating to improve the adhesion between the wafer and the photoresist. Figure 3 As shown in (a), a photoresist coating operation is performed on the surface of the contact layer 4 after the pretreatment, and a positive photoresist (e.g., linear phenolic resin) is selected for uniform coating, with a uniform coating thickness of 3 to 8 μm. The positive photoresist undergoes chemical changes after exposure, so that the exposed portion can be dissolved and removed during development. A spin coater is used for photoresist coating. During the spin coating process, those skilled in the art can adjust the thickness of the photoresist layer 5 by controlling the viscosity, drop amount, and spin coating parameters of the photoresist, and ensure the uniformity and thickness consistency of the photoresist layer. The specific spin coating process is not described in detail in this invention.

[0056] In the above step S3, a photolithography process is used to cover the photoresist layer 5 with a preset mask, and an exposure method such as contact exposure or proximity exposure is used with an exposure dose of 100 to 500 mJ / cm 2 , set the exposure time according to the photosensitivity of the photoresist, so that the photoresist layer 5 undergoes a photochemical reaction in the light-transmitting area of ​​the mask, changing its solubility. After the exposure is completed, the wafer is placed in a positive photoresist developer (such as tetramethylammonium hydroxide solution, with a concentration of 0.2-0.5%) for development. The development time is 30 to 100 seconds. At this time, the unexposed part of the photoresist will be dissolved and removed by the developer because its solubility has not changed, while the exposed part of the photoresist will remain, thus forming a layer like the photoresist layer. Figure 3 (b) shows a plurality of first hollow portions 51 with rectangular cross sections, while exposing the contact layer below the first hollow portions 51 to serve as etching windows for subsequent etching steps.

[0057] In the above step S4, a wet etching process is used to etch the contact layer below the first hollow portion 51. The wafer with the photoresist pattern is placed in an etching solution, and the etching solution is selected from a solution that can chemically react with the contact layer material, such as a mixed solution of hydrochloric acid and phosphoric acid. Figure 3 As shown in (c), during the etching process, the etching solution starts to etch downward from the upper surface of the contact layer at the bottom of the first hollow portion 51. Due to the difference in etching rate of the etching solution in different directions, the cross-sectional width of the second hollow portion 41 of the contact layer is gradually narrowed from top to bottom. At the same time, a contact portion 42 is formed between the two adjacent second hollow portions 41, and the cross-sectional width of the contact portion 42 is gradually narrowed from bottom to top. By controlling the parameters such as the formula, temperature, and stirring speed of the etching solution, effective control of the shape of the second hollow portion 41 and the contact portion 42 is achieved to form the required grid line infrastructure (i.e., contact portion 42). Compared with the traditional rectangular structure, the trapezoidal structure of the contact portion 42, which gradually widens from top to bottom, can effectively reduce the vertical reflection of light on the side wall of the grid line, so that more light can enter the interior of the battery to be absorbed and utilized, thereby improving light absorption efficiency.

[0058] In the above step S5, if Figure 3As shown in (d), the wafer that has completed wet etching is subjected to photoresist stripping liquid, acetone, isopropyl alcohol and other reagents to remove the photoresist on its surface. For example, it is immersed in acetone solution for about 15 to 30 minutes to fully dissolve the remaining photoresist in the photoresist layer. The wafer is then taken out and repeatedly rinsed with deionized water to remove the residual acetone solution and dissolved photoresist, ensuring that the wafer surface is clean and free of photoresist residue.

[0059] In the above step S6, if Figure 3 As shown in Figure (e), a mask 6 is provided at the bottom of the second hollow portion 41. The mask material can be a photoresist material. The mask layer can be formed on the surface of the pre-processed wafer by spin coating or evaporation. The mask layer is then patterned using a photolithography process to cover only the bottom area of ​​the second hollow portion, leaving the outer surface of the contact portion exposed.

[0060] In the above step S7, if Figure 3 As shown in (f), the pre-treated wafer with the mask 6 is placed in a vacuum coating device, vacuumed, and metal is deposited on the surface of the wafer by electron beam evaporation or magnetron sputtering. During the deposition process, metal atoms will be deposited on the outer surface of the contact portion, and as the deposition time increases, a metal grid line layer 7 is gradually formed. After the deposition is completed, the wafer is taken out of the vacuum coating device, and the mask is removed by chemical stripping to obtain a solar cell grid line laid on top of other functional layers, and the cross-sectional width of the grid line gradually narrows from bottom to top. The grid line of this structure can not only effectively collect the carriers generated by the battery, but also because of its unique shape, such as Figure 4 As shown, when the incident light hits the inclined surface of the metal grid line layer 7 of the solar cell grid line, the light is diffusely reflected by the inclined surface ( Figure 4 Part of the light is guided to the surface of other functional layers 1 for secondary absorption, thus ensuring the carrier collection efficiency while greatly reducing the incident light energy loss and improving the photoelectric conversion efficiency of the solar cell.

[0061] The grid line structure finally formed through the above steps in this embodiment can reflect more incident light into the interior of the battery, reduce the loss of light due to vertical reflection, increase the propagation path and absorption opportunity of light in the solar cell, effectively improve the light absorption efficiency, and thus improve the photoelectric conversion efficiency of the solar cell.

[0062] In one embodiment, the step S4 of etching downward the contact layer below the first hollow portion using a wet etching process to form a plurality of second hollow portions in the contact layer includes:

[0063] S41: preparing an etching solution, wherein the etching solution includes a mixed acid and a surfactant, wherein the mixed acid includes phosphoric acid and hydrochloric acid, the surfactant includes at least one of Triton X-100, tetramethylammonium hydroxide, and ethylenediamine pyrocatechol, the volume ratio of phosphoric acid to hydrochloric acid ranges from 1:2 to 1:4, and the volume ratio of the surfactant to the mixed acid is from 0.1% to 0.5%;

[0064] S42: placing the wafer with the photoresist removed from a local area into the etching solution to start etching downwards the contact layer below the first hollow portion until etching reaches the bottom of the contact layer, thereby forming a plurality of second hollow portions in the contact layer.

[0065] In this embodiment, in step S41, phosphoric acid and hydrochloric acid are mixed in a volume ratio of 1:2 to 1:4, and one or more surfactants selected from Triton X-100, tetramethylammonium hydroxide (TMAH), and ethylenediamine pyrocatechol (EDP) are added at a volume ratio of 0.1% to 0.5%, and stirred at 40 to 50°C to obtain a uniform etching solution. The surfactant is used to enrich in the sidewall region of the etched contact layer during the etching process, forming a physically adsorbed layer to hinder the contact between the etchant and the sidewall material to a certain extent, while also slowing down and regulating the sidewall etching rate through chemical coordination.

[0066] In the above-mentioned steps S42, wafer is placed in etching tank so that wafer is fully immersed in etching solution.In etching process, etching solution begins to etch downwards from the interface of the first hollow portion and contact layer, and because mixed acid and contact layer material chemical reaction occur, contact layer material dissolves gradually, and along with the passage of etching time, etching depth constantly increases.When etching to the bottom of the contact layer, wafer is taken out from etching solution, put into deionized water and clean.Particularly, those skilled in the art can determine suitable etching duration according to multiple experiments, to etch to the bottom of the contact layer, about to carve through the contact layer and form the second hollow portion of expected shape.Through this step, many second hollow portions are formed at the contact layer, due to the synergistic effect of each component in the etching solution, the cross-sectional width of the second hollow portion is gradually narrowed from top to bottom, has realized expected grid line infrastructure.

[0067] In one embodiment, the step S42 of placing the wafer after removing the photoresist from the local area into the etching solution to etch the contact layer below the first hollow portion downward until the bottom of the contact layer is etched to form a plurality of second hollow portions in the contact layer includes:

[0068] S421: placing the wafer after removing the photoresist from the local area into an etching solution preheated to 40-50° C. at room temperature, stopping heating the etching solution, and continuing etching at a stirring speed of 200-300 rpm for a first preset time period;

[0069] S422: adjusting the stirring speed to 100-200 rpm, and continuing etching until etching reaches the bottom of the contact layer, thereby forming a plurality of second hollow portions in the contact layer.

[0070] In this embodiment, in the above step S421, at room temperature (about 25°C), the wafer that has been photolithographically patterned (i.e., the wafer after removing the photoresist in the local area) is placed in an etching tank, and the wafer is immersed in an etching solution that has been preheated to 40-50°C. The external heating of the etching solution is stopped, and the etching reaction is carried out using the residual heat of the etching solution itself. At the same time, the magnetic stirrer is started, and the stirring speed is set to 200-300rpm, so that the etching solution forms a disturbance on the surface of the wafer, reduces product accumulation, and promotes the rapid progress of the etching reaction. This stage continues etching for the first preset time, which is determined according to the initial thickness of the contact layer and the etching rate, for example, it can be 1 minute, 2 minutes, etc. By performing initial etching at a higher temperature (40-50°C) and a faster stirring speed (200-300rpm), the contact layer can be quickly etched vertically.

[0071] In the above step S422, during the reaction process, the temperature of the etching solution gradually drops to 25-30°C, thereby gradually reducing the lateral etching rate of the contact layer. After the first preset time period, the stirring speed is adjusted to 100-200 rpm to slow down the flow intensity of the etching solution. At this time, the temperature of the etching solution gradually decreases due to heat exchange with the environment, and the etching rate slows down accordingly, which is conducive to achieving more precise etching control. As the etching reaction approaches the bottom of the contact layer, the synergistic effect of the mixed acid and the surfactant becomes more prominent: the complexing ability of phosphoric acid prevents over-etching, and the surfactant suppresses the sidewall etching rate, so that the cross-sectional width of the second hollow portion gradually narrows from top to bottom, forming the required inverted trapezoidal structure.

[0072] When etching reaches the bottom of the contact layer (i.e., exposing the interface of the underlying functional layer), the wafer is removed from the etching solution and rinsed in deionized water to terminate the etching reaction. By controlling the stirring speed and etching temperature at a low level, combined with the optimization of the etching selectivity by the surfactant, the resulting second hollow portion has an inverted trapezoidal structure, with the width of the contact portion gradually narrowing from bottom to top to form a positive trapezoidal shape.

[0073] Through the above-mentioned step-by-step etching process, the cross-sectional angle of the second hollow portion (ie, the angle between the sidewall of the second hollow portion and the horizontal plane) can be controlled within the range of 50 to 70°.

[0074] It is understandable that in actual production, those skilled in the art may adjust parameters such as the first preset time, stirring speed and etching temperature according to the specific composition and thickness of the contact layer material.

[0075] In one embodiment, the step S7 of depositing metal on the surface of the pre-processed wafer to form a metal grid line layer outside the contact portion, removing the mask, and obtaining the solar cell grid line laid on the other functional layers, wherein the cross-sectional width of the solar cell grid line gradually narrows from bottom to top, includes:

[0076] S71: performing multi-layer evaporation on the surface of the pre-processed wafer to deposit metal on the outer side of the contact portion to form a metal gate line layer with a triangular cross section;

[0077] S72: performing an annealing process on the metal gate line layer at a preset annealing temperature, so that the metal gate line layer outside the contact portion has a smooth transition, forming a metal gate line layer with a triangular cross section;

[0078] S73: removing the mask to obtain the solar cell grid lines laid on the other functional layers, wherein the cross-sectional width of the solar cell grid lines gradually narrows from bottom to top.

[0079] In this embodiment, in the above step S71, a multi-layer evaporation method is adopted, and each layer of metal is first quickly deposited on the trapezoidal top of the contact part through segmented control, and then slowly covered on the side of the trapezoid, so as to finally form a metal grid line layer with a cross-section close to a triangle.

[0080] In the above step S72, the wafer on which metal deposition is completed is transferred to an annealing furnace protected by nitrogen, and heated to a preset annealing temperature at a heating rate of 5 to 10°C / min for annealing. In a specific embodiment, the step S73 of annealing the metal gate line layer at the preset annealing temperature includes: annealing the metal gate line layer for 10 to 30 minutes at a preset annealing temperature of 250 to 350°C in an inert gas (nitrogen or argon) atmosphere, with a gas flow rate of 5 to 10 L / min and a vacuum degree of 10 to 100 Pa. For example, the temperature is raised to 150°C at a rate of 5°C / min and held for 5 minutes, and then heated at a rate of 10°C / min and held for 5 minutes.

[0081] / min to the target temperature to eliminate thermal stress; maintain at the target temperature for 20 minutes to allow the metal atoms to fully diffuse and recombine; cool to 100℃ at a rate of 8℃ / min, and then cool naturally to room temperature to prevent cracks caused by sudden cooling. For silver grid lines, the annealing temperature is set to 250℃; for gold grid lines, the annealing temperature is set to 300℃. During the annealing process, the metal atoms obtain enough energy to rearrange, so that the roughness of the surface of the metal grid line layer is reduced, the side walls are smoother, and the top of the metal grid line layer is sharpened into a triangle. At the same time, a more stable alloy interface is formed between the metal grid line layer and the contact part, the bottom filling is closed, and the contact resistance is reduced. The annealing time is controlled at 10 to 30 minutes, and then cooled to room temperature at a rate of 3 to 5℃ / min. Through the annealing treatment, the cross-sectional shape of the solar cell grid line is further optimized from a quasi-triangle to an ideal isosceles triangle structure. Preferably, the angle range of the vertex angle of the isosceles triangle is controlled to be 50 to 70 degrees. The size of the solar cell grid line can be specifically measured by a microscope in the prior art (such as a SEM scanning electron microscope, etc.), which will not be described in detail in the present invention.

[0082] In the above step S73, the mask at the bottom of the second hollow portion is removed. The wafer is immersed in a special photoresist stripping solution and ultrasonically treated for 5 to 10 minutes to completely dissolve the mask material. The wafer is then repeatedly rinsed with deionized water to remove the residual stripping solution and the dissolved mask material. At this time, the metal layer at the bottom of the second hollow portion is removed together with the mask, while the metal grid line layer outside the contact portion is completely retained, and finally a solar cell grid line (including the metal grid line layer and the contact portion) is formed on top of the other functional layers. The cross-sectional width of the grid line gradually narrows from bottom to top, forming an ideal isosceles triangle structure, and the bottom is tightly combined with the contact portion, thereby ensuring good current collection efficiency.

[0083] The solar cell grid lines prepared in this embodiment have a narrow top structure that effectively reduces obstruction of incident light, and the inclined sidewalls can guide light to be reflected to other functional layers for secondary absorption, thereby improving light utilization. Furthermore, compared to traditional rectangular cross-section grid lines, the triangular cross-section solar cell grid lines of this application increase the contact area between the metal grid line layer and the contact layer, thereby effectively reducing contact resistance and optimizing solar cell performance.

[0084] Taking the rectangular cross-section gate line and the triangular cross-section gate line with the same base width w and gate line length L as an example, the contact resistance of the two is compared. c =ρ / A, where ρ is the contact resistivity and A is the effective contact area.

[0085] For traditional rectangular grid lines, the contact area A1 = w*L;

[0086] For triangular cross-section grid lines, the contact area Where h is the height of the triangle.

[0087] It can be seen that A2>A1, the contact area A of the solar cell grid line and other functional layers increases, and the contact resistance R c Reduced, that is, the contact resistance of the triangular cross-section grid line of this embodiment is smaller than that of the conventional rectangular grid line in the prior art, and the photoelectric conversion efficiency of the solar cell using the triangular cross-section grid line of this embodiment is greatly improved.

[0088] In addition, when h is higher, that is, the triangle angle is smaller, the contact area A2 is larger and the contact resistance R c However, too small a vertex angle makes processing more difficult and may also introduce etching impurities. Therefore, in order to balance the contact resistance optimization and process difficulty, the vertex angle of the prepared triangular cross-section gate line can be preferably set to 50-70°.

[0089] In one embodiment, the step S72 of performing multi-layer evaporation on the surface of the pre-processed wafer to deposit metal on the outside of the contact portion to form a metal gate line layer with a triangular cross-section includes:

[0090] S721: Vapor-depositing a first metal layer on the surface of the pre-processed wafer at a first evaporation rate for a second preset time to deposit a first metal layer on the outer side of the contact portion, wherein the material of the first metal layer is at least one of Ti and Ni, and the deposition thickness of the first metal layer on the top surface of the contact portion is greater than the deposition thickness on the side surface of the contact portion;

[0091] S722: Vapor-depositing a second metal layer on the surface of the first metal layer at a second evaporation rate for a third preset time to deposit a second metal layer outside the first metal layer, wherein a material of the second metal layer is at least one of Ag and Au, the second evaporation rate is less than the first evaporation rate, and a deposition thickness of the second metal layer on the top surface of the contact portion is greater than a deposition thickness on the side surface of the contact portion;

[0092] S723: Evaporating the surface of the second metal layer at a third evaporation rate for a fourth preset time to deposit a third metal layer on the outside of the second metal layer, wherein the material of the third metal layer is at least one of Ag and Au, the third evaporation rate is greater than the second evaporation rate, and the deposition thickness of the third metal layer on the top surface of the contact portion is greater than the deposition thickness on the side surface of the contact portion.

[0093] In one embodiment, the first evaporation rate is The second evaporation rate is The third evaporation rate is

[0094] In one embodiment, the thickness of the first metal layer is in the range of 0-50 nm, the thickness of the second metal layer is in the range of 50-300 nm, and the thickness of the third metal layer is in the range of 300-1000 nm.

[0095] In this embodiment, in the above-mentioned step S721, the above-mentioned second preset duration can be adjusted according to the target thickness, for example, set to 1 to 10 seconds, and a first metal layer with a thickness of 30 to 50 nm and a side thickness of 0 to 20 nm, preferably 10 to 20 nm, is formed on the top surface of the contact portion, and Ti, Ni, etc. form compressive stress with the contact layer. The faster evaporation rate causes metal atoms such as Ti / Ni to be preferentially deposited on the top surface area of ​​the contact portion. From the top of the contact portion to the side bottom edge of the contact portion, the thickness of the first metal layer gradually decreases, thereby increasing the angle between the side wall and the bottom surface of the gate line. In some optional embodiments, you can choose not to implement the above-mentioned step S721 (i.e., set the second preset duration to 0 seconds), and directly deposit the second metal layer, the third metal layer, etc. on the outside of the contact portion.

[0096] In the above-mentioned step S722, the above-mentioned third preset time length can be adjusted according to the target thickness, for example, set to 500 to 750 seconds. The lower second evaporation rate allows metal to be deposited on the top surface of the contact part while a certain thickness of metal is also deposited on the side. The thickness of the second metal layer gradually decreases from the top of the contact part to the bottom edge of the side of the contact part.

[0097] In the above step S723, the above fourth preset time length can be adjusted according to the target thickness, for example, set to 500 to 1000 seconds. The higher third evaporation rate allows the top of the contact portion to continue to accumulate preferentially, and the thickness of the third metal layer gradually decreases from the top of the contact portion to the side bottom edge of the contact portion. The width of the top of the gate line gradually narrows to form a triangular upper half, thereby forming a metal gate line layer with a triangular cross-section.

[0098] Through the multi-layer evaporation process, a triangular metal grid line with a sidewall inclination angle of 50° to 80° can be prepared, meeting the requirements of high-performance solar cells for low shading rate, high conductivity and long-term stability of the grid line.

[0099] In a specific embodiment, the process parameters of S721-S723 are set as follows:

[0100] Made of Ti, The first evaporation rate is 10 seconds, and the first metal layer is deposited; the material Ag is used, The second evaporation rate is 600 seconds, and the second metal layer is deposited; the material Ag is used, The third evaporation rate is 500 seconds, and the third metal layer is deposited; finally, a solar cell grid line with a triangular cross-sectional structure and a sidewall inclination angle of about 60° is obtained (the solar cell grid line includes a contact portion and a deposited multi-layer metal grid line layer).

[0101] The present invention further provides a solar cell grid line, characterized in that it is prepared using the method for preparing a solar cell grid line of any of the above embodiments.

[0102] The solar cell gridlines fabricated in the embodiments of the present invention form a unique structure with a cross-sectional width that gradually narrows from bottom to top. This structure reflects more incident light into the cell, reducing light loss due to vertical reflection, increasing the propagation path and absorption opportunities of light within the solar cell, effectively improving light absorption efficiency and thus the photovoltaic conversion efficiency of the solar cell. A good electrical contact interface is formed between the metal gridline layer and the contact layer. After annealing, an alloyed interface is formed between the metal gridline and the contact layer, significantly reducing contact resistance, effectively improving carrier collection efficiency and reducing energy loss.

[0103] The present invention further provides a solar cell comprising other functional layers and the solar cell grid lines of the aforementioned embodiment, wherein a plurality of parallel and spaced solar cell grid lines are arranged above the other functional layers.

[0104] The solar cell of this embodiment adopts the aforementioned solar cell grid lines. The reduction of the shading area increases light absorption, and the grid lines with low contact resistance and high conductivity improve the carrier collection efficiency, thereby significantly improving the photoelectric conversion efficiency.

[0105] Obviously, the embodiments described above are only some embodiments of the present invention, rather than all embodiments. The preferred embodiments of the present invention are given in the accompanying drawings, but they do not limit the patent scope of the present invention. The present invention can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive. Although the present invention has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned specific embodiments, or to make equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the present invention specification and drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present invention.

Claims

1. A method for preparing a solar cell grid line, characterized in that: The preparation method comprises: preparing a wafer, wherein the wafer includes a contact layer and other functional layers stacked from top to bottom; coating a photoresist on the surface of the contact layer to form a photoresist layer; Using a photolithography process, a preset stripe pattern is transferred to the photoresist layer through a preset mask, and the photoresist in a local area is removed by a development process, thereby forming a plurality of first hollow portions with a rectangular cross-section in the photoresist layer, exposing the contact layer below the first hollow portions; The contact layer below the first hollow portion is etched downward using a wet etching process to form a plurality of second hollow portions in the contact layer, wherein the cross-sectional width of the second hollow portions gradually narrows from top to bottom, and contact portions are formed between two adjacent second hollow portions, wherein the cross-sectional width of the contact portions gradually narrows from bottom to top; removing the remaining photoresist of the photoresist layer; Disposing a mask at the bottom of the second hollow portion to obtain a pre-processed wafer; Metal is deposited on the surface of the pre-processed wafer to form a metal grid line layer outside the contact portion, and the mask is removed to obtain the solar cell grid line laid on the other functional layers, wherein the cross-sectional width of the solar cell grid line gradually narrows from bottom to top.

2. The method for preparing a solar cell grid line according to claim 1, wherein: The step of etching downward the contact layer below the first hollow portion using a wet etching process to form a plurality of second hollow portions in the contact layer includes: Prepare an etching solution, the etching solution comprising a mixed acid and a surfactant, wherein the mixed acid comprises phosphoric acid and hydrochloric acid, the surfactant comprises at least one of Triton X-100, tetramethylammonium hydroxide, and ethylenediamine pyrocatechol, the volume ratio of phosphoric acid to hydrochloric acid ranges from 1:2 to 1:4, and the volume ratio of the surfactant to the mixed acid is from 0.1% to 0.5%; The wafer with the photoresist removed from a local area is placed in the etching solution to start etching the contact layer below the first hollow portion downwards until the bottom of the contact layer is etched, forming a plurality of second hollow portions in the contact layer.

3. The method for preparing a solar cell grid line according to claim 2, wherein: The step of placing the wafer after removing the photoresist from a local area into the etching solution to begin etching the contact layer below the first hollow portion downward until etching reaches the bottom of the contact layer, thereby forming a plurality of second hollow portions in the contact layer, includes: At room temperature, the wafer after removing the photoresist from a local area is placed in an etching solution preheated to 40-50° C., the etching solution is stopped from being heated, and the etching is continued for a first preset time at a stirring speed of 200-300 rpm; The stirring speed is adjusted to 100-200 rpm, and etching is continued until the bottom of the contact layer is etched to form a plurality of second hollow portions in the contact layer.

4. The method for preparing a solar cell grid line according to claim 1, wherein: The steps of depositing metal on the surface of the pre-processed wafer to form a metal grid line layer outside the contact portion, removing the mask to obtain the solar cell grid line laid on the other functional layers, wherein the cross-sectional width of the solar cell grid line gradually narrows from bottom to top, include: Performing multi-layer evaporation on the surface of the pre-processed wafer to deposit metal on the outside of the contact portion to form a metal grid line layer with a triangular cross section; annealing the metal gate line layer at a preset annealing temperature so that the metal gate line layer outside the contact portion has a smooth transition to form a metal gate line layer with a triangular cross section; The mask is removed to obtain the solar cell grid lines laid on the other functional layers, wherein the cross-sectional width of the solar cell grid lines gradually narrows from bottom to top.

5. The method for preparing a solar cell grid line according to claim 4, wherein: The step of performing multi-layer evaporation on the surface of the pre-processed wafer to deposit metal on the outside of the contact portion to form a metal grid line layer with a triangular cross-section includes: Depositing a first metal layer on the outer side of the contact portion at a first evaporation rate and a second preset time on the surface of the pre-processed wafer, wherein the material of the first metal layer is at least one of Ti and Ni, and the deposition thickness of the first metal layer on the top surface of the contact portion is greater than the deposition thickness on the side surface of the contact portion; Depositing a second metal layer on the surface of the first metal layer at a second evaporation rate for a third preset time to deposit a second metal layer outside the first metal layer, wherein a material of the second metal layer is at least one of Ag and Au, the second evaporation rate is less than the first evaporation rate, and a deposition thickness of the second metal layer on a top surface of the contact portion is greater than a deposition thickness on a side surface of the contact portion; A fourth preset length of time is evaporated on the surface of the second metal layer at a third evaporation rate to deposit a third metal layer on the outside of the second metal layer, the material of the third metal layer is at least one of Ag and Au, the third evaporation rate is greater than the second evaporation rate, and the deposition thickness of the third metal layer on the top surface of the contact portion is greater than the deposition thickness on the side surface of the contact portion.

6. The method for preparing a solar cell grid line according to claim 5, wherein: The first evaporation rate is The second evaporation rate is The third evaporation rate is 7. The method for preparing a solar cell grid line according to claim 5, wherein: The thickness of the first metal layer is in the range of 0-50 nm, the thickness of the second metal layer is in the range of 50-300 nm, and the thickness of the third metal layer is in the range of 300-1000 nm.

8. The method for preparing a solar cell grid line according to claim 5, wherein: The step of annealing the metal gate line layer at a preset annealing temperature includes: The metal gate line layer is annealed at a preset annealing temperature of 250 to 350° C. in an inert gas atmosphere for 10 to 30 minutes.

9. A solar cell grid line, characterized in that: The solar cell grid line is prepared by the method for preparing the solar cell grid line according to any one of claims 1 to 8.

10. A solar cell, characterized in that: The solar cell grid line comprises other functional layers and the solar cell grid line according to claim 9, wherein a plurality of parallel and spaced solar cell grid lines are arranged above the other functional layers.

Images