Dual-firmware operation method of single-core MCU, electronic equipment and storage medium
By dividing Flash and SRAM spaces on a single-core MCU, running the two program firmware independently, and implementing calls through interrupt handling functions, the problem that a single-core MCU cannot be independently developed and debugged is solved, and independent development and debugging is achieved while reducing costs and improving security.
Patent Information
- Application Number
- CN202510691572.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-27
- Publication Date
- 2025-09-02
AI Technical Summary
In the prior art, single-core MCUs cannot realize independent development and debugging of algorithms and applications, and the security of library files is weak, and using dual-core MCUs is costly and difficult to develop.
Through automated programs, the MCU's Flash and SRAM are divided into independent spaces, and the two program firmwares are run respectively, and function calls and data sharing are realized through interrupt processing functions to ensure independence and security.
Independent development and debugging of algorithms and applications is implemented on single-core MCUs, reducing maintenance difficulties, reducing costs, and maintaining security.
Smart Images
Figure CN120578428A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a dual-firmware operation method for a single-core MCU, an electronic device, and a storage medium. Background Art
[0002] An MCU (Microcontroller Unit) is a small computer system integrated on a single chip, commonly used in embedded systems and IoT devices. As a highly integrated chip, an MCU integrates multiple functional modules, including a CPU, memory, input / output interfaces, and peripherals.
[0003] Single-core MCUs typically only run one program firmware, while multi-core MCUs can run their own program firmware on each core. For products involving core algorithms, the development of the algorithm and application is often undertaken by different departments, and the core algorithm must be kept confidential from other departments. In related technologies, there are two solutions: The first is to encapsulate the algorithm into a library, and the application calls the library function. However, the disadvantage of this solution is that the algorithm and application are fully integrated, and independent development and debugging cannot be achieved. If a problem is discovered after-sales, both need to be upgraded as a whole. In addition, library files usually contain symbolic information, and their security is weaker than that of binary files. The second solution is to use a dual-core MCU, with one core running the algorithm and the other running the application. However, this solution not only significantly increases the cost, but also increases the development difficulty compared to a single-core MCU. Summary of the Invention
[0004] The present invention provides a dual-firmware operation method for a single-core MCU, an electronic device, and a storage medium, aiming to solve at least one of the technical problems existing in the prior art.
[0005] The technical solution of the present invention is a dual-firmware operation method for a single-core MCU, comprising:
[0006] Determine, by an automated program, a first storage space size of a Flash memory of the MCU, a second storage space size occupied by the first program firmware, and a third storage space size occupied by the second program firmware; and divide the Flash memory into a first Flash space for the first program firmware and a second Flash space for the second program firmware based on the first storage space size, the second storage space size, and the third storage space size;
[0007] Determine a fourth storage space size of the SRAM of the MCU, a first operating data size of the first program firmware, and a second operating data size of the second program firmware; and divide the SRAM into a first used space of the first program firmware, a second used space of the second program firmware, and a third shared space shared by the first program firmware and the second program firmware according to the fourth storage space size, the first operating data size, and the second operating data size;
[0008] The first program firmware and the second program firmware are controlled to run on the MCU.
[0009] According to some embodiments of the present invention, dividing the SRAM into a first usage space of the first program firmware, a second usage space of the second program firmware, and a third shared space shared by the first program firmware and the second program firmware includes:
[0010] The first running data of the first program firmware is compiled at the first SRAM address of the SRAM and the first SRAM address is used when the first program firmware is running, the second running data of the second program firmware is compiled at the second SRAM address of the SRAM and the second SRAM address is used when the second program firmware is running, and the third running data common to the first program firmware and the second program firmware is compiled at the third SRAM address of the SRAM and the third SRAM address is used when the first program firmware and the second program firmware communicate, so that the SRAM is divided into the first usage space, the second usage space and the third shared space.
[0011] According to some embodiments of the present invention, dividing the Flash into a first Flash space for the first program firmware and a second Flash space for the second program firmware includes:
[0012] The first program firmware is compiled at a first Flash address of the Flash and burned to the first Flash address, and the second program firmware is compiled at a second Flash address of the Flash and burned to the second Flash address, so that the Flash is divided into the first Flash space and the second Flash space.
[0013] According to some embodiments of the present invention, controlling the first program firmware and the second program firmware to run on the MCU includes:
[0014] When the first program firmware and the second program firmware are respectively run separately on the MCU, mapping the first vector table of the first program firmware to the first Flash address, initializing the first device used by the first main program of the first program firmware to run, and running the first main program to execute application-related services;
[0015] Mapping the second vector table of the second program firmware to the second Flash address, initializing the second device used when the second main program of the second program firmware runs, and running the second main program to execute algorithm-related services.
[0016] According to some embodiments of the present invention, controlling the first program firmware and the second program firmware to run on the MCU includes:
[0017] When the first program firmware and the second program firmware are run in parallel on the MCU, in the second program firmware, encapsulating the target function of the second program firmware into a function interface;
[0018] Relocating the first vector table of the first program firmware to the first Flash address, initializing a first device used when a first main program of the first program firmware runs, and running the first main program;
[0019] When the program reaches an interrupt processing function in the first main program, the function interface is called through a jump function in the interrupt processing function to execute the target function;
[0020] After the interrupt processing function is finished running, the first main program continues to run.
[0021] According to some embodiments of the present invention, calling the function interface to execute the target function through a jump function in the interrupt handling function, and continuing to run the first main program after the interrupt handling function ends, includes:
[0022] Pushing the current CPU operating environment of the first program firmware into the stack and saving it;
[0023] Setting a target function address of the second program firmware and target function parameters of the second program firmware;
[0024] Based on the target function address and the target function parameters, use the jump function in the interrupt handling function to jump to the target function address to call the function interface, and control the CPU to fetch and execute the target function from the target function address;
[0025] After the interrupt processing function is finished running, it jumps back to the first program firmware, pops the stack to restore the CPU running environment before the jump, and continues to run the first main program.
[0026] According to some embodiments of the present invention, controlling the CPU to fetch and execute the target function from the target function address includes:
[0027] The CPU is controlled to obtain the instruction code of the target function from the target function address in the second Flash space, decode the instruction code, and execute the instruction.
[0028] The technical solution of the present invention also relates to an electronic device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the dual-firmware operation method of a single-core MCU as described above.
[0029] The technical solution of the present invention also relates to a storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the dual-firmware operation method of the single-core MCU as described above is implemented.
[0030] The beneficial effects of the present invention include: determining the first storage space size of the MCU's Flash, the second storage space size occupied by the first program firmware, and the third storage space size occupied by the second program firmware through an automated program; dividing the Flash into the first Flash space of the first program firmware and the second Flash space of the second program firmware according to the first storage space size, the second storage space size, and the third storage space size; then determining the fourth storage space size of the MCU's SRAM, the first running data size of the first program firmware, and the second running data size of the second program firmware; dividing the SRAM into the first use space of the first program firmware, the second use space of the second program firmware, and the third shared space shared by the first program firmware and the second program firmware according to the fourth storage space size, the first running data size, and the second running data size; and controlling the first program firmware and the second program firmware to run on the MCU. Using two program firmwares on a single-core MCU, if defects are found in the application or algorithm program during the product life cycle, only the defective program firmware needs to be updated separately, which reduces the maintenance difficulty. In addition, the dual-firmware operation method of the single-core MCU reduces costs compared to the multi-core MCU.
[0031] In addition, additional aspects and advantages of the present invention will be set forth in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1This is an optional flowchart of a dual-firmware operation method for a single-core MCU in an embodiment of the present invention.
[0033] Figure 2 This is a schematic diagram of Flash space division in an embodiment of the present invention.
[0034] Figure 3 Schematic diagram of SRAM space division in an embodiment of the present invention.
[0035] Figure 4 1 is a schematic diagram of the first program firmware and the second program firmware running separately on the MCU in an embodiment of the present invention.
[0036] Figure 5 Schematic diagram of the first program firmware and the second program firmware running in parallel on the MCU in an embodiment of the present invention.
[0037] Figure 6 It is a schematic diagram of the operation of the interrupt processing function in an embodiment of the present invention. DETAILED DESCRIPTION
[0038] The following will be combined with the embodiments and drawings to clearly and completely describe the concept, specific structure and technical effects of the present invention so as to fully understand the purpose, scheme and effect of the present invention. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other unless there is a conflict.
[0039] It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, terms such as "upper," "lower," "left," "right," "top," and "bottom" used in this disclosure are intended solely to describe the relative positions of the components of the disclosure as shown in the accompanying drawings.
[0040] In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. The terms used in this specification are only for describing specific embodiments and are not intended to limit the present invention. The term "and / or" as used herein includes any combination of one or more of the related listed items.
[0041] It should be understood that although the terms first, second, third, etc. may be used to describe various elements in the present invention, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, a first element may also be referred to as a second element, and similarly, a second element may also be referred to as a first element without departing from the scope of the present invention.
[0042] Reference Figures 1 to 6In some embodiments, the technical solution of the present invention is a dual-firmware operation method for a single-core MCU, including but not limited to steps S101 to S103. Each step is introduced in turn below.
[0043] Step S101: Determine the first storage space size of the MCU's Flash, the second storage space size occupied by the first program firmware, and the third storage space size occupied by the second program firmware through an automated program, and divide the Flash into the first Flash space of the first program firmware and the second Flash space of the second program firmware according to the first storage space size, the second storage space size, and the third storage space size.
[0044] Specifically, an automation program is a software tool that automatically executes a series of predefined tasks or operations without human intervention. Firmware is software embedded in a hardware device that controls its operation and functionality. Flash memory is the non-volatile memory of a single-core MCU, used to permanently store program code (firmware), constant data (such as strings and lookup tables), and read-only configuration parameters.
[0045] In a specific embodiment, a dual-firmware operation method of a single-core MCU of the present invention is implemented through a script.
[0046] Step S102: Determine the fourth storage space size of the MCU's SRAM, the first operating data size of the first program firmware, and the second operating data size of the second program firmware. According to the fourth storage space size, the first operating data size, and the second operating data size, divide the SRAM into a first usage space for the first program firmware, a second usage space for the second program firmware, and a third shared space for the first program firmware and the second program firmware.
[0047] Specifically, SRAM is a volatile memory of a single-core MCU, used to store runtime data (variables, stacks, buffers).
[0048] It should be understood that the first program firmware and the second program firmware communicate with each other through the third shared space.
[0049] In some embodiments, dividing the SRAM into a first usage space for the first program firmware, a second usage space for the second program firmware, and a third shared space for the first program firmware and the second program firmware includes:
[0050] The first running data of the first program firmware is compiled at the first SRAM address of the SRAM and the first SRAM address is used when the first program firmware is running, the second running data of the second program firmware is compiled at the second SRAM address of the SRAM and the second SRAM address is used when the second program firmware is running, and the third running data common to the first program firmware and the second program firmware is compiled at the third SRAM address of the SRAM and the third SRAM address is used when the first program firmware and the second program firmware communicate, so that the SRAM is divided into a first usage space, a second usage space and a third shared space.
[0051] In some embodiments, dividing the Flash into a first Flash space for the first program firmware and a second Flash space for the second program firmware includes:
[0052] The first program firmware is compiled at a first Flash address of the Flash and burned to the first Flash address, and the second program firmware is compiled at a second Flash address of the Flash and burned to the second Flash address, so that the Flash is divided into a first Flash space and a second Flash space.
[0053] It should be noted that independent Flash spaces, namely the first Flash space and the second Flash space, are allocated to the first program firmware and the second program firmware. The first program firmware can only use the first Flash space, and the second program firmware can only use the second Flash space. The SRAM is divided into three parts, namely the first usage space, the second usage space, and the third shared space. The first program firmware can only use the first usage space and the third shared space, and the second program firmware can only use the second usage space and the third shared space. The third shared space is used to store variables used by both the first program firmware and the second program firmware.
[0054] Reference Figure 2 , Firmware.bin is the first program firmware, Algo.bin is the second program firmware, 0x08000000 is the first Flash address, and 0x08020000 is the second Flash address. A 128KByte space starting at 0x08000000 is allocated to the first program firmware, and a 128KByte space starting at 0x08020000 is allocated to the second program firmware. These are just example data; the specific first Flash address, second Flash address, second storage space size, and third storage space size are determined based on actual conditions.
[0055] Reference Figure 3, Firmware.bin is the first program firmware, Algo.bin is the second program firmware, ShareMemony is the third shared space, 0x20000000 is the first SRAM address, 0x20004000 is the second SRAM address, and Max_size-0x800 is the third SRAM address. These are just example data. The specific first SRAM address, second SRAM address, third SRAM address, first running data size, and second running data size are determined according to actual conditions.
[0056] Step S103: Control the first program firmware and the second program firmware to run on the MCU.
[0057] In some embodiments, controlling the first program firmware and the second program firmware to run on the MCU includes:
[0058] When the first program firmware and the second program firmware are respectively run separately on the MCU, mapping the first vector table of the first program firmware to the first Flash address, initializing the first device used by the first main program of the first program firmware to run, and running the first main program to execute application-related services;
[0059] The second vector table of the second program firmware is mapped to the second Flash address, the second device used when the second main program of the second program firmware is run is initialized, and the second main program is run to execute algorithm-related services.
[0060] It should be noted that the first program firmware and the second program firmware are respectively run independently on the MCU, which means that the first program firmware and the second program firmware are independently compiled and independently run on the same MCU.
[0061] Specifically, when the first program firmware and the second program firmware are run separately on the MCU, no mutual function calls or data sharing occurs between the first program firmware and the second program firmware. A vector table is a data structure typically used to store a set of pointers to specific functions or data.
[0062] Reference Figure 4 , Firmware 1 represents the first program firmware, and Firmware 2 represents the second program firmware. Figure 2The Flash partition is divided into two parts, and the first program firmware is compiled at 0x08000000 of Flash and burned to the address 0x08000000. When the first program firmware starts running, the first vector table of the first program firmware is mapped to 0x08000000 (that is, the aforementioned first Flash address), the first device used when the first main program of the first program firmware is run is initialized, and the first main program is run to execute application-related services. The second program firmware is compiled at 0x08020000 of Flash and burned to the address 0x08020000. When the second program firmware starts running, the second vector table of the second program firmware is mapped to 0x08020000 (that is, the aforementioned second Flash address), the second device used when the second main program of the second program firmware is run is initialized, and the second main program is run to execute algorithm-related services.
[0063] Reference Figure 4 When the first program firmware and the second program firmware are respectively run separately on the MCU, in the first main program, when running to the interrupt processing function in the first main program, the target function of the first program firmware is called through the jump function in the interrupt processing function to execute the target function of the first program firmware. In the second main program, when running to the interrupt processing function in the second main program, the target function of the second program firmware is called through the jump function in the interrupt processing function to execute the target function of the second program firmware.
[0064] In some embodiments, controlling the first program firmware and the second program firmware to run on the MCU includes:
[0065] When the first program firmware and the second program firmware are run in parallel on the MCU, in the second program firmware, the target function of the second program firmware is encapsulated into a function interface;
[0066] Relocating a first vector table of the first program firmware to a first Flash address, initializing a first device used when a first main program of the first program firmware runs, and running the first main program;
[0067] When the program reaches the interrupt processing function in the first main program, the function interface is called through the jump function in the interrupt processing function to execute the target function;
[0068] After the interrupt handling function is finished, the first main program continues to run.
[0069] It should be noted that the first program firmware and the second program firmware run in parallel on the MCU, which means that the first program firmware and the second program firmware run on the same MCU at the same time.
[0070] Specifically, when the first program firmware and the second program firmware run in parallel on the MCU, there are function calls and data sharing between the first program firmware and the second program firmware. The interrupt processing function (ISR, Interrupt Service Routine) is a code segment specifically used to respond to interrupt events. When an interrupt occurs, the CPU automatically jumps to the ISR for execution and returns to the main program after the processing is completed. The jump function (Jump Function) is a function or instruction used to change the program execution flow in programming. It allows the program to jump from the current execution location to another location to continue execution. The Central Processing Unit (CPU) is the computing and control core of the computer system and is the final execution unit for information processing and program execution.
[0071] Reference Figure 5 , Firmware 1 represents the first program firmware, and Firmware 2 represents the second program firmware. Figure 2 The first program firmware is compiled into Flash at 0x08000000 and burned to address 0x08000000, while the second program firmware is compiled into Flash at 0x08020000 and burned to address 0x08020000. When the interrupt handling function in the first main program is executed, the function interface of the second program firmware, such as API2_A, API2_B, and API2_C, is called. After power-on, the first program firmware starts running, relocating the first vector table of the first program firmware to 0x08000000, initializing the first device used by the first main program of the first program firmware, and running the first main program. The second program firmware does not actively run, that is, the code such as the second vector table relocation, second device initialization, and second main program of the second program firmware does not actively run. The second program firmware will only execute the corresponding function when the first program firmware jumps to the API2_A, API2_B, and API2_C functions through the jump function. After execution, it returns to the first program firmware to continue executing the code below the first main program.
[0072] Reference Figure 5 , 0x0802xxxx means that in the first main program, by calling the address where the function is located, the API2_A function, API2_B function and API2_C function of the second program firmware are called.
[0073] Reference Figure 6 Since the second program firmware will not perform the second vector table relocation, if there is a target function in the second program firmware, such as the INT2_A function, which needs to be executed in the interrupt handling function, the target function needs to be encapsulated into a function interface and then executed through the jump function of the interrupt handling function of the first program firmware.
[0074] In some embodiments, calling a function interface through a jump function in an interrupt handling function to execute a target function, and continuing to run the first main program after the interrupt handling function is finished, includes:
[0075] Pushing the current CPU operating environment of the first program firmware into the stack and saving it;
[0076] Setting the target function address of the second program firmware and the target function parameters of the second program firmware;
[0077] Based on the target function address and target function parameters, the jump function in the interrupt handling function is used to jump to the target function address to call the function interface, and the CPU is controlled to fetch and execute the target function from the target function address;
[0078] After the interrupt processing function is finished running, it jumps back to the first program firmware, pops the stack to restore the CPU running environment before the jump, and continues to run the first main program.
[0079] Specifically, the fetch-execute cycle is a fundamental concept in computer science that describes the process by which a computer's central processing unit (CPU) executes program instructions. This process, often referred to as an instruction cycle, is the basic unit of CPU operation. The fetch-execute process consists of two main phases: fetch and execute.
[0080] In some embodiments, controlling the CPU to fetch and execute the target function from the target function address includes:
[0081] The control CPU obtains the instruction code of the target function from the target function address in the second Flash space, decodes the instruction code, and executes the instruction.
[0082] In a specific embodiment, an absolute jump instruction BLX is used to jump to the target function address of the second program firmware. BLX (Branch with Link and Exchange) is an instruction in the ARM assembly language that is used to implement a jump and save a return address, while switching the operating state of the processor.
[0083] Specifically, on the same MCU, independent Flash spaces are allocated for the first program firmware and the second program firmware, namely, a first Flash space and a second Flash space. Independent SRAM spaces are allocated for the first program firmware and the second program firmware on the same MCU, namely, a first usable space, a second usable space, and a third shared space. An absolute address is assigned to the functions and variables called by the first program firmware, and an absolute jump instruction is used to jump to the specified address to execute the function. After execution, a return instruction is used to return.
[0084] It is understandable that the advantages of using two program firmwares on a single-core MCU are: each department develops its own program firmware and burns it to its own Flash address without interfering with each other, and the core algorithm can be kept confidential; during the product life cycle, if defects are found in the application or algorithm program, only the defective program firmware needs to be updated separately; it has a higher cost advantage than using a multi-core MCU.
[0085] It's understandable that running two firmware programs in parallel on a single-core MCU, each with its own independent Flash and SRAM memory, prevents interference. The two firmware programs can be compiled, burned, run, and debugged independently, or run in parallel and debugged together. Custom communication methods between the two firmware programs allow each to call the other's functions and share data.
[0086] In a specific embodiment, Flash is used to store program code, and SRAM is used to store program variables. The first program firmware and the second program firmware are both composed of program code and program variables, so independent flash space and SRAM space are allocated to the first program firmware and the second program firmware respectively. Because the first program firmware and the second program firmware need to communicate with each other, a shared space is divided for the first program firmware and the second program firmware to use simultaneously. For example, the first program firmware has a variable self_var1 located at address 0x20000004, and only the first program firmware can use the variable self_var1; the second program firmware has a variable self_var2 located at address 0x20004008, and only the second program firmware can use the variable self_var2; the shared variable share_var is located at address 0x20007CE0, and both the first program firmware and the second program firmware can read and write the shared variable share_var.
[0087] In a specific embodiment, the initialization of the first device and the second device is clock initialization, as well as initialization of devices such as a serial port, a timer, and an analog-to-digital converter that will be used in the program.
[0088] In a specific embodiment, in the first main program and the second main program, after an interrupt occurs, the main program task will be suspended to execute the interrupt handling function.
[0089] As can be seen, through the automated program, the first storage space size of the MCU's Flash, the second storage space size occupied by the first program firmware, and the third storage space size occupied by the second program firmware are determined. Based on the first storage space size, the second storage space size, and the third storage space size, the Flash is divided into the first Flash space of the first program firmware and the second Flash space of the second program firmware. The fourth storage space size of the MCU's SRAM, the first operating data size of the first program firmware and the second operating data size of the second program firmware are determined. Based on the fourth storage space size, the first operating data size, and the second operating data size, the SRAM is divided into the first used space of the first program firmware, the second used space of the second program firmware, and the third shared space shared by the first and second program firmwares, thereby controlling the operation of the first and second program firmwares on the MCU. Using two program firmwares on a single-core MCU means that if defects are discovered in the application or algorithm program during the product life cycle, only the defective program firmware needs to be updated separately, reducing maintenance difficulty. In addition, the dual-firmware operation method of a single-core MCU reduces costs compared to multi-core MCUs.
[0090] An embodiment of the present invention further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-mentioned dual-firmware operation method for a single-core MCU. The electronic device can be any intelligent terminal, such as a computer.
[0091] An embodiment of the present invention further provides a storage medium storing a computer program. When the computer program is executed by a processor, the dual-firmware operation method of the single-core MCU is implemented.
[0092] It should be appreciated that the method steps in the embodiments of the present invention can be implemented or executed by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, for this purpose, the program can be run on a programmed application-specific integrated circuit.
[0093] Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof. The computer program includes a plurality of instructions that can be executed by one or more processors.
[0094] Further, the methods can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write storage medium, RAM, ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. In addition, the machine-readable code, or portions thereof, can be transmitted over a wired or wireless network. When such media includes instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the invention described herein includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques of the present invention, the present invention can also include the computer itself.
[0095] The computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data that is stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents a physical and tangible object, including a specific visual depiction of the physical and tangible object produced on the display.
[0096] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the aforementioned embodiments. As long as the technical effects of the present invention are achieved by the same means, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Within the scope of protection of the present invention, various modifications and variations of the technical solutions and / or implementation methods are possible.
Claims
1. A dual-firmware operation method for a single-core MCU, characterized in that: include: Determine, by an automated program, a first storage space size of a Flash memory of the MCU, a second storage space size occupied by the first program firmware, and a third storage space size occupied by the second program firmware; and divide the Flash memory into a first Flash space for the first program firmware and a second Flash space for the second program firmware based on the first storage space size, the second storage space size, and the third storage space size; Determine a fourth storage space size of the SRAM of the MCU, a first operating data size of the first program firmware, and a second operating data size of the second program firmware; and divide the SRAM into a first used space of the first program firmware, a second used space of the second program firmware, and a third shared space shared by the first program firmware and the second program firmware according to the fourth storage space size, the first operating data size, and the second operating data size; The first program firmware and the second program firmware are controlled to run on the MCU.
2. The dual-firmware operation method of a single-core MCU according to claim 1, characterized in that: Dividing the SRAM into a first usage space of the first program firmware, a second usage space of the second program firmware, and a third shared space shared by the first program firmware and the second program firmware includes: The first running data of the first program firmware is compiled at the first SRAM address of the SRAM and the first SRAM address is used when the first program firmware is running, the second running data of the second program firmware is compiled at the second SRAM address of the SRAM and the second SRAM address is used when the second program firmware is running, and the third running data common to the first program firmware and the second program firmware is compiled at the third SRAM address of the SRAM and the third SRAM address is used when the first program firmware and the second program firmware communicate, so that the SRAM is divided into the first usage space, the second usage space and the third shared space.
3. The dual-firmware operation method of a single-core MCU according to claim 1, characterized in that: Dividing the Flash into a first Flash space for the first program firmware and a second Flash space for the second program firmware includes: The first program firmware is compiled at a first Flash address of the Flash and burned to the first Flash address, and the second program firmware is compiled at a second Flash address of the Flash and burned to the second Flash address, so that the Flash is divided into the first Flash space and the second Flash space.
4. The dual-firmware operation method of a single-core MCU according to claim 3, characterized in that: Controlling the first program firmware and the second program firmware to run on the MCU includes: When the first program firmware and the second program firmware are respectively run separately on the MCU, mapping the first vector table of the first program firmware to the first Flash address, initializing the first device used by the first main program of the first program firmware to run, and running the first main program to execute application-related services; Mapping the second vector table of the second program firmware to the second Flash address, initializing the second device used when the second main program of the second program firmware runs, and running the second main program to execute algorithm-related services.
5. The dual-firmware operation method of a single-core MCU according to claim 3, characterized in that: Controlling the first program firmware and the second program firmware to run on the MCU includes: When the first program firmware and the second program firmware are run in parallel on the MCU, in the second program firmware, encapsulating the target function of the second program firmware into a function interface; Relocating the first vector table of the first program firmware to the first Flash address, initializing a first device used when a first main program of the first program firmware runs, and running the first main program; When the program reaches an interrupt processing function in the first main program, the function interface is called through a jump function in the interrupt processing function to execute the target function; After the interrupt processing function is finished running, the first main program continues to run.
6. The dual-firmware operation method of a single-core MCU according to claim 5, characterized in that: Calling the function interface to execute the target function through the jump function in the interrupt handling function, and continuing to run the first main program after the interrupt handling function ends, including: Pushing the current CPU operating environment of the first program firmware into the stack and saving it; Setting a target function address of the second program firmware and target function parameters of the second program firmware; Based on the target function address and the target function parameters, use the jump function in the interrupt handling function to jump to the target function address to call the function interface, and control the CPU to fetch and execute the target function from the target function address; After the interrupt processing function is finished running, it jumps back to the first program firmware, pops the stack to restore the CPU running environment before the jump, and continues to run the first main program.
7. The dual-firmware operation method of a single-core MCU according to claim 6, characterized in that: Controlling the CPU to fetch and execute the target function from the target function address includes: The CPU is controlled to obtain the instruction code of the target function from the target function address in the second Flash space, decode the instruction code, and execute the instruction.
8. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements the dual-firmware operation method of a single-core MCU according to any one of claims 1 to 7.
9. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the dual-firmware operation method of a single-core MCU according to any one of claims 1 to 7 is implemented.