Core-based dynamic calibration circuit and method for communication clock and data phase

Abstract

This invention discloses a communication clock and data phase dynamic calibration circuit and method based on a chip architecture, comprising a master control MCU DIE and n controlled ASIC DIEs 1 to 1 controlled ASIC DIEs. n The main control MCU DIE has n+1 global delay modules GDL1 to GDL1. n+1 n controlled ASIC DIEs 1 to n controlled ASIC DIEs n Each of the internal units is equipped with a local phase unit LPU1 to LPU, which correspond to each other. n This invention eliminates data sampling failures caused by timing path differences, achieving a bit error rate of ≤10% in multi-DIE scenarios. ‑9 Reliable communication significantly reduces the bit error rate of multi-DIE synchronous communication data transmission.

Description

Technical Field

[0001] This invention relates to a phase dynamic calibration circuit and method, particularly a communication clock and data phase dynamic calibration circuit and method based on a chip architecture, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Chinese Patent Publication No. CN119149473A discloses a communication method based on a multi-DIE extension of a chip architecture. The method configures a multi-DIE extension communication structure, which includes a master control MCU DIE and several controlled ASIC DIEs. The handshake protocol for read / write operations includes ST, SP, MODE, DEVADDR, REG_ADDR, WDATA, RDATA, and parity. The service transmission protocol includes sending a transmission function enable command and waiting for the controlled ASIC DIEs to prepare data before returning to the master control MCU DIE. This method facilitates the expansion of multiple DIEs, offering greater flexibility, and provides a dedicated service data transmission path without consuming register read / write control line bandwidth.

[0003] This solution still has the following drawbacks:

[0004] 1. Clock synchronization defects: Due to factors such as package delay differences, temperature drift (-40℃~125℃), and uneven traces, the unified clock CLK causes a data sampling window offset, such as... Figure 4 As shown;

[0005] 2. Surge in bit error rate: When the communication frequency is >8MHz, the bit error rate of register read / write (WDATA / RDATA) exceeds 10. -5 The data packet loss rate is >0.1%;

[0006] 3. Limitations of static solutions: Fixed phase adjustment (such as clock reversal) cannot be adapted to high-frequency, multi-load scenarios. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a communication clock and data phase dynamic calibration circuit and method based on chip architecture to eliminate data sampling failure caused by timing path differences.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] The communication clock and data phase dynamic calibration circuit based on the chip architecture includes a main control MCU DIE and n controlled ASIC DIEs (1 to n controlled ASIC DIEs). n The main control MCU DIE has n+1 global delay modules GDL1 to GDL1. n+1n controlled ASIC DIEs 1 to n controlled ASIC DIEs n Each of the internal units is equipped with a local phase unit LPU1 to LPU, which correspond to each other. n The input of the global delay module GDL1 is connected to the output TX of the main control MCU DIE, and the output of the global delay module GDL1 is connected to the local phase unit LPU1~LPU n The input terminals are connected to the local phase units LPU1 to LPU. n The output terminals are respectively connected to the corresponding controlled ASIC DIE1 to controlled ASIC DIE1. n The input RX connection is used to control ASIC DIE1 to control ASIC DIE. n Output TX and global delay modules GDL2~GDL n+1 The input terminals are connected to the global delay modules GDL2 to GDL. n+1 The output terminal is connected to the input RX of the main control MCU DIE.

[0010] Furthermore, the n+1 global delay modules GDL1 to GDL n+1 and local phase units LPU1~LPU n All of them are delay circuits.

[0011] Furthermore, the global delay modules GDL1 to GDL n+1 It contains an 8-stage current-starved inverter chain with a delay range of 0–5 ns.

[0012] Furthermore, the local phase units LPU1~LPU n Includes 32 levels of voltage-controlled delay lines with an adjustment accuracy of 15ps / level.

[0013] A dynamic calibration method for a communication clock and data phase dynamic calibration circuit based on a chip architecture includes the following steps:

[0014] Real-time monitoring of verification error rate and temperature;

[0015] When the error rate is greater than the error rate threshold and the temperature drift is greater than or equal to the temperature threshold, start the binary scan and lock the sampling phase value PHASE_CFG with the lowest bit error rate (BER).

[0016] Furthermore, the error rate threshold is 0.1%, and the temperature threshold is 10°C.

[0017] Furthermore, the binary search method specifically involves:

[0018] S1. Set m equally spaced phase points [PHASE1, PHASE2, ..., PHASE] m], where PHASE1 = PHASE min PHASE m = PHASE max PHASE min It is the minimum value of the phase adjustment threshold, PHASE max It is the maximum value of the phase adjustment threshold, with an interval step size of T;

[0019] S2. Sequentially assign m equally spaced phase points [PHASE1, PHASE2, ..., PHASE] to each phase point. m Record the sampled phase values ​​PHASE_CFG and test their bit error rate (BER);

[0020] S3. Select the two adjacent phase points with the lowest bit error rate (BER) PHASE i and PHASE i+1 Construct the optimization interval [PHASE] i PHASE i+1 ], where 1≤i≤m-1, and assume phase point PHASE i The bit error rate (BER) is less than the phase point (PHASE). i+1 The bit error rate (BER);

[0021] S4. In the optimization interval [PHASE] i PHASE i+1 Select the midpoint PHASE in the [selection] section. j Then calculate the intermediate point PHASE j The bit error rate (BER) will be used to determine the intermediate point phase. j and phase point PHASE min Construct a new optimization interval [PHASE] i PHASE i+1 ], and PHASE i =PHASE min PHASE i+1 =PHASE j The interval step size T = T / 2, and the phase point PHASE min It is the phase point PHASE i and PHASE i+1 Phase points with low bit error rate (BER);

[0022] S5. Repeat step S4 until the interval step size T reaches the preset interval step size, and then determine the last intermediate point PHASE. j Bit error rate (BER) and phase point (PHASE) min The size of the bit error rate (BER);

[0023] S6. If the last intermediate point PHASEj The bit error rate (BER) is less than or equal to the phase point PHASE. min If the bit error rate (BER) is set, then the sampling phase value PHASE_CFG is locked as the last intermediate point PHASE. j If the last intermediate point PHASE j The bit error rate (BER) is greater than the phase point (PHASE). min If the bit error rate (BER) is determined, then the sampled phase value PHASE_CFG is locked as the phase point PHASE. min ;

[0024] S7. Write the locked sampling phase value PHASE_CFG into the DIE configuration register to complete dynamic phase calibration.

[0025] Compared with existing technologies, this invention has the following advantages and effects: This invention provides a communication clock and data phase dynamic calibration circuit and method based on a chip architecture, eliminating data sampling failures caused by timing path differences, and achieving a bit error rate ≤10% in multi-DIE scenarios. -9 Reliable communication significantly reduces the bit error rate of multi-DIE synchronous communication data transmission. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the communication clock and data phase dynamic calibration circuit based on the chip architecture of the present invention.

[0027] Figure 2 This is a schematic diagram comparing the sampling windows before and after phase adjustment of the communication clock and data phase dynamic calibration circuit based on the chip architecture of the present invention.

[0028] Figure 3 This is a flowchart of the phase dynamic calibration method of the present invention.

[0029] Figure 4 This is a schematic diagram of communication timing deviations in existing technologies. Detailed Implementation

[0030] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0031] like Figure 1As shown, the communication clock and data phase dynamic calibration circuit based on chip architecture of the present invention includes a master control MCU DIE and n controlled ASIC DIEs 1 to 2 controlled ASIC DIEs. n The main control MCU DIE has n+1 global delay modules GDL1 to GDL1. n+1 n controlled ASIC DIEs 1 to n controlled ASIC DIEs n Each of the internal units is equipped with a local phase unit LPU1 to LPU, which correspond to each other. n The input of the global delay module GDL1 is connected to the output TX of the main control MCU DIE, and the output of the global delay module GDL1 is connected to the local phase unit LPU1~LPU n The input terminals are connected to the local phase units LPU1 to LPU. n The output terminals are respectively connected to the corresponding controlled ASIC DIE1 to controlled ASIC DIE1. n The input RX connection is used to connect controlled ASIC DIE1 to controlled ASIC DIE. n Output TX and global delay modules GDL2~GDL n+1 The input terminals are connected to the global delay modules GDL2 to GDL. n+1 The output terminal is connected to the input RX of the main control MCU DIE.

[0032] Among them, there are n+1 global delay modules GDL1 to GDL n+1 and local phase units LPU1~LPU n All of them are delay circuits.

[0033] Global Delay Modules GDL1~GDL n+1 It contains an 8-stage current-starved inverter chain with a delay range of 0–5 ns.

[0034] Local phase unit LPU1~LPU n Includes 32 levels of voltage-controlled delay lines with an adjustment accuracy of 15ps / level.

[0035] like Figure 3 As shown, a dynamic calibration method for a communication clock and data phase dynamic calibration circuit based on a chip architecture includes the following steps:

[0036] Real-time monitoring of verification error rate and temperature;

[0037] When the error rate is greater than the error rate threshold and the temperature drift is greater than or equal to the temperature threshold, start the binary scan and lock the sampling phase value PHASE_CFG with the lowest bit error rate (BER).

[0038] The error rate threshold is 0.1%, and the temperature threshold is 10℃.

[0039] The binary scan method is specifically as follows:

[0040] S1. Set m equally spaced phase points [PHASE1, PHASE2, ..., PHASE] m ], where PHASE1 = PHASE min PHASE m = PHASE max PHASE min It is the minimum value of the phase adjustment threshold, PHASE max It is the maximum value of the phase adjustment threshold, with an interval step size of T;

[0041] S2. Sequentially assign m equally spaced phase points [PHASE1, PHASE2, ..., PHASE] to each phase point. m Record the sampled phase values ​​PHASE_CFG and test their bit error rate (BER);

[0042] S3. Select the two adjacent phase points with the lowest bit error rate (BER) PHASE i and PHASE i+1 Construct the optimization interval [PHASE] i PHASE i+1 ], where 1≤i≤m-1, and assume phase point PHASE i The bit error rate (BER) is less than the phase point (PHASE). i+1 The bit error rate (BER);

[0043] S4. In the optimization interval [PHASE] i PHASE i+1 Select the midpoint PHASE in the [selection] section. j Then calculate the intermediate point PHASE j The bit error rate (BER) will be used to determine the intermediate point phase. j and phase point PHASE min Construct a new optimization interval [PHASE] i PHASE i+1 ], and PHASE i =PHASE min PHASE i+1 =PHASE j The interval step size T = T / 2, and the phase point PHASE min It is the phase point PHASE i and PHASE i+1 Phase points with low bit error rate (BER);

[0044] S5. Repeat step S4 until the interval step size T reaches the preset interval step size, and then determine the last intermediate point PHASE. j Bit error rate (BER) and phase point (PHASE) min The size of the bit error rate (BER);

[0045] S6. If the last intermediate point PHASE j The bit error rate (BER) is less than or equal to the phase point PHASE. min If the bit error rate (BER) is set, then the sampling phase value PHASE_CFG is locked as the last intermediate point PHASE. j If the last intermediate point PHASE j The bit error rate (BER) is greater than the phase point (PHASE). min If the bit error rate (BER) is determined, then the sampled phase value PHASE_CFG is locked as the phase point PHASE. min ;

[0046] S7. Write the locked sampling phase value PHASE_CFG into the DIE configuration register to complete dynamic phase calibration.

[0047] This invention provides a communication clock and data phase dynamic calibration circuit and method based on a chip architecture, eliminating data sampling failures caused by timing path differences and achieving a bit error rate ≤10 in multi-DIE scenarios. -9 Reliable communication significantly reduces the bit error rate of multi-DIE synchronous communication data transmission.

[0048] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A communication clock and data phase dynamic calibration circuit based on a chip architecture, characterized in that: Includes the main control MCU DIE and n controlled ASICs DIE1 to n controlled ASICs DIE n The main control MCU DIE has n+1 global delay modules GDL1 to GDL1. n+1 n controlled ASIC DIEs 1 to n controlled ASIC DIEs n Each of the internal units is equipped with a local phase unit LPU1 to LPU, which correspond to each other. n The input of the global delay module GDL1 is connected to the output TX of the main control MCU DIE, and the output of the global delay module GDL1 is connected to the local phase unit LPU1~LPU n The input terminals are connected to the local phase units LPU1 to LPU. n The output terminals are respectively connected to the corresponding controlled ASIC DIE1 to controlled ASIC DIE1. n The input RX connection is used to control ASIC DIE1 to control ASIC DIE. n Output TX and global delay modules GDL2~GDL n+1 The input terminals are connected to the global delay modules GDL2 to GDL. n+1 The output terminal is connected to the input RX of the main control MCU DIE.

2. The communication clock and data phase dynamic calibration circuit based on chip architecture according to claim 1, characterized in that: The n+1 global delay modules GDL1~GDL n+1 and local phase units LPU1~LPU n All of them are delay circuits.

3. The communication clock and data phase dynamic calibration circuit based on chip architecture according to claim 2, characterized in that: The global delay modules GDL1 to GDL n+1 It contains an 8-stage current-starved inverter chain with a delay range of 0–5 ns.

4. The communication clock and data phase dynamic calibration circuit based on chip architecture according to claim 2, characterized in that: The local phase units LPU1 to LPU n Includes 32 levels of voltage-controlled delay lines with an adjustment accuracy of 15ps / level.

5. A dynamic calibration method for a communication clock and data phase dynamic calibration circuit based on a chip architecture as described in any one of claims 1-4, characterized in that... Includes the following steps: Real-time monitoring of verification error rate and temperature; When the error rate is greater than the error rate threshold and the temperature drift is greater than or equal to the temperature threshold, start the binary scan and lock the sampling phase value PHASE_CFG with the lowest bit error rate (BER).

6. The dynamic calibration method according to claim 5, characterized in that: The error rate threshold is 0.1%, and the temperature threshold is 10℃.

7. The dynamic calibration method according to claim 5, characterized in that: The binary search method specifically refers to: S1. Set m equally spaced phase points [PHASE1, PHASE2, ..., PHASE] m ], where PHASE1 = PHASE min PHASE m =PHASE max PHASE min It is the minimum value of the phase adjustment threshold, PHASE max It is the maximum value of the phase adjustment threshold, with an interval step size of T; S2. Sequentially assign m equally spaced phase points [PHASE1, PHASE2, ..., PHASE] to each phase point. m Record the sampled phase values ​​PHASE_CFG and test their bit error rate (BER); S3. Select the two adjacent phase points with the lowest bit error rate (BER) PHASE i and PHASE i+1 Construct the optimization interval [PHASE] i PHASE i+1 ], where 1≤i≤m-1, and assume phase point PHASE i The bit error rate (BER) is less than the phase point (PHASE). i+1 The bit error rate (BER); S4. In the optimization interval [PHASE] i PHASE i+1 Select the midpoint PHASE in the [selection] section. j Then calculate the intermediate point PHASE j The bit error rate (BER) will be used to determine the intermediate point phase. j and phase point PHASE min Construct a new optimization interval [PHASE] i PHASE i+1 ], and PHASE i =PHASE min PHASE i+1 =PHASE j The interval step size T = T / 2, and the phase point PHASE min It is the phase point PHASE i and PHASE i+1 Phase points with low bit error rate (BER); S5. Repeat step S4 until the interval step size T reaches the preset interval step size, and then determine the last intermediate point PHASE. j Bit error rate (BER) and phase point (PHASE) min The size of the bit error rate (BER); S6. If the last intermediate point PHASE j The bit error rate (BER) is less than or equal to the phase point PHASE. min If the bit error rate (BER) is set, then the sampling phase value PHASE_CFG is locked as the last intermediate point PHASE. j If the last intermediate point PHASE j The bit error rate (BER) is greater than the phase point (PHASE). min If the bit error rate (BER) is determined, then the sampled phase value PHASE_CFG is locked as the phase point PHASE. min ; S7. Write the locked sampling phase value PHASE_CFG into the DIE configuration register to complete dynamic phase calibration.

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