LDPC decoding performance evaluation system under AWGN channel

Abstract

The invention discloses an LDPC decoding performance evaluation system under an AWGN channel, which is realized based on an FPGA hardware platform, and comprises a baseband data framing module used for generating a pseudo-random number with a corresponding length according to a coding and decoding type, adding a frame header and completing framing; the LDPC coding module is used for coding the framed baseband data; the BPSK AWGN channel module is used for simulating a channel, completing BPSK mapping and adding Gaussian white noise; the log likelihood ratio LLR information conversion module is used for converting the data added with the Gaussian white noise into LLR soft decision information and transmitting the LLR soft decision information to the frame synchronization module; the frame synchronization module is used for completing frame synchronization with configurable various parameters for the LLR soft decision information; the LDPC decoding module is used for decoding the LLR soft decision information after the frame synchronization; and the LDPC decoding performance evaluation module is used for displaying the decoding state information in real time and counting the frame error rate.

Description

Technical Field

[0001] The present invention relates to the fields of electronics and communication technology, and in particular to an LDPC decoding performance evaluation system under an AWGN channel. Background Art

[0002] LDPC (Low-Density Parity Check) codes are widely used in modern communication systems due to their excellent performance and ability to approach the Shannon limit. The performance of LDPC codes is affected by code length, code rate, channel characteristics, and the decoding algorithm used. Typically, designers need to evaluate decoding performance after completing the encoding and decoding design. Currently, most literature uses software simulation to evaluate decoding performance, but the time cost required for this approach is often prohibitive. The method described in the document "FPGA Implementation of an LDPC Code Hardware Simulation Platform" (Journal of Nanjing University (Science and Technology Edition), Vol. 6, No. 3, May 2014) uses a hardware simulation platform, but the noise generator module implementation of this method is somewhat complex and requires the design of specialized PC control software, which increases additional development costs. Therefore, it is essential to design a hardware platform that is simple to implement, easy to operate, and highly portable to accelerate the evaluation of decoding performance. Summary of the Invention

[0003] The purpose of the present invention is to overcome the defects of the prior art and propose an LDPC decoding performance evaluation system under an AWGN channel.

[0004] In view of this, the present invention proposes an LDPC decoding performance evaluation system under AWGN channel, which is implemented based on FPGA hardware platform and is characterized by including:

[0005] The baseband data framing module is used to generate a pseudo-random number of corresponding length according to the encoding and decoding type, and add a frame header to complete the framing;

[0006] LDPC encoding module, used to encode the framed baseband data;

[0007] BPSK AWGN channel module, used to simulate the channel, complete BPSK mapping and add Gaussian white noise;

[0008] The log-likelihood ratio (LLR) information conversion module is used to convert the data with added Gaussian white noise into LLR soft decision information and transmit it to the frame synchronization module;

[0009] Frame synchronization module, used to complete frame synchronization with multiple configurable parameters for LLR soft decision information;

[0010] LDPC decoding module, used to decode LLR soft decision information after frame synchronization; and

[0011] The LDPC decoding performance evaluation module is used to display decoding status information in real time and calculate the frame error rate.

[0012] Preferably, the processing process of the baseband data framing module includes:

[0013] The frame length is determined by the LDPC decoding type: if the type is LDPC (8160, 7136) long code, the frame length after adding the frame header is 8192 bits; if the type is LDPC (512, 256) short code, the frame length after adding the frame header is 544 bits;

[0014] Generate a counter of corresponding length according to the frame length, fill the frame header at the first 32 bits, and add a pseudo-random sequence at the position of frame length - 32 bits.

[0015] Preferably, the pseudo-random sequence is realized by calling a linear feedback shift register LFSR under System Generator, and the number of register chains of the LFSR is set to a maximum of 64 bits.

[0016] Preferably, the coding of the LDPC coding module includes: 1 / 2 LDPC coding and 7 / 8 LDPC coding.

[0017] Preferably, the BPSK AWGN channel module is implemented by calling the BPSK AWGNChannel component under System Generator, and the input end SNR of the component is defined as the channel Eb / N0 in dB.

[0018] Preferably, the log-likelihood ratio (LLR) information conversion module processing process includes:

[0019] According to the Bayesian formula, the LLR coefficient LLR(y) of BPSK modulation under AWGN channel is generated:

[0020]

[0021] Among them, σ 2 is the actual noise power, y is the amplitude of the received signal; the coefficient Obtained by addressing the ROM lookup table.

[0022] Preferably, in the frame synchronization module, the multiple configurable parameters include: frame length, frame header, number of frame header error tolerance bits, number of check states, and number of synchronization state loss times.

[0023] Preferably, the decoding of the LDPC decoding module includes: 1 / 2 LDPC decoding and 7 / 8 LDPC decoding.

[0024] Preferably, the LDPC decoding performance evaluation module uses VIO provided by the programming tool Vivado / ISE to set the channel Eb / N0 online.

[0025] Preferably, the FPGA hardware platform is a Xilinx KC705 evaluation board, and the setting of the working clock takes into account the throughput achieved by the encoding and decoding algorithm and the highest working clock that the FPGA can meet the timing constraints.

[0026] Compared with the prior art, the advantages of the present invention are:

[0027] 1. The present invention uses a hardware platform to greatly accelerate the evaluation of LDPC decoding performance and reduce the time cost of software simulation evaluation decoding.

[0028] 2. The method of the present invention is simple to implement and easy to operate. By calling the components in System Generator, the generation of baseband signal sources, BPSK modulation and AWGN channel modeling can be completed. System Generator is a solution for algorithm design in FPGA using Simulink. Many modules in Xilinx are integrated into Simulink. Algorithms can be designed directly by dragging and dropping, and fixed-point simulation can be performed directly. HDL code or netlist can be directly generated by System Generator with a clear structure.

[0029] 3. By calling the VIO IP core provided by the Vivado or ISE programming tool, the Eb / N0 parameters can be adjusted online in smaller steps and the frame error rate can be calculated without adding additional development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is the structural block diagram of the LDPC decoding performance evaluation system under AWGN channel. DETAILED DESCRIPTION

[0031] The present invention discloses an LDPC decoding performance evaluation system under AWGN channel, which is implemented based on FPGA hardware platform and includes:

[0032] The baseband data framing module is used to generate a pseudo-random number of corresponding length according to the encoding and decoding type, and add a frame header to complete the framing;

[0033] LDPC encoding module, used to encode the framed baseband data;

[0034] BPSK AWGN channel module, used to simulate the channel, complete BPSK mapping and add Gaussian white noise;

[0035] The log-likelihood ratio (LLR) information conversion module is used to convert the data with added Gaussian white noise into LLR soft decision information and transmit it to the frame synchronization module;

[0036] Frame synchronization module, used to complete frame synchronization with multiple configurable parameters for LLR soft decision information;

[0037] LDPC decoding module, used to decode LLR soft decision information after frame synchronization;

[0038] The LDPC decoding performance evaluation module is used to display decoding status information in real time and calculate the frame error rate.

[0039] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0040] Example

[0041] The embodiment of the present invention proposes an LDPC decoding performance evaluation system under an AWGN channel, which takes advantage of System Generator for digital signal processing and uses a field programmable gate array (FPGA) hardware platform to complete board-level performance testing of LDPC decoding.

[0042] Figure 1 The structural block diagram of the LDPC decoding performance evaluation system under AWGN channel is given, which shows the connection relationship between various functional modules.

[0043] The baseband data framing module first needs to determine the frame length (FrameLength) based on the LDPC decoding type. If the LDPC (8160, 7136) long code is used, the frame length after adding the frame header (32'h1ACFFC1D) is 8192 bits. If the LDPC (512, 256) short code is used, the frame length after adding the frame header (32'h1ACFFC1D) is 544 bits. The baseband data framing module generates a counter of the corresponding length based on the frame length, fills the first 32 bits with the frame header, and adds a pseudo-random sequence at the (FrameLength-32) bit position.

[0044] The pseudo-random sequence is implemented by calling the linear feedback shift register (LFSR) under System Generator. To ensure the randomness of each frame of data during the test phase, the number of LFSR register chains is set to a maximum of 64 bits. In addition, the LFSR also supports Galois and Fibonacci structures, and can use "XOR gate" or "NOR gate" methods.

[0045] The LDPC encoding module receives the pseudo-random sequence frame output by the baseband data framing module and selects the LDPC (8160, 7136) long code or the LDPC (512, 256) short code according to the encoding type.

[0046] BPSK AWGN channel modeling is achieved by calling the BPSK AWGN Channel component in System Generator to add noise to the signal and complete BPSK mapping. The advantage of the BPSK AWGN Channel component is that it not only completes BPSK mapping, but also does not require artificial noise simulation. The Eb / N0 in dB units can be directly set. The input of this component is the SNR (equivalent to Eb / N0 in this embodiment) and the baseband data DIN output by the encoding module. The SNR is represented by a fixed point (0, 8, 4) and is an unsigned number with a total data bit width of 8 bits and a decimal bit width of 4 bits. The specific value is set through VIO.

[0047] The log-likelihood ratio (LLR) information conversion module is used to generate the LLR information required by the decoder. According to the Bayesian formula, the BPSK LLR coefficient generation formula is:

[0048]

[0049] Let μ = 1, then: Among them, σ 2 is the actual noise power, y is the amplitude of the received signal, and the coefficient The coefficient can be obtained by addressing a ROM lookup table.

[0050] The LLR coefficient expression stored in the ROM lookup table needs to consider the binary point of the SNR expressed in fixed point and convert the dB value to the original value: 4*10^([0:255] / 16 / 10)=4*10^([0:255] / 160).

[0051] The SNR fixed point is (0,8,4), representing a range of 0 to 15.9375 dB. The corresponding LLR coefficient range is 4 to 156.9676. To accurately represent the LLR coefficient, the fixed point is (0,18,10).

[0052] The information after BPSK AWGN channel modeling is multiplied by the LLR coefficient to obtain the LLR information and send it to the frame synchronization module. The LLR information is fixed at (1, 6, 2), indicating a signed number. The total data bit width is 6 bits and the decimal bit width is 2 bits.

[0053] In a BPSK AWGN channel, the input 0 / 1 baseband signal is mapped, with 0 being mapped to +1 and 1 being mapped to -1. After adding noise to the baseband data channel model, the frame synchronization module at the receiver only needs to extract the highest bit of the LLR information to complete BPSK demapping and search for the frame header for frame synchronization.

[0054] The decoding module completes LDPC (8160, 7136) long code decoding or LDPC (512, 256) short code decoding according to the decoding type, and counts the current decoding status, the number of frames with correct decoding, and the number of frames with incorrect decoding, and sends them to the VIO for monitoring.

[0055] VIO is an IP core directly callable by the Vivado tool. In this embodiment, it is used to set the channel Eb / N0, display decoding status, correctly decoded frame counts, and decoded error frame counts, and calculate FER. Refer to the FER curves for different decoding types provided in the CCSDS document to select an appropriate range for channel Eb / N0 settings, with each test step being 0.2dB. Table 1 shows a comparison chart of VIO Eb / N0 settings for LDPC (512, 256) decoding.

[0056] Table 1 LDPC (512, 256) decoding VIO setting Eb / N0 schematic

[0057]

[0058] To reduce the time cost of evaluating decoding performance while balancing the throughput of the encoding and decoding algorithm with the maximum clock rate the FPGA can withstand (setup and hold timing requirements), the design uses a maximum operating clock of 100 MHz. To ensure test reliability, when Eb / N0 is low, the number of frame errors increases rapidly, shortening the single test time. When the number of decoding error frames reaches a certain number, the current test is terminated. When Eb / N0 is high, the number of frame errors increases slowly, increasing the single test time until the required number of frames is reached.

[0059] The specific testing process is:

[0060] Step 1) After the device loads the program, set the encoding and decoding mode through VIO;

[0061] Step 2) Set the channel Eb / N0 to a value close to the decoding threshold through VIO;

[0062] Step 3) Observe whether the decoding error frame count is greater than 20 frames. If so, record the current frame error rate (FER) and increase the channel Eb / N0 in steps of 0.2 dB. If not, continue waiting until the decoding error frame count reaches 20 frames.

[0063] Step 4) looping through step 3) to record the frame error rate FER at the current Eb / N0;

[0064] Step 5) As Eb / N0 increases, the probability of decoding error frame counts decreases. Therefore, when there are no decoding error frames, but the total number of test frames reaches the required upper limit, for example, when the number of test frames is greater than 1e10 frames, the current Eb / N0 is recorded and the test is stopped.

[0065] Step 6) Draw the corresponding FER curves under different channel Eb / N0 and compare them with the FER curves given in the CCSDS literature to evaluate the decoding performance.

[0066] It is worth noting that in the embodiment of the above system, the modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0067] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention and are intended to be encompassed by the claims of the present invention.

Claims

1. A LDPC decoding performance evaluation system under AWGN channel, implemented based on FPGA hardware platform, characterized by: include: The baseband data framing module is used to generate a pseudo-random number of corresponding length according to the encoding and decoding type, and add a frame header to complete the framing; LDPC encoding module, used to encode the framed baseband data; BPSK AWGN channel module, used to simulate the channel, complete BPSK mapping and add Gaussian white noise; The log-likelihood ratio (LLR) information conversion module is used to convert the data with added Gaussian white noise into LLR soft decision information and transmit it to the frame synchronization module; Frame synchronization module, used to complete frame synchronization with multiple configurable parameters for LLR soft decision information; LDPC decoding module, used to decode LLR soft decision information after frame synchronization; and The LDPC decoding performance evaluation module is used to display decoding status information in real time and calculate the frame error rate.

2. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that The processing process of the baseband data framing module includes: The frame length is determined by the LDPC decoding type: if the type is LDPC (8160, 7136) long code, the frame length after adding the frame header is 8192 bits; if the type is LDPC (512, 256) short code, the frame length after adding the frame header is 544 bits; Generate a counter of corresponding length according to the frame length, fill the frame header at the first 32 bits, and add a pseudo-random sequence at the position of frame length - 32 bits.

3. The LDPC decoding performance evaluation system under AWGN channel according to claim 2, characterized in that: The pseudo-random sequence is realized by calling a linear feedback shift register LFSR under the System Generator, and the number of register chains of the LFSR is set to a maximum of 64 bits.

4. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that The coding of the LDPC coding module includes: 1 / 2 LDPC coding and 7 / 8 LDPC coding.

5. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that The BPSKAWGN channel module is implemented by calling the BPSK AWGN Channel component under System Generator. The input SNR of this component is defined as the channel Eb / N0 in dB.

6. The LDPC decoding performance evaluation system under AWGN channel according to claim 5, characterized in that: The log-likelihood ratio (LLR) information conversion module processing process includes: According to the Bayesian formula, the LLR coefficient LLR(y) of BPSK modulation under AWGN channel is generated: Among them, σ 2 is the actual noise power, y is the amplitude of the received signal; the coefficient Obtained by addressing the ROM lookup table.

7. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that: In the frame synchronization module, the various configurable parameters include: frame length, frame header, frame header error tolerance bit number, check state times, and synchronization state loss times.

8. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that: The decoding of the LDPC decoding module includes: 1 / 2 LDPC decoding and 7 / 8 LDPC decoding.

9. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that: The LDPC decoding performance evaluation module uses the VIO provided by the programming tool Vivado / ISE to set the channel Eb / N0 online.

10. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that: The FPGA hardware platform is a Xilinx KC705 evaluation board. The setting of the working clock takes into account the throughput achieved by the encoding and decoding algorithm and the maximum working clock that the FPGA can meet the timing constraints.

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