Semiconductor member and method for manufacturing the same

Abstract

The invention relates to a gallium nitride-based semiconductor component (100), in particular a transistor, comprising a substrate and / or drain layer (14), a drift layer (13) of a first type of doping, in particular a channel layer (12) of a second type of doping, and a source layer (11) of the first type of doping, the channel layer being arranged between the source layer and the drift layer in the vertical direction, the channel layer being arranged between the source layer and the drift layer in the vertical direction, and the source layer being arranged between the drift layer and the channel layer in the vertical direction. The semiconductor component further has a gate trench which extends in a vertical direction from the source layer (12, 15) to the drift layer (13) and is adjacent to at least a portion of the channel layer (12) and the source layer (11), and wherein the semiconductor component further has one or more shielding regions (31) of a second type of doping, which shielding regions (31) of the second type of doping extend in the vertical direction from the source layer (12, 15) to the drift layer (13) and are adjacent to at least a portion of the channel layer (12) and the source layer (11). Each of the shielding regions is located at least partially below the gate trench in the vertical direction and at least partially inside the drift layer (13), one or more of the shielding regions being formed by diffusion. The invention also relates to a method for producing a semiconductor component.

Description

Technical Field

[0001] The present invention relates to a semiconductor component, in particular to a transistor, in particular a so-called trench metal oxide semiconductor field effect transistor (Trench MOSFET), and to a method for producing such a semiconductor component. Background Art

[0002] Field-effect transistors, particularly so-called MOSFETs (metal-oxide-semiconductor field-effect transistors) or MISFETs (metal-insulator-semiconductor field-effect transistors), are used in many fields. One variant is the so-called trench MOSFET (T-MOSFET), in which the channel is designed vertically. Here, for example, trenches ("trenches") penetrate an n-doped source layer and a channel layer located between the source layer and the n-doped drift layer; gate electrodes are then arranged in these trenches. Summary of the Invention

[0003] According to the present invention, a semiconductor component and a method for producing a semiconductor component are provided. Advantageous embodiments are described below.

[0004] The present invention relates to semiconductor components, in particular field-effect transistors, in particular having trenches, and to their manufacture. Different types of doping are used in semiconductor materials, namely n-type doping and p-type doping, wherein different components can be doped differently. For ease of understanding, field-effect transistors will be described below with reference to specific doping types, with n-type doping being defined as the first type of doping and p-type doping as the second type of doping. However, it will be understood that n-type and p-type doping can also be interchanged, i.e., n-type doping can be the second type of doping and p-type doping can be the first type of doping.

[0005] Such field-effect transistors typically have a substrate layer and / or drain layer, an n-doped drift layer, a channel layer, typically p-doped, and an n-doped source layer. The channel layer is located vertically between the source and drift layers. For example, the n-doped drift layer is applied to the substrate layer and / or drain layer as a so-called epitaxial layer or epitaxially grown layer.

[0006] Furthermore, such a field effect transistor has a gate trench (so-called trench) that extends vertically from the source layer to the drift layer and is adjacent to at least a portion of the channel layer and the source layer. Furthermore, such a field effect transistor may have a gate electrode that is introduced into the gate trench and is isolated from the drift layer and the channel layer, for example, by means of a so-called gate oxide.

[0007] Furthermore, such a field effect transistor has a source contact material layer adjacent to the source layer. The gate electrode is isolated from the source contact material layer. Similarly, such a field effect transistor has a drain contact material layer adjacent to the substrate layer and / or the drain layer. Here, the source contact material layer serves as a source electrode or a connection terminal, and accordingly, the source contact material layer serves as a source electrode or a connection terminal.

[0008] It should be noted that this type of field-effect transistor can have multiple such gate trenches and gate electrodes. So-called fins are formed between the gate trenches, and the aforementioned layer structure is located in the fins. This is a particular advantage of trench MOSFETs, because the vertical arrangement allows multiple gate electrodes to be arranged side by side.

[0009] Such field-effect transistors can be used alone or together with other field-effect transistors, for example as power switches. Preferred areas of application are, for example, electric drive systems for vehicles, for example in current converters (DC / DC converters, inverters), chargers for electric vehicles, or solar inverters.

[0010] Semiconductor components, such as field-effect transistors, can often be based on gallium nitride (GaN). This enables components with lower on-resistance and higher breakdown voltage compared to similar components based on, for example, silicon (Si) or silicon carbide (SiC). Gallium nitride transistors or transistors based on GaN can be primarily used, for example, as so-called high electron mobility transistors (HEMTs), in which current flows laterally at the substrate surface via a two-dimensional electron gas, which forms the transistor channel. Such lateral components can be manufactured by heteroepitaxial growth of a functional GaN layer on a silicon wafer.

[0011] However, for high breakdown voltage and low on-resistance per unit area, vertical structures, in which current flows from the front side of the substrate to the back side of the substrate, are more advantageous in terms of both structure size and internal electric field distribution. There are different concepts for transistor channels, such as the trench gate MOSFET (abbreviated as trench MOSFET or TMOS) mentioned above and the so-called planar gate MOSFET (also called VDMOS).

[0012] It can be advantageous for the production of vertical components to be able to produce n-type and p-type doping in a position-selective manner. In the case of transistors based on silicon and silicon carbide (in particular power transistors), this can be achieved, for example, by means of ion implantation of doping species (dotierspezies). In the case of p-type implantation, for example, this allows the generation of channels as well as shielding, short-circuit current limiting and edge termination regions or structures for MOSFETs. The short-circuit current limiting structures are based on the so-called JFET effect and are therefore also referred to below as JFET regions or JFET areas.

[0013] Regarding the shielding area or shielding structure and the JFET area or JFET range, concepts of varying complexity can be considered, which differ in their effectiveness with regard to shielding and the JFET effect and also vary in their space requirements.

[0014] For example, in a trench MOSFET structure, in addition to the trench gate structure, a p-type region can be implanted into the gate trench, making the lower end of the p-type region deeper than the bottom of the gate trench. This reduces the field load on the gate dielectric in the off state.

[0015] In trench-gate structures with a so-called split gate, an implanted p-type region (also called bubble implant) can also be realized directly below the gate trench.

[0016] In FinMOS structures, the so-called npn region can be reduced to a narrow fin, thereby enabling a particularly space-saving realization of the channel and shielding structures.

[0017] In the case of gallium nitride (GaN) or GaN-based semiconductor components such as transistors, magnesium (Mg) is a common p-type dopant. However, after the magnesium atoms are implanted, they must be incorporated into the GaN crystal lattice in a so-called activation step in order to function as acceptors. For GaN, this requires temperatures of 1300°C and above.

[0018] It has been shown that GaN components doped with magnesium can be successfully activated for GaN epilayers on native GaN substrates, but this has not been possible so far for GaN grown heteroepitaxially on foreign substrates.

[0019] However, when producing shielding or JFET regions by ion implantation, the high temperatures of at least 1300°C required to activate the implanted magnesium species as acceptors are particularly problematic. At ambient pressure, the surface of gallium nitride begins to decompose into gallium and nitrogen at approximately 800°C. In order to withstand these temperatures without damage during activation, complex processes under overpressure (in the order of megapascals to gigapascals) must be used, or the gallium nitride must be protected during the process with a suitable capping material. The first approach has proven to be industrially unfeasible. Similarly, capping materials do not provide unlimited protection at temperatures of 1300°C and above and may even crystallize themselves at these temperatures, making their removal difficult.

[0020] Furthermore, the maximum process temperature of GaN transistors fabricated on foreign substrates (such as silicon, sapphire or engineered polyaluminum nitride substrates) is limited (e.g. due to thermal stress or the melting temperature of the substrate), making magnesium implantation and subsequent activation impossible or at least impractical.

[0021] Against this background, it is now proposed to diffuse one or more p-type doped shielding regions (e.g., the aforementioned JFET regions) into the drift layer of a GaN-based semiconductor component. These shielding regions are each at least partially located vertically below the gate trench and at least partially within the drift layer. Furthermore, magnesium is diffused therein, in particular.

[0022] This diffusion can be carried out at lower temperatures than those required for ion implantation, i.e., at temperatures between 1100° C. and 1300° C., and in particular with a relatively constant depth profile (Tiefenprofil), with a dopant concentration of, for example, 2×10 18 cm -3 to 3×10 18 cm -3 .

[0023] Thus, by using diffusion, it is possible to provide a GaN-based semiconductor component, such as a power transistor, with a p-type shield or JFET region without resorting to implantation processes with their associated disadvantages. This can sometimes significantly simplify the manufacturing process.

[0024] In an embodiment, the shielding region or at least one of the plurality of shielding regions is a first shielding region that is at least substantially located next to the gate trench in a horizontal direction. For example, two such first shielding regions may be provided, one located on the left and one on the right side of the gate trench.

[0025] In an embodiment, the first shielding region is adjacent to the channel layer. It can also be configured that the first shielding region is spaced apart from the gate trench in a vertical direction.

[0026] In an embodiment, the source contact material layer is adjacent to the first shielding region and may also be adjacent to the channel layer and the source layer.

[0027] However, in the embodiment, it may also be provided that the first shielding region is adjacent to the gate trench.

[0028] In one embodiment, the shielding region or at least one of the plurality of shielding regions is a second shielding region that is located vertically below the gate trench, i.e., extends at least approximately the same as the gate trench in a lateral direction. In this case, the semiconductor component may include an isolation layer that is vertically disposed between the gate trench and the second shielding region.

[0029] In addition to semiconductor components or transistors, the present invention also relates to a method for manufacturing the semiconductor components. First, a substrate layer and / or a drain layer are provided, onto which an n-type doped layer including an n-type doped drift layer is applied. A channel layer and an n-type doped source layer are then formed on the n-type doped drift layer. Furthermore, a gate trench and one or more p-type doped shielding regions are formed, in particular by diffusion of magnesium. For this purpose, a shielding trench can be formed, for example.

[0030] In this case, the gate trench and the shield trench can be formed jointly, ie, in a common process step, or one can be formed first and then the other. Various examples will be explained later in conjunction with different advantages.

[0031] In one embodiment, it is further provided that a nitrogen region is formed, in particular by implantation, in which the shielding region is formed. In this way, the thickness of this region can be controlled more precisely.

[0032] It is understood that further steps may be required for the final transistor chip, such as edge termination and outward routing of contact paths, etc.; conventional measures can be used here.

[0033] Further advantages and embodiments of the invention emerge from the description and the drawings.

[0034] The invention is schematically illustrated by way of example in the drawings and is described below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 6 Field-effect transistors in various embodiments are schematically shown.

[0036] Figures 7 to 14 The sequence of a method for producing a field-effect transistor according to various embodiments is schematically shown. DETAILED DESCRIPTION

[0037] exist Figures 1 to 6 Schematically depicting field-effect transistors in various embodiments, in particular as power transistors. Identical elements, components or layers are denoted by the same reference numerals.

[0038] The field-effect transistor is designed as a so-called trench MOSFET. Gallium nitride (GaN) is provided as the semiconductor material on which the field-effect transistor is based. A cross-sectional view of the field-effect transistor is shown here, with the z-direction being the vertical direction; the field-effect transistor has a greater extent in the xy plane (the y-direction here points into the plane of the drawing).

[0039] The following description of field effect transistors will use n-type doping as the first type of doping and p-type doping as the second type of doping. As mentioned above, the doping types can also be interchanged.

[0040] according to Figure 1 The field effect transistor 100 includes an n-doped drift layer 13 , a channel layer (a layer forming an electron channel) 12 , and a source layer 11 . The channel layer 12 and the source layer 11 can be formed on the drift layer 13 .

[0041] The drift layer 13 is applied to the drain layer 14 of the field-effect transistor 100, wherein the drain layer may also include a substrate layer, such as a semiconductor substrate. The field-effect transistor 100 also has a drain contact material layer 22, such as a drain electrode, adjacent to or in contact with the drain layer 14. The field-effect transistor 100 also has a source contact material layer 21, such as a source electrode, adjacent to or in contact with the source layer 11.

[0042] Field effect transistor 100 further comprises a gate 23, which typically comprises a gate electrode with an isolation layer or gate oxide layer (not shown separately here), by means of which the gate electrode is isolated from drift layer 13, channel layer 12, and source layer 11. Therefore, the gate or the gate electrode with the isolation layer is introduced into the gate trench.

[0043] The gate 23 can be used to switch a conductive channel on the channel layer 12 on or off. In the on state, the conductive channel allows current to flow from the source layer 11 to the drift layer 13 .

[0044] A first shielding region 31, for example a JFET region, extends into the drift layer 13, which is produced by diffusion of magnesium from a magnesium source and is also contacted, in particular, via the source electrode 21. The lower edge of this first shielding region 31 extends deeper into the drift layer 13 in the vertical direction (here in the z direction) than the lower edge of the gate 23 or the corresponding gate trench.

[0045] Since the first shielding region 31 is a p-doped semiconductor region, it has all known advantages with regard to electrical shielding of the gate 23 in the off state, short-circuit limitation in the short-circuit state, and reverse conductivity of the integrated body diode in reverse operation.

[0046] By providing shielding regions such as the shield and JFET structure 31 by diffusion of magnesium, these regions can be manufactured at lower temperatures of 1100 to 1300°C so that the above-mentioned problems of activating implanted species at 1300°C and above do not arise.

[0047] Therefore, it is advantageous to be able to manufacture shielding or JFET structures such as the first shielding region without damaging the gallium nitride surface or the entire transistor layer. Furthermore, this also enables the use of such shielding or JFET structures for gallium nitride transistors on foreign substrates.

[0048] Although according to Figure 1 The field effect transistor 100 shows a very general embodiment, but more specific embodiments will be explained below.

[0049] according to Figure 2 The field effect transistor 200 shows an implementation of a trench MOSFET with a laterally offset deep shield layer 31. In this case, the channel layer 12 is constructed as a p-type doped channel layer (p-type body layer) and is labeled 15. The source layer 11 is constructed as a heavily doped n-type. + The GaN source layer is labeled as 16 .

[0050] The gate trench penetrates the channel layer 15 and the source layer 16 and extends into the drift layer 13. The gate 23 introduced into the gate trench is exemplarily constructed as a MOS structure having a gate dielectric (e.g., a gate oxide) and a gate electrode 24, wherein the gate electrode 24 is preferably composed of polysilicon. The gate is electrically isolated from the source electrode 21 by an isolation layer or isolation dielectric 42. The source electrode 21 contacts the source layer 16 and the channel layer 15.

[0051] First shielding region 31 is offset laterally (here, in the x-direction) relative to the gate trench. It is generated by the diffusion of magnesium from a magnesium source into drift layer 13. Shielding region 31 is electrically connected to source electrode 21. In other words, shielding region 31 is at the same electrical potential as source layer 16 and channel layer 15.

[0052] The shielding region 31 extends in the component substantially in a vertical direction (here, the z direction), wherein the lower edge of the shielding region 31 extends deeper into the drift layer 13 than the bottom of the gate trench.

[0053] The magnesium concentration in the shielding region 31 is particularly higher than the magnesium concentration in the channel layer 15 (p-type body region) and the dopant concentration in the drift layer 13 (in the drift layer, for example, silicon can be used as a dopant to provide an n-type dopant). Preferably, the magnesium concentration in the shielding region 31 is higher than 1×10 18 cm -3 .

[0054] Due to this structure, when the transistor is turned off, a space charge zone is formed in the drift layer 13 essentially starting from the lower edge of the shielding region 31. This protects the gate dielectric 41 from high electric field loads and increases the reliability of the component.

[0055] As mentioned earlier, for vertical GaN power transistors, it is advantageous to create such a structure by diffused magnesium rather than implanted magnesium, as this avoids the extremely high temperatures exceeding 1300°C.

[0056] Another advantage of fabrication by diffusion is that the depth of the shielding region 31 can be adjusted very precisely via the temperature and duration of the diffusion process. Producing such a region by implantation would require extremely high implantation energies of 1 MeV and above. These process steps are particularly complex. The proposed implementation by diffusion avoids this problem. Since the diffusion coefficient of magnesium in the gallium nitride crystal is higher in the vertical

[0001] direction than in the lateral direction, such a substantially vertically extending region can be easily implemented.

[0057] The surface of the magnesium-diffused region may become rough in some cases. Since, in the proposed implementation, shielding region 31 is laterally offset relative to the gate, the surface quality of this region is not critical to the component's functionality. Alternatively, the surface can be optimized by removing the gallium nitride near the surface of the contact region, for example, using plasma etching. Consequently, shielding region 31 is located at least substantially—and in particular, even completely—next to the gate trench in the horizontal direction (but still vertically below it).

[0058] according to Figure 3 The field effect transistor 300 is shown Figure 2 A variant of the mid-trench MOSFET. Here, the shielding region 31 still extends deeper into the drift layer 13 at its lower edge than the bottom of the gate trench. However, the shielding region 31 also has a significant lateral extent, resulting in only a narrow n-conductive region in the drift layer 13 between the two shielding regions 31. Consequently, the shielding region 31 also functions as a JFET region, which limits current during a short circuit via the JFET effect. The shielding region 31 is still at least substantially located next to the gate trench in the horizontal direction and is even spaced apart from it in the vertical direction.

[0059] Optionally, the n-type doping of the drift region between the shielding regions 31 (or JFET regions) can be increased. This makes it possible to achieve a particularly advantageous compromise between low on-resistance and high component reliability in the event of a short-circuit fault, since the short-circuit current is limited by the JFET effect, but the conductivity of the JFET region remains high in the on-state due to the increased doping.

[0060] Preferably, the lateral distance (here in the x-direction) between the two shielding regions 31 below the gate trench is less than 800 nm. The possibility of using nitrogen implantation to realize such a structure will also be discussed below. Although, as mentioned above, the diffusion coefficient of magnesium in the vertical direction is greater, the nitrogen implantation can be used to realize the lateral extension of the shielding regions 31 formed by diffusion.

[0061] according to Figure 4 The field effect transistor 400 shows an implementation of a vertical power transistor having a diffused bubble shielding region 32 (hereinafter also referred to as a second shielding region). The second shielding region 32 is located vertically below the gate trench and is separated from the gate or gate electrode 24 and the gate dielectric 41 by an additional isolation dielectric or isolation layer 43.

[0062] This implementation makes it particularly advantageous to realize components with particularly small cell sizes or cell pitches, and thus with particularly low specific on-resistance. Furthermore, the gate dielectric is particularly well protected from high electric field loads. Preferably, the lateral width of the second shielding region 32 is greater than the lateral width of the gate trench. In particular, the second shielding region 32 extends at least substantially beyond the corresponding width of the gate trench in the horizontal or lateral direction.

[0063] according to Figure 5 The field effect transistor 500 shows an embodiment in which a diffused second shielding region 32 and a laterally offset first shielding or JFET region 31 are provided. This embodiment combines the Figure 3 and Figure 4 The field effect transistors 300 and 400 have advantages in terms of gate dielectric shielding, cell pitch, and short-circuit current reduction.

[0064] according to Figure 6 The field effect transistor 600 shows an embodiment of a so-called fin field effect transistor (FinMOS) with a diffused first shielding or JFET region 31. Instead of the relatively wide mesa structure consisting of the source layer 16 and the channel layer 15 (p-body region) in the above-described embodiments, narrow fins (preferably only a few hundred nanometers wide, for example less than 500 nm or less than 300 nm) are structured and surrounded on both sides by a gate or a portion of a gate (with a gate electrode 24 and a gate dielectric 41, respectively).

[0065] In this way, a particularly high channel density can be achieved, thereby reducing the specific on-resistance, and a particularly effective reduction in short-circuit current can be achieved. Due to the extremely narrow fins of several hundred nanometers, a low doping level of the channel layer 15 can be selected, because the fin effect of the double-sided gate electrodes allows the channel layer 15 or the p-type body region to be depleted even with low doping.

[0066] exist Figures 7 to 13 In FIG, the process of the method for manufacturing a field effect transistor in different embodiments is schematically shown. Figures 1 to 6 The same elements, components or layers are denoted by the same reference numerals.

[0067] exist Figure 7 , an embodiment of a manufacturing method for producing a diffused shielding region, in particular the first shielding region 31, is shown. In step 700, trenches 702 are produced at locations where the diffused shielding region will be produced later. This can be achieved, for example, by dry chemical plasma etching using a mask layer 44. The mask layer 44 can, for example, comprise or consist of silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). The trenches can, for example, be produced only very shallowly, or in extreme cases, not even at all (i.e., the mask layer is only partially removed), or the trenches can extend right into the drift layer 13.

[0068] In step 710, a magnesium source layer 33 is applied. This magnesium source layer has magnesium-providing properties. The magnesium source layer 33 can be, for example, pure magnesium, magnesium oxide, magnesium fluoride, or a magnesium-gallium nitride mixture. However, a magnesium compound free of silicon and oxygen is preferred. The magnesium source layer can be produced, for example, by sputtering or evaporation.

[0069] In step 720, magnesium is diffused from the magnesium source layer 33 into the gallium nitride layer. The diffusion can be performed at a temperature between 1100°C and 1300°C. For example, multiple temperature steps at different temperatures can also be used. During the diffusion process, magnesium diffuses preferentially in the vertical direction (here, the z-direction) and, to a lesser extent, in the lateral directions. This material-specific property is due to magnesium's higher diffusion coefficient in the vertical direction.

[0070] Here, the mask layer 44 is used to prevent magnesium diffusion so that no magnesium diffuses into the surface of the source layer 11. Advantageously, magnesium diffuses laterally from the trench sidewalls into the source layer 11 and the channel layer 12, thereby automatically placing the shielding region 31 and the channel layer 12 at the same potential.

[0071] In step 730, the magnesium source layer 33 is removed. In step 740, the mask layer 44 is removed. Both steps can be accomplished by wet chemical etching.

[0072] exist Figure 8 Another embodiment of the manufacturing method is shown in FIG. Figure 7 In addition to the mask layer 44, a spacer layer 45 is produced on the sidewalls of the trench in step 800. This can also be a dielectric, such as silicon dioxide or silicon nitride.

[0073] Such a spacer layer 45 can be produced, for example, by first depositing it uniformly over the entire structure and then removing it using a directional dry chemical etching process that primarily etches the horizontal surfaces, so that the spacer layer 45 remains on the sidewalls of the trench.

[0074] The subsequent steps 810 to 850 are the same as those in the Figure 7 The steps 700 to 740 correspond to each other, wherein the spacer layer 45 can also be removed in step 850 .

[0075] The advantage of this manufacturing variant is that the lateral diffusion can be controlled very precisely due to the well-controlled thickness of the spacer layer 45. This can be advantageous since the JFET effect in the shielding or JFET region 31 is determined by the lateral diffusion. In addition, this manufacturing measure is useful for example for Figure 4 The component shown is advantageous, for example, a field effect transistor with bubble diffusion, because no diffusion occurs on the side walls, which is obviously necessary for bubble diffusion so that it does not change the channel properties.

[0076] exist Figure 9 Another embodiment of the production method is shown in . Here, the mask layer is completely omitted, ie, after the individual layers are provided in step 900 , the magnesium source layer 33 is applied directly to the structured surface having the trenches in step 910 and diffused in step 920 .

[0077] In step 930 , the magnesium source layer 33 is removed, and the magnesium diffused into the surface of the source layer 11 is removed. This can be done, for example, by chemical mechanical polishing (CMP). This results in the shielding region 31 , step 930 .

[0078] The advantage of this manufacturing method is that the mask layer can be omitted. However, this manufacturing method is limited to shallow diffusions, because the diffusion depth must remain the same as the thickness in the source layer 11. This manufacturing method is particularly advantageous when, for depositing the mask layer 44, alignment tolerances with respect to the already existing trenches are required that are technically difficult to achieve.

[0079] Figures 7 to 9 The production variants in FIG. 1 show different possibilities for realizing the mask.

[0080] exist Figure 10 Another embodiment of a manufacturing method for controlling the diffusion profile is shown in FIG. By implanting a deeper nitrogen profile, the diffusion of magnesium, which is shallowly implanted at high concentrations into the gallium nitride layer, can be controlled. Without nitrogen implantation, magnesium diffuses deeper into the gallium nitride crystal than with nitrogen implantation. Very deep and, in particular, uncontrolled diffusion of magnesium can negatively impact component design.

[0081] exist Figure 10In the step 1000, the mask layer 44 applied is also used to produce nitrogen regions 51 in a self-aligned manner by means of nitrogen ion implantation, step 1010. Here, the nitrogen concentration of the implantation is preferably between 3×10 18 cm -3 to 3×10 19 cm -3 within the range.

[0082] The subsequent steps 1020 to 1050 are the same as those in the embodiment of the present invention. Figure 7 The distribution of the diffused shielding region 31 is substantially determined by the distribution of the nitrogen region 51 .

[0083] In the previous variants, the ratio of vertical and lateral diffusion of magnesium is determined by the diffusion coefficient. However, by means of the implantation of the nitrogen region 51, the diffusion can be better controlled. In particular, Figure 8 In combination with the spacer layer 45, the distribution of magnesium can be adjusted very flexibly.

[0084] Figures 11 to 13 Implementation methods of manufacturing methods in different implementation modes in semiconductor processes are shown, each taking a trench MOSFET as an example.

[0085] according to Figure 11 After providing the various layers in step 1100, trenches 1112 are formed for the shielding or JFET region 31 in step 1110. Shielding or JFET region 31 can then be produced according to one embodiment of the above-described fabrication method, represented here by step 1120. Gate trenches 1132 are formed in step 1130, a gate is formed in step 1140, and the transistor cell is completed in step 1150.

[0086] The advantage of this manufacturing approach is that the high-temperature process of diffusion is already completed before the gate is formed, so there are no restrictions on the maximum temperature budget of the gate. In addition, during the diffusion, the subsequent inversion channel on the sidewalls of the gate trench has not yet formed, so the risk of contamination of the channel area (on the sidewalls of the gate trench) by magnesium is low.

[0087] Another advantage is that Figure 11 As shown, shield trenches 1112 and gate trenches 1132 of different depths can be used. This allows for a very flexible adjustment of the depth of the shielding region 31. This variant can be particularly cleverly combined with the Figure 10 The mask layer used to make the shield trenches is used as an implantation mask for the nitrogen regions 51 .

[0088] exist Figure 12In the illustrated method, after the layers are provided in step 1200, gate trenches 1214 and shield trenches 1212 are simultaneously formed in step 1210. In step 1220, magnesium is diffused only in the shield trench region using a mask layer 44 (not shown here). Steps 1230 and 1240 correspond to steps 1140 and 1150.

[0089] The advantage of this variant is that there are no alignment tolerances between the gate and shield trenches, so the shield or JFET region is precisely symmetrical to the gate trench. This is beneficial for the JFET's short-circuit-limiting properties. The disadvantage is that in this case, a suitable masking layer must be used to ensure that the channel region in the gate trench is not contaminated by magnesium.

[0090] exist Figure 13 In the illustrated embodiment, after the layers have been provided in step 1300, the gate trench 1314 and the shield trench 1312 are formed simultaneously in step 1310. However, the gate or gate complex is then first produced, step 1320, and then the shield region 31 is diffused, step 1330. This is advantageous because the gate can be completely metal-free before magnesium contamination can occur. The disadvantage is that in this case the gate complex must withstand the high temperatures of magnesium diffusion. This variant can be particularly advantageous with Figure 10 The step 1340 is combined with the nitrogen implantation in the step 1150, wherein the isolation layer 42 serves as an implantation mask for the nitrogen region 51. Step 1340 corresponds to step 1150 or 1240.

[0091] exist Figure 14 In the illustrated method, after providing the various layers in step 1400, the gate trench and the gate complex are first formed in steps 1410 and 1420. Subsequently, a shielding trench is formed in step 1430, and magnesium is diffused in step 1440. This method can be advantageous when the gate formation involves a process based on the absence of other features on the wafer surface besides the gate trench. This is the case, for example, for maskless recess processing of gate trenches filled with polysilicon. Furthermore, in this variant, the entire process at the front end can also remain metal-free. Step 1440 corresponds to step 1150 or 1240.

[0092] The proposed magnesium diffusion is particularly noticeable in the product, since diffusion produces a constant magnesium concentration profile up to a certain depth, whereas during injection, the magnesium is introduced in multiple so-called injection steps, where each injection leaves an approximately Gaussian distribution, which differs from the constant distribution after diffusion.

Claims

1. A semiconductor component (100, 200, 300, 400, 500, 600), in particular a transistor, based on gallium nitride, wherein: The semiconductor component has: - a substrate layer and / or a drain layer (14); - a drift layer (13) doped with a first type of doping; - a channel layer (12, 15), said channel layer being in particular doped with the second type; - a source layer (11, 16) of a first type of doping, The channel layer is arranged between the source layer and the drift layer in a vertical direction. The semiconductor component further comprises a gate trench, which extends from the source layer (12, 15) to the drift layer (13) in a vertical direction and is adjacent to at least a portion of the channel layer (12, 15) and the source layer (11, 16). The semiconductor component further comprises one or more shielding regions (31, 32) of the second type of doping, each of which is at least partially located below the gate trench in a vertical direction and at least partially inside the drift layer (13). Wherein, one or more of the shielding areas are constructed by diffusion.

2. The semiconductor component according to claim 1, wherein One or more of the shielding regions (31, 32) are at least partially constructed from diffused magnesium.

3. The semiconductor component according to claim 1 or 2, wherein One of the shielding regions or at least one of the plurality of shielding regions is a first shielding region (32), which is at least substantially located beside the gate trench in a horizontal direction. The semiconductor component according to claim 3 , wherein: The first shielding region (31) is adjacent to the channel layer (12, 15). The semiconductor component according to claim 3 , wherein The first shielding region (31) is spaced apart from the gate trench in a vertical direction.

6. The semiconductor component according to any one of claims 3 to 5, further comprising a source contact material layer (21), wherein the source contact material layer is adjacent to the first shielding region (31).

7. The semiconductor component according to claim 6, wherein The source contact material layer (21) is also adjacent to the channel layer (12, 15) and the source layer (11, 16). The semiconductor component according to claim 3 , wherein The first shielding region (31) is adjacent to the gate trench.

9. The semiconductor component according to claim 1, wherein: One of the shielding regions or one of the plurality of shielding regions is a second shielding region (32), the second shielding region being arranged vertically below the gate trench, The semiconductor component has an isolation layer (43), which is vertically arranged between the gate trench and the second shielding region (32).

10. The semiconductor component according to claim 1, further comprising a gate electrode (24), which is introduced into the gate trench and is isolated from the drift layer (13), the channel layer (12, 15) and the source layer (11, 16).

11. The semiconductor component according to any of the preceding claims, further comprising a layer of drain contact material (22), the layer of drain contact material being adjacent to the substrate layer and / or the drain layer (14).

12. A method for producing a semiconductor component according to any one of the preceding claims, comprising the steps of: - providing a substrate layer and / or a drain layer (14); - applying a layer comprising a drift layer (13) of a first type of doping; - constructing a channel layer (12, 15) and a source layer of a first type of doping; - forming a gate trench and forming a shielding region of a second type of dopant or at least one of a plurality of shielding regions of a second type of dopant (31, 32) by means of diffusion.

13. The method according to claim 11, further comprising: - before forming one shielding region of the second doping type or at least one of a plurality of shielding regions of the second doping type, forming a shielding trench (1112, 1212, 1312).

14. The method according to claim 13, wherein: The gate trench and the shield trench are constructed together, or the gate trench is constructed first and then the shield trench, or the shield trench is constructed first and then the gate trench.

15. The method according to any one of claims 11 to 14, further comprising: The nitrogen region is formed, in particular, by implantation, wherein a screening region doped with the second type or at least one of a plurality of screening regions doped with the second type is formed in the nitrogen region by diffusion.

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