Monolithic array of semiconductor devices, template wafer, method of manufacturing template wafer, method of manufacturing array of semiconductor devices

Abstract

A monolithic array of semiconductor devices on a wafer includes a first semiconductor device occupying a first device region on the wafer, the first device region being located over a first porous region in the wafer. The first porous region has a first structure, a first porosity, and a first size. The second semiconductor device occupies a second device region on the wafer. The first semiconductor device and the second semiconductor device have the same epitaxial structure, and the second semiconductor device is not located over the porous region having the same structure, porosity, and size as the first porous region. A stencil wafer, a method of manufacturing a stencil wafer for a monolithic array of semiconductor devices, and a method of manufacturing an array of semiconductor devices are provided.

Description

Technical Field

[0001] The present invention relates to a monolithic array of semiconductor devices on a wafer, a display device including the monolithic array, a template wafer, and a manufacturing method. In particular, the present invention relates to a monolithic array of optoelectronic semiconductor devices, high electron mobility transistor devices, or radio frequency devices formed on a template wafer including an array of porous regions. Background Art

[0002] III-V semiconductor materials are particularly important for semiconductor device design, especially the III-nitride semiconductor material family.

[0003] “III-V” semiconductors include binary, ternary, and quaternary alloys of Group III elements (such as Ga, Al, and In) with Group V elements (such as N, P, As, and Sb), and have attracted great attention in many applications such as electronics and optoelectronics.

[0004] Of particular interest is a class of semiconductor materials known as "Group III nitrides," which include gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), as well as their ternary and quaternary alloys. (Al,In)GaN is a term encompassing AlGaN, InGaN, and GaN. Group III nitride materials have not only achieved commercial success in solid-state lighting and power electronics but also demonstrated unique benefits in quantum light sources and light-matter interactions.

[0005] Even though various Group III nitride materials are of commercial interest, gallium nitride (GaN) is widely considered to be one of the most important new semiconductor materials and is receiving particular attention in many application areas.

[0006] The present invention will be described primarily with reference to GaN and InGaN, but may be advantageously applied to alternative Group III nitride material combinations.

[0007] It is well known that the introduction of voids into bulk III-nitrides (such as GaN) can have a profound impact on their material properties (optical, mechanical, electrical, and thermal). Therefore, the possibility of tuning a wide range of material properties of GaN and III-nitride semiconductors by modifying their porosity has attracted great attention in the field of optoelectronic applications.

[0008] The present inventors have also discovered that by using a porous III-nitride material as a substrate or template to achieve overgrowth of additional semiconductor layers and semiconductor devices, beneficial properties such as strain relaxation can be imparted to the overgrown device through the porous layer. However, after the desired overgrowth of the semiconductor device, it may be desirable to remove the semiconductor device from the porous template and transfer the semiconductor device to another carrier for fabrication into an electronic or optoelectronic device. The present invention is directed to facilitating the safe and reliable removal of semiconductor devices from the substrate on which the semiconductor device was grown.

[0009] In the present invention, according to the description in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728), a region or layer of semiconductor material can be made porous by electrochemical etching.

[0010] Problems that need to be solved

[0011] Integrating different semiconductor devices or components into an integrated end product is a major challenge in device manufacturing.

[0012] To manufacture integrated semiconductor devices, in which multiple different types of semiconductor devices (e.g., multiple LEDs emitting different colors) are integrated onto a single device chip, it is typically necessary to grow each of the different semiconductor devices separately on its own template wafer, typically using different semiconductor materials. The different semiconductor devices can then be removed from their growth templates and integrated onto a shared carrier wafer before the shared wafer is processed into an end product. For example, it is often desirable to integrate multiple different LED types emitting at different peak emission wavelengths onto a single carrier wafer for the manufacture of a multi-color display device.

[0013] To avoid the complexity and cost of separate growth, transfer, and integration steps, it is highly desirable to manufacture all required semiconductor devices monolithically—that is, on the same wafer template. After epitaxial growth of the different semiconductor devices on the wafer, the required devices will already be located at the desired locations on the shared wafer, where they need to be processed into the final product. This would eliminate the need to grow individual devices separately and transfer them to a shared wafer, thereby speeding up device manufacturing and reducing cost and complexity.

[0014] Because conventional III-nitride LEDs (standard LEDs, mini-LEDs, micro-LEDs, and nano-LEDs) can only emit one color at a time, there is currently no viable monolithic integration method available for display or other light-emitting applications. This means that for multicolor light-emitting devices, multiple single-color LEDs with different epitaxial structures, often formed from different semiconductor materials, have to be fabricated separately and then integrated onto a shared wafer.

[0015] For "large" (not mini, micro, or nano) LEDs, there are packaging innovations that allow three separate LEDs emitting red (R), green (G), and blue (B) light to be packaged into a single die or package, or three packaged R, G, and B LEDs to be mounted on the same printed circuit board (PCB) or circuit board. These red, green, and blue LEDs can be made of the same material system or different material systems. For example, the red, green, and blue LEDs can be based on gallium nitride, AlInGaP, or gallium arsenide.

[0016] For mini LEDs, similar to "big" LEDs, mini LEDs of different colors can be packaged together using mass transfer or pick & place technology, where LED chips of different colors are integrated, mounted or packaged on the same circuit of a single die.

[0017] For Micro-LEDs, due to the small size of Micro-LEDs and the required pixel density, the above packaging, mounting or mass transfer / pick & place methods cannot work well with reasonable yield and cost-effectiveness.

[0018] The key issue is that conventionally, a single LED epitaxial layer or LED chip can only produce an LED that emits a single color, and heterogeneous integration of multiple individual chips is already very difficult and complex. In addition, red LEDs and blue-green LEDs are usually grown from different semiconductor materials, which requires different lift-off processes and makes the integration of different colors difficult.

[0019] Efforts have been made to demonstrate all three RGB color (red, green, and blue) LEDs on the same substrate / wafer, using the following approach:

[0020] 1. Selective area epitaxy or nanowire / nanorod / nanocone / nanosheet method - by changing the mask / window (usually with dielectric materials such as SiO2 or SiN × The size of the opening (used as a mask) is used to limit the selective area of ​​LED epitaxy and control the size of the nanostructure, thereby controlling the multiple quantum wells (MQW) and indium content (In%) on the sidewall or surface of the nanostructure to emit light of different colors.

[0021] 2. Stacking method, using vertical stacking or horizontal stacking:

[0022] Vertical stacking involves fabricating R, G, and B LEDs (of any size) (the R, G, and B LED epitaxy / materials can be obtained from the same or different material systems), processing and singulating the LEDs, and simultaneously grinding, polishing, thinning, and removing the original substrate. Each color LED is then stacked one on top of the other to form a pixel. Given that all R, G, and B LED epitaxy must be fabricated on a foreign substrate and the active LED pn junction is an extremely thin layer, the process is extremely complex and yields very low. These shortcomings make this method unsuitable for commercial device manufacturing. Furthermore, the technology can lead to issues with light being absorbed by the LEDs, as the vertical stacking of the R, G, and B LEDs can cause issues with optical performance and crosstalk between different pixels. Each color LED has completely different optical and electrical properties, and each LED requires its own electrical contacts, making the technology even more difficult. Overall, the vertical stacking integration process is extremely complex and, at least not suitable for display applications.

[0023] Lateral stacking – Similar to mass transfer processes, each R, G, and B LED needs to be stacked / transferred side by side laterally in a sub-pixel format, one color after the next. This technique results in the same issues as complex processing, low yield, and defects caused by combining LEDs with different characteristics.

[0024] Therefore, monolithic integration of RGB LEDs on the same wafer presents numerous challenges and requires improvements in many areas. Yield losses in existing technologies result in high manufacturing costs. It would be desirable to be able to manufacture monolithic integrated devices using simple epitaxy without the need for transfer / stacking / selective area epitaxy, as this would result in lower costs and higher yields in the integrated end product. Display applications require high performance and color uniformity. For display applications, system integration, and power management, it is also beneficial for different semiconductor devices on the integrated wafer to have similar optical and / or electrical characteristics.

[0025] The present invention aims to solve these problems and provide a manufacturing method with high yield and simple process in the entire display manufacturing process.

[0026] To simplify LED manufacturing processes and reduce mass production costs, Poro Technologies has released LEDs with an embedded nanoporous architecture that enables GaN-based LEDs to output a full color gamut. These LEDs are described in international patent applications PCT / GB2021 / 050152 (published as WO2021 / 148808) and PCT / GB2021 / 052020 (published as WO2022 / 029434). Summary of the Invention

[0027] In the present invention, the embedded patterned nanoporous architecture enables the monolithic integration of multiple different semiconductor devices on a single wafer. For example, the present invention enables the monolithic integration of multiple LEDs with different emission colors (different peak emission wavelengths) on a single semiconductor wafer.

[0028] The present invention is defined by the independent claim, to which reference should now be made. Preferred or advantageous features of the invention are set out in the dependent claims.

[0029] In a first aspect of the present invention, a monolithic array of semiconductor devices on a wafer is provided, comprising: a first semiconductor device occupying a first device region on the wafer, the first device region being directly above or above a first porous region in the wafer, the first porous region having a first structure, a first porosity, and a first size; and a second semiconductor device occupying a second device region on the wafer. The first semiconductor device and the second semiconductor device may have the same epitaxial semiconductor device structure, and the second semiconductor device is not located above a porous region having the same structure, porosity, and / or size as the first porous region.

[0030] The first semiconductor device and the second semiconductor device may have the same epitaxial device structure, but respond differently in response to the same driving conditions. The first semiconductor device and the second semiconductor device may have the same layered structure. The presence of a porous region of the underlying semiconductor material may affect the composition of the overlying grown device, for example by changing the indium incorporation (or incorporation of other elements) in the active region of the device located above the porous region during the epitaxial growth of the device. Therefore, even if the two devices are formed in the same epitaxial, the chemical composition of the active region in the first semiconductor device may be slightly different from the chemical composition of the active region in the second semiconductor device. The porous region may also affect the layer thickness of the active region of the device, resulting in a slight difference in layer thickness between the first semiconductor device and the second semiconductor device.

[0031] As described in detail below, the first semiconductor device and the second semiconductor device are preferably formed simultaneously on a wafer using a single epitaxial deposition process, so that the two semiconductor devices have the same epitaxial structure. Therefore, the number of layers, layer thickness, and layer composition of the device structure of the first semiconductor device and the second semiconductor device are preferably the same.

[0032] The first semiconductor device and the second semiconductor device may differ in lateral shape and size because the first device region may differ in size and shape from the second device region.

[0033] Because the wafer designs underlying the first and second semiconductor devices are different, the unique electronic and / or optical properties of the first and second semiconductor devices will be different even though the semiconductor structures include the same device structure.

[0034] The inventors have discovered that the electronic and / or optical performance of a semiconductor device is affected by growing the device on top of an underlying porous region. When a semiconductor device is epitaxially grown on top of a porous region of semiconductor material, the crystal structure of the overgrown device inherits certain properties of the underlying porous material, meaning that the device will exhibit different characteristics from the same device structure grown on top of a non-porous material. Differences in the properties of the underlying porous region (e.g., variations in porosity, thickness, and lateral dimensions of the porous region) can have different effects on the overlying structure, so growing the same device structure on top of two different porous regions (or one porous region and one non-porous region) will produce two devices that behave differently.

[0035] Benefits provided to semiconductor devices by overlying growth over the porous region include strain relaxation, lattice parameter expansion, reduced wafer warpage, and favorable mechanical and thermal effects during growth of the light emitting region at high temperatures.

[0036] The removal of dislocations from the semiconductor material in the porous region during the porosification process significantly reduces the strain in the porous region of the wafer. Epitaxially grown semiconductor structures contain strain, which can be increased if the layered structure contains layers of different compositions because the mismatch in the lattice dimensions of the different layers results in increased strain in the crystal structure. The inventors have discovered that forming pores in the region of the structure can significantly reduce the strain in the structure by removing dislocations and increasing the compliance of the remaining porous region. Therefore, when a semiconductor device structure is epitaxially grown on top of the porous region, the porous material is more easily adapted to lattice matching of the overlying device structure and any intermediate layers. This results in the strain experienced by the overlying grown semiconductor device being significantly lower than if the same device structure were deposited on a completely non-porous wafer.

[0037] Since the semiconductor device formed on the porous region experiences lower strain, there are fewer structural defects in the device structure that serve as non-radiative recombination centers and impair device performance.

[0038] The first semiconductor device is preferably formed over the first porous region during fabrication, such that the first porous region influences the structural and mechanical properties of a semiconductor layer epitaxially deposited over the porous region. During growth, the semiconductor material layer deposited over the porous region experiences benefits such as reduced strain, expanded lattice parameters, and reduced wafer warpage, which are imparted to the active region of the device and influence its structure and its electronic and / or light-emitting behavior.

[0039] Once a semiconductor device is epitaxially grown on the porous region and the quality of the active region of the device is enhanced by the influence of the porous region, the beneficial effect of the porous region on the device properties is permanently imparted to the semiconductor device.

[0040] For example, the inventors have discovered that growing an LED structure on a porous region of a Group III nitride material results in a significant shift in emission wavelength toward longer wavelengths compared to the same LED structure grown on a non-porous substrate.

[0041] The inventors demonstrated this in the following ways: they grew a conventional green / yellow light (emitting in the range of 500nm-570nm or 570nm-590nm) InGaN LED structure on a non-porous GaN wafer and proved that the LED emitted green / yellow light as expected; they grew the same "green / yellow light" InGaN LED structure on a template containing a porous region, and when an electrical bias was applied across the LED, the LED emitted red light in the range of 600nm-750nm.

[0042] By providing a monolithic array of semiconductor devices in which one or more first semiconductor devices are located above a first porous region and one or more second semiconductor devices are not located above the same porous region, the first semiconductor devices and the second semiconductor devices can behave differently in use even if they have the same device structure. This advantageously allows arrays of semiconductor devices with different performance characteristics (e.g., LEDs emitting at different peak wavelengths) to be manufactured as a monolithic array in a single step, without the transfer and re-spacing steps required in the prior art.

[0043] By controlling the presence or absence of an underlying nanoporous region in the wafer beneath the semiconductor device, and by controlling the size and porosity of the porous region where it exists, the present invention enables the monolithic production of semiconductor devices with different properties on the same wafer using only a single epitaxial growth process. For example, in a preferred embodiment, by overlying LEDs of different colors on different porous / non-porous regions of the wafer, LEDs emitting different colors can be formed on the same wafer using a single epitaxial growth process for all LEDs.

[0044] The first semiconductor device is located above the first porous region due to the presence of the porous region below the first semiconductor device when the first semiconductor device is overlying the first device region. By overlying the first semiconductor device above the first porous region, the inventors discovered that the first semiconductor device will be affected by the underlying first porous region because the crystal structure of the first semiconductor device inherits certain properties of the underlying porous material, which affect the performance of the first semiconductor device. The characteristics of the porous region (including the first porosity and first size (thickness and / or lateral size) of the first porous region) affect the crystal structure of the overlying first semiconductor device, thereby affecting its behavior.

[0045] However, the second semiconductor device is not overlyingly grown on the porous region having the same properties as the first porous region.

[0046] A second semiconductor device may be overlyingly grown on a second region of the wafer that does not have the same properties as the first porous region. The second region may be non-porous or porous, but the porous second region differs from the first porous region in some respects. For example, the second region may be a second porous region of a Group III nitride material. The second porous region may have a different thickness, and / or a different composition, and / or a different structure (e.g., a different sequence of material layers), and / or a different average pore size, and / or a different porosity percentage compared to the first porous region. If one or more of these parameters are different in the second porous region compared to the first porous region, the properties imparted to the overlying second semiconductor device will be different from the properties imparted to the first semiconductor device by the first porous region.

[0047] The second semiconductor device may be located on a second porous region having the same structure and porosity as the first porous region but a different thickness. Alternatively, the second semiconductor device may be located on a second porous region having the same structure and size as the first porous region but a different porosity percentage or average pore size.

[0048] In a first preferred embodiment, the second semiconductor device may be formed on a second porous region that is different from the first porous region (e.g., a second porous region having a different porosity and / or size than the first porous region). In this case, the different porosity and / or size of the second porous region will have a different effect on the overlying second semiconductor device than the first porous region has on the first semiconductor device. Therefore, even if the device structures are the same, the electronic and / or optical properties of the second semiconductor device will be different from those of the first semiconductor device.

[0049] Alternatively, in a second preferred embodiment, the second semiconductor device may not be located above the porous region. In other words, the wafer may be completely non-porous below the second device region. In this embodiment, the second semiconductor device is grown overlying the non-porous portion of the wafer, with no porous material located below the second device region. Thus, the electronic and / or optical properties of the second semiconductor device are not affected by the presence of any porous region below the device. Therefore, even if the device structures are identical, the electronic and / or optical properties of the second semiconductor device will differ from those of the first semiconductor device because the first semiconductor device is affected by the underlying porous material while the second semiconductor device is not.

[0050] chip

[0051] The wafer preferably includes a substrate and a plurality of layers of semiconductor material on the substrate.

[0052] Preferably, all semiconductor materials used in the present invention are Group III nitride semiconductor materials. Therefore, the wafer preferably comprises multiple layers of Group III nitride semiconductor materials on a substrate. Each semiconductor layer in the wafer (excluding the substrate) is preferably formed from one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0053] The substrate can be silicon, sapphire, SiC, or β-Ga2O3. The crystal orientation of the substrate can be polar, semi-polar, or non-polar. The thickness of the substrate can typically vary from 100 μm to 1500 μm. Wafers can have various sizes, such as 1 cm 2 , or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, 16 inches in diameter or larger.

[0054] The wafer may also be referred to as a template because the multilayer semiconductor wafer serves as a template for overlying growth during the fabrication process.

[0055] Each porous region is preferably formed in a sub-surface layer of the wafer. The porous region may be located in a layer of semiconductor material between a non-porous surface layer of the wafer and the substrate. Preferably, the first semiconductor device and the second semiconductor device are located on the non-porous surface layer of the wafer.

[0056] The array may include electrical contacts operably coupled to the first semiconductor device and the second semiconductor device such that the first semiconductor device and the second semiconductor device may be independently driven by a power source.

[0057] First porous zone

[0058] The first porous region preferably occupies a portion of the semiconductor material layer in the wafer, particularly preferably a portion of the subsurface layer.

[0059] The first porous area preferably does not occupy the entire layer of the wafer because the first porous area is not located below the second semiconductor device. When viewed from above in plan view, the first porous area preferably occupies a discrete portion of the wafer footprint. When the wafer includes a plurality of first porous areas (e.g., an array of first porous areas), the array of first porous areas occupies an array of discrete portions of the wafer footprint. The wafer can be patterned to form the array of first porous areas. Preferably, each first porous area is surrounded by non-porous semiconductor material in the same layer and above and below the first porous area.

[0060] The first semiconductor device is preferably grown on a semiconductor wafer template comprising the first porous region. The semiconductor wafer template may also comprise a plurality of semiconductor material layers arranged to provide a suitable substrate for the overlying growth of the device structure.

[0061] The thickness of the first porous region may be at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the thickness of the porous region may be between 1 nm and 10,000 nm.

[0062] The porosity of the first porous zone may be between 1% and 99%, or between 10% and 80%, or between 20% and 70%, or between 30% and 60%.The porosity of the first porous zone may be measured as a percentage of the total pore volume relative to the entire first porous zone volume.

[0063] The degree of porosity has been found to affect the performance characteristics of overlying semiconductor devices, such as the magnitude of the wavelength shift induced by the porous region. Generally speaking, the higher the porosity percentage, the greater the wavelength shift of the LED compared to the same LED structure formed on a non-porous template.

[0064] The first porous region is preferably formed of one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0065] Second porous zone

[0066] In a first preferred embodiment, a second semiconductor device is located above a second porous region of the wafer. The second porous region may have a second porosity that is different from the first porosity and / or a size that is different from the first size. Therefore, the second porous region is different from the first porous region, which means that the performance of the second semiconductor device grown overlying the first porous region will be different from that of the first semiconductor device formed above the first porous region.

[0067] The second porous area occupies a part for the semiconductor material layer in the wafer, particularly preferably occupies a part for subsurface layer.Preferred second porous area and first porous area are positioned in the same wafer layer.The second porous area and first porous area preferably occupy different lateral positions in the wafer, so that the first semiconductor device and the second semiconductor device on the first device area and the second device area cover their own corresponding porous area separately.

[0068] The second porous area preferably does not occupy the entire layer of the wafer, so the second porous area is located below the second semiconductor device but not below the first semiconductor device. When viewed from above in plan view, the second porous area preferably occupies a discrete portion of the wafer footprint. When the wafer comprises a plurality of second porous areas (e.g., an array of second porous areas), the array of second porous areas occupies an array of discrete portions of the wafer footprint. The wafer can be patterned to form the array of second porous areas. Preferably, each second porous area is surrounded by non-porous semiconductor material in the same layer and above and below the second porous area.

[0069] The second semiconductor device is preferably grown on the semiconductor wafer template including the second porous region.

[0070] The second porous region may have a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the second porous region may have a thickness between 1 nm and 10,000 nm.

[0071] The second porous region may have a second thickness that is different from the thickness of the first porous region. The thickness of the second porous region may be greater than or less than the thickness of the first porous region. The lateral dimensions of the second porous region may be different from the lateral dimensions of the first porous region.

[0072] The first porous region may have a first shape, and the second porous region may have a second shape different from the first shape.

[0073] The porosity of the second porous zone may be between 1% and 99%, or between 10% and 80%, or between 20% and 70%, or between 30% and 60%.The porosity of the second porous zone may be measured as a percentage of the total pore volume relative to the total volume of the second porous zone.

[0074] The degree of porosity has been found to affect the performance characteristics of overlying semiconductor devices, such as the magnitude of the wavelength shift induced by the porous region. Generally speaking, the higher the porosity percentage, the greater the wavelength shift of the LED compared to the same LED structure formed on a non-porous template.

[0075] The second porous region can have a higher or lower porosity percentage than the first porous region.The second porous region can comprise a smaller average pore size or a larger average pore size than the first porous region.

[0076] The second porous region is preferably formed of one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0077] The porosity of each porous region may be between 1% and 99% porosity, preferably between 20% and 90% porosity or between 30% and 80% porosity.

[0078] The thickness of each porous region may be greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm.

[0079] Each porous region may include a continuous porous Group III nitride material layer segment occupying a portion of a wafer layer that also includes non-porous Group III nitride material segments and / or porous Group III nitride material segments having different porosities.

[0080] Each porous region may include a single layer segment of porous GaN, or a single layer segment of porous InGaN, or a stack including one or more layers of porous GaN and / or one or more layers of porous InGaN.

[0081] A second semiconductor device on the non-porous region

[0082] In a second preferred embodiment, the second semiconductor device is not located above the porous region. In other words, the footprint of the wafer directly below the second device region is non-porous throughout its thickness. There may be no porous semiconductor material located directly between the wafer substrate and the second semiconductor device.

[0083] In this embodiment, the second semiconductor device is overlyingly grown on the non-porous portion of the wafer, and no porous material is located beneath the second device region. Therefore, the electronic and / or optical properties of the second semiconductor device are not affected by the presence of any porous region beneath the device. Therefore, even if the device structures are identical, the electronic and / or optical properties of the second semiconductor device will be different from those of the first semiconductor device because the first semiconductor device is affected by the underlying porous material while the second semiconductor device is not.

[0084] Other semiconductor devices

[0085] In addition to the first semiconductor device and the second semiconductor device on the wafer, the monolithic array may include one or more additional semiconductor devices.

[0086] The monolithic array may include a third semiconductor device, which also has the same semiconductor device structure as the first semiconductor device and the second semiconductor device. The third semiconductor device may occupy a third device area on the wafer, and the third semiconductor device is not located on a porous area having the same porosity and size as the first porous area. This means that the performance of the third semiconductor device will be different from that of the first semiconductor device under the same driving conditions. The third semiconductor device may be located on a third porous area, the third porous area having a porosity different from the first porosity and / or a third size different from the first size of the first porous area. In an embodiment where the second semiconductor device is located on the second porous area, the third porous area may have a third porosity different from the second porosity and / or a third size different from the second size of the second porous area. Alternatively, in an embodiment where the second semiconductor device is located on the second porous area, the third semiconductor device may not be located on any porous area.

[0087] The portion of the wafer below the third semiconductor device should have different porosity characteristics than the portions of the wafer below the first and second semiconductor devices, thereby causing the characteristics of the third semiconductor device to be different from the characteristics of the first and second semiconductor devices.

[0088] Advantageously, the first semiconductor device, the second semiconductor device, and the third semiconductor device may have the same device structure but respond differently in response to the same driving conditions.

[0089] In a preferred embodiment, for example, the first semiconductor device, the second semiconductor device, and the third semiconductor device may be red, green, and blue light emitting LEDs, and form pixels of a display device.

[0090] The monolithic array can include additional semiconductor devices (e.g., a fourth semiconductor device or a fifth semiconductor device) having the same semiconductor device structure on the wafer over portions of the wafer having different porosity characteristics. By controlling the porosity characteristics (e.g., the porosity percentage, pore size, and size of different porous regions in the wafer), any number of semiconductor devices having different operating characteristics can be provided by epitaxy of a single device.

[0091] Array of a plurality of first semiconductor devices and a second semiconductor device

[0092] In a particularly preferred embodiment, the monolithic array comprises an array of a plurality of first semiconductor devices on a wafer, positioned above a corresponding array of first porous regions in the wafer; and an array of a plurality of second semiconductor devices on the wafer.

[0093] A second array of semiconductor devices may be located above a corresponding array of second porous regions in the wafer.

[0094] Alternatively, each second semiconductor device in the array is not located over a porous region of the wafer.Each second semiconductor device in the array may be located over a non-porous region of the wafer.

[0095] The monolithic array may optionally include an array of a plurality of third semiconductor devices on the wafer overlying a corresponding array of third porous regions in the wafer, the third porous regions having different porosity characteristics than the first porous regions.

[0096] semiconductor devices

[0097] The present invention is not limited to a particular semiconductor device, as a variety of electronic and optoelectronic semiconductor device structures are known in the art, and the effects of the present invention can be achieved using a variety of conventional semiconductor device types and structures.

[0098] Regardless of the type of device formed on the wafer, if a first device and a second device are formed over regions with different porosity characteristics, the electronic and / or optical properties of the devices will be different even if their epitaxial device structures are the same.

[0099] The first semiconductor device may have a different size, shape, and / or geometry than the second semiconductor device. For example, the area of ​​the first device may be larger than the area of ​​the second device, such that the first semiconductor device has a larger lateral dimension than the second semiconductor device. When the first and second semiconductor devices are optoelectronic devices such as LEDs, for example, the lateral dimension of the LED may affect its brightness and, optionally, the wavelength emitted by the LED. Therefore, it may be desirable to have sub-pixels of different semiconductor devices have different sizes to compensate for differences in brightness at different emission wavelengths.

[0100] In a preferred embodiment, the semiconductor device structure is an optoelectronic device structure, such as a light emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL), so that the first semiconductor device and the second semiconductor device are both optoelectronic devices.

[0101] Alternatively, the semiconductor device structure may be an electronic or electrical component, such as a high electron mobility transistor (HEMT) or a radio frequency (RF) device. The semiconductor device structure may be a high electron mobility transistor (HEMT), such that both the first semiconductor device and the second semiconductor device are HEMTs; or the semiconductor device structure may be an RF device, such that both the first semiconductor device and the second semiconductor device are RF devices.

[0102] Particularly preferably, the semiconductor device structure is an LED structure, such as a mini-LED, micro-LED, or nano-LED structure. The LED may include a light-emitting region, which preferably includes a multiple quantum well (MQW) containing multiple quantum wells (QWs), or quantum dots, quantum wires, or other quantum nanostructures.

[0103] The LED includes an n-doped portion, a p-doped portion, and a light emitting region between the n-doped and p-doped portions, the light emitting region including a light emitting layer that emits light at a peak emission wavelength under an electrical bias applied across the light emitting region.

[0104] The lateral dimensions (width and length) of the light-emitting area and / or LED can be greater than 100 μm and less than 300 μm. In this case, the LED can be referred to as a "mini-LED." In preferred embodiments, the mini-LED can be square, round, or square with rounded corners, with dimensions such as 300 μm x 300 μm, 200 μm x 200 μm, or 100 μm x 100 μm.

[0105] Alternatively, the lateral dimensions (width and length) of the light-emitting area and / or LED may be less than 100 μm. In this case, the LED may be referred to as a "micro-LED." The lateral dimensions of the micro-LED may preferably be less than 80 μm, 70 μm, 60 μm, 50 μm, 30 μm, 25 μm, 20 μm, 15 μm, 10 μm, 5 μm, 3 μm, or 2 μm.

[0106] In a preferred embodiment, the micro-LED may be square, round or rounded square, with dimensions of, for example, 75μm×75μm, 50μm×50μm, 40μm×40μm, 30μm×30μm, 25μm×25μm, 20μm×20μm, 10μm×10μm, 5μm×5μm, 2μm×2μm, 1μm×1μm, 500nm×500nm or smaller.

[0107] Alternatively, the lateral dimensions (width and length) of the light emitting area and / or LED may be less than 1 μm. In this case, the LED may be referred to as a "nano-LED." The lateral dimensions of the nano-LED may preferably be less than 500 nm, 200 nm, 100 nm, or 50 nm.

[0108] The shape of the LED can be circular, triangular, rectangular, square, oval, diamond, hexagonal, pentagonal, and any combination thereof. In the case of irregularly shaped pixel designs, at least one dimension should fall within the above-defined dimensions in order for the LED to be classified as a mini-LED or micro-LED. For example, the width or diameter of the LED is preferably less than 100 μm for the LED to be classified as a micro-LED.

[0109] Preferably, the first semiconductor device and the second device are both LED sub-pixels, so that the first semiconductor device and the second semiconductor device constitute a device pixel.

[0110] The semiconductor device structure may be a single emission wavelength LED structure such that the first semiconductor device and the second semiconductor device are LEDs that emit light at a single peak emission wavelength in response to a drive current.

[0111] In a preferred embodiment, the first semiconductor device may be an LED that emits light at a first peak wavelength in response to a first drive current, and the second semiconductor device may emit light at a second peak wavelength different from the first peak wavelength in response to the same first drive current. As described above, this difference in emission characteristics is caused by the different porosity characteristics of the crystalline segments overlying the first and second devices. This is because the presence, porosity, and size of the porous region can affect the crystal structure and emission behavior of any overlying LED.

[0112] In a particularly preferred embodiment, the first semiconductor device is an LED located above the first porous region, and the second semiconductor device is an LED not located above the porous region. The first semiconductor device, LED, emits red light in response to a drive current, while the second semiconductor device, LED, emits green / blue light in response to the same drive current. A single LED semiconductor structure (corresponding to a conventional green / blue LED design) can therefore provide two different emission colors when a single epitaxial growth is performed on a monolithic wafer simply by overlying the first LED above the porous region and not overlying the second LED above the porous region. The presence of the first porous region below the first LED causes the conventional peak emission wavelength of the LED structure to red-shift, so that the second LED emits light at the desired emission wavelength, while the first LED emits light at a longer, red emission wavelength.

[0113] Variable wavelength LED

[0114] In another preferred embodiment, the first and / or second semiconductor devices may be variable-wavelength LEDs configured to emit a variable peak emission wavelength in response to changes in the drive current supplied to the LEDs. Thus, in addition to variations in peak emission wavelength resulting from differences in the porosity characteristics of the wafer segments underlying the first and second semiconductor devices, the emission wavelength of one or both LEDs may be adjusted by supplying different drive currents to the LEDs.

[0115] The variable wavelength light emitting diode (LED) preferably comprises:

[0116] n-doped part;

[0117] p-doped part;

[0118] a light emitting region between the n-doped portion and the p-doped portion, the light emitting region including a light emitting layer that emits light at a peak emission wavelength when an electrical bias is applied across the light emitting region;

[0119] The LED is configured to receive a power supply, wherein the peak emission wavelength of the LED can be continuously controlled within the emission wavelength range by varying or controlling the power supply. The peak emission wavelength of the variable wavelength LED is preferably continuously controllable or continuously variable within the emission wavelength range of at least 40 nm by varying or controlling the power supply.

[0120] Since the peak emission wavelength of a variable wavelength LED is preferably continuously controllable or continuously variable within the emission wavelength range, the LED may be referred to as a variable wavelength LED.

[0121] The variable wavelength emission behavior of the LED structure is achieved by the fact that the LED structure (n-doped portion, light-emitting region, and p-doped portion) is grown on a template containing a porous region. The inventors have discovered that the presence of a porous region of the Group III nitride material in the template structure before the overlying growth of the LED structure leads to higher quality crystal growth, thereby obtaining significant benefits, including the possibility of changing the emission wavelength of the LED light-emitting region. The mechanism by which the porous region enables the LED to achieve variable wavelength emission is still under investigation. The benefits provided by the porous region to the LED include: strain relaxation, lattice parameter expansion, reduced wafer warpage, and mechanical and thermal effects when growing the light-emitting region at high temperatures.

[0122] Therefore, the first semiconductor device can be a variable-wavelength LED because it is grown overlying the porous region of semiconductor material. In embodiments that include a second porous region, the second semiconductor device can also be a variable-wavelength LED. If the second semiconductor device is not formed over the second porous region, it would not inherit the crystal structure features that enable the LED to emit light across a range of wavelengths.

[0123] The variable wavelength LED is configured to receive power or drive current from a power supply or LED driver. "Power supply" herein refers to the power or current provided to drive the LED during use.

[0124] The peak emission wavelength of the LED is preferably continuously controllable or continuously variable within the emission wavelength range by varying or controlling the amplitude of the drive current supplied to the variable wavelength LED.

[0125] In conventional LED devices, changes in the drive current supplied to the LED produce only minimal shifts in the emission wavelength. However, the present inventors have discovered that, compared to conventional LED materials, this wavelength shift can be broadened and controlled to a much greater extent. Compared to the several nanometers of emission range of prior art devices, the LEDs of the present invention can be controlled to emit light over a much wider range (e.g., at least 40 nm). Because the present LEDs can be tuned to emit light over such a wide wavelength range, they are referred to as variable-wavelength LEDs.

[0126] The LED may be a dynamically color tunable LED, whose peak emission wavelength is adjustable by changing the driving conditions provided to the LED by a power supply.

[0127] Preferably, an LED can emit light at a single peak emission wavelength in response to a stable power supply, but can also emit light at different peak emission wavelengths in response to changes in the power supply. Thus, an LED can be used to emit light of a specific color for a long period of time, or it can be configured to emit light of various wavelengths by providing varying driving conditions.

[0128] Preferably, the n-doped part, the p-doped part and the light emitting region all comprise or consist of a Group III nitride material (preferably GaN, InGaN, AlGaN or AlInGaN).

[0129] The variable wavelength LED preferably comprises a single epitaxially grown diode structure comprising an n-doped portion, a p-doped portion and a light emitting region. Thus, all variable peak emission wavelengths of the LED are generated by the same LED diode structure and composition.

[0130] The LED preferably includes a porous region of a Group III nitride material. The light-emitting region of the LED is preferably formed above the porous region of the Group III nitride material. In some embodiments, either the n-doped portion or the p-doped portion may include the porous region of the Group III nitride material. In other embodiments, the n-doped portion, the p-doped portion, and the light-emitting region are disposed on a substrate comprising the porous region of the Group III nitride material. During epitaxial growth of the LED, the light-emitting region is preferably grown overlying the porous region after formation.

[0131] The present inventors have discovered that porous regions of Group III nitride materials can enable the same LED to emit light at a range of peak emission wavelengths, rather than at a single, specific wavelength. By varying the power supply provided to the LED, the LED's peak emission wavelength can be varied across the emission wavelength range. Thus, the present invention provides a variable-wavelength LED that can be controlled to emit light at any wavelength across a continuous range of emission wavelengths. By varying the driving conditions provided to the LED by the power supply, the LED can be configured to emit light at any wavelength within the LED's emission wavelength range, rather than being limited to a discrete peak emission wavelength.

[0132] The inventors have discovered that the ability to enable LEDs to emit light at wavelengths tunable across a wide emission range can be achieved by integrating a porous region of a Group III nitride semiconductor material into the LED structure or forming the LED diode structure on a porous region of a Group III nitride semiconductor material. The benefits provided by the porous region to the LED include strain relaxation, lattice parameter expansion, reduced wafer warpage, and favorable mechanical and thermal effects when growing the light-emitting region at high temperatures.

[0133] During fabrication, the light-emitting region of the LED is preferably formed above a porous region of Group III nitride material, allowing the porous region to influence the structure and mechanical properties of the semiconductor layer epitaxially deposited thereon. The semiconductor material layer deposited above the porous region during growth can benefit from reduced strain, expanded lattice parameters, and reduced wafer warpage, which are then imparted to the light-emitting region of the LED and influence its structure and light-emitting behavior.

[0134] Once the epitaxial growth of the LED light-emitting (active) region is completed on the porous region, and the influence of the porous region improves the quality of the active region, the beneficial effect of the porous region on the light-emitting properties of the LED is permanently imparted to the active region. Therefore, the LED diode structure can remain on the porous region (in this case, the variable wavelength LED includes a porous region of Group III nitride material), or alternatively, the porous region can be removed from the LED structure during the processing of the LED into a device after epitaxial growth.

[0135] The width of the emission wavelength range can vary depending on the structure and composition of the LED structure (n-doped portion, light-emitting region, and p-doped portion), as well as the structure and porosity of the porous region. The width of the emission wavelength range can also vary depending on the size and shape of the LED (pixel size and shape).

[0136] In a preferred embodiment, the peak emission wavelength can be controlled within an emission wavelength range of at least 40 nm, 50 nm, 60 nm, 70 nm, or 80 nm by varying the power supply. Preferably, the peak emission wavelength can be controlled within an emission wavelength range of up to 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 400 nm, or 450 nm. Thus, the emission wavelength range achievable by the LED of the present invention is far greater than the emission range achievable by prior art LEDs.

[0137] The variable wavelength LED is advantageously controllable to emit light at any peak emission wavelength within its emission wavelength range. By changing the power supply characteristics and the LED pixel size and shape, the variable wavelength LED can be controlled to emit light at any selected peak emission wavelength within this range.

[0138] Preferably, the emission wavelength of the variable wavelength LED is continuously variable across its emission wavelength range in response to continuous variation of the driving condition provided by the power supply across the range of driving conditions.

[0139] The location of the emission wavelength range within the electromagnetic spectrum may also vary depending on the design of the variable-wavelength LED structure (n-doped portion, luminescent region, and p-doped portion). For example, the wavelengths included in the emission wavelength range may depend on the number and composition of the luminescent layers in the variable-wavelength LED. It is known in the art that there are many different types of LED active regions that emit at different wavelengths across the visible spectrum. By forming the luminescent regions of the LED of the present invention with different luminescent regions, an emission wavelength range covering different parts of the spectrum can be obtained.

[0140] The emission wavelength range of the variable wavelength LED can be 400nm-850nm, 400nm-800nm, 400nm-690nm, or 400nm-675nm. The emission wavelength range can be a subrange within the 400nm-750nm range. By selecting different LED active areas and controlling the size and shape of the LED pixel, the emission wavelength range can be adjusted to cover any part of this range.

[0141] Preferably, the variable wavelength LED has an emission wavelength range with a lower limit lower than 410 nm, 430 nm, 450 nm, 470 nm, 500 nm, 520 nm, 540 nm, or 560 nm, and an upper limit higher than 570 nm, 580 nm, 600 nm, 610 nm, 630 nm, 650 nm, or 675 nm. As previously mentioned, the first and second limits of the emission wavelength range can be adjusted depending on the selected LED structure and the LED shape and size.

[0142] For example, in a preferred embodiment, the lower limit of the emission wavelength may be 400nm-450nm (violet light) or 450nm-500nm (blue light) or 500nm-570nm (green light), and the upper limit may be 570nm-590nm (yellow light), 590nm-610nm (orange light) or 610nm-700nm (red light).

[0143] In a preferred embodiment, the emission wavelength range of the variable wavelength LED can extend from a lower limit of less than 500 nm to an upper limit of greater than 610 nm. Thus, by varying the power supply, the peak emission wavelength of the LED can be varied to emit light at any wavelength between blue (<500 nm) and red (>610 nm). Providing a single LED design that can be controlled to emit light at wavelengths of blue (450 nm-500 nm), green (500 nm-570 nm), as well as yellow (570 nm-590 nm), orange (590 nm-610 nm), and red (610 nm-760 nm) light provides significant benefits for LED displays.

[0144] In other preferred embodiments, by changing the power supply to the LED, the emission wavelength range of the variable wavelength LED can be extended to between 520nm and 660nm or between 550nm and 650nm.

[0145] In a particularly preferred embodiment, the peak emission wavelength can be controlled between 540nm-680nm or 560nm-675nm by changing the power supply. Therefore, the same LED can be controlled to emit light at any peak emission wavelength between 540nm green and 680nm red. Historically, green and red LEDs have been more difficult to manufacture than short-wavelength blue LEDs due to difficulties such as the need to incorporate the required indium content into the light-emitting region. Providing a single LED design that can be controlled to emit light at wavelengths of green (500nm-570nm), as well as yellow (570nm-590nm), orange (590nm-610nm) and red (610nm-760nm) light provides significant benefits to LED displays.

[0146] In another preferred embodiment, the peak emission wavelength can be controlled between 520nm-675nm or 550nm-650nm by changing the power supply.

[0147] Even though variable wavelength LEDs can emit light across a continuous range of emission wavelengths, in some embodiments, it may be desirable to control the LED to operate in multiple discrete emission modes (e.g., in response to a power supply having multiple drive modes). For example, a simplified color display can be provided by driving the LED in multiple different modes corresponding to discrete emission colors, where, in known methods, the discrete emission colors are mixed to achieve a desired visual effect.

[0148] Preferably, the variable wavelength LED can be controlled to emit light at at least two discrete peak emission wavelengths by changing the driving conditions provided by the power supply (e.g., two discrete driving current amplitudes). The LED can be controlled to emit light at a first peak emission wavelength in response to a first driving condition provided by the power supply (which can be a driving current with a first amplitude), and to emit light at a second peak emission wavelength in response to a second driving condition provided by the power supply (which can be a driving current with a second amplitude different from the first amplitude).

[0149] Preferably, the variable wavelength LED can be controlled to emit light at at least three discrete peak emission wavelengths by changing the driving conditions provided by the power supply. Therefore, the peak emission wavelength of the variable wavelength LED can be changed between at least three "colors" in the electromagnetic spectrum.

[0150] The variable wavelength LED can be controlled to emit light at a first peak emission wavelength in response to a first driving condition provided by the power supply, emit light at a second peak emission wavelength in response to a second driving condition provided by the power supply, and emit light at a third peak emission wavelength in response to a third driving condition provided by the power supply.

[0151] Preferably, the variable wavelength LED can be controlled to emit a blue peak emission wavelength in response to a first driving condition provided by the power supply, emit a green peak emission wavelength in response to a second driving condition provided by the power supply, and emit a red peak emission wavelength in response to a third driving condition provided by the power supply.

[0152] The variable wavelength LED can be controlled to emit a first peak emission wavelength in the range of 400nm-500nm in response to a first driving condition provided by the power supply, emit a second peak emission wavelength in the range of 500nm-550nm in response to a second driving condition provided by the power supply, and emit a third peak emission wavelength greater than 600nm in response to a third driving condition provided by the power supply.

[0153] Preferably, the variable wavelength LED can be controlled to emit a first peak emission wavelength in the range of 430nm-460nm in response to a first driving condition provided by the power supply, emit a second peak emission wavelength in the range of 510nm-560nm in response to a second driving condition provided by the power supply, and emit a third peak emission wavelength in the range of 600nm-660nm in response to a third driving condition provided by the power supply.

[0154] The first driving condition, the second driving condition, and the third driving condition may be a first current density, a second current density, and a third current density, or a first power density, a second power density, and a third power density.

[0155] The morphology of the quantum wells (QWs) in the active light-emitting region can vary. For example, the light-emitting region can contain uniform QWs with well-defined interfaces, or fragmented QWs with ill-defined interfaces, fragmentation, or fluctuations in quantum well width / composition or quantum dot-like localized centers. This control over the QW morphology allows for the control and regulation of a variable emission wavelength range.

[0156] The light emitting region preferably comprises a plurality of quantum wells (QWs). The quantum wells may be continuous, fragmented or discontinuous.

[0157] Variable wavelength LEDs can include a current confinement layer, or current limiting layer, which is an electrolyte layer configured to confine the lateral region of current conduction of the LED. The use of a current confinement layer can advantageously allow for further control of the current density, thereby better controlling the peak emission wavelength of the LED.

[0158] The current confinement layer can advantageously achieve regulation of the power density supplied to the variable wavelength LED to control the peak emission wavelength.

[0159] The current confinement layer is preferably an electrolyte material layer, such as SiO2, SiN or SiN x and other electrolyte materials.

[0160] The current confinement layer can be located in a variety of locations on the variable wavelength LED as long as the lateral area of ​​current conduction of the LED is confined.The current confinement layer can be located between the n-type electrical contact and the p-type electrical contact of the LED.

[0161] The current confinement layer can be positioned adjacent to the n-doped portion or the p-doped portion of the LED. For example, the current confinement layer can be positioned between the n-doped portion and the light-emitting region. Alternatively, the current confinement layer can be positioned between the light-emitting region and the p-doped portion. The current confinement layer can be positioned between the electrical contacts and the LED structure (n-doped portion, p-doped portion, and light-emitting region).

[0162] Preferably, the current confinement layer comprises a hole extending through the current confinement layer, or one or more holes extending through the current confinement layer. The hole is preferably located in the center of the current confinement layer, for example, the current confinement layer may comprise a circular opening in the center of the LED structure.

[0163] The variable wavelength LED may be configured such that the electrical contact contacts the LED structure through an aperture in the current confinement layer, such that the area of ​​the aperture defines a contact area where the contact and the LED structure meet.

[0164] The lateral dimensions of the apertures are preferably much smaller than the lateral dimensions of the LED.By providing apertures through the electrolyte current confining layer a high local current density can be achieved, which advantageously can achieve improved control of the power through the LED.

[0165] For example, the lateral width (or diameter) of the hole may be equal to or less than 50% of the lateral width of the LED structure (LED mesa). The width of the hole may be equal to or less than 45%, 40%, 35%, 30%, 25%, or 20% of the width of the LED structure.

[0166] The relative area of ​​the pores relative to the total area of ​​the current confining layer (blocking region) can be varied to modify the local current density.

[0167] The light emitting region preferably comprises a multiple quantum well (MQW) comprising a plurality of quantum wells (QWs), or a quantum dot, quantum wire or other quantum nanostructure.

[0168] In some embodiments, the light emitting region includes a plurality of quantum wells (QWs), and the quantum wells are continuous.

[0169] The present inventors have discovered that non-uniformity in the light-emitting area has a significant impact on extending the range of emission wavelengths across which the light-emitting area can emit light in response to changes in the power supplied to the LED. In the prior art, light-emitting area non-uniformity is often viewed as a problematic defect that is undesirable and should be avoided at all costs, as the goal is generally high-quality, low-defect semiconductor wafers. The present inventors have circumvented this bias in the prior art and discovered that intentionally creating non-uniformity in the light-emitting area can advantageously extend the emission wavelength range, resulting in a variable-wavelength LED capable of emitting light over a wider range of wavelengths than in the prior art.

[0170] In alternative embodiments of the present invention, the light-emitting region is non-uniform, fragmented, or discontinuous. The light-emitting region can be intentionally introduced to achieve carrier localization center effects in the InGaN quantum wells, such as multiple QW regions with different indium compositions, well widths, and quantum barriers, resulting in well width fluctuations, non-uniform InGaN quantum dots or nanostructures, or fragmented, or broken, or gapped, or discontinuous quantum wells, or quantum wells formed on polar, semi-polar, or non-polar surfaces.

[0171] In a preferred embodiment, the light emitting region includes a plurality of quantum wells (QWs), and the quantum wells are non-uniform, fragmented, or discontinuous.

[0172] Multiple QWs may include well width fluctuations. For example, the well width of a QW may fluctuate by at least 2%, 5%, 10%, 20%, 25%, 50%, or 75%. Well width fluctuations may occur between quantum wells (vertically) as well as within a single quantum well (laterally).

[0173] Multiple QWs may also include alloy composition fluctuations. For example, the indium composition of a QW may vary by 2%, 5%, 10%, 20%, 25%, 50%, or 75% across the light emitting region.

[0174] The inventors have discovered that fluctuations in well width and / or alloy composition can induce carrier localization centers at the upper or lower interface of the QW. Any carrier localization centers will induce variable wavelength in the variable-wavelength LED of the present invention. The greater the density of these carrier localization centers, the wider the achievable variable wavelength range.

[0175] The variable wavelength LED may comprise a V-shaped pit extending or propagating across the light emitting active region. Preferably, the LED comprises a plurality of V-shaped pits extending across the light emitting region.

[0176] Preferably, the variable wavelength LED may comprise a density (measured looking down at the LED structure) of at least 1×10 7 / cm 2 , for example, at least 5×10 7 / cm 2 or at least 1×108 / cm 2 , for example, between 1×10 7 / cm 2 to 5×10 9 / cm 2 There is a V-shaped pit between them.

[0177] Variable wavelength LEDs may include densities less than 5×10 9 / cm 2 V-shaped pits (for example, the density of V-shaped pits is less than 1×10 9 / cm 2 or less than 5×10 8 / cm 2 ).

[0178] V-pits are a well-known phenomenon in epitaxial semiconductor growth, and methods for growing V-pits in semiconductor structures are known in the art. For example, V-pits and their growth are described in the prior art (The effect of nanometer-scale V-pits on electronic and optical properties and efficiency droop of GaN-based green light-emitting diodes; Zhou et al; Scientific Reports | (2018) 8:11053 | DOI: 10.1038 / s41598-018-29440-4).

[0179] These V-pits appear V-shaped when viewed in cross-section, but are actually conical or funnel-shaped cavities formed in semiconductor structures using conventional bottom-up epitaxial growth methods. Even though the V-pits appear V-shaped in cross-section, they typically appear hexagonal when viewed from above. The tip of the V-pit always points downward toward the earlier deposited layers in the semiconductor structure, as the V-pit gradually widens as subsequent epitaxial layers are deposited on top of the structure.

[0180] Even though V-pits are known in the art, they are generally considered problematic defects in semiconductor structures, which are undesirable since the goal is generally to obtain high-quality, low-defect semiconductor wafers.

[0181] In the rare cases where V-pits have been integrated into semiconductor structures, they have been used as a screening mechanism to form a higher bandgap region, thereby preventing carriers from following threading dislocations downward as a leakage path.

[0182] However, in some preferred embodiments of the present invention, a V-shaped pit is intentionally integrated into the variable wavelength LED structure. The V-shaped pit extends deep enough into the semiconductor structure to terminate at a layer below the active light-emitting area. This means that the V-shaped pit must extend through the thickness of the active light-emitting area.

[0183] The present inventors have discovered that a V-shaped pit extending across the light emitting region of an LED structure can advantageously expand the range of emission wavelengths that a variable wavelength LED can emit.

[0184] As the V-shaped pit extends through the LED active area, a quantum well (QW) layer that is flat across the rest of the structure grows on the sloped sidewalls of the V-shaped pit during bottom-up epitaxial growth. The QWs deposited on the pit sidewalls are deformed and stretched around the sides of the pit, ultimately having a different thickness and composition than the planar QWs across the main body of the structure.

[0185] Around the V-shaped pit, the QW layer of semiconductor material grows as a flat, planar layer. Therefore, the active light-emitting area is flat around the V-shaped pit. However, at the V-shaped pit, the active layer deforms and stretches down along the sidewalls into the pit. This stretching effect changes the thickness of the QWs on the pit's sidewalls, making them different from the planar QW layer formed on the rest of the LED structure.

[0186] The inventors found that V-pits can produce local strain relaxation, and the MQWs (multiple quantum wells) deposited on the sidewalls of these V-pits will have different thickness and composition than the rest of the MQWs, so the MQWs in the region of the V-pits will produce different emission wavelengths.

[0187] The quantum wells grown on the sidewalls of the V-shaped pit are thinner than the planar QWs in other parts of the structure, which affects the QW bandgap and causes the QWs in this area to emit light at a wavelength different from the wavelength emitted by the planar QWs in other parts of the structure. In addition, the QWs on the sidewalls of the pit may eventually have a higher indium (In) content than the surrounding planar QWs. Since the sidewalls expose the semi-polar plane of the QW (which incorporates more indium during epitaxial growth), the QWs in the area of ​​the V-shaped pit may have a higher indium (In) content than the planar QWs around the pit. Higher indium incorporation generally results in a longer peak emission wavelength. The QW thickness and indium content jointly affect the emission wavelength produced by the light-emitting region. Therefore, the presence of the V-shaped pit in the LED structure can advantageously change the composition and thickness of the QWs in the light-emitting region, thereby expanding the emission wavelength range over which the LED can be driven to emit light.

[0188] V-shaped pits can grow from threading dislocations in semiconductor structures. As additional layers are grown on top of the layer containing the threading dislocation, the threading dislocations extend upward through the structure, at which point the dislocations expand into V-shaped pits. Technicians typically aim to keep threading dislocation density low in order to obtain "high-quality," low-defect wafers.

[0189] Alternatively, a three-dimensional epitaxial growth mode can be used to grow the V-shaped pit. 3D epitaxial deposition techniques known in the art are typically used to grow "islands" or "pyramids" of semiconductor material on a template. By using 3D epitaxial deposition techniques to control the deposition of the LED structure, V-shaped pits can be artificially grown at desired locations without the need for threading dislocations to "seed" the formation of the V-shaped pits. By using this deposition control, the bottom (lowest point) of the pit can be created at a desired location in the structure (both the desired lateral position and the desired height in the structure, such as a specific layer of the semiconductor structure below the active light-emitting area).

[0190] The bottom of the V-shaped pit may be located in a connection layer of the semiconductor structure, which may be located between the porous region and the n-doped portion.

[0191] The bottom of the V-shaped pit may be located in a pre-strained layer of the semiconductor structure, and the pre-strained layer may be located above the n-doped portion and below the light emitting region.

[0192] Preferably, each variable wavelength LED comprises a plurality of V-shaped pits extending across the active light emitting area.

[0193] Preferably, the variable wavelength LED comprises a density of at least 1×10 7 / cm 2 , for example, at least 5×10 7 / cm 2 or at least 1×10 8 / cm 2 The LED may include a density less than 5×10 9 / cm 2 , for example, less than 1×10 9 / cm 2 or less than 5×10 8 / cm 2 V-shaped pit.

[0194] For example, the variable wavelength LED may include a density of 1×10 7 / cm 2 to 5×10 9 / cm 2 , or 5×10 7 / cm 2 to 5×10 9 / cm 2 , or 1×108 / cm 2 to 5×10 8 / cm 2 V-shaped pit.

[0195] The variable wavelength LED may include more than 0.1 V-shaped pits, or more than 1 V-shaped pit, or more than 2 V-shaped pits per square micrometer.

[0196] It is preferable to control the concentration of V-pits in a variable wavelength LED because too many V-pits can negatively impact the light emission of the LED by disrupting radiative recombination. For example, the LED may include fewer than 10 V-pits per square micron, or fewer than 8 V-pits per square micron, or fewer than 6 V-pits per square micron.

[0197] In a preferred embodiment, the LED structure may include no more than 109 threading dislocations per square centimeter. Preferably, the semiconductor structure below the active light-emitting region (typically the substrate, porous region, and connecting layer) includes no more than 109 threading dislocations per square centimeter. The threading dislocation density is preferably limited to this level so that subsequent epitaxial growth does not produce excessive V-shaped pits in the light-emitting region.

[0198] The density and size (depth) of the V-shaped pits can be controlled. The size of the V-shaped pits can be controlled by the position and growth conditions of the pre-strained layer and the low-temperature InGaN layer that induce the pits.

[0199] The morphology of the quantum wells (QWs) in the active light-emitting region can be varied. For example, the light-emitting region can contain uniform QWs with well-defined interfaces, or fragmented QWs with ill-defined interfaces, fragmentation, or fluctuations in quantum well width / composition or quantum dot-like localized centers. This control over the QW morphology enables control and regulation of the variable emission wavelength range.

[0200] The light emitting region preferably comprises a plurality of quantum wells (QWs), which may be continuous, fragmented or discontinuous.

[0201] If the quantum well is continuous and highly uniform in thickness and composition, then recombination of charge carriers can only occur in a well-defined manner. Conversely, if the quantum well is fragmented or discontinuous, a large number of nanostructures will be generated, resulting in different band gaps and thus different colors of light.

[0202] Display devices

[0203] In a second aspect, the present invention may provide a display device comprising a monolithic array of semiconductor devices on a wafer according to the first aspect of the present invention. In the display device of the second aspect, the first semiconductor device and the second semiconductor device are both LED sub-pixels, such that the first semiconductor device and the second semiconductor device form a device pixel, and the device comprises an array of multiple device pixels on the wafer. The first LED sub-pixel and the second LED sub-pixel preferably emit light at different peak emission wavelengths in response to a drive current. One or both of the first LED sub-pixel and the second LED sub-pixel may optionally be a variable wavelength LED as described above.

[0204] The array of multiple device pixels preferably includes an array of multiple first semiconductor devices forming a first array of LED sub-pixels, which is interleaved with an array of multiple second semiconductor devices forming a second array of LED sub-pixels.

[0205] The present invention thus advantageously allows the formation of display devices by fabricating a monolithic array of LED subpixels, each containing an array of subpixels emitting at different peak emission wavelengths, on a wafer in a single device epitaxial step. Previously, such multi-wavelength display devices could only be produced by growing the different color subpixels separately, then transferring and combining them onto a shared wafer. The present invention thus significantly simplifies the production of multi-color display devices, eliminating many of the expensive, cumbersome, and technically challenging processes required in the prior art.

[0206] The display device optionally includes an array of a plurality of third semiconductor devices forming a third LED sub-pixel array such that each device pixel is composed of three sub-pixels emitting light at different peak emission wavelengths.

[0207] All features described above with respect to the first aspect of the present invention are equally applicable to the second aspect of the present invention.

[0208] Template wafer

[0209] In a third aspect, the present invention may provide a template wafer for a monolithic array of semiconductor devices. The template wafer may include:

[0210] a surface layer of a non-porous Group III nitride material;

[0211] a first porous region of the Group III-nitride material below the surface layer, the first porous region having a first structure, a first porosity, and a first size; and

[0212] a second region of Group III nitride material below the surface layer;

[0213] wherein the first porous region and the second region occupy different lateral portions of the wafer such that the first porous region is located below a first area of ​​the surface layer and the second region is located below a second area of ​​the surface layer;

[0214] wherein the second region is a non-porous region, or wherein the second region is a second porous region that does not have the same structure, porosity and size as the first porous region.

[0215] The lateral region of the surface layer directly above the first porous region preferably forms a first device region on which a first semiconductor device can be overly grown. A separate lateral region of the surface layer directly above the second region preferably forms a second device region on which a second semiconductor device can be overly grown.

[0216] The template wafer is preferably the wafer described above with respect to the first and second aspects of the present invention. Therefore, the features of the wafers described with respect to these aspects are all applicable to the template wafer of the third aspect.

[0217] As previously described, by using this type of wafer template, multiple semiconductor devices can be overly grown using a single epitaxial layer on the surface layer of the wafer, and the different properties of the first porous region and the second region will cause these overlying devices to behave differently during use. This allows the monolithic growth of semiconductor structures with different electronic and / or optoelectronic properties to be achieved using a single epitaxial layer. By designing the porous and non-porous regions below the surface layer of the wafer, the wafer template can be designed to determine the properties of the overlying semiconductor devices.

[0218] Preferably, the wafer includes a substrate and a plurality of semiconductor material layers on the substrate.

[0219] Preferably, all semiconductor materials used in the present invention are Group III nitride semiconductor materials. Therefore, the wafer preferably comprises multiple layers of Group III nitride semiconductor materials on a substrate. Each semiconductor layer in the wafer (excluding the substrate) is preferably formed from one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0220] The substrate can be silicon, sapphire, silicon carbide, or β-Ga2O3. The crystal orientation of the substrate can be polar, semi-polar, or non-polar. The substrate thickness typically varies from 100 μm to 1500 μm. The wafer size can vary, for example, 1 cm 2 , 2-inch, 4-inch, 6-inch, 8-inch, 12-inch or 16-inch diameter or larger.

[0221] The wafer may alternatively be referred to as a template because the multilayer semiconductor wafer is used as a template for overlying growth during the fabrication process.

[0222] Each porous region is preferably formed in a sub-surface layer of the wafer. The porous region may be located in a layer of semiconductor material disposed between a non-porous surface layer of the wafer and the substrate. The first semiconductor device and the second semiconductor device are preferably located on the non-porous surface layer of the wafer.

[0223] The first porous region preferably occupies part of a sub-surface layer of semiconductor material in the wafer.

[0224] The first porous area preferably does not occupy the entire wafer layer because it is not located below the second semiconductor device. When viewed from above in plan view, the first porous area preferably occupies a discrete portion of the wafer footprint. When the wafer includes a plurality of first porous areas (e.g., an array of first porous areas), the array of first porous areas occupies an array of discrete portions of the wafer footprint. The wafer can be patterned to form the array of first porous areas. Preferably, each first porous area is surrounded by non-porous semiconductor material in the same layer and in the upper and lower layers of the first porous area.

[0225] In a preferred embodiment, the second region is a non-porous region of Group III nitride material.

[0226] In an alternative preferred embodiment, the second region is a second porous region of the wafer having a second porosity different from the first porosity, and / or a second size different from the first size.

[0227] The second porous region occupies a portion of a semiconductor material layer in the wafer. The second porous region can be located in the same wafer layer as the first porous region, or alternatively, the second porous region can be located in a different wafer layer. The second porous region and the first porous region preferably occupy different lateral locations in the wafer such that the first semiconductor device and the second semiconductor device in the first device region and the second device region each overlap their respective porous regions.

[0228] The second porous area preferably does not occupy the entire wafer layer, so that the second porous area is located below the second semiconductor device but not below the first semiconductor device. When looking down at the plan view, the second porous area preferably occupies a discrete portion of the wafer footprint. When the wafer includes a plurality of second porous areas (e.g., a second porous area array), the second porous area array occupies an array of discrete portions of the wafer footprint. The wafer can be patterned to form the second porous area array. Preferably, each second porous area is surrounded by the non-porous semiconductor material in the same layer and the upper and lower layers of the second porous area.

[0229] The second porous region may have a higher or lower porosity percentage than the first porous region.The second porous region may comprise a smaller or larger average pore size than the first porous region.

[0230] The second porous region may have a second thickness that is different from the thickness of the first porous region.

[0231] The thickness of the first and / or second porous region may be at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the thickness of the first and / or second porous region may be between 1 nm and 10,000 nm.

[0232] The first porous region may have a first shape, and the second porous region may have a second shape different from the first shape.

[0233] The second porous region is preferably formed of one of GaN, InGaN, AlGaN, AlInGaN or AlN.

[0234] The porosity of each porous region may be between 1% and 99% porosity, preferably between 20% and 90% porosity or between 30% and 80% porosity.

[0235] The thickness of each porous region may be greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm.

[0236] Each porous region may include a continuous porous Group III nitride material layer segment occupying a portion of a wafer layer that also includes non-porous Group III nitride material segments and / or porous Group III nitride material segments having different porosities.

[0237] Each porous region may include a single layer segment of porous GaN, or a single layer segment of porous InGaN, or a stack of one or more layers of porous GaN and / or one or more layers of porous InGaN.

[0238] In addition to the first porous region and the second region in the wafer, the wafer may also include one or more additional porous regions.

[0239] The wafer surface may include a third device region that is not located above a porous region having the same porosity and size as the first porous region. This means that under the same driving conditions, a third semiconductor device overlying the third device region will behave differently from the first semiconductor device. The third porous region may have a third porosity that is different from the first porosity of the first porous region and / or a third size that is different from the first size of the first porous region. In an embodiment in which the wafer includes a second porous region, the third porous region may have a third porosity that is different from the second porosity of the second porous region and / or a third size that is different from the second size of the second porous region. Alternatively, in an embodiment in which the wafer includes a second porous region, the third device region may not be located above any porous region.

[0240] The portion of the wafer below the third device region should have different porosity characteristics from the portion of the wafer below the first semiconductor device and the second semiconductor device, so that the characteristics of the third semiconductor device overlying the third device region are different from the characteristics of the same device formed on the first device region and the second device region.

[0241] The wafer surface can include additional device regions (e.g., a fourth device region or a fifth device region) on the top surface of the wafer. These different device regions are located above portions of the wafer having different porosity characteristics. By controlling the porosity characteristics, such as the porosity percentage, pore size, and size, of the different porous regions in the wafer, any number of semiconductor devices with different operating characteristics can be provided through epitaxy of a single device.

[0242] In a particularly preferred embodiment, the wafer may include an array of subsurface first porous regions (each first porous region having the same porosity and size) and an array of subsurface second regions (each second region having the same porosity and size as the other second regions, but not having the same porosity characteristics as the first porous region). The wafer may thus be configured such that the wafer surface includes an array of first device regions and an array of second device regions, such that the first semiconductor device array and the second semiconductor device array may be grown directly overlying the device regions on the wafer.

[0243] Fabrication of template wafers

[0244] In a fourth aspect, the present invention may provide a method for manufacturing a template wafer for a monolithic array of semiconductor devices, comprising the steps of:

[0245] Providing a wafer, the wafer comprising: a surface layer of undoped Group III nitride material, a first region of Group III nitride material below the surface layer, and a second region of Group III nitride material below the surface layer, wherein the first region is n-type Group III nitride material having a first carrier concentration;

[0246] A first region of an n-type Group III nitride material is electrochemically porosified to form a first porous region in a subsurface layer, wherein the first porous region has a first structure, a first porosity, and a first size; wherein a second region is not porosified, or wherein the second region is porosified to form a second porous region, which does not have the same structure, porosity, and size as the first porous region.

[0247] The method of the fourth aspect is preferably a method for manufacturing the template wafer described in the third aspect of the present invention.

[0248] The porous region can be formed by making the n-doped Group III nitride material region porous using the porousization process described in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0249] In a preferred embodiment, the second region of Group III nitride material may be an n-type Group III nitride material, and wherein the method includes the step of electrochemically porosifying the second region of n-type Group III nitride material to form a second porous region in the subsurface layer.

[0250] The wafer preferably includes a substrate and a plurality of semiconductor material layers on the substrate, preferably a plurality of Group III nitride semiconductor material layers on the substrate.

[0251] The second n-type region is preferably a subsurface n-type region located below a surface layer of the wafer, and wherein the second n-type region is preferably made porous by through-surface etching through the surface layer.

[0252] In an alternative embodiment, the second region of Group III nitride material may be undoped, and thus the second region is not porosified during the electrochemical porosification of the n-doped first region.

[0253] Prior to performing through-surface electrochemical porosification, the wafer surface may be selectively masked with a mask layer, such that regions of the wafer beneath the mask layer are not porosified.

[0254] In some preferred embodiments, the carrier density of the n-type second region can be the same as the carrier density of the n-type first region, which becomes the first porous region. However, during the porosification process, the n-type second region remains non-porous by selectively masking the surface area of ​​the wafer. The use of the mask layer thus enables selective porosification of the first porous region.

[0255] Alternatively, the carrier density of the n-type second region may be different from the carrier density of the n-type first region, which becomes the first porous region. Since porosification depends largely on the conductivity of a given material region, this difference in carrier density may result in the first porous region and the second porous region having different porosity characteristics after porosification.

[0256] The method for manufacturing a template wafer may include controlling the carrier concentration in the regions to be made porous by ion implantation or doping specific regions to reduce or increase their conductivity. Regions of Group III nitride material with higher n-type conductivity are more susceptible to being made porous, so selectively controlling the conductivity of each region means that the regions to be made porous can be individually located and the desired porosity characteristics can be predetermined. Differences in doping levels between regions can be advantageous, meaning that even if different regions are made porous simultaneously or separately using the same etching conditions, the resulting porosity characteristics in these different regions can still differ.

[0257] The method may comprise the step of doping regions of the wafer with nitrogen or magnesium to reduce the n-type conductivity of these regions. The method may comprise the step of doping regions of the wafer with Si, Ca or O to increase the n-type conductivity of these regions.

[0258] The first region preferably occupies part of a semiconductor material layer in the wafer, and the n-type first region is preferably made porous by etching through the surface layer. The second region also preferably occupies part of a semiconductor material layer in the wafer. It is particularly preferred that the second region and the first region be located in the same wafer layer.

[0259] The method may include the following steps: masking a surface layer of a wafer with a mask layer prior to porosification, patterning the mask layer to expose an array of first device areas, and porosifying the array of first porous areas through the exposed first device areas on the surface layer. By selectively patterning the mask layer to expose predetermined areas of the wafer surface, the lateral dimensions of the subsurface area to be porosified can be defined. This allows for the formation of specific first and / or second porous areas within the wafer at desired lateral locations within the wafer.

[0260] In a preferred embodiment, the first and second porous regions are made porous one by one by masking the surface area above a given n-type region while making the other n-type regions porous.

[0261] During the porosification of the first porous region, a second device region of the surface layer above the second region of the Group III nitride material may be masked with a mask layer so that the second region is not porosified during the porosification of the first porous region.

[0262] During the porosification of the second porous region, the first device region of the surface layer above the first region of the Group III nitride material may be masked with a mask layer so that the first region below the first device region is not porosified during the porosification of the second porous region.

[0263] Before making the surface porous, it is preferred to use a mask layer of a photoresist material or an electrolyte material layer (such as SiO2 or SiN xor other electrolytes) or polymer layers (positive or negative). The mask layer thickness is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, or at least 200 nm, or at least 1 μm, or at least 2 μm, or at least 5 μm, or at least 10 μm.

[0264] To introduce different porosity characteristics into the second region, the second porous region can be made porous using etching conditions that differ from those used to make the first porous region porous. For example, the second porous region can be made porous using an etching electrolyte that differs from the electrolyte used to make the first porous region porous. The electrolyte used to make the first and / or second porous regions porous is preferably selected from the following list: oxalic acid, KOH, NaOH, HF, nitric acid, and HCl.

[0265] At least one of the first and / or second porous regions can be made porous using photoelectrochemical etching under illumination, such as ultraviolet light or white light. Different illumination is used during the porosification of the first and second porous regions, or illumination is used during the porosification of only one of the first and second porous regions.

[0266] The porosification of the second porous region may be performed at a temperature different from that of the first porous region. For example, the porosification may be performed at a temperature of -150°C to +150°C.

[0267] The porosification of the second porous region can be performed at a pressure different from the pressure at which the first porous region is porosified. For example, the pressure range during the porosification process can be from atmospheric pressure of 760 Torr to low vacuum 10 -3 Torr, or to medium vacuum 10 -3 to 10 -5 Entrust.

[0268] The second porous region may have a second thickness different from that of the first porous region. The thickness of the porous region is not particularly limited, but may be greater than 1 nm, more preferably greater than 10 nm, and particularly preferably at least 40 nm, 50 nm, or 100 nm.

[0269] The first region can have a different size and / or shape and / or geometry than the second region. For example, in some embodiments, the first porous region can have a larger lateral dimension than the second region, such that a first device region formed above the first porous region can be larger than a second device region formed above the second region.

[0270] Preferably, the porosity of the one or more porous regions is controlled by an electrochemical etching process to make the porous region porous. The porosity of the first porous region and / or the second porous region may be between 1% and 99% porosity, preferably between 20% and 90% porosity or between 30% and 80% porosity.

[0271] The porous region may comprise a continuous segment of a porous III-nitride material layer that occupies a portion of an otherwise non-porous III-nitride material wafer layer. The porous region may comprise a single layer segment of porous GaN, or a single layer segment of porous InGaN, or a stack of one or more layers of porous GaN and / or one or more layers of porous InGaN.

[0272] In a particularly preferred embodiment, the wafer comprises a first district of a plurality of III-nitride materials below the surface layer and a second district of a plurality of III-nitride materials below the surface layer. A plurality of first districts are preferably simultaneously porous. In the porous process of a plurality of first districts, the region of the surface layer above the second district can be masked with a mask layer. A plurality of first districts preferably form a discrete "island" array in the first district that occupies a separate lateral position in the subsurface layer. A plurality of second districts preferably form a discrete "island" array in the second district that occupies a separate lateral position in the subsurface layer.

[0273] After being made porous, the wafer is preferably patterned to form a plurality of first porous regions and a plurality of second regions (optionally second porous regions). The wafer may also be patterned to form more porous regions having different structures, porosity characteristics or sizes.

[0274] Method for manufacturing semiconductor device array

[0275] In a fifth aspect, the present invention provides a method for manufacturing a monolithic array of semiconductor devices on a wafer, comprising the steps of:

[0276] providing a first device region on the wafer above a first porous region in the wafer, the first porous region having a first structure, a first porosity, and a first size;

[0277] forming a first semiconductor device by depositing a semiconductor device structure over the first device region;

[0278] forming a second semiconductor device by depositing the same semiconductor device structure over a second device region on the wafer;

[0279] The second device region is not located above a porous region having the same structure, porosity and size as the first porous region.

[0280] The first semiconductor device and the second semiconductor device have the same device structure but behave differently in response to the same driving conditions.

[0281] The method of the fifth aspect may include any wafer manufacturing steps according to the fourth aspect of the present invention. Alternatively, the template wafer of the fourth aspect may be designed and produced separately, and the method of the fifth aspect may include the step of forming semiconductor devices on the wafer.

[0282] The method of the fifth aspect is preferably a method for manufacturing the semiconductor device monolithic array according to the first aspect of the present invention. The features of the wafer and monolithic array described above are equally applicable to the method of the fifth aspect of the present invention.

[0283] A first semiconductor device is grown overlying a first device region, with a porous region located below the first device region. By growing the first semiconductor device overlying the first porous region, the inventors discovered that the first semiconductor device will be affected by the underlying first porous region, as the crystal structure of the first semiconductor device inherits certain properties from the underlying porous material, which affect the performance of the first semiconductor device. The porous region's characteristics, including the first porosity and first dimensions (thickness and / or lateral dimensions) of the first porous region, affect the crystal structure of the overlying first semiconductor device, thereby affecting the behavior of the first semiconductor device.

[0284] The second semiconductor device is not overlyingly grown on the porous region having the same properties as the first porous region.

[0285] The semiconductor devices are formed using conventional semiconductor deposition techniques known in the art.

[0286] In a first preferred embodiment, the second semiconductor device may be formed on a second porous region that is different from the first porous region (e.g., the second porous region has a different porosity and / or size than the first porous region). In this case, the different porosity and / or size of the second porous region will affect the overlying second semiconductor device in a manner different from the effect of the first porous region on the first semiconductor device. As a result, even though the device structures are the same, the electronic and / or optical properties of the second semiconductor device will be different from those of the first semiconductor device.

[0287] Alternatively, in a second preferred embodiment, the second semiconductor device may not be located above the porous region. In other words, the wafer may be entirely non-porous below the second device region. In this embodiment, the second semiconductor device is grown overlying the non-porous portion of the wafer, with no porous material located below the second device region. Therefore, the electronic and / or optical properties of the second semiconductor device are not affected by the presence of any underlying porous region. Therefore, even if the device structures are identical, the electronic and / or optical properties of the second semiconductor device will differ from those of the first semiconductor device because the first semiconductor device is affected by the underlying porous material while the second device is not.

[0288] In a first preferred embodiment, the second device region is formed over a second porous area of ​​the wafer, the second porous area having a porosity different from the first porosity and / or a size different from the first size.

[0289] Preferably, the method includes the following steps: forming a first device area array on the surface of the chip, wherein the first device area array is located above the corresponding first porous area array in the chip, and forming a second device area array on the chip, wherein the second device area array is located above the corresponding second porous area array in the chip.

[0290] In a second preferred embodiment, the second semiconductor device is not located above the porous region. In other words, the footprint of the wafer directly below the second device region is non-porous throughout its thickness. There may be no porous semiconductor material located directly between the wafer substrate and the second semiconductor device.

[0291] In this embodiment, the second semiconductor device is overlyingly grown on the non-porous portion of the wafer, and no porous material is located beneath the second device region. Therefore, the electronic and / or optical properties of the second semiconductor device are not affected by the presence of any porous region beneath the device. Therefore, even if the device structures are identical, the electronic and / or optical properties of the second semiconductor device will be different from those of the first semiconductor device because the first semiconductor device is affected by the underlying porous material while the second device is not.

[0292] The first device region and / or the second device region may be defined by an exposed region of the wafer surface after the mask layer is removed.

[0293] The method may include the following steps: forming a first device area array on a wafer, the first device area array being located above a corresponding first porous area array in the wafer, and forming a second device area array on the wafer, wherein the second device area array is not located above the porous area of ​​the wafer. The method may include the steps of forming a first semiconductor device array and a second semiconductor device array having the same device structure on the first device area array and the second device area array, respectively. The first semiconductor device array and the second semiconductor device array are preferably formed simultaneously using a single epitaxial growth process.

[0294] The first device region may have a different size and / or shape and / or geometry than the second device region. In a preferred embodiment, the first device region is larger than the second device region. The first semiconductor device and the second semiconductor device are preferably formed to fill their respective device regions, which allows the first semiconductor device to be grown to have a larger lateral dimension (larger area or footprint) than the second semiconductor device.

[0295] The first device region and the second device region are preferably formed on a non-porous surface layer of the wafer.

[0296] The first semiconductor device and the second semiconductor device are preferably formed simultaneously by depositing semiconductor device structures on a plurality of device regions of a wafer.All semiconductor devices may be deposited in a single device epitaxy.

[0297] The method may include forming electrical contacts operably coupled to the first semiconductor device and the second semiconductor device such that the first semiconductor device and the second semiconductor device are independently drivable.

[0298] As described above with respect to the first aspect, the semiconductor device may be of a variety of different semiconductor device types.

[0299] In a preferred embodiment, the semiconductor device structure is an optoelectronic device structure (such as a light emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL)), so that the first semiconductor device and the second semiconductor device are both optoelectronic devices.

[0300] Alternatively, the semiconductor device structure may be an electronic or electrical component (such as a high electron mobility transistor (HEMT) or a radio frequency (RF) device). The semiconductor device structure may be a high electron mobility transistor (HEMT), such that both the first semiconductor device and the second semiconductor device are HEMTs; or the semiconductor device structure may be a radio frequency device, such that both the first semiconductor device and the second semiconductor device are radio frequency devices.

[0301] Particularly preferably, the semiconductor device structure is an LED structure (eg, a mini LED, a micro LED, or a nano LED structure).

[0302] Preferably, the first semiconductor device and the second device are both LED sub-pixels, such that the first semiconductor device and the second semiconductor device form a device pixel.

[0303] Manufacturing method of variable wavelength LED

[0304] As described above, in a preferred embodiment of the present invention, the semiconductor device formed on the wafer may be a variable wavelength LED.

[0305] Therefore, a method for fabricating a monolithic array of semiconductor devices on a wafer may include forming a variable wavelength LED. The method may include the steps of forming the variable wavelength LED by depositing a variable wavelength LED device structure over a first device region; and forming a second variable wavelength LED by depositing the same variable wavelength LED device structure over a second device region of the wafer.

[0306] Forming a variable wavelength LED may include the steps of growing:

[0307] n-doped part;

[0308] p-doped portion; and

[0309] A light emitting region is located between the n-doped portion and the p-doped portion, the light emitting region including a light emitting layer that emits light at a peak emission wavelength under an electrical bias across the light emitting region.

[0310] The method may include the step of overlying an n-doped portion, a p-doped portion, and a light emitting region overlying the porous region of the Group III nitride material.

[0311] The method may include forming a porous region of the Group III nitride material in at least one of the n-doped portion or the p-doped portion, and forming a light emitting region over the porous region of the Group III nitride material.

[0312] The light emitting layer can emit light at a peak emission wavelength between 400 nm and 800 nm, or between 450 nm and 800 nm, or between 500 nm and 800 nm, or between 550 nm and 800 nm, or between 610 nm and 800 nm under an electrical bias across the light emitting region.

[0313] The method may comprise the step of connecting a variable wavelength LED to a variable power supply.

[0314] The method may include connecting a variable wavelength LED to an LED driver configured to provide a variable power supply to the LED. The LED driver may be configured to control the power, current, or voltage of the power supply provided to the LED. The LED driver may be configured to provide a pulsed, continuous wave (CW), or quasi-continuous wave (quasi-CW) power supply to the LED.

[0315] A variable wavelength LED structure including an n-doped portion, a p-doped portion, and a light emitting region may be an LED structure for emitting light at a wavelength lower than the peak emission wavelength of the LED, such that the porous region of the Group III nitride material red-shifts the emission wavelength of the light emitting region to the peak emission wavelength.

[0316] The n-doped portion, the p-doped portion, and the light emitting region are preferably formed of a Group III nitride semiconductor material.

[0317] In a preferred embodiment, the light emitting region may include a light emitting indium gallium nitride layer for emitting light with a peak emission wavelength of 500nm-550nm or 550nm-600nm, wherein the overlying growth on the porous region of the Group III nitride material causes the emission wavelength of the light emitting region to shift to a peak emission wavelength between 600nm-750nm under electrical bias.

[0318] The light-emitting region can include a light-emitting indium gallium nitride layer configured to emit light at a peak wavelength of 500 nm to 550 nm, or 500 nm to 580 nm, or 510 nm to 570 nm, or 530 nm to 560 nm, or 550 nm to 600 nm. The light-emitting indium gallium nitride layer can be one or more layers known to emit light at these wavelengths when grown in conventional LEDs (e.g., on non-porous GaN substrates). However, the inventors have discovered that growing a conventional yellow or green LED structure on top of a porous Group III nitride layer can result in an LED that emits light at a peak emission wavelength between 600 nm and 750 nm under electrical bias.

[0319] The method may include the step of growing a yellow or green LED structure over the porous region of the Group III nitride material.

[0320] In a preferred embodiment, the light-emitting layer is a light-emitting indium gallium nitride layer. The LED preferably also includes a GaN material region. Due to the lattice mismatch between GaN and InGaN, the stress relaxation effect generated by the porous region is particularly advantageous.

[0321] The method may include forming a light-emitting active region having carrier localization centers in a quantum well, preferably an InGaN quantum well, such as a plurality of QW region types with different indium compositions, well widths, and quantum barriers, or quantum wells that are non-uniform, fragmented, broken, gapped, or discontinuous, resulting in well width fluctuations, InGaN quantum dots or nanostructures, or quantum wells formed on polar, semi-polar, or non-polar surfaces.

[0322] The method may include the step of forming a plurality of quantum wells (QWs), wherein the QWs are non-uniform, fragmented, or discontinuous.

[0323] The plurality of quantum wells may include indium composition fluctuations and / or well width fluctuations.

[0324] The method may include the step of forming one or more V-shaped pits in each variable wavelength LED structure, extending through the thickness of the light emitting region. Preferably, the method includes the step of forming at least 0.1 V-shaped pits per square micron, at least 1 V-shaped pit per square micron, or at least 2 V-shaped pits per square micron. Preferably, the method includes the step of forming a V-shaped pit with a density of at least 1×10 7 / cm 2 V-shaped pits (e.g. at least 5×10 7 / cm 2 or at least 1×10 8 / cm 2 , for example, the density is 1×10 7 / cm 2 to 5×10 9 / cm 2Preferably, the method comprises forming a V-shaped pit with a density of less than 5×10 9 / cm 2 V-shaped pits (e.g. less than 1×10 9 / cm 2 or less than 5×10 8 / cm 2 V-shaped pit) steps.

[0325] V-pits are a well-known phenomenon in epitaxial semiconductor growth, and methods for growing V-pits in semiconductor structures are known in the art. For example, V-pits and their growth are described in the prior art (The effect of nanometer-scale V-pits on electronic and optical properties and efficiency droop of GaN-based green light-emitting diodes; Zhou et al; Scientific Reports | (2018) 8:11053 | DOI: 10.1038 / s41598-018-29440-4).

[0326] The V-shaped pit can be grown in the semiconductor structure so that it ends in the layer below the active light-emitting area. This means that the V-shaped pit must extend through the thickness of the active light-emitting area.

[0327] By controlling the growth conditions during epitaxial deposition of a layer above a layer containing threading dislocations, V-shaped pits can be grown from threading dislocations in a semiconductor structure. As additional layers are grown above the layer containing threading dislocations, the threading dislocations extend upward through the structure, and by controlling the growth conditions, the dislocations are expanded into V-shaped pits.

[0328] The V-shaped pits can alternatively be grown using a three-dimensional epitaxial growth mode. 3D epitaxial deposition techniques known in the art are typically used to grow "islands" or "pyramids" of semiconductor material on a template. By controlling the deposition of the LED structure using 3D epitaxial deposition techniques, V-shaped pits can be artificially grown at desired locations without the need for threading dislocations to "seed" the formation of the V-shaped pits. By using this deposition control, the bottom (lowest point) of the pit can be created at a desired location in the structure (both the desired lateral position and the desired height in the structure, such as a specific semiconductor structure layer below the active light-emitting area).

[0329] The bottom of the V-shaped pit may be located in a connection layer of the semiconductor structure, and the connection layer may be located between the porous region and the n-doped portion.

[0330] The bottom of the V-shaped pit may be located in a pre-strained layer of the semiconductor structure, the pre-strained layer being located above the n-doped portion and below the light emitting region.

[0331] Preferably, each variable wavelength LED comprises a plurality of V-shaped pits extending across the active light emitting area.

[0332] The density and size (depth) of the V-shaped pits can be controlled. The size of the V-shaped pits can be controlled by the position and growth conditions of the pre-strained layer and the low-temperature InGaN layer that induce the pits.

[0333] The quantum wells (QWs) in the active light emitting region may be deposited such that the quantum wells are continuous and / or have a uniform thickness. Alternatively, the quantum wells (QWs) in the active light emitting region may be deposited such that the quantum wells are fragmented or discontinuous.

[0334] Manufacturing steps - variable wavelength LED

[0335] The n-type region, the light-emitting region, and the p-type region (which may be referred to as an LED structure) are preferably grown on a semiconductor wafer template, wherein the semiconductor wafer template includes at least a first porous region and, optionally, further includes porous regions having different porosity characteristics. The semiconductor wafer template may also include multiple layers of semiconductor material arranged to provide a suitable substrate for the overlying growth of the LED structure.

[0336] The method may include a first step of electrochemically porosifying the group III nitride material layer to form a porous region of the group III nitride material. This may be achieved using the wafer-level porosification process described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0337] Preferably, the method may include the step of forming a porous region of the Group III nitride material by electrochemical porosification through the non-porous Group III nitride material layer, such that the non-porous Group III nitride material layer forms a non-porous intermediate layer. The non-porous intermediate layer may advantageously provide a smooth surface for overlying growth of other layers (e.g., one or more connecting layers of Group III nitride material).

[0338] The porous region can be formed by making one or more layers or regions of a Group III nitride material porous on a substrate. The substrate can be silicon, sapphire, SiC, or β-Ga2O3. The crystal orientation of the substrate can be polar, semi-polar, or non-polar. The substrate thickness can typically vary between 100 μm and 1500 μm.

[0339] The porous region may be a porous layer, such that the method includes the steps of overlying the following on the porous III-nitride material layer: an n-doped portion; a p-doped portion; and an LED light-emitting region. Preferably, the porous region may be a continuous porous layer, for example, formed by a continuous porous III-nitride material layer.

[0340] The porous region may comprise a plurality of porous layers, and optionally a plurality of non-porous layers. In a preferred embodiment of the invention, the porous region is a stack of alternating porous and non-porous layers, the top surface of the stack defining the top of the porous region and the bottom surface of the stack defining the bottom of the porous region.

[0341] Alternatively, the porous region may be a layer of Group III nitride material that includes one or more porous regions, such as one or more porous regions in an otherwise non-porous layer of Group III nitride material.

[0342] In a preferred embodiment, the porous region or layer may have a lateral dimension equal to the lateral dimension (width or length) of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes may have various sizes, such as 1 cm in diameter. 2 , or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches. However, by patterning one or more layers and / or depositing regions of different carrier concentrations in the same layer, smaller porous regions that do not span the entire substrate can be formed. Thus, the lateral dimensions of the porous layer or porous region can vary from about 1 / 10 of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself.

[0343] Prior to the porosification step, a doped region of n-doped III-nitride semiconductor material may be deposited on the substrate, preferably comprising a layer or a stack of layers. The III-nitride layer may comprise a combination of one or more of the following elements: Al, Ga, In (ternary or quaternary layers). The thickness of the III-nitride stack is preferably between 10 nm and 4000 nm. The doping concentration of the III-nitride region may be between 1×10 17 cm -3 -5×10 20 cm -3 between.

[0344] Preferably, an intermediate layer of undoped Group III nitride material is deposited on top of the doped material and then made porous. The thickness of the intermediate layer is preferably between 1 nm and 3000 nm, more preferably between 5 nm and 2000 nm. When the intermediate layer is undoped, it remains non-porous after the porosification step, which advantageously provides a good surface for epitaxial overgrowth of other semiconductor layers.

[0345] In a preferred embodiment, the doped region comprises an alternating stack of doped and undoped layers. In a preferred embodiment, the stack comprises 5-50 pairs of layers. The thickness of each highly doped layer can vary between 10 nm and 200 nm, and the thickness of the lowly doped or undoped layers can range from 5 nm to 180 nm.

[0346] As is known in the art, electrochemical porosification removes material from the n-type doped regions of the Group III nitride material and forms vacancies in the semiconductor material.

[0347] In a preferred embodiment, the LED structure is formed on multiple porous Group III nitride material layers. Therefore, the porous region may not be a single porous layer of Group III nitride material, but rather a stack of multiple Group III nitride material layers, at least some of which are porous. The stack of porous layers may preferably be a stack of alternating porous and non-porous layers.

[0348] The method preferably includes the following steps: before growing an n-doped region, an LED light emitting region and a p-doped region overlying the connecting layer, depositing one or more connecting layers of group III nitride material on the surface of the intermediate layer of group III nitride material.

[0349] Alternatively, in the absence of a non-porous intermediate layer above the porous region, the method may comprise the step of depositing a connecting layer of Group III-nitride material onto the surface of the porous region of Group III-nitride material.

[0350] The method may include the further step of overlying the n-doped region, the LED light emitting region, and the p-doped region on the connection layer.

[0351] The variable wavelength LED produced by the manufacturing method is preferably the variable wavelength LED described above with respect to the first aspect.

[0352] Manufacturing display devices

[0353] In a sixth aspect, the present invention may provide a method for manufacturing a display device, comprising manufacturing a semiconductor device array on a wafer according to the fifth aspect of the present invention. In the method of the sixth aspect, the first semiconductor device and the second semiconductor device are both LED sub-pixels, such that the first semiconductor device and the second semiconductor device constitute a device pixel, and the method comprises forming an array of a plurality of device pixels on the wafer.

[0354] Since all aspects of the present invention are interrelated, any features described in relation to one aspect may be equally applicable to other aspects of the present invention.

[0355] It should be understood that the methods and structures of the present invention are not limited to the specific examples described herein and may be implemented in other examples without departing from the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0356] Specific embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0357] Figure 1 A schematic side cross-sectional view of a template wafer according to one aspect of the present invention;

[0358] Figure 2 is a schematic side cross-sectional view of two semiconductor device monolithic arrays according to one aspect of the present invention;

[0359] Figure 3 is a schematic side cross-sectional view of a monolithic array of three semiconductor devices according to one aspect of the present invention;

[0360] Figure 4 For processing into display devices Figure 3 A schematic side cross-sectional view of a device;

[0361] Figure 5A is a schematic plan view of a semiconductor wafer before being made porous according to an embodiment of the present invention;

[0362] Figure 5B for Figure 5A A schematic plan view of a semiconductor wafer after being made porous in the first porous area;

[0363] Figure 6A is a schematic plan view of a semiconductor wafer before being made porous according to an embodiment of the present invention;

[0364] Figure 6B yes Figure 6A A schematic plan view of a semiconductor wafer after being made porous in the first porous region and the second porous region;

[0365] Figure 6C After the first semiconductor device array and the second semiconductor device array are overly grown according to the preferred embodiment of the present invention, Figure 6B A schematic plan view of a semiconductor wafer;

[0366] Figure 7 is a plan view schematically illustrating a monolithic array of two different types of semiconductor devices on a wafer according to a preferred embodiment of the present invention;

[0367] Figure 8 A schematic plan view of a wafer template comprising an array of first porous areas and second non-porous areas according to a preferred embodiment of the present invention;

[0368] Figure 9After the first semiconductor device array is overly grown on the first porous region and the second semiconductor device array is overly grown on the second non-porous region according to a preferred embodiment of the present invention, Figure 8 A schematic plan view of a semiconductor wafer;

[0369] Figure 10 A schematic plan view of a wafer template comprising an array of first porous areas and second non-porous areas according to a preferred embodiment of the present invention;

[0370] Figure 11 After the first semiconductor device array is overly grown on the first porous region and the second semiconductor device array is overly grown on the second non-porous region according to the preferred embodiment of the present invention, Figure 10 A schematic plan view of a semiconductor wafer;

[0371] Figure 12A This is an optical microscope image of a plan view of a semiconductor wafer before being porous;

[0372] Figure 12B for Figure 12B Planar image of a semiconductor wafer after being porous.

[0373] Figure 13 An optical micrograph of a plan view of a patterned semiconductor wafer showing a cross-shaped porous region formed in a particular wafer layer, the cross-shaped porous region being surrounded by non-porous semiconductor material;

[0374] Figure 14 shows the different emission wavelengths produced by the same epitaxial LED structure located over a porous region of a semiconductor wafer compared to a non-porous region of the semiconductor wafer;

[0375] Figure 15 This is a series of five EL images of the same micro-LED pixel driven at different currents in constant wave mode (CW), showing five different emission colors;

[0376] Figure 16A The relationship between emission wavelength and current density of a 25 μm × 25 μm variable wavelength LED pixel array (100 × 100) driven by a 100 μs pulse with a 1% duty cycle in pulse mode;

[0377] Figure 16B The relationship between emission wavelength and current density of a 30 μm × 30 μm variable wavelength LED pixel array (100 × 100) driven by a 100 μs pulse with a 1% duty cycle in pulse mode;

[0378] Figure 17The intensity versus wavelength graph of a single variable wavelength LED driven with different currents using 100 microsecond pulses with a 1% duty cycle in pulse drive mode;

[0379] Figures 18A-18G shows an alternative embodiment of a non-uniform, fragmented or discontinuous light emitting region of a variable wavelength LED that can be used in the preferred embodiment of the present invention;

[0380] Figure 19A TEM image of the cross section of a conventional non-variable wavelength LED;

[0381] Figure 19B TEM image of a light emitting region of a variable wavelength LED including a V-shaped pit that can be used in an embodiment of the present invention;

[0382] Figure 19C For the preferred embodiment of the present invention Figure 19B TEM image of a variable wavelength LED showing a porous region and a light-emitting region including multiple V-shaped pits;

[0383] Figure 20A This is the relationship between the peak emission wavelength and the driving current density of a conventional non-variable wavelength LED;

[0384] Figure 20B is a graph showing the relationship between the peak emission wavelength and the driving current density of a variable wavelength LED according to an embodiment of the present invention;

[0385] Figure 20C is a graph showing the relationship between the peak emission wavelength and the driving current density of a variable wavelength LED according to another embodiment of the present invention;

[0386] Figure 21A is a graph showing the relationship between the peak emission wavelength and the driving current density of another variable wavelength LED that can be used in an embodiment of the present invention;

[0387] Figures 21B-21D yes Figure 21A Photograph of a variable-wavelength LED, with the inset emission spectra showing the different peak emission wavelengths at different drive current densities. DETAILED DESCRIPTION

[0388] Figure 1 A multi-well template wafer 10 suitable for processing into a monolithic array of semiconductor devices according to the present invention is shown.

[0389] The porous template includes a porous region of Group III nitride material that occupies a portion of a non-porous Group III nitride material layer on a substrate. A non-porous buffer layer 20 is positioned between the substrate and the layer comprising the porous region, and a non-porous surface layer 30 of Group III nitride material is disposed above the upper surface of the porous region. Optionally, additional layers of Group III nitride material may be positioned between the substrate and the porous region, and between the porous region and the surface of wafer 10.

[0390] The porous region can be generated by epitaxially growing a layer of group III nitride material on the substrate, wherein a portion of the layer is formed of an n-doped group III nitride material and another portion of the same layer is formed of an undoped group III nitride material. The undoped group III nitride material layer is then deposited on top of the layer comprising the n-doped material. The porous region is then formed by making the n-doped region porous using the porosification process specified in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728), while the undoped material in the template wafer remains non-porous.

[0391] As mentioned above, this porosification leads to a relaxation of strain in the crystal lattice, which means that the subsequent overlying growth of other semiconductor layers benefits from the reduction of the compressive strain in their crystal lattices.

[0392] After the porosification step, the wafer 10 comprises a porous region that remains where the n-doped Group III-nitride material was previously present and a non-porous surface layer 30 overlying the porous region.

[0393] The porosity of the porous region is controlled by the electrochemical etching process and the initial doping level of the porous n-type Group III nitride material. The porosity of the porous region can be controlled to be between 1% and 99% porous, preferably between 20% and 90% porous, or between 30% and 80% porous, although lesser or greater porosities may also be used.

[0394] The thickness of the porous region after being made porous depends on the starting structure of the n-type Group III nitride material after being made porous. The thickness of the porous region is preferably greater than 1 nm, more preferably greater than 10 nm, and particularly preferably at least 40 nm, 50 nm, or 100 nm. However, the thickness of the material required to achieve the strain relaxation benefits provided by the porous region can vary depending on the type of Group III nitride material used to make the porous region.

[0395] The porous region created by the porosification process can be a bulk layer of a III-nitride material having a uniform composition and a uniform porosity throughout the porous region. Alternatively, the porous region can include multiple layers of porous materials of different compositions and / or porosities to form a porous stack of III-nitride materials. For example, the porous region can be a continuous porous GaN layer, or a continuous porous InGaN layer, or a stack comprising one or more layers of porous GaN and / or one or more layers of porous InGaN. The inventors have found that the strain relaxation benefits of a porous region for overlying growth can be obtained in a wide range of porous regions having different thicknesses, compositions, and layered stacks.

[0396] In the embodiment shown in the figures, the porous region occupies a portion of a single layer of wafer 10 .

[0397] The undoped capping layer 30 of the III-nitride material on the doped region and the undoped capping layer 30 of the III-nitride material on the undoped region in the same layer of the porous region remain non-porous after the through-surface porosification of the n-doped region. The thickness of the non-porous capping layer 30 is preferably at least 2 nm, or at least 5 nm, or at least 10 nm, preferably 5 nm to 3000 nm. Providing the undoped capping layer on the doped region advantageously results in a non-porous III-nitride material layer covering the porous region after the porosification. The non-porous capping layer can advantageously allow for better overlying growth of other materials above the porous region.

[0398] The porous region can include one or more layers of one or more Group III nitride materials and can have a range of thicknesses while still providing strain relaxation benefits that affect the electronic and / or optoelectronic properties of a semiconductor device overlying the porous region. For example, the presence of a porous region below an overlying LED can shift the peak emission wavelength of an InGaN light-emitting layer overlying the porous region. In preferred embodiments, the porous region can, for example, include GaN and / or InGaN.

[0399] exist Figure 1 Various semiconductor device structures can be grown over the template wafer shown. Although other electronic or optoelectronic semiconductor devices can be used in the present invention, the present invention is illustrated with reference to LEDs.

[0400] In particular, LED structures containing InGaN light-emitting layers known in the art for making yellow or green LEDs can be overly grown on porous templates using standard LED fabrication steps. However, when grown above the porous region of the template, the LED device structure, which normally emits light at a first wavelength, will emit light at a red-shifted, longer wavelength.

[0401] Thus, the presence of a porous region of Group III nitride material acts as a template or pseudo-substrate for overlying growth of known InGaN LED structures, allowing for the fabrication of longer wavelength LEDs in a straightforward manner.

[0402] In the present invention, unlike the prior art, not all semiconductor devices on a wafer are formed on the same porous region. Figure 1 As shown, in the present invention, the porous region occupies only a portion of the lateral area of ​​the wafer, and therefore, only a portion of the surface layer of the wafer is located above the porous region, while another portion of the surface layer is not located above the porous region.

[0403] Figure 2 A monolithic array 100 of two LED devices formed on a wafer 10 by a single epitaxy is shown. A first LED device 150A is formed in a first device region above a porous region, and an identical second LED device 150B having the same epitaxial structure as the first LED device is formed in a second device region above a portion of the wafer that does not contain the porous region. Because the first LED 150A has been overly grown on the porous region of the III-nitride material, the peak emission wavelength of the first LED 150A will be red-shifted relative to the identical second LED 150B that was not overly grown on any porous material. Even though the two LEDs 150A, 150B are identical and monolithically formed in a single epitaxy, the light emission properties of the two LEDs are therefore different. This enables monolithic integration of LEDs of different colors using a single device epitaxy.

[0404] The properties of the porous region can be varied to adjust the red shift imparted on the overlying grown LED. For example, the doping level of the n-doped material to be made porous can be varied to obtain different resulting porous regions. The type of electrolyte or electrolyte concentration used in the porosification process can be varied to change the properties of the resulting porous region. The etching voltage and / or current used in the porosification process can be varied to change the characteristics of the resulting porous region. The size and structure of the porous region can also be varied by changing the size and structure of the n-doped Group III nitride material deposited on the substrate. By varying these factors, a wide range of porous regions can be formed, which in turn can impart a wide range of wavelength shifts on the overlying grown optoelectronic device.

[0405] In some embodiments, multiple separate porous regions may be provided in a single wafer.

[0406] The separate porous regions may be formed simultaneously in the same porosification step, for example by forming two separate regions with different doping levels.

[0407] Alternatively, individual porous regions can be formed one by one by masking the surface layer of the wafer 10, patterning the mask layer by photolithography to expose certain device regions, and then performing a through-surface porosification through the exposed device regions to make the n-doped regions below the exposed device regions porous. The exposed device regions can then be masked, followed by exposing a second set of device regions, and then performing a through-surface porosification through the second set of exposed device regions to make the n-doped regions below the second set of exposed device regions porous. Using this process, different porosification techniques (e.g., different electrolytes and etching parameters) can be applied to the two device regions, resulting in different resulting porous regions.

[0408] Figure 3 An alternative embodiment of a monolithic array 200 of three LEDs on a wafer is shown, wherein the wafer comprises three separate regions having different porosity characteristics: a first porous region upon which a first LED 150A has been overlying grown; a second porous region upon which a second LED 150B has been overlying grown; and a third porous region upon which a third LED 150C has been overlying grown. Figure 2 In the case of , all LEDs are structurally identical because the LEDs are deposited on the wafer in a single epitaxial growth step, which forms all three LEDs simultaneously.

[0409] Individual LEDs 150A, 150B, and 150C can be formed by masking the surface layer of a template wafer using a dielectric mask layer (not shown) and, for example, removing regions of the mask layer by photolithography to expose first, second, and third device regions on the surface layer. With these device regions exposed and the remainder of the wafer surface masked by the dielectric, the epitaxial layers of the LED structure can be deposited only in the unmasked regions of the wafer surface layer. Thus, the first, second, and third LEDs can be grown simultaneously using the same epitaxial deposition step.

[0410] The porosity characteristics of the porous regions, such as porosity percentage, average pore size, size, etc., can differ between the three porous regions. The structure of the porous regions can also differ between the porous regions. For example, one porous region can be a continuous layer of uniform porosity, while another porous region can include multiple layers of porous material. The porosity characteristics of the underlying porous region have an impact on the crystal structure of the semiconductor device grown overlying it. For example, the porosity percentage of the porous region may affect the strain experienced by the semiconductor structure grown overlying it. The differences in the porosity characteristics of the three porous regions mean that the first, second and third LEDs grown overlying the first, second and third porous regions inherit different characteristics from the porous regions below them. Even if the first, second and third LEDs are grown simultaneously with the same epitaxial structure, the different underlying porous regions will therefore produce differences between the electronic / optoelectronic characteristics of the three LED devices.

[0411] Figure 4 Shown after additional processing steps Figure 3 In a monolithic array, this additional processing step isolates the three LEDs and provides electrical contacts that allow the three LEDs to be individually controlled by providing separate drive currents to each LED on the wafer.

[0412] The present invention is not limited to any precise structure of the LED device. However, in the schematic illustration of the figure, the layers of the LED device are as follows:

[0413] 1-Connection layer 1 of group III nitride material

[0414] n-doped layer of group II-III nitride material

[0415] 3-Luminous area

[0416] 4-Non-doped capping layer

[0417] 5-Electron blocking III-nitride layer (EBL)

[0418] 6-p doped layer

[0419] 7-Transparent conductive layer

[0420] 8-Passivation layer

[0421] 9-Electrical p contact

[0422] 10-Electrical n contact

[0423] 11-Device backplane / micro driver circuit board

[0424] The thickness and composition of these layers can vary, as is known in the art. Figure 4 The technology of the device is well known in the art.

[0425] Figure 5A FIG. 1 is a schematic plan view of a semiconductor wafer before being made porous according to an embodiment of the present invention. Figure 5B The same wafer is shown after porosification of the n-doped portion of the wafer into a first porous region. Figure 5C The same wafer is shown after overlying growth of a first array of semiconductor devices over the porous region and a second array of semiconductor devices over the non-porous region.

[0426] In the plan view of the figure, the non-porous surface layer actually located above the n-doped / porous region has been omitted for illustration purposes, so that the lateral footprint of the various regions in the wafer is visible.

[0427] Figure 5CThe wafer 500 is prepared by selectively doping an array of first regions 50 with an n-type dopant during epitaxial growth. The wafer is patterned to form first regions spaced apart across the wafer. This increases the carrier concentration in the selected n-doped first regions, while the array of second regions 60 remains undoped.

[0428] Prior to electrochemical porosification, the upper surface of the wafer is covered with a mask layer. The mask layer is then patterned to remove an array of selected areas of the mask layer to expose areas of the surface layer located above the array of first regions 50. Through-surface electrochemical porosification is then performed on the wafer 500, such that the n-type first regions 50 are porosified into an array of porous regions 55. While the remainder of the wafer is undoped and masked, the remainder of the wafer 500 remains non-porous after the porosification process, as shown in FIG. Figure 5B The undoped second region 60 remains unchanged after being made porous, thereby forming a non-porous second region 60 of the wafer.

[0429] The porous region can be endowed with different porous properties. For example, by controlling etching conditions / environmental conditions, the porosity, porous thickness, pore size, etc. can be controlled and regulated.

[0430] This masking and covering process can be done once or repeated several times.

[0431] The patterned area can be of any shape / geometry / combination / configuration, i.e. any size, shape and pattern can be achieved.

[0432] The resolution of the porous patterning process can be very high, at the nanometer scale, such as 1nm, 10nm, 100nm, 200nm, 500nm, 1μm, 2μm, 5μm, 10μm, 100μm, or more. Since photolithography is more precise than this, this patterning resolution / definition is not limited, and there are several different ways to control / improve the resolution. Namely, etch conditions, illumination, epitaxial design of different layers, and implantation to improve etch selectivity.

[0433] like Figure 5C As shown in , semiconductor devices may then be grown overlying the wafer 500 .

[0434] The area of ​​the wafer surface above each porous region 55 forms an array of first device areas on which a first set of devices can be grown overlying the array. All devices grown on these first device areas will experience the same porous region below them, so identical devices grown on top of the array of porous regions 55 will all operate in the same manner. Figure 5CIn FIG. 5 , a first array of semiconductor devices is overlyingly grown on an array of porous regions 55. A separate array of second semiconductor devices is overlyingly grown on an array of non-porous regions 60.

[0435] The first semiconductor device and the second semiconductor device are deposited in the same device epitaxy and are therefore identical in composition and structure. However, because the first device is overlying grown on the porous region 55 and the second device is overlying grown on the non-porous region 60, the two sets of devices will exhibit different electronic / optoelectronic properties.

[0436] Figures 6A-6C An alternative embodiment of the present invention is shown in which the second region is an n-doped region 70 rather than an undoped region. Figure 6B As shown, in this embodiment, the n-doped second region is porousified to form a second porous region 75, which can be performed simultaneously with the porousification of the first porous region (if the second n-doped region 70 has a different carrier density than the first n-doped region 50), or alternatively, this can also be performed in a separate porousification step during masking of the first device area.

[0437] The porosity characteristics of the first porous region 55 and the second porous region 75 are different. By doping these regions to different degrees or by changing the etching parameters used to make the corresponding regions porous, factors such as size, layer structure, porosity percentage, average pore size, etc. can be changed so that the second porous region is different from the first porous region.

[0438] When performing porosification of the subsurface n-doped regions through the surface layer of the wafer 500, a mask layer of electrically insulating material can be deposited on the surface layer and patterned to expose selected areas of the surface layer of the wafer. Porosification is then performed through the exposed areas to porosify any n-doped subsurface material beneath the exposed areas, while areas of material beneath the masked portions of the surface layer remain non-porous regardless of their conductivity.

[0439] By masking the surface layer above the first region while simultaneously making the second region porous through exposed areas of the surface layer above the second region, or vice versa, different etching parameters can be used to etch the first and second regions. For example, different etching voltages and / or currents can be used, or different electrolytes can be used. This can advantageously allow the porosity characteristics of these regions to be varied to a greater extent than would be possible by simply varying the carrier density of these regions.

[0440] like Figure 6C As shown, Figure 5C Similarly, a first array of semiconductor devices is grown overlying the array of porous regions 55, and a second array of semiconductor devices is grown overlying the array of second porous regions 75. Figure 6CIn this case, the second semiconductor device is grown overlying the porous material, so the performance of the second device will be similar to that of the Figure 5C The performance of the same device in the examples is different.

[0441] Figure 6C The first and second semiconductor devices in FIG. 5 are deposited in the same device epitaxy and are therefore identical in composition and structure. However, because the first device is overlying grown on a first porous region 55, while the second device is overlying grown on a second porous region 75 having different porosity characteristics, the two sets of devices will exhibit different electronic / optoelectronic properties.

[0442] Figure 7 FIG. 1 is a plan view of a monolithic array of two different types of semiconductor devices on a wafer according to a preferred embodiment of the present invention.

[0443] As mentioned above, a variety of different semiconductor devices may be overly grown on a wafer. Regardless of the type of device structure being overly grown, if the template wafer contains locally patterned porous and non-porous regions beneath the device, the optical and electrical properties of the devices will differ depending on which region of the wafer they are formed on.

[0444] Before the devices are grown overlying the wafer, the surface layer can be masked and then photolithographically patterned to expose an array of first and second device regions. The first device region is located above the first porous region 55, while the second device region is located above the second region 60 (or second porous region 75). By known epitaxial deposition techniques, the devices can be grown overlying the wafer so that the device structure layers are deposited only in the exposed areas of the wafer surface that are not masked. In this way, the lateral size and shape of the device can be controlled. Therefore, mini-LED, micro-LED (μLED) or even nano-LED pixels can be grown by changing the size of the exposed areas that are patterned into the mask layer before overlying growth, so that the pixels or sub-pixels are aligned above the porous / non-porous areas.

[0445] In a particularly preferred embodiment, an LED can be formed on the wafer. As described above, the LED can be a monochromatic LED, wherein the peak emission wavelength of the LED above the porous material is red-shifted relative to the same device structure above the non-porous wafer portion. Alternatively, a variable wavelength LED can be formed on the wafer, such that the peak emission wavelength of the variable wavelength LED can be adjusted over a wide wavelength range by varying the drive current supplied to the variable wavelength LED.

[0446] exist Figure 7 In the embodiment shown, Figure 5B or Figure 6BAn array of two types of variable wavelength LED devices is formed on such a wafer. As described above, the variable wavelength LEDs are preferably formed on a porous region of a Group III nitride material, whose light emitting region has discontinuities (e.g., a high density of V-shaped pits extending through the light emitting region), which enables emission over a wide wavelength range.

[0447] exist Figure 7 In the figure, a red-green variable-wavelength LED is shown grown overlying a first porous region 55, while a green-blue variable-wavelength LED is shown formed over a second porous region 75. The different emission wavelength ranges of the two LED types can be determined by the different properties of the first and second porous regions, respectively. By varying the driving conditions applied to the LEDs, the peak emission wavelength of each LED can be individually controlled within its given wavelength range.

[0448] Thus, by epitaxy of a single LED structure, a first array of pixels can be formed, where the first array of pixels can emit red-green light due to the underlying first porous region 55, and a second array of pixels can emit green / blue light due to the underlying second porous region 75. This advantageously allows the formation of two LED arrays emitting a wide range of wavelengths on a single wafer from epitaxy of a single device.

[0449] Even though a square array of LEDs is shown in the figures, alternative arrangements are of course possible.

[0450] Figure 8 is a schematic plan view of a wafer template including an array of first porous areas and second non-porous areas according to a preferred embodiment of the present invention.

[0451] By controlling the carrier concentration of the subsurface n-type region, and optionally the exposed areas formed in the mask layer before porosification, the size and shape of the porous and non-porous regions can be controlled. The porous region can be controlled to have the same, larger, or smaller size or a different shape than the non-porous region.

[0452] exist Figure 8 In this embodiment, a first device region is located on the surface area directly above the porous region, while a second device region is located on the surface area directly above the non-porous region. These first device regions differ in size from the second device region located above the non-porous region. As a result, an LED overlying the first device region has larger lateral dimensions than an LED overlying the non-porous material overlying the second device region. By overlying LEDs of different lateral dimensions, the light-emitting area of ​​the LED can be varied, which in turn determines the brightness of the emitted light.

[0453] Figure 9After the first semiconductor device array is overly grown on the first porous region and the second semiconductor device array is overly grown on the second non-porous region according to a preferred embodiment of the present invention, Figure 8 Schematic diagram of a plan view of a semiconductor wafer.

[0454] Figure 9 A particularly preferred embodiment is shown in which a conventional green LED structure is overly grown on the wafer. Figure 9 The porous region of the wafer is located below the first LEDs, which causes a red shift in the peak emission wavelength of these LEDs. The second LEDs are formed above the non-porous portion of the wafer, which does not shift their emission wavelengths. This difference in emission wavelengths caused by the porous region in the wafer means that the first LEDs emit a peak emission wavelength in the red, while the identical second LEDs emit a peak emission wavelength in the green / blue.

[0455] Since red LEDs typically emit at a lower brightness than green / blue LEDs, a larger lateral dimension of the first (red) LED may advantageously help provide brightness compensation.

[0456] The ratio of the lateral area occupied by the porous area / non-porous area can be controlled to be larger, smaller or equal to each other. For example, the porous area under the red LED can have a lateral area that is twice as large as the lateral area of ​​the non-porous area under the green / blue LED.

[0457] exist Figure 9 In the embodiment of FIG. 5 , each LED constitutes a sub-pixel, and each pair of sub-pixels (one red, plus one green / blue) constitutes a device pixel.

[0458] Alternatively, LEDs of different colors can also be formed on a wafer in a corresponding manner.

[0459] Figure 10 is a schematic plan view of a wafer template including an array of first porous areas and second non-porous areas according to a preferred embodiment of the present invention.

[0460] exist Figure 10 In one embodiment, an array of porous regions is formed in a wafer, interspersed with an array of non-porous regions. The arrays of porous and non-porous regions are positioned relative to each other to form pairs of porous and non-porous regions, with additional porous regions positioned between adjacent pairs. The porous regions have lateral dimensions greater than the non-porous regions.

[0461] choose Figure 10 The arrangement of porous and non-porous regions in the template wafer provides a template for overlying growth of LEDs to produce a Figure 11 A monolithic array of LEDs is shown.

[0462] Figure 11 After the first LED array is overly grown on the porous region and the second LED array is overly grown on the non-porous region according to a preferred embodiment of the present invention, Figure 10 Schematic diagram of a plan view of a semiconductor wafer.

[0463] like Figure 9 As shown, in this embodiment, the porous region is larger and has a different shape than the non-porous region in the wafer. Therefore, the first LED overlying the porous region is also larger and has a different shape than the second LED overlying the non-porous region. In a preferred embodiment, the first LED is a red LED, either a single-wavelength red LED or a variable-wavelength LED intended for use in a display device to emit red light.

[0464] In the variable wavelength LED as described above, red light is emitted in response to a low driving current, and thus the brightness of the emitted red light is lower than that of a green LED of an equivalent light emitting area.

[0465] exist Figure 11 In an embodiment, an array of first red LEDs and second green / blue LEDs are arranged as sub-pixels of a display pixel array, and additional red LEDs formed above the additional porous area serve as "shared" red pixels that can be used to add red light to the red light emitted by the red sub-pixels on either side.

[0466] Alternative pixel arrangements and LED colors may also be used.

[0467] Figure 12A is a plan view optical microscope image of a semiconductor wafer before porousification, and Figure 12B for Figure 12B This is a plan view image of a semiconductor wafer after porosification. In this example, the wafer was not patterned to form regions of different carrier concentrations, and no mask layer was used to mask the surface layer regions during the porosification process. This means that Figure 12B The porosity in the porous wafer is shown to be uniform.

[0468] Figure 13 This is a plan-view optical microscope image of a patterned semiconductor wafer, showing a cross-shaped porous region surrounded by non-porous semiconductor material in a specific wafer layer. This illustrates how porous regions of precise shape and size can be created by masking predetermined areas of the wafer surface before porosification. By doping the region to be porosified, for example using ion implantation, the resolution and selectivity of the porosification process can be improved.

[0469] Figure 14The different emission wavelengths produced by the same epitaxial LED structure located on a porous region of a semiconductor wafer are shown compared to those located on a non-porous region of the semiconductor wafer. In this wafer, a region around the periphery of the wafer is masked during the porosification process, preventing the etching electrolyte from contacting the wafer surface or wafer edge in this region. Consequently, the subsurface n-type material in this masked region is not porosified.

[0470] Figure 14 A photoluminescence (PL) wavelength map is shown, comparing the porous region and non-porous region of a single, continuous LED epitaxial structure on the same wafer after LED epitaxy across the entire wafer. The PL wavelength map clearly shows that the peak emission wavelength (545.2 nm) of the LED structure in the non-porous region of the wafer is much shorter in wavelength than the peak emission wavelength (572.2 nm) of the same LED structure overlying the porous region, with a very clear boundary between the luminescence behavior of the porous and non-porous regions of the wafer. As described above, by selectively doping and masking different regions of the wafer, it can be transferred to the mini-scale, micro-scale, or nano-scale, allowing the wafer to be pre-patterned to transform a single LED epitaxy into an array of semiconductor devices with different electronic and / or optoelectronic properties.

[0471] In some preferred embodiments of the present invention, the first semiconductor device and the second semiconductor device are LEDs. In particular, the first and / or second semiconductor devices may be variable-wavelength LEDs that are adjustable to emit a peak emission wavelength within a wavelength range greater than 40 nm. For example, all LED devices on a wafer may be variable-wavelength LEDs formed above the porous region of the wafer, or the first semiconductor device may be a variable-wavelength LED formed above the first porous region, while the second semiconductor device is a "single-wavelength" (non-variable-wavelength) LED having the same structure as the first LED but not overlying the porous region.

[0472] Figure 15 This is a series of five EL images of the same variable-wavelength micro-LED InGaN pixel driven at different currents in constant wave mode (CW), showing five different emission colors. In the image on the left, you can see that the micro-LED emission color is red at a drive current of 50μA. In the second image on the left, at a drive current of 100μA, you can see that the micro-LED emission color is red-orange. In the third image on the left, at a drive current of 1mA, you can see that the micro-LED emission color is orange. In the fourth image on the left, at a drive current of 10mA, you can see that the micro-LED emission color is yellow-green. In the image on the right, at a drive current of 20mA, you can see that the micro-LED emission color is green.

[0473] Therefore, by varying the drive current between 50 μA and 20 mA, the same micro-LED can emit light at wavelengths ranging from red to green. The spectral width of this emission wavelength range is approximately 90 nm (from approximately 570 nm to approximately 660 nm). This is a wider range of emission wavelengths than can be achieved with a single LED in the prior art.

[0474] Figure 16A Graph showing the relationship between emission wavelength and current density for a 25 μm×25 μm InGaN LED pixel array (100×100 array, containing 10,000 pixels) driven in pulse mode with a 100 μs pulse at a 1% duty cycle. Figure 16B Graph showing the relationship between emission wavelength and current density for a 30 μm×30 μm InGaN LED pixel array (100×100 array, containing 10,000 pixels) driven in pulse mode with 100 μs pulses at 1% duty cycle.

[0475] Both figures demonstrate the controllability of peak emission wavelength using a pulsed drive power supply. Specifically, the wavelength is linearly correlated with current density (plotted on a logarithmic scale). This linearity can also be manipulated when driving using a pulsed voltage power supply. Thus, the variable emission wavelength of an LED can be controlled using voltage or current drive schemes in either CW or pulsed modes, all of which are standard features of display driver ICs.

[0476] For the purposes of LED display design, a linear relationship between the driving current density and the resulting emission wavelength is highly advantageous because it enables precise control of the emission wavelength by varying the current density of the power supply.

[0477] Figure 17 Figure 2 shows the intensity versus wavelength relationship of a variable-wavelength InGaN LED driven with different DC currents. The power supply was operated in pulsed drive mode with 100-microsecond pulses at a 1% duty cycle.

[0478] Figure 17 This again demonstrates a gradual, continuous shift in the LED's peak emission wavelength as the power supply current changes. At a drive current of 200mA, the peak emission wavelength is approximately 575nm, with an intensity of approximately 10μW / nm. However, as the drive current decreases, the peak emission wavelength gradually shifts to longer wavelengths and lower emission intensities. When the drive current reaches 7mA, the peak emission wavelength reaches approximately 675nm, with an intensity of approximately 0.1μW / nm.

[0479] Figures 18A-18G Alternative embodiments of light emitting regions of variable wavelength LEDs that may be used as semiconductor devices in embodiments of the present invention are shown.

[0480] Example of MQW:

[0481] 1. Continuous MQW

[0482] 2. V-shaped pit

[0483] 3. Broken QW, gap QW, fragmented QW

[0484] 4. Quantum Dots (QD)

[0485] 5. Well width fluctuation

[0486] 6.Alloy composition

[0487] 7. Different combinations of MQW and underlying materials

[0488] These structural features can be identified and examined by standard materials characterization techniques such as cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD), energy dispersive X-ray spectroscopy (EDX or EDS), and 3D atom probe (3DAP).

[0489] Figure 18A A continuous MQW emission region of an LED is shown, where three identical quantum barriers (QBs) are arranged between four identical QWs.

[0490] Figure 18B Shown Figure 18A A continuous MQW, wherein a V-shaped pit extends through the light-emitting region, the V-shaped pit terminates with a threading dislocation, and has a QW at its semipolar plane.

[0491] Figure 18C An MQW is shown where the QW layer includes a discontinuity or gap in the semiconductor material.

[0492] Figure 18D It is shown that quantum dots (QDs) in MQWs produce non-uniform MQWs. The QDs can be disposed on or in the QB or QW layer, for example in the gaps in the QW structure.

[0493] Figure 18E An MQW with fluctuating well width is shown, where the thickness of the QW layer is non-uniform in the light-emitting region. The QWs can have different widths from one another, or within a single QW.

[0494] Figure 18F An MQW with fluctuating alloy compositions in the light-emitting region is shown. The compositions of the QB and QW layers vary from layer to layer. Specifically, the indium (In%) composition varies within the same QW, e.g., in QW2, the In% varies between 10%-12%, 10%-15%, 10%-25%, or 10%-35%.

[0495] Figure 18GMQWs containing different combinations of MQWs and underlying layers are shown. The In% composition varies between different QWs. For example, QW1 has an In% of 15%, QW2 has an In% of 25%, and QW3 has an In% of 30%. In embodiments of the present invention, low-In% QWs are preferably located at the bottom of the MQW due to strain and thermal effects, while high-In% QWs are preferably located at the top. In a preferred embodiment, for example, QW1 is a blue-emitting QW, QW2 is a green-emitting QW, and QW3 is a red-emitting QW.

[0496] Figure 19A TEM image of a cross section of a conventional non-variable wavelength LED. In this non-variable wavelength LED, the MQWs are uniform and smooth at both the upper and lower interfaces (five MQWs are shown here).

[0497] Figure 19B and 19C TEM images show a variable wavelength LED including V-shaped pits, which can be used in embodiments of the present invention. In this variable wavelength LED, the MQW is non-uniform. This non-uniformity can be induced by various methods, one example being V-shaped pits and semipolar surfaces that contain more indium and thinner QWs. Another example is Figure 19B As shown, the MQWs are non-uniform in terms of broken QWs, discontinuous QWs, fragmented QWs, QWs with fluctuating well widths or In composition.

[0498] Figure 19C Shown Figure 19B FIG. 1 is a cross-section of a variable wavelength LED showing a porous region and a light emitting region including a plurality of V-shaped pits that can be used in a preferred embodiment of the present invention.

[0499] In this structure, the light emitting region includes multiple emission wavelength regions that are intentionally introduced, such as multiple types of QW regions having V-shaped pits extending across the light emitting region.

[0500] A V-pit is actually a hexagonal pit when viewed from above, but is V-shaped when viewed in cross section. The V-pit can be initialized at each site of a dislocation during the growth of InGaN, GaN, InGaN / InGaN superlattice, or InGaN / GaN superlattice structure under MQW under special epitaxial growth conditions, such as low growth temperature (e.g., <1000°C, <900°C, <800°C, or <700°C) and a nitrogen environment.

[0501] Figure 20A This is a graph showing the relationship between the peak emission wavelength and the driving current density for a conventional non-variable wavelength LED. By varying the driving current density applied to the LED, the emission wavelength can be slightly altered within a wavelength range of approximately 15 nm.

[0502] Figure 20B This is a graph showing the relationship between the peak emission wavelength and the driving current density of a variable wavelength LED that can be used as the first or second semiconductor device in an embodiment of the present invention. In a variable wavelength LED, changing the current density of the driving power supply will cause a greater change in the peak emission wavelength (WLP) of the LED. In this embodiment, the driving current density is between approximately 0.1 and 100 A / cm 2 When the wavelength changes between , the peak emission wavelength changes from about 635 nm to about 550 nm, and the emission wavelength range is about 85 nm.

[0503] Figure 20C Figure 2 shows the relationship between the peak emission wavelength and the driving current density of a variable-wavelength LED according to another embodiment of the present invention. In this embodiment, the driving current density is varied to cause the peak emission wavelength to change from approximately 720 nm to approximately 580 nm, resulting in an emission wavelength range of approximately 140 nm.

[0504] Figure 21A FIG. 1 is a graph showing the relationship between the peak emission wavelength and the driving current density of another variable wavelength LED according to the present invention. In this embodiment, the driving current density is about 0.1 to 200 A / cm 2 When the wavelength changes between 10 nm and 50 nm, the peak emission wavelength shifts from 615 nm to 508 nm, with an emission wavelength range of approximately 100 nm. Due to limited testing capabilities, the data in this figure only extends to 514.5 nm. Therefore, the current density at 508 nm is an estimate. However, the achievable emission wavelength range can be significantly extended in both directions.

[0505] Figures 21B-21D yes Figure 21A A photograph of a variable-wavelength LED shows the same variable-wavelength LED emitting light at four different wavelengths within its emission wavelength range. The inset emission spectra show the different peak emission wavelengths at different drive current densities. This shows the same variable-wavelength LED emitting light at peak emission wavelengths of orange (615nm), yellow (556nm), green (534nm), and blue (508nm) in response to different drive current densities.

Claims

1. A monolithic array of semiconductor devices on a wafer, comprising: a first semiconductor device occupying a first device region on the wafer, the first device region being located above a first porous region in the wafer, the first porous region having a first structure, a first porosity, and a first size; a second semiconductor device occupying a second device region on the wafer; wherein the first semiconductor device and the second semiconductor device have the same epitaxial structure; and The second semiconductor device is not located on a porous region having the same structure, porosity and size as the first porous region.

2. The semiconductor device monolithic array according to claim 1, wherein: The first semiconductor device and the second semiconductor device have the same epitaxial device structure, but respond differently in response to the same driving conditions.

3. The semiconductor device monolithic array according to claim 1 or 2, wherein: The first porous region occupies a portion of a semiconductor material layer in the wafer.

4. The semiconductor device monolithic array according to claim 1, 2 or 3, wherein: The second semiconductor device is located over a second porous region of the wafer, the second porous region having a second porosity different from the first porosity and / or having a size different from the first size.

5. The semiconductor device monolithic array according to claim 4, wherein: The second porous region occupies a portion of a layer of semiconductor material in the wafer.

6. The semiconductor device monolithic array according to claim 4 or 5, wherein: The second porous region and the first porous region are located in the same wafer layer.

7. The semiconductor device monolithic array according to any one of claims 4, 5 or 6, wherein: The second porous region has a percent porosity that is different from the percent porosity of the first porous region.

8. The semiconductor device monolithic array according to any one of claims 4 to 7, wherein: The second porous region has a second thickness that is different from a thickness of the first porous region.

9. The semiconductor device monolithic array according to any one of claims 4 to 8, wherein: The first porous region has a first shape, and the second porous region has a second shape different from the first shape.

10. The semiconductor device monolithic array according to any one of claims 4 to 9, wherein: The array includes a first semiconductor device array on the chip and a second semiconductor device array on the chip, wherein the first semiconductor device array is located above a corresponding first porous area array in the chip, and the second semiconductor device array is located above a corresponding second porous area array in the chip.

11. The semiconductor device monolithic array according to any one of claims 1 to 3, wherein: The second semiconductor device is not formed over the porous region of the wafer.

12. The semiconductor device monolithic array according to claim 11, wherein: The array includes a first array of semiconductor devices on the wafer above a corresponding first array of porous regions in the wafer and a second array of semiconductor devices on the wafer, wherein the second semiconductor devices are not located above the porous regions of the wafer.

13. A monolithic array of semiconductor devices according to any preceding claim, wherein The first semiconductor device and the second semiconductor device have different sizes, shapes and / or geometries.

14. A monolithic array of semiconductor devices according to any preceding claim, wherein The first device region is larger than the second device region.

15. A monolithic array of semiconductor devices according to any preceding claim, wherein The wafer includes a substrate and a plurality of semiconductor material layers on the substrate, preferably a plurality of Group III nitride semiconductor material layers on the substrate.

16. A monolithic array of semiconductor devices according to any preceding claim, wherein The first semiconductor device and the second semiconductor device are located on the non-porous surface layer of the wafer.

17. A monolithic array of semiconductor devices according to any preceding claim, wherein The porosity of each porous region is between 1% and 99% porosity, preferably between 20% and 90% porosity or between 30% and 80% porosity.

18. A monolithic array of semiconductor devices according to any preceding claim, wherein The thickness of each porous region is greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm, 50 nm or 100 nm.

19. A monolithic array of semiconductor devices according to any preceding claim, wherein Each of the porous regions comprises a continuous segment of a layer of porous Group III-nitride material occupying a portion of an otherwise non-porous Group III-nitride material wafer layer.

20. A monolithic array of semiconductor devices according to any preceding claim, wherein Each of the porous regions includes a single layer segment of porous GaN, or a single layer segment of porous InGaN, or a stack of one or more layers of porous GaN and / or one or more layers of porous InGaN.

21. A monolithic array of semiconductor devices according to any preceding claim, wherein The array includes electrical contacts operably coupled to the first semiconductor device and the second semiconductor device such that the first semiconductor device and the second semiconductor device can be independently driven by a power source.

22. A monolithic array of semiconductor devices according to any preceding claim, wherein: The semiconductor device structure is a photoelectric device structure.

23. A monolithic array of semiconductor devices according to any preceding claim, wherein The semiconductor device structure is an LED structure, preferably a mini LED structure, a micro LED structure or a nano LED structure.

24. The semiconductor device monolithic array according to claim 23, wherein: The first semiconductor device and the second device are both LED sub-pixels, such that the first semiconductor device and the second semiconductor device form a device pixel.

25. The monolithic array of semiconductor devices according to claim 22, 23 or 24, wherein: The first semiconductor device emits light at a first peak wavelength in response to a first drive current, and wherein the second semiconductor device emits light at a second peak wavelength different from the first peak wavelength in response to the same first drive current.

26. The monolithic array of semiconductor devices according to claim 22, 23, 24 or 25, wherein: The first semiconductor device is an LED located above the first porous region, and the second semiconductor device is an LED not located above the porous region, wherein the first semiconductor device LED emits red light in response to a driving current, and the second semiconductor device LED emits green / blue light in response to the same driving current.

27. The semiconductor device monolithic array according to any one of claims 22 to 26, wherein: The first semiconductor device and / or the second semiconductor device is a variable wavelength LED configured to emit a variable peak emission wavelength in response to a change in a driving current supplied to the LED.

28. The semiconductor device monolithic array according to any one of claims 1 to 21, wherein: The semiconductor device structure is a high electron mobility transistor (HEMT), so that the first semiconductor device and the second semiconductor device are both HEMTs.

29. The semiconductor device monolithic array according to any one of claims 1 to 21, wherein: The semiconductor device structure is a radio frequency device, so that the first semiconductor device and the second semiconductor device are both radio frequency devices.

30. A display device comprising a monolithic array of semiconductor devices on a wafer according to any one of claims 1 to 27, wherein The first semiconductor device and the second semiconductor device are each an LED sub-pixel, such that the first semiconductor device and the second semiconductor device form a device pixel, wherein the device comprises an array of a plurality of device pixels on the wafer.

31. A template wafer for a monolithic array of semiconductor devices, comprising: a surface layer of a non-porous Group III nitride material; a first porous region of Group III-nitride material below the surface layer, the first porous region having a first structure, a first porosity, and a first size; and a second region of Group III nitride material below the surface layer; wherein the first porous region and the second region occupy different lateral portions of the wafer such that the first porous region is located below a first area of ​​the surface layer and the second region is located below a second area of ​​the surface layer; wherein the second region is a non-porous region, or wherein the second region is a second porous region that does not have the same structure, porosity and size as the first porous region.

32. The template wafer according to claim 31, wherein The wafer includes a substrate and a plurality of semiconductor material layers on the substrate, preferably a plurality of Group III nitride semiconductor material layers on the substrate.

33. The template wafer according to claim 31 or 32, wherein: The first porous region occupies a portion of a semiconductor material layer in the wafer.

34. The template wafer according to claim 31, 32 or 33, wherein: The second region is a second porous region of the wafer having a second porosity different from the first porosity and / or having a size different from the first size.

35. The template wafer of claim 34, wherein: The second porous region occupies a portion of a semiconductor material layer in the wafer. Preferably, the second porous region is located in the same wafer layer as the first porous region.

36. The template wafer according to claim 34 or 35, wherein: The second porous region has a percent porosity that is different from the percent porosity of the first porous region.

37. The template wafer of claim 34, 35 or 36, wherein: The second porous region has a second thickness that is different from a thickness of the first porous region.

38. The template wafer according to any one of claims 34 to 37, wherein The first porous region has a first shape, and the second porous region has a second shape different from the first shape.

39. The template wafer according to any one of claims 31 to 38, wherein The porosity of each porous region is between 1% and 99% porosity, preferably between 20% and 90% porosity or between 30% and 80% porosity.

40. The template wafer according to any one of claims 31 to 39, wherein The thickness of each porous region is greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm, 50 nm or 100 nm.

41. The template wafer according to any one of claims 31 to 40, wherein Each of the porous regions comprises a continuous segment of a layer of porous Group III-nitride material occupying a portion of an otherwise non-porous Group III-nitride material wafer layer.

42. The template wafer according to any one of claims 31 to 41, wherein Each of the porous regions includes a single layer segment of porous GaN, or a single layer segment of porous InGaN, or a stack comprising one or more layers of porous GaN and / or one or more layers of porous InGaN.

43. A method of manufacturing a template wafer for a monolithic array of semiconductor devices, comprising the steps of: Providing a wafer, the wafer comprising: a surface layer of undoped Group III nitride material, a first region of Group III nitride material below the surface layer, and a second region of Group III nitride material below the surface layer, wherein the first region is an n-type Group III nitride material having a first carrier concentration; and The first region of the n-type Group III nitride material is electrochemically porosified to form a first porous region in the subsurface layer, wherein the first porous region has a first structure, a first porosity and a first size; wherein the second region is not porosified, or wherein the second region is porosified to form a second porous region, and the second porous region does not have the same structure, porosity and size as the first porous region.

44. The method for manufacturing a template wafer according to claim 43, wherein: The second region of Group III nitride material is an n-type Group III nitride material, and wherein the method includes the step of electrochemically porosifying the second region of n-type Group III nitride material to form the second porous region in the subsurface layer.

45. The method for manufacturing a template wafer according to claim 43 or 44, wherein: The second n-type region is a subsurface n-type region located below a surface layer of the wafer, and wherein the second n-type region is made porous by through-surface etching through the surface layer.

46. ​​The method for manufacturing a template wafer according to claim 43, 44 or 45, wherein: The carrier density of the n-type second region is the same as that of the n-type first region becoming the first porous region, but the surface area of ​​the wafer is selectively masked during the porosification process so that the n-type second region remains non-porous.

47. The method for manufacturing a template wafer according to any one of claims 43 to 46, wherein: The carrier density of the n-type second region is different from the carrier density of the n-type first region serving as the first porous region.

48. The method for manufacturing a template wafer according to claim 43, wherein: The second region of the Group III nitride material is undoped and therefore is not porosified during the electrochemical porosification of the n-doped first region.

49. The method for manufacturing a template wafer according to any one of claims 43 to 48, comprising the step of controlling the carrier concentration of the region to be made porous by ion implantation or doping.

50. A method of manufacturing a template wafer according to claim 49, comprising the step of doping regions of the wafer with nitrogen or magnesium to reduce the n-type conductivity of these regions.

51. Method for manufacturing a template wafer according to claim 49 or 50, comprising the step of doping regions of the wafer with Si, Ca or O to increase the n-type conductivity of these regions.

52. The method for manufacturing a template wafer according to any one of claims 43 to 51, wherein: The second region and the second area are located in the same wafer layer.

53. The method for manufacturing a template wafer according to any one of claims 43 to 52, wherein: The method includes the following steps: masking a surface layer of the wafer with a mask layer before porosification, patterning the mask layer to expose a first device area array, and porosifying a first porous area array through the exposed first device areas on the surface layer.

54. The method for manufacturing a template wafer according to any one of claims 43 to 53, wherein: During the porosification of the first porous region, a second device region located above the second region of the Group III nitride material is masked with a mask layer so that the second region is not porosified during the porosification of the first porous region.

55. The method for manufacturing a template wafer according to any one of claims 43 to 54, wherein: During the porousization process of the second porous region, the first device region of the surface layer located above the first region of the Group III nitride material is masked with a mask layer, so that the first region below the first device region is not porous during the porousization process of the second porous region.

56. The method for manufacturing a template wafer according to any one of claims 43 to 55, wherein: The first porous region and the second porous region are sequentially made porous by masking the surface area above a given n-type region while making other n-type regions porous.

57. The method for manufacturing a template wafer according to any one of claims 53 to 56, wherein: The surface layer is masked with a mask layer of a photoresist material, or a layer of an electrolyte material or a layer of a polymer material.

58. The method for manufacturing a template wafer according to any one of claims 53 to 57, wherein: The mask layer has a thickness of at least 10 nm, or at least 50 nm, or at least 100 nm, or at least 200 nm, or at least 1 μm, or at least 2 μm, or at least 5 μm, or at least 10 μm.

59. The method for manufacturing a template wafer according to any one of claims 43 to 58, wherein: The second porous region is made porous using etching conditions different from those used to make the first porous region porous.

60. The method for manufacturing a template wafer according to any one of claims 43 to 59, wherein: The second porous region is made porous using an etching electrolyte different from the electrolyte used in the process of making the first porous region porous.

61. The method for manufacturing a template wafer according to any one of claims 43 to 60, wherein: The electrolyte used during the porosification of the first porous region and / or the second porous region is selected from the following list: oxalic acid, KOH, NaOH, HF, nitric acid, HCl.

62. The method for manufacturing a template wafer according to any one of claims 43 to 61, wherein: At least one of the first porous region and / or the second porous region is made porous using photoelectrochemical etching under irradiation, such as ultraviolet light irradiation or white light irradiation.

63. The method for manufacturing a template wafer according to claim 62, wherein: Different irradiation is used during the porosification of the first porous zone and the second porous zone, or irradiation is used during the porosification of only one of the first porous zone or the second porous zone.

64. The method for manufacturing a template wafer according to any one of claims 43 to 63, wherein: The second porous region is made porous at a temperature different from the temperature at which the first porous region is made porous.

65. The method for manufacturing a template wafer according to claim 64, wherein: The porosification is performed at a temperature of -150°C to +150°C.

66. The method for manufacturing a template wafer according to any one of claims 43 to 66, wherein: The porosification of the second porous region is performed at a pressure different from the pressure at which the first porous region is porosified.

67. The method for manufacturing a template wafer according to any one of claims 43 to 66, wherein: The pressure range of the porosification process is from atmospheric pressure 760 Torr to low vacuum 10 -3 Torr, or medium vacuum 10 -3 to 10 -5 Entrust.

68. The method for manufacturing a template wafer according to any one of claims 43 to 67, wherein: The second porous region has a second thickness that is different from a thickness of the first porous region.

69. The method for manufacturing a template wafer according to any one of claims 43 to 68, wherein: The first region and the second region have different sizes and / or shapes and / or geometric structures. Preferably, the first device region is larger than the second device region.

70. The method for manufacturing a template wafer according to any one of claims 43 to 69, wherein: The porosity of the one or more porous regions is controlled by an electrochemical etching process, and the porosity of the porous region may be between 1% and 99% porosity, preferably between 20% and 90% porosity or between 30% and 80% porosity.

71. The method for manufacturing a template wafer according to any one of claims 43 to 70, wherein: The thickness of each porous region is greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm, 50 nm or 100 nm.

72. The method for manufacturing a template wafer according to any one of claims 43 to 71, wherein: Each of the porous regions comprises a continuous segment of a layer of porous Group III-nitride material occupying a portion of an otherwise non-porous Group III-nitride material wafer layer.

73. The method for manufacturing a template wafer according to any one of claims 43 to 72, wherein: Each of the porous regions includes a single layer segment of porous GaN, or a single layer segment of porous InGaN, or a stack comprising one or more layers of porous GaN and / or one or more layers of porous InGaN.

74. The method for manufacturing a template wafer according to any one of claims 43 to 73, wherein: The wafer includes a substrate and a plurality of semiconductor material layers on the substrate, preferably a plurality of Group III nitride semiconductor material layers on the substrate.

75. The method for manufacturing a template wafer according to any one of claims 43 to 74, wherein: The wafer includes a plurality of first regions of Group III nitride material below the surface layer and a plurality of second regions of Group III nitride material below the surface layer, and wherein the plurality of first regions are simultaneously porosified.

76. A method for manufacturing an array of semiconductor devices on a wafer, comprising the steps of: providing a first device region on the wafer above a first porous region in the wafer, the first porous region having a first structure, a first porosity, and a first size; providing a second device region on the wafer; forming a first semiconductor device by depositing a semiconductor device structure over the first device region; as well as forming a second semiconductor device by depositing the same semiconductor device structure over the second device region; The second device region is not located above a porous region having the same structure, porosity and size as the first porous region.

77. The method for manufacturing a semiconductor device array according to claim 76, wherein: The first semiconductor device and the second semiconductor device have the same device structure, but respond differently in response to the same driving conditions.

78. The method for manufacturing a semiconductor device array according to claim 76 or 77, wherein: The method comprises the steps of manufacturing the wafer according to any one of claims 43 to 75.

79. The method for manufacturing a semiconductor device array according to claim 76, 77 or 78, wherein: The second device region is formed over a second porous area of ​​the wafer, the second porous area having a second porosity different from the first porosity and / or having a size different from the first size.

80. The method for manufacturing a semiconductor device array according to any one of claims 76 to 79, wherein: The method includes the following steps: forming a first device area array on the surface of the chip, the first device area array being located above a corresponding first porous area array in the chip; and forming a second device area array on the chip, the second device area array being located above a corresponding second porous area array in the chip.

81. The method for manufacturing a semiconductor device array according to any one of claims 76 to 80, wherein: The second device region is not formed over the porous region of the wafer.

82. The method for manufacturing a semiconductor device array according to claim 81, wherein: The method includes the following steps: forming a first device area array on the wafer, wherein the first device area array is located above a corresponding first porous area array in the wafer; and forming a second device area array on the wafer, wherein the second device area is not located above the porous area of ​​the wafer.

83. The method for manufacturing a semiconductor device array according to any one of claims 76 to 82, wherein: The first device region and the second device region have different sizes and / or shapes and / or geometric structures. Preferably, the first device region is larger than the second device region.

84. The method for manufacturing a semiconductor device array according to any one of claims 76 to 83, wherein: The first device region and the second device region are formed on the non-porous surface layer of the wafer.

85. The method for manufacturing a semiconductor device array according to any one of claims 76 to 84, wherein: The first semiconductor device and the second semiconductor device are simultaneously formed by depositing the semiconductor device structure on a plurality of device regions of the wafer.

86. The method for manufacturing a semiconductor device array according to any one of claims 76 to 85, wherein: The method includes forming electrical contacts operably coupled to the first semiconductor device and the second semiconductor device such that the first semiconductor device and the second semiconductor device are independently drivable.

87. The method for manufacturing a semiconductor device array according to any one of claims 76 to 86, wherein: The semiconductor device structure is a photoelectric device structure.

88. The method for manufacturing a semiconductor device array according to any one of claims 76 to 87, wherein: The semiconductor device structure is an LED structure, preferably a mini LED structure, a micro LED structure or a nano LED structure.

89. The method for manufacturing a semiconductor device array according to claim 88, wherein: The first semiconductor device and the second device are both LED sub-pixels, such that the first semiconductor device and the second semiconductor device form a device pixel.

90. The method for manufacturing a semiconductor device array according to any one of claims 76 to 86, wherein: The semiconductor device structure is a high electron mobility transistor (HEMT), so that the first semiconductor device and the second semiconductor device are both HEMTs.

91. The method for manufacturing a semiconductor device array according to any one of claims 76 to 86, wherein: The semiconductor device structure is a radio frequency device, so that the first semiconductor device and the second semiconductor device are both radio frequency devices.

92. A method for manufacturing a display device, comprising manufacturing a semiconductor device array on a chip as described in any one of claims 76 to 89, wherein the first semiconductor device and the second semiconductor device are both LED sub-pixels, so that the first semiconductor device and the second semiconductor device form a device pixel, wherein the method comprises forming a device pixel array on the chip.

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