Method for checking residual copper rate of PCB (Printed Circuit Board)

Abstract

The invention provides a method for checking the residual copper rate of a PCB (Printed Circuit Board). The method comprises the following steps of: defining the residual copper rate delta of a certain layer on the PCB; setting a PCB residual copper rate delta checking mode; calculating the residual copper rate delta of a certain layer on the PCB through definition, checking according to a set checking mode of the residual copper rate delta of the PCB, and determining whether the residual copper rate delta of the PCB meets a target value requirement or not: if the residual copper rate delta of the PCB does not meet the target value requirement, recording a dissatisfaction item, optimizing and modifying a PCB design file, and checking again after modification until the target value requirement is met; if yes, the current inspection work is completed. According to the method for checking the residual copper rate of the PCB, multiple checking modes are set, the residual copper rate is calculated, specific checking is carried out at the last stage of PCB design, the problem that the residual copper rate is abnormal is found out, the reason of abnormality is found out, the problem is solved, and the problem that the residual copper rate is different is solved at the design stage.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB (Printed Circuit Board) manufacturing, and in particular to a method for inspecting the residual copper rate of a PCB circuit board. Background Art

[0002] The residual copper rate (the percentage of the copper area of ​​a particular layer of a circuit board relative to the total board area) is a key factor affecting PCB quality. For multi-layer boards, especially high-rise boards, if the residual copper rates vary significantly between layers, the heat dissipation rate will also vary significantly between layers. This can lead to warping during production, especially after soldering. This can seriously affect the board's usability and reliability, and can even cause the board to be scrapped.

[0003] For boards with large differences in residual copper rates on each layer, board manufacturers will recommend adding balancing copper blocks during production to alleviate the differences in residual copper rates during pre-production reviews. However, this approach is only an optimization method and cannot fundamentally solve the problem.

[0004] The difference in residual copper rate occurs during the design phase. There is an urgent need for a method to check the residual copper rate so that the problem can be found and solved fundamentally during the design phase without causing trouble to the back-end production. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the main object of the present invention is to provide a method for inspecting the residual copper rate of a PCB circuit board to solve one or more problems in the prior art.

[0006] The technical solutions of the present invention are as follows:

[0007] A method for inspecting the residual copper rate of a PCB circuit board comprises the following steps:

[0008] The residual copper rate δ of a certain layer on the PCB is defined as the ratio of the copper area S of a certain layer on the PCB to the total area S0 of the PCB.

[0009] Set the PCB circuit board residual copper rate δ inspection mode, the inspection mode includes:

[0010] (1) Single-layer partition inspection mode: The difference in residual copper rate δ in each area of ​​a single layer of the PCB circuit board is less than or equal to the target value;

[0011] (2) Symmetrical layer inspection mode: The difference in residual copper rate δ of the symmetrical layer of the PCB circuit board is less than or equal to the target value;

[0012] (3) Multi-layer inspection mode: The absolute value of the sum of the residual copper rates δ of the symmetrical layers of the PCB circuit board is less than or equal to the target value;

[0013] By defining and calculating the residual copper rate δ of a certain layer on the PCB circuit board and performing single-layer partition inspection, symmetrical layer inspection, and multi-layer inspection according to the set inspection mode, it is determined whether the residual copper rate δ of the PCB circuit board meets the target value requirement. If not, the unsatisfied items are recorded, and the PCB circuit board design file is optimized and modified. After modification, the inspection is repeated until the target value requirement is met. If it is satisfied, the current inspection work is completed.

[0014] In some embodiments, the copper area S of a certain layer on the PCB circuit board includes: copper area St, pad area Sp, signal line area Sx, and hole ring area Sk; the copper area S of a certain layer on the PCB circuit board = ΣSt+ΣSp+ΣSx+ΣSk.

[0015] Convert the electrical properties on the circuit board into area calculations of geometric figures, and process holes, wires, and copper separately. During later inspection and optimization, only the copper area is increased, and the area data of holes and wires can be directly retrieved, reducing the amount of calculated data.

[0016] In some embodiments, the single-layer partition checking mode includes:

[0017] Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i;

[0018] Divide a certain layer Li of the PCB into k areas;

[0019] Check whether any layer of the PCB circuit board meets |δ im -δ in |≤σ, where m, n are 1, 2, 3…, k; δ im Indicates the residual copper rate value of the mth partition of the PCB circuit board layer Li; δ in It represents the residual copper rate value of the nth partition of the PCB circuit board layer Li, and σ is the target value.

[0020] Currently, residual copper rate calculations only calculate the residual copper rate of the entire layer, without dividing the same layer into individual blocks. However, inconsistent copper areas in different areas of the same layer can also cause board problems. This invention overcomes this shortcoming by implementing a single-layer partition inspection mode.

[0021] In some embodiments, the symmetric layer inspection mode includes:

[0022] Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i;

[0023] Taking the center line of the circuit board as the axis of symmetry, L1 and L i For symmetric layers, L2 and L i-1 For symmetric layers, L3 and L i-2 It is a symmetrical layer, ...;

[0024] Check whether the difference of residual copper rate δ of the symmetrical layer of the PCB circuit board meets the following requirements:

[0025] |δ1-δ i |≤σ;|δ2-δ i-1 |≤σ;|δ3-δ i-2 |≤σ;……;

[0026] Among them, δ i is the residual copper rate of a certain layer of the PCB circuit board, and σ is the target value.

[0027] Symmetrical layer inspections are currently performed at the board manufacturing plant. If the requirements are not met, small isolated copper blocks need to be added. These isolated copper blocks, which have no electrical properties, can cause electromagnetic compatibility (EMC) issues. However, performing symmetrical layer inspections of residual copper at the design end can add copper sheets with electrical properties without causing any additional EMC issues.

[0028] In some embodiments, the multi-layer inspection mode includes:

[0029] Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i;

[0030] Taking the center line of the circuit board as the axis of symmetry, L1 and L i For symmetric layers, L2 and L i-1 For symmetric layers, L3 and L i-2 It is a symmetrical layer, ...;

[0031] Check whether the absolute value of the sum of the residual copper rate δ of the symmetrical layers of the PCB circuit board meets the following requirements:

[0032] |(δ1+δ2)-(δ i-1 +δ i )|≤σ;

[0033] |(δ2+δ3)-(δ i-2 +δ i-1 )|≤σ;

[0034] |(δ1+δ3)-(δ i-2 +δ i )|≤σ;

[0035] |(δ1+δ2+δ3)-(δ i-2 +δ i-1 +δ i )|≤σ;

[0036] ...;

[0037] Among them, δ i is the residual copper rate of a certain layer of the PCB circuit board, and σ is the target value.

[0038] In some embodiments, the copper area St is calculated by the following steps:

[0039] Get the coordinates of each point of the polygon copper foil, which are (x1, y1), (x2, y2), ..., (x n ,y n );

[0040] According to the Gaussian area formula, calculate the total area S of the copper envelope:

[0041]

[0042] Calculate the through hole area Sk enclosed within the copper sheet;

[0043] Calculate the copper area St = S-Sk;

[0044] The copper area St on the PCB circuit board is accumulated to obtain the total copper area ΣSt.

[0045] In some embodiments, the through-hole area Sk includes:

[0046] (1) The through hole and the copper foil completely overlap, and the through hole area is Sk1;

[0047] (2) There is an independent isolation ring between the through hole and the copper foil. The area of ​​the through hole is Sk2-1, and the area of ​​the isolation ring is Sh;

[0048] (3) There are cross isolation rings between multiple through holes and copper foil, the through hole area is Sk2-2, and the isolation ring area is Sh;

[0049] Sk=ΣSk1+Σ(Sk2-1)+Σ(Sk2-2)+ΣSh.

[0050] In some embodiments, the pad area Sp is calculated by the following steps:

[0051] Get the pad size on the PCB circuit board;

[0052] According to the geometric shape of the pad, calculate the area Sp of the pad;

[0053] The pad areas Sp of different shapes on the PCB are accumulated to obtain the total pad area ΣSp.

[0054] In some embodiments, the signal line area Sx is calculated by the following steps:

[0055] Get the length and width of the signal line on the PCB circuit board;

[0056] Calculate the area Sx of the signal line;

[0057] The areas Sx of multiple signal lines on the PCB are accumulated to obtain the total area ΣSx of the signal lines.

[0058] In some embodiments, the annular ring area Sk is calculated by the following steps:

[0059] Get the size of the hole ring on the PCB circuit board;

[0060] Calculate the area of ​​the annular ring Sk;

[0061] The areas Sk of multiple annular rings on the PCB are accumulated to obtain the total area of ​​the annular rings ΣSk.

[0062] The present invention has the following advantages over the prior art: the present invention provides a method for inspecting the residual copper rate of a PCB circuit board. The method sets multiple inspection modes and calculates the residual copper rate, performs specific inspections at the end of the PCB design phase, discovers abnormal residual copper rates, finds the causes of the abnormalities, and solves the problems. Thus, the problem of residual copper rate differences is solved in the design phase, and the residual copper rate of the PCB circuit board is controlled at the beginning of the design phase, thereby saving costs and improving efficiency.

[0063] It should be understood that the contents described in the Summary of the Invention section are not intended to limit the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. In addition, the implementation of any embodiment of the present invention does not mean that multiple or all of the above-mentioned beneficial effects must be simultaneously possessed or achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are merely exemplary, and those skilled in the art can, without inventive effort, derive other implementation drawings based on the provided drawings.

[0065] The structures, proportions, sizes, etc. illustrated in this specification are intended solely to complement the contents disclosed herein and to facilitate understanding and reading by persons skilled in the art. They are not intended to limit the conditions under which the present invention may be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportions, or adjustments in sizes, provided they do not affect the efficacy and objectives of the present invention, shall remain within the scope of the technical contents disclosed herein.

[0066] Figure 1 The present invention shows an overall flow chart of a method for inspecting the residual copper rate of a PCB circuit board;

[0067] Figure 2Shows a schematic diagram of the PCB circuit board structure of some embodiments of the present invention;

[0068] Figure 3 A schematic diagram of the copper structure of a PCB circuit board according to some embodiments of the present invention is shown;

[0069] Figure 4 Shown Figure 3 A partial enlarged view of

[0070] Figure 5 Shows a schematic cross-sectional view of a 6-layer board structure according to some embodiments of the present invention;

[0071] Figure 6 Shows the residual copper rate inspection program flow and interface display schematic diagram of some embodiments of the present invention;

[0072] Figure 7 It shows the process flow and interface display diagram of the residual copper rate single-layer partition inspection program in some embodiments of the present invention;

[0073] Figure 8 It shows the residual copper rate symmetrical layer / multi-layer inspection process and interface display schematic diagram of some embodiments of the present invention;

[0074] Figure 9 Schematic diagrams showing the display of residual copper rate inspection program results in some embodiments of the present invention are shown, wherein (a) is a display interface showing if the inspection passes, and (b) is a display interface showing if the inspection fails.

[0075] In the picture:

[0076] 1. Signal line; 2. Angle ring; 3. Solder pad; 4. Copper sheet;

[0077] 101, through hole with area SK1; 201, through hole with area Sk2-1; 202, through hole with area Sk2-2;

[0078] 301, copper layer; 302, dielectric layer.

[0079] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the embodiments and drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0081] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0082] It should be understood that the terms "comprises / comprising," "consisting of," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a product, apparatus, process, or method that includes a list of elements includes not only those elements but also, if necessary, other elements not explicitly listed, or elements inherent to such product, apparatus, process, or method. In the absence of further limitations, elements defined by the phrases "comprises / comprising," "consisting of," do not preclude the presence of additional identical elements in the product, apparatus, process, or method that includes the elements.

[0083] It should also be understood that terms such as "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device, component or structure referred to must have a specific direction, be constructed or operate in a specific direction, and should not be understood as limiting the present invention.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0085] The implementation of the present invention is described in detail below in conjunction with preferred embodiments.

[0086] The present invention proposes a method for inspecting the residual copper rate of a PCB circuit board. Figure 1 As shown, Figure 1The overall process of the inspection method includes: S101: defining the residual copper rate δ of a certain layer on the PCB circuit board, where the residual copper rate δ is the ratio of the copper area S of a certain layer on the PCB circuit board to the total area S0 of the circuit board. S102: setting the inspection mode for the residual copper rate δ of the PCB circuit board. S103: determining whether the residual copper rate δ of the PCB circuit board meets the target value requirement by defining and calculating the residual copper rate δ of a certain layer on the PCB circuit board and inspecting according to the set inspection mode for the residual copper rate δ of the PCB circuit board: if not, optimizing and modifying the PCB circuit board design file until the target value requirement is met; if met, completing the current inspection work. The inspection method for the residual copper rate of the PCB circuit board provided by the present invention sets a plurality of inspection modes and performs residual copper rate calculations, performs specific inspections at the end of the PCB design stage, discovers the problem of abnormal residual copper rate, finds the cause of the abnormality, solves the problem, and solves the problem of residual copper rate difference in the design stage.

[0087] It should be noted that there are three inspection modes for the residual copper rate δ of PCB circuit boards:

[0088] (1) Single-layer partition inspection mode: The difference in residual copper rate δ in each area of ​​a single layer of the PCB circuit board is less than or equal to the target value;

[0089] (2) Symmetrical layer inspection mode: The difference in residual copper rate δ of the symmetrical layer of the PCB circuit board is less than or equal to the target value;

[0090] (3) Multi-layer inspection mode: The absolute value of the sum of the difference between the residual copper rates δ of the symmetrical layers of the PCB circuit board is less than or equal to the target value.

[0091] The following describes in detail the specific process of the inspection method provided by the present invention using a specific embodiment:

[0092] First, it's important to note that the areas with conductors on a PCB are copper metal, while areas without conductors are the board material. The copper metal on the PCB is referred to as residual copper. A PCB with many signals and power supplies requires more layers to carry the signal paths, making it more likely that the residual copper rate will be inconsistent.

[0093] In step S101, the residual copper rate δ on the PCB is first defined. The residual copper rate δ is the ratio of the copper area S of a certain layer on the PCB to the total area S0 of the PCB. It is easy to understand that the total area S0 of the board is a fixed value. That is, when the board structure is determined, the total area S0 of the board can be calculated using geometric relationships. The copper area S on the board includes: the copper area St, the pad area Sp, the signal line area Sx, and the annular ring area Sk. These areas are all made of metallic copper and exist in the form of copper foil during the production stage. They are factors that affect the residual copper rate. It is easy to understand that the copper area S of a certain layer on the PCB = ΣSt + ΣSp + ΣSx + ΣSk. In other words, the copper area of ​​a certain layer on the PCB is the sum of the areas of each component. To obtain the copper area of ​​a certain layer on the PCB, it is only necessary to calculate the area of ​​each component.

[0094] In some embodiments, a layer of a PCB circuit board such as Figure 2 As shown, a certain layer of the circuit board includes: copper sheet 4, pad 3, signal line 1, and hole ring 2. The calculation process of each part area is introduced respectively.

[0095] (1) If Figure 3 、 Figure 4 As shown, the calculation steps of the total area St of the copper sheet 4 are as follows:

[0096] Get the coordinates of each point of the polygon copper sheet 4, which are (x1, y1), (x2, y2), ..., (xn, yn);

[0097] According to the Gauss area formula, calculate the total area S of the copper foil 4 envelope:

[0098]

[0099] Calculate the area of ​​the through hole enveloping the copper sheet 4, where the through hole includes:

[0100] (1) The through hole and the copper foil completely overlap, such as Figure 4 The darker circle 101 in the figure has a through-hole area of ​​Sk1;

[0101] (2) There is an independent isolation ring between the through hole and the copper sheet, such as Figure 4 The lighter colored circle 201 and the white ring with isolation band in the copper foil have the through hole area of ​​Sk2-1 and the isolation ring area of ​​Sh;

[0102] (3) There are cross isolation rings between multiple through holes and copper sheets, such as Figure 4 The lighter circle 202 and the copper foil have a white ring with an isolation zone, and the two white rings intersect. The through hole area is Sk2-2, and the isolation ring area is Sh.

[0103] Calculate the area of ​​copper sheet 4: St = S - ΣSk1 - Σ(Sk2-1) - Σ(Sk2-2) - ΣSh;

[0104] The area St of the copper sheet 4 on the PCB circuit board is accumulated to obtain the total area ΣSt of the copper sheet 4.

[0105] (2) The steps for calculating the area Sp of the pad 3 are as follows:

[0106] Get the size of pad 3 on the PCB;

[0107] According to the geometric shape of the pad 3, calculate the area Sp of the pad 3;

[0108] The areas Sp of pads 3 of different shapes on the PCB circuit board are accumulated to obtain the total area ΣSp of the pads 3.

[0109] (3) The steps for calculating the area Sx of signal line 1 are as follows:

[0110] Get the length and width of signal line 1 on the PCB circuit board;

[0111] Calculate the area Sx of signal line 1;

[0112] The areas Sx of multiple signal lines 1 on the PCB are accumulated to obtain the total area ΣSx of the signal line 1.

[0113] (IV) The calculation steps of the hole ring 2 area Sk are as follows:

[0114] Get the size of the hole ring 2 on the PCB circuit board;

[0115] Calculate the area Sk of annular ring 2;

[0116] The areas Sk of multiple annular rings 2 on the PCB are accumulated to obtain the total area ΣSk of the annular rings 2.

[0117] From this we can obtain: the copper area of ​​a certain layer on the PCB circuit board S = ΣSt + ΣSp + ΣSx + ΣSk.

[0118] In step S102, a single-layer partition check is first performed. To ensure consistency, the difference in residual copper rate between each area of ​​the single layer cannot be too large. It is required that the difference in residual copper rate δ between each area of ​​the single layer of the PCB circuit board is less than or equal to the target value.

[0119] Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i;

[0120] Divide a certain layer Li of the PCB into k areas;

[0121] Check whether any layer of the PCB circuit board meets |δ im -δ in|≤σ, where m, n are 1, 2, 3…, k; δ im Indicates the residual copper rate value of the mth partition of the PCB circuit board layer Li; δ in Indicates the residual copper rate value of the nth partition of the Li layer of the PCB circuit board.

[0122] In some embodiments, the L1 layer of the PCB is divided into n equal regions, L11, L12, L13, ..., L1n. It should be noted that a larger value of n results in smaller regions, allowing for more precise inspection of residual copper rate differences. However, this also makes it difficult to optimize the PCB design. Therefore, a value of n should not be too large. This is for illustrative purposes only, and the present invention does not further explore the appropriate value of n.

[0123] Check whether the L1 layer of the PCB circuit board meets |δ 1m -δ 1n |≤σ, that is, whether the absolute value of the difference in the residual copper rate between any two partitions is less than a predetermined value σ. If so, the inspection passes; otherwise, the inspection fails. Generally, the smaller the σ value, the better. According to industry standards, the σ value is 15%.

[0124] Then, the symmetrical layer inspection is performed, requiring that the difference in the residual copper rate δ of the symmetrical layer of the PCB circuit board is less than or equal to the target value.

[0125] Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i;

[0126] Taking the center line of the circuit board as the axis of symmetry, L1 and L i For symmetric layers, L2 and L i-1 For symmetric layers, L3 and L i-2 It is a symmetrical layer, ...;

[0127] Check whether the difference of residual copper rate δ of the symmetrical layer of the PCB circuit board meets the following requirements:

[0128] |δ1-δ i |≤σ;|δ2-δ i-1 |≤σ;|δ3-δ i-2 |≤σ;……;

[0129] Among them, δ i is the residual copper rate of a certain layer of the PCB circuit board, and σ is the target value.

[0130] In some embodiments, see Figure 5 The PCB circuit board is a 6-layer board, where the yellow part is the copper layer 301 of each layer, which is the wiring layer of the PCB design, corresponding to L1-L6, and the gray part is the dielectric layer 302, which is used to isolate each copper layer.

[0131] For the convenience of explanation, the residual copper rates of layers 1-6 are set as δ1, δ2, δ3, δ4, δ5, and δ6, where δ1 and δ6 are symmetrical layers, δ2 and δ5 are symmetrical layers, and δ3 and δ4 are symmetrical layers. In the design, the absolute value of the difference in the residual copper rate of the symmetrical layer must not exceed the target value:

[0132] |δ1-δ6|≤σ; |δ2-δ5|≤σ; |δ3-δ4|≤σ.

[0133] According to industry requirements, the difference in residual copper rate of the symmetrical layer of the circuit board should not exceed 15%, that is, the difference target value σ = 15%.

[0134] Finally, a multi-layer inspection is performed, requiring that the absolute value of the sum of the residual copper rates δ of the symmetrical layers of the PCB circuit board is less than or equal to the target value.

[0135] Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i;

[0136] Taking the center line of the circuit board as the axis of symmetry, L1 and L i For symmetric layers, L2 and L i-1 For symmetric layers, L3 and L i-2 It is a symmetrical layer, ...;

[0137] Check whether the absolute value of the sum of the residual copper rate δ of the symmetrical layers of the PCB circuit board meets the following requirements:

[0138] |(δ1+δ2)-(δ i-1 +δ i )|≤σ;|(δ2+δ3)-(δ i-2 +δ i-1 )|≤σ;|(δ1+δ3)-(δ i-2 +δ i )|≤σ;|(δ1+δ2+δ3)-(δ i-2 +δ i-1 +δ i )|≤σ;……;

[0139] Among them, δ i is the residual copper rate of a certain layer of the PCB circuit board, and σ is the target value.

[0140] Taking a 6-layer PBC circuit board as an example, the residual copper rates of layers 1-6 are set to δ1, δ2, δ3, δ4, δ5, and δ6, where δ1 and δ6 are symmetrical layers, δ2 and δ5 are symmetrical layers, and δ3 and δ4 are symmetrical layers. The design must ensure that the absolute value of the difference between the sum of the residual copper rates of the symmetrical layers is no greater than the target value:

[0141] |(δ1+δ2)-(δ5+δ6)|≤σ;

[0142] |(δ2+δ3)-(δ4+δ5)|≤σ;

[0143] |(δ1+δ3)-(δ4+δ6)|≤σ;

[0144] |(δ1+δ2+δ3)-(δ4+δ5+δ6)|≤σ.

[0145] Generally speaking, the smaller the σ value is, the better. According to industry standards, the σ value is 15%.

[0146] In step S103, the residual copper rate δ of a certain layer on the PCB is defined and calculated, and an inspection is performed according to the set inspection mode of the residual copper rate δ of the PCB to determine whether the residual copper rate δ of the PCB meets the target value requirement. If not, the PCB design file is optimized and modified until the target value requirement is met. If so, the current inspection work is completed.

[0147] First, calculate the residual copper area of ​​each part of the PCB circuit board, then add them up to get the copper area S of a certain layer on the PCB circuit board and the total area S0 of the board. Use the residual copper rate calculation formula δ = S / S0 * 100% to get the residual copper rate δ, and then check the residual copper rate δ of the PCB circuit board.

[0148] It should be noted that after the first inspection, the inspection results are output and stored. After modification and optimization, the first inspection results can be called up for a selective second inspection, either re-inspecting all items or only checking the items that did not meet the requirements of the first inspection. This operation can greatly improve inspection efficiency.

[0149] In view of the complexity of the above multiple inspection mode operation, a set of PCB circuit board residual copper rate inspection procedures are designed based on this inspection method. Figure 6 It is the residual copper rate inspection step and its program interface.

[0150] Corresponding to the residual copper rate inspection method, the residual copper rate inspection program is designed into three modes: single-layer partition inspection mode, symmetrical layer inspection mode and multi-layer inspection mode.

[0151] Click the button on the right side of the corresponding mode in the program interface to start the inspection in that mode:

[0152] (1) Single-layer partition inspection mode such as Figure 7 As shown, first set the parameters, including the number of partitions and the target value σ, then run the inspection program to obtain the residual copper rate inspection results. Click the layer buttons at the bottom of the interface to display the residual copper rate inspection results of each layer. Figure 9 As shown, the inspection program will automatically pop up a window to display the inspection results: See Figure 9 (a) If the residual copper rate meets the set target value, the pop-up window will display PASS; see Figure 9 (b) If the detected residual copper rate does not meet the target value, a pop-up window will display the unsatisfied items.

[0153] (2) Symmetric layer inspection mode such as Figure 8 As shown, first set the parameters, including the number of layers and the target value σ, and then run the inspection program to obtain the residual copper rate inspection results, as shown in Figure 9 As shown, the inspection program will automatically pop up a window to display the inspection results: See Figure 9 (a) If the residual copper rate meets the set target value, the pop-up window will display PASS; see Figure 9 (b) If the detected residual copper rate does not meet the target value, a pop-up window will display the unsatisfied items.

[0154] (3) Multi-layer inspection mode such as Figure 8 As shown in the figure (using the same interface as the symmetrical layer inspection mode), first set the parameters, including the number of layers and the target value σ, and then run the inspection program to obtain the residual copper rate inspection results, as shown in the figure. Figure 9 As shown, the inspection program will automatically pop up a window to display the inspection results: See Figure 9 (a) If the residual copper rate meets the set target value, the pop-up window will display PASS; see Figure 9 (b) If the detected residual copper rate does not meet the target value, a pop-up window will display the unsatisfied items.

[0155] It should be noted that during the process of PCB circuit board design optimization and modification, when the residual copper rate δ differs too much, the copper content of each part can be adjusted in the following way: if the residual copper rate is low, increase copper plating in positions where there is no copper; if the residual copper rate is high, reduce copper plating in the corresponding positions.

[0156] By using the inspection method provided by the present invention, the residual copper rate is inspected at the end of the PCB circuit board design phase, abnormal residual copper rate problems are discovered, the causes of the abnormality are found, and the PCB design files are modified in a timely manner, so that the problem of residual copper rate differences is solved in the design phase.

[0157] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. The present invention is not limited here.

[0158] Although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present invention. Certain features described in the context of a separate embodiment may also be implemented in a single implementation in combination. Conversely, the various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable combination. Without departing from the scope and spirit of the illustrated embodiments, many modifications and variations will be apparent to those skilled in the art.

Claims

1. A method for inspecting the residual copper rate of a PCB circuit board, characterized in that: The steps include: The residual copper rate δ of a certain layer on the PCB is defined as the ratio of the copper area S of a certain layer on the PCB to the total area S0 of the PCB. Set the PCB circuit board residual copper rate δ inspection mode, the inspection mode includes: (1) Single-layer partition inspection mode: The difference in residual copper rate δ in each area of ​​a single layer of the PCB circuit board is less than or equal to the target value; (2) Symmetrical layer inspection mode: The difference in residual copper rate δ of the symmetrical layer of the PCB circuit board is less than or equal to the target value; (3) Multi-layer inspection mode: The absolute value of the sum of the residual copper rates δ of the symmetrical layers of the PCB circuit board is less than or equal to the target value; By defining and calculating the residual copper rate δ of a certain layer on the PCB circuit board and performing single-layer partition inspection, symmetrical layer inspection, and multi-layer inspection according to the set inspection mode, it is determined whether the residual copper rate δ of the PCB circuit board meets the target value requirement. If not, the unsatisfied items are recorded, and the PCB circuit board design file is optimized and modified. After modification, the inspection is repeated until the target value requirement is met. If it is satisfied, the current inspection work is completed.

2. The inspection method according to claim 1, characterized in that: The copper area S of a certain layer on the PCB circuit board includes: copper skin area St, pad area Sp, signal line area Sx, and hole ring area Sk; the copper area S of a certain layer on the PCB circuit board = ΣSt+ΣSp+ΣSx+ΣSk.

3. The inspection method according to claim 1, characterized in that: The single-layer partition inspection mode includes: Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i; Divide a certain layer Li of the PCB into k areas; Check whether any layer of the PCB circuit board meets |δ im -δ in |≤σ, where m, n are 1, 2, 3…, k; δ im Indicates the residual copper rate value of the mth partition of the PCB circuit board layer Li; δ in It represents the residual copper rate value of the nth partition of the PCB circuit board layer Li, and σ is the target value.

4. The inspection method according to claim 1, characterized in that: The symmetry layer inspection mode includes: Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i; Taking the center line of the circuit board as the axis of symmetry, L1 and L i For symmetric layers, L2 and L i-1 For symmetric layers, L3 and L i-2 It is a symmetrical layer, ...; Check whether the difference of residual copper rate δ of the symmetrical layer of the PCB circuit board meets the following requirements: |δ1-δ i |≤σ;|δ2-δ i-1 |≤σ;|δ3-δ i-2 |≤σ;……; Among them, δ i is the residual copper rate of a certain layer of the PCB circuit board, and σ is the target value.

5. The inspection method according to claim 1, characterized in that: The multi-layer inspection mode includes: Assume that the PCB circuit board includes S layers, and S takes the value 1, 2, ..., i; Taking the center line of the circuit board as the axis of symmetry, L1 and L i For symmetric layers, L2 and L i-1 For symmetric layers, L3 and L i-2 It is a symmetrical layer, ...; Check whether the absolute value of the sum of the residual copper rate δ of the symmetrical layers of the PCB circuit board meets the following requirements: |(δ1+δ2)-(δ i-1 +d i )|≤σ; |(δ2+δ3)-(δ i-2 +d i-1 )|≤σ; |(δ1+δ3)-(δ i-2 +d i )|≤σ; |(δ1+δ2+δ3)-(δ i-2 +d i-1 +d i )|≤σ; ……； Among them, δ i is the residual copper rate of a certain layer of the PCB circuit board, and σ is the target value.

6. The inspection method according to claim 2, characterized in that: Calculate the copper area St by the following steps: Get the coordinates of each point of the polygon copper foil, which are (x1, y1), (x2, y2), ..., (x n ,y n ); According to the Gaussian area formula, calculate the total area S of the copper envelope: Calculate the through hole area Sk enclosed within the copper sheet; Calculate the copper area St = S-Sk; The copper area St on the PCB circuit board is accumulated to obtain the total copper area ΣSt.

7. The inspection method according to claim 6, characterized in that: The through hole area Sk includes: (1) The through hole and the copper foil completely overlap, and the through hole area is Sk1; (2) There is an independent isolation ring between the through hole and the copper foil. The area of ​​the through hole is Sk2-1, and the area of ​​the isolation ring is Sh; (3) There are cross isolation rings between multiple through holes and copper foil, the through hole area is Sk2-2, and the isolation ring area is Sh; Sk=ΣSk1+Σ(Sk2-1)+Σ(Sk2-2)+ΣSh.

8. The inspection method according to claim 2, characterized in that: Calculate the pad area Sp by following the steps below: Get the pad size on the PCB circuit board; According to the geometric shape of the pad, calculate the area Sp of the pad; The pad areas Sp of different shapes on the PCB are accumulated to obtain the total pad area ΣSp.

9. The inspection method according to claim 2, characterized in that: Calculate the signal line area Sx by the following steps: Get the length and width of the signal line on the PCB circuit board; Calculate the area Sx of the signal line; The areas Sx of multiple signal lines on the PCB are accumulated to obtain the total area ΣSx of the signal lines.

10. The inspection method according to claim 2, characterized in that: Calculate the annular ring area Sk by the following steps: Get the size of the hole ring on the PCB circuit board; Calculate the area of ​​the annular ring Sk; The areas Sk of multiple annular rings on the PCB are accumulated to obtain the total area of ​​the annular rings ΣSk.

Images