Dynamically reorganizable coil structure and application thereof

Abstract

The invention provides a coil structure capable of being dynamically recombined and application thereof. N basic coils are arranged; each coil comprises N excitation structures which are uniformly arranged to form an induction unit with a space period of N, and N is a positive integer; each coil comprises N-1 high levels and one low level; all the coils are arranged in a spatially staggered manner, so that the signal of each coil is delayed by one minimum time unit relative to the previous coil on the time axis. A dynamic recombination structure formed by the N basic coil units supports any combination mode, realizes combination of multi-coil output signals with any phase deviation, supports flexible switching of signal modes of different periods, and greatly improves function expandability and signal control precision of a system.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a dynamically reconfigurable coil structure and application thereof. Background Art

[0002] In the structural design of inductive sensors, the coil layout and signal output method directly influence the system's sensitivity, anti-interference capabilities, and multifunctional adaptability. Traditional coil structures lack reconfigurability in terms of spatial arrangement and output signal form, making it difficult to adapt to complex scenarios or expand functionality. Therefore, developing a coil architecture with dynamic combination capabilities and its associated signal processing solutions has become a key technical direction. Summary of the Invention

[0003] The purpose of the present invention is to provide a dynamically reconfigurable coil structure and its application, which can realize the combination of multi-coil output signals with arbitrary phase offsets, support flexible switching of signal modes with different periods, and greatly improve the functional scalability and signal control accuracy of the system.

[0004] In a first aspect, the present invention provides a dynamically reconfigurable coil structure comprising N basic coils; each coil comprises N evenly arranged excitation structures, forming an induction unit with a spatial period of N, where N is a positive integer; Each coil contains N-1 high levels and 1 low level; All coils are arranged in a spatially staggered manner so that the signal of each coil is delayed by one minimum time unit relative to the previous coil on the time axis.

[0005] The present invention provides the following beneficial effects: by providing N basic coils, each comprising N evenly spaced excitation structures, forming an induction unit with a spatial period of N, where N is a positive integer; each coil contains N-1 high-level signals and one low-level signal; and all coils are spatially staggered, such that the signal of each coil is delayed by one minimum time unit relative to the previous coil on the time axis. The dynamic recombinant architecture constructed from these N basic coil units supports arbitrary combinations, enabling the combination of multi-coil output signals with arbitrary phase offsets and flexible switching of signal modes with different periods, significantly improving the system's functional scalability and signal control accuracy.

[0006] Optionally, each coil output signal is output through an amplifier or MUX-INV module with controllable polarity, and the signal output direction is forward or reverse.

[0007] Optionally, the excitation structure is a coil protrusion, an inductor slot or an excitation point.

[0008] In a second aspect, the present invention provides a coil array signal output method, based on any possible combination of the structures of the first aspect, including: Each coil outputs a cycle waveform It is a specific envelope with a period of N, and the periodic waveform satisfies: in, , represents the phase delay of the kth coil, and t is the minimum time unit.

[0009] Optionally, all coil signals are equally spaced in phase to form a discrete phase basis .

[0010] Optionally, set the polarity ±1 for any coil combination and calculate the total output signal through digital circuit combination: in, ,The combinational logic is implemented through digital circuits, including polarity switching, differential weighting and ,combinatorial adders.

[0011] Optionally, the output combined waveform period is a divisor of the fundamental period N∙t, satisfying: in, ; So the output frequency is , where d is a factor of N; When N=6, waveforms with periods of 2t, 3t, or 6t can be combined; When N is a prime number, a waveform with a period of N·t can be combined.

[0012] In a third aspect, the present invention provides a digital signal processing device for use in the method described in the second aspect, comprising: A multi-channel synchronous sampling input unit, which consists of a set of high-speed sampling D-flip-flop arrays and is used to synchronously acquire the periodic waveform of each coil channel so that the combined calculation is completed in the same clock domain; An output shaping module includes a digital filter, a comparator, or waveform edge detection logic, which is used to convert the combined signal into a single-cycle TTL output, eliminate spikes, smooth the combined boundary, extract the frequency envelope, or modulate the edge signal.

[0013] Optionally, a polarity control matrix is ​​also included; The polarity control matrix is ​​used to allow each channel signal to enter a group of selectors and programmable inverters; the control signal comes from a control register, which configures the signal to be forward or reverse.

[0014] Optionally, a differential weighted combination unit is also included; The combination unit is used to send the polarity-adjusted N-channel signal inputs into the weighted combiner to perform symbol weighting, add, subtract or shield a certain channel of signal; and / or the combination unit is a structured addition tree or LUT+DSP multiplication-addition structure.

[0015] Optionally, it also includes a combination strategy management module; The management module is used to store and schedule preset combination templates, and command-triggered dynamic switching of combination templates to implement multi-mode detection / encoding functions or template selection based on a state machine or external commands.

[0016] For the beneficial effects of the second to third aspects, please refer to the description of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a coil structure that can be dynamically reconfigured when N=5 provided in an embodiment of the present invention; Figure 2 A schematic diagram of a coil structure that can be dynamically reconfigured when N=4 provided in an embodiment of the present invention; Figure 3 A schematic diagram of a coil structure that can be dynamically reconfigured when N=6 provided in an embodiment of the present invention; Figure 4 This is a coil output waveform diagram after digital signal processing and binarization when N=6 provided in an embodiment of the present invention; Figure 5 and Figure 6 When N=6, the embodiment of the present invention provides a digital signal processing binary combination digital circuit output; Figure 7 This is a coil output waveform diagram after digital signal processing and binarization when N=4 provided in an embodiment of the present invention; Figure 8 and Figure 9 When N=4, the embodiment of the present invention provides a digital signal processing binary combination digital circuit output; Figure 10 A single basic coil output waveform with a sine wave or triangular wave envelope provided in an embodiment of the present invention; Figure 11 A schematic structural diagram of a coil array signal output device provided by an embodiment of the present invention; Figure 12 A schematic diagram of the principle of a coil array signal output device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0019] The technical solutions in the embodiments of the present invention are described below in conjunction with the drawings in the embodiments of the present invention. Among them, in the description of the embodiments of the present invention, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular expressions "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present invention, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0020] References to "one embodiment" or "some embodiments" described in this specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in one or more embodiments of the present invention. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", and "in some other embodiments" appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. The term "connected" includes direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0021] In the embodiments of the present invention, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0022] like Figure 1 、 Figure 2 or Figure 3 As shown, the present invention provides a dynamically reconfigurable coil structure, including N basic coils; each coil includes N evenly arranged excitation structures, forming an induction unit with a spatial period of N, where N is a positive integer; each coil contains N-1 high levels and 1 low level (for example, the periodic response signal of each coil is defined as [1,1,...,1,0], that is, there are N-1 high levels and 1 low level in N sampling points); all coils are arranged in a spatially staggered manner, so that the signal of each coil is delayed by 1 minimum time unit (tick) relative to the previous coil on the time axis.

[0023] In the timing domain, this constitutes a complete "phase array" system, covering discrete phases from 0 to N-1, as shown in the example Figure 4 shown.

[0024] In some embodiments, each coil output signal is output through an amplifier or MUX-INV module with controllable polarity, and the signal output direction is forward or reverse, thereby providing a ±1 weight configuration capability for the combined signal.

[0025] In other embodiments, the excitation structure is a coil protrusion, an inductor slot, or an excitation point.

[0026] The advantages of the embodiments of the present invention are: 1. Existing coil structures are fixed and have a single output mode. However, this invention utilizes a dynamic recombinant architecture consisting of N basic coil units, supporting any combination. Each basic coil outputs through a controllable amplifier with adjustable positive and negative polarity. Multiple coil signals are combined and differentially processed through digital logic, supporting any periodic phase combination; the combined waveform is programmable; and the signal-to-noise ratio is enhanced, improving adaptability.

[0027] 2. Existing coil outputs are only in-phase superposition and lack a differential mode. However, this invention switches the coil signal polarity (positive / negative) through the amplifier pin configuration to achieve differential output. Each coil is connected to an adjustable amplifier, and the output is determined to be positive or negative by the control signal. This can construct a high-precision differential signal, suppress common-mode interference, and improve sensor resolution.

[0028] Based on the above structure, the present invention further provides a coil array signal output method, comprising: Signal model: Each coil outputs a cycle waveform Is a specific envelope with a period of N (such as a sine wave, a triangle wave, Figure 10 As shown), the periodic waveform satisfies: in, , represents the phase delay of the kth coil, and t is the minimum time unit (tick).

[0029] In some embodiments, the phase structure: all coil signals are equally spaced in phase, forming a discrete phase basis. .

[0030] In other embodiments, the combined signal is constructed by setting the polarity ±1 for any coil combination and calculating the total output signal through digital circuit combination: in, The combinational logic is implemented using digital circuits, including polarity switching, differential weighting, and a combinational adder. This structure allows the generation of new periodic waveforms, where the specific period T_comb is determined by the relative phase relationship of the signals in the combination.

[0031] In some further embodiments, the period theory limits the output combined waveform period T_comb to a divisor of the fundamental period N∙t, satisfying: in, ; So the output frequency is , where d is a factor of N; When N=6, waveforms with periods of 2t, 3t, or 6t can be combined; When N is a prime number (such as N=5, 7), a waveform with a period of N·t can be combined.

[0032] The system has the ability to synthesize a limited set of frequencies, and each frequency point is determined by differential combination logic. Using this principle, functions such as frequency multiplexing, modulation and demodulation, and electromagnetic encoding can be constructed. In the sensor, the representative output can switch between different combination modes according to the target to achieve multi-functional multiplexing.

[0033] The advantages of the embodiments of the present invention are: The existing digital processing part cannot flexibly combine phase differential waveforms. However, the present invention proposes a digital combination algorithm based on multi-phase periodic signals, which is applicable to any number of coils. The analog output waveform is a periodic signal, and multiple adjacent phase signals are combined in tick units. The algorithm is implemented as a differential superposition device.

[0034] Based on the above method, Figure 11As shown, the present invention also provides a numerical signal processing device, comprising: Multi-channel synchronous sampling input unit 1, which consists of a set of high-speed sampling D-type flip-flop arrays, is used to synchronously acquire the periodic waveform of each coil channel, so that the combined calculation is completed in the same clock domain; it supports input channels N = 2 to 32 and is compatible with coil arrays of different specifications.

[0035] Output shaping module 5, which includes a digital filter, comparator, or waveform edge detection logic, is used to convert the combined signal into a single-cycle TTL output (for counting / ranging), eliminate spikes, smooth the combined boundary, extract the frequency envelope, or modulate the edge signal.

[0036] In some embodiments, the device further includes a polarity control matrix 2; the polarity control matrix is ​​used to allow each channel signal to enter a group of selectors and programmable inverters; the control signal comes from a control register, and the signal is configured to be forward or reverse.

[0037] In some embodiments, the device further includes a differential weighted combination unit 3; the combination unit is used to input the N polarity-adjusted signal inputs into the weighted combiner to perform sign weighting, add, subtract or shield a certain signal; and / or the combination unit is a structured addition tree or a LUT+DSP multiplication-addition structure.

[0038] In some embodiments, the device also includes a combination strategy management module 4; the management module is used to store and schedule preset combination templates, instructions to trigger dynamic switching of combination templates, realize multi-mode detection / encoding functions or realize template selection based on state machines or external commands.

[0039] Exemplary: like Figure 12 As shown, the numerical signal processing device includes the following functional modules: 1. Multi-channel synchronous sampling input unit (Synchronized Input Buffer) It consists of a set of high-speed sampling D-type flip-flop arrays. The periodic waveform of each coil channel is collected synchronously to ensure that the combined calculation is completed in the same clock domain. It supports input channels N=2 to 32 and is compatible with coil arrays of different specifications.

[0040] 2. Polarity Control Matrix (PCM) Each channel signal enters a set of selectors (MUX) and programmable inverters (XOR or INV); the control signal comes from the control register, which configures the signal as forward or reverse; the polarity control word is an N-bit wide logic vector that supports periodic refresh and adapts to dynamic reconstruction requirements.

[0041] 3. Differential Weighted Combiner The polarity-adjusted N-channel signal inputs are fed into a weighted combiner; The implementation form is: Structured adder tree: composed of multiple 1-bit adders (full adders / serial XOR); Or LUT+DSP multiplication-addition structure (applicable to FPGA); It supports symbol weighting (±1, 0) to achieve the function of adding, subtracting, or shielding a certain signal; the output is a combined signal S(t), and the period is the minimum common period after the constructed combination.

[0042] 4. Pattern Controller Stores and schedules preset combination templates (such as differential structures such as ABC and DEF); supports instruction-triggered dynamic switching of combination templates to achieve multi-mode detection / encoding functions; can be expanded into a microinstruction controller to achieve template selection based on state machines or external commands.

[0043] 5. Optional Output Shaper Includes digital filters (IIR / FIR), comparators, or waveform edge detection logic; Applies to: Convert the combined signal into a single-cycle TTL output (for counting / ranging); Eliminate spikes and smooth combination boundaries; Extract frequency envelope or modulation edge signals.

[0044] If implemented using FPGA, the above modules can be implemented as reusable IP cores using Verilog / System Verilog; Weighted control and combined output can be implemented by software on MCU or SoC.

[0045] For ease of understanding, this embodiment further illustrates the specific implementation process of the above method in conjunction with a specific application scenario system, for example: Example 1: Coil structure design with N=6 like Figure 5 and Figure 6 As shown (the attached figure is a square wave, the actual waveform can be other specific envelope waveforms) Use 6 basic coil units, numbered L0~L5; Each coil has 6 protrusions arranged in a sequential period, each period is [1,1,1,1,1,0]; The output signal of each coil is a periodic waveform with a phase difference of 1 tick: A=L0 output, B=L1 (delay 1t), ...F=L5 (delay 5t) Each coil outputs through a differential amplifier to control the polarity ±1; Digital logic combination: (AC)+(DF)→period is 3t (AB)+(CD)+(EF)→period is 2t ABCDEF → period is 6t Example 2: Coil structure design with N=4 like Figure 7 、 Figure 8 and Figure 9 As shown, (the attached figure is a square wave, and the actual waveform can be other specific envelope waveforms) Use 4 basic coil units, numbered L0~L3; Each coil has 4 protrusions with a period of [1,1,1,0]; The output signal of each coil has a 1tick phase difference; Number combination: (AB)+(CD)→period is 2t A+BCD→the period is 4t.

[0046] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0047] Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments can be performed by instructing a processor through a program. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, or any combination thereof. The storage medium can be any available medium accessible by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0048] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0049] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dynamically reconfigurable coil structure, characterized in that: It includes N basic coils; each coil includes N evenly arranged excitation structures, forming an induction unit with a spatial period of N, where N is a positive integer; Each coil contains N-1 high levels and 1 low level; All coils are arranged in a spatially staggered manner so that the signal of each coil is delayed by one minimum time unit relative to the previous coil on the time axis.

2. The structure according to claim 1, characterized in that Each coil output signal is output through an amplifier or MUX-INV module with controllable polarity, and the signal output direction is forward or reverse.

3. The structure according to claim 1 or 2, characterized in that The excitation structure is a coil protrusion, an inductor slot or an excitation point.

4. A coil array signal output method, based on the structure of any one of claims 1 to 3, characterized in that: include: Each coil outputs a cycle waveform It is a specific envelope with a period of N, and the periodic waveform satisfies: in, , represents the phase delay of the kth coil, and t is the minimum time unit.

5. The method according to claim 4, characterized in that All coil signals are equally spaced in phase, forming a discrete phase basis .

6. The method according to claim 4, characterized in that Set the polarity ±1 for any coil combination and calculate the total output signal through digital circuit combination: in, ,The combinational logic is implemented through digital circuits, including polarity switching, differential weighting and ,combinatorial adders.

7. The method according to claim 4, characterized in that The output combined waveform period is a divisor of the fundamental period N∙t, satisfying: in, ; So the output frequency is , where d is a factor of N; When N=6, waveforms with periods of 2t, 3t, or 6t can be combined; When N is a prime number, a waveform with a period of N·t can be combined.

8. A numerical signal processing device, used in the method according to any one of claims 4 to 7, characterized in that: include: A multi-channel synchronous sampling input unit, which consists of a set of high-speed sampling D-flip-flop arrays and is used to synchronously acquire the periodic waveform of each coil channel so that the combined calculation is completed in the same clock domain; An output shaping module includes a digital filter, a comparator, or waveform edge detection logic, which is used to convert the combined signal into a single-cycle TTL output, eliminate spikes, smooth the combined boundary, extract the frequency envelope, or modulate the edge signal.

9. The device according to claim 8, characterized in that Also included is a polarity control matrix; The polarity control matrix is ​​used to allow each channel signal to enter a group of selectors and programmable inverters; the control signal comes from a control register, which configures the signal to be forward or reverse.

10. The device according to claim 8, characterized in that Also included is a differential weighted combination unit; The combination unit is used to send the polarity-adjusted N-channel signal inputs into the weighted combiner to perform symbol weighting, add, subtract or shield a certain channel of signal; and / or the combination unit is a structured addition tree or LUT+DSP multiplication-addition structure.

11. The device according to claim 8, characterized in that It also includes a portfolio strategy management module; The management module is used to store and schedule preset combination templates, and command-triggered dynamic switching of combination templates to implement multi-mode detection / encoding functions or template selection based on a state machine or external commands.

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