Verification method and system for maximum likelihood sequence detection chip

Abstract

The invention provides a verification method and system for a maximum likelihood sequence detection chip, and the method comprises the steps: creating a random environment, and creating a random model in the random environment; a verification environment is created, the reference model runs in the verification environment, and the to-be-tested device runs in the verification environment; running a random environment, generating random configuration information by the random environment, and sending the random configuration information to the reference model; the reference model forms a test signal according to the received configuration information and inputs the test signal to the device to be tested; the reference model generates reference data according to the configuration information and outputs the reference data to the checker, the to-be-tested device operates according to the test signal and then generates operation data and outputs the operation data to the checker, and the checker compares the reference data with the operation data and generates a verification result. The invention further provides a verification system for implementing the method. According to the invention, the generation of the configuration information and the decoupling of the verification environment can be realized, and the accuracy of chip verification is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a verification method for a SerDes-based maximum likelihood sequence detection chip and a verification system for implementing the verification method. Background Art

[0002] A SerDes chip converts parallel data into high-speed serial data or restores serial data back to parallel data. As the communication rate of SerDes chips increases, for example, to 56Gbps or even 112Gpbs, inter-symbol interference (ISI) may occur during signal transmission due to path loss, reflections, and crosstalk. Traditional simple threshold detection or DFE methods cannot effectively compensate for channel impairments. Therefore, it is necessary to introduce a maximum likelihood sequence detection (MLSD) algorithm into SerDes chips. Such chips are called maximum likelihood sequence detection chips. Due to the high complexity of implementing maximum likelihood sequence detection chips, chip verification is required to ensure that the designed chip meets the preset requirements.

[0003] Existing chip verification methods involve a verification device sending a fixed-length test signal to the chip under test. Typically, noise is added to the test signal to verify the device's performance. The verification device then receives the response data from the device under test and determines whether the device meets pre-set requirements based on the received response data.

[0004] However, traditional testing methods often use fixed test signals input to the DUT, making it difficult to fully detect DUT issues, resulting in incomplete and inaccurate chip verification. Chinese invention patent application publication number CN119203174A discloses a verification method for a chip encryption module. The method first obtains random input data, determines a first calculation result based on the random input data and the DUT, and then determines a random detection result corresponding to the random input data based on the random input data and a pre-set detection model. Then, based on the random detection result and the first calculation result, a first verification result corresponding to the DUT is determined.

[0005] In the above method, during the test process, the driver module inputs random data to the device under test, so that the stimulus signal input to the device under test is not a fixed sequence, but a randomly generated sequence, which can detect more hidden problems of the chip. However, since the driver module is also a module running under the test device and also belongs to the verification environment, although the random data output by the driver module is only a random test vector randomly generated within a certain constraint range, this constraint range is not managed separately, and when the driver module itself is also a module in the verification environment, there will be implicit coupling between the configuration information input into the verification environment and the verification environment, resulting in limited coverage, affecting the accuracy and comprehensiveness of the verification. In addition, this test method only generates random test vectors, and does not generate random configuration information for coverage points for testing. Since random test vectors often cannot cover a large number of coverage points, there will still be test blind spots that are not covered for chip verification, affecting the accuracy of the test. Summary of the Invention

[0006] The first object of the present invention is to provide a verification method for a maximum likelihood sequence detection chip that can improve verification coverage and verification accuracy.

[0007] A second object of the present invention is to provide a verification system for a maximum likelihood sequence detection chip that implements the above verification method.

[0008] To achieve the first purpose of the present invention, the verification method of the maximum likelihood sequence detection chip provided by the present invention includes creating a random environment and creating a random model in the random environment; creating a verification environment, a reference model running in the verification environment, and the device to be tested running in the verification environment; running the random environment, generating random configuration information by the random environment and sending it to the reference model, the configuration information generated by the random environment includes the running configuration information of the reference model and / or the configuration information of the registers of the device to be tested; the reference model forms a test signal according to the received configuration information, and inputs the test signal to the device to be tested; the reference model generates reference data according to the configuration information and outputs it to the checker, the device to be tested generates running data after running according to the test signal and outputs it to the checker, and the checker compares the reference data with the running data and generates a verification result.

[0009] It can be seen from the above scheme that the present invention creates a random environment and a verification environment, and the random environment generates random configuration information and sends it to the reference model. That is, the configuration information is not randomly generated by the driver module running in the verification environment, but is randomly generated by a pre-created random environment according to the actual application scenario of the chip. In this way, generating random configuration information through a random model can achieve decoupling of the generation of configuration information and the verification environment, effectively avoiding the implicit coupling between the configuration information and the verification environment, and can cover a wider range of various operating conditions of the chip, making the verification of the chip more accurate.

[0010] In addition, since the present invention randomly generates configuration information based on pre-set configuration parameters, the configuration information is randomly generated, and the verification environment tests the device to be tested based on the test signal formed on the basis of the configuration information. The configuration information of the present invention includes the operation configuration information of the reference model, the configuration information of the register of the device to be tested, etc., so the configuration information actually sets the operation conditions of the reference model and the configuration of the device to be tested, and simulates the operation under different operation conditions by randomly generating these configuration conditions. Therefore, the test signal of the present invention is not a set of randomly generated vectors, but a test signal generated based on the randomly generated configuration information, so that during the verification process of the device to be tested, it can be tested under random configuration conditions. Compared with the random test signal composed of only random vectors, the present invention can cover more operation conditions, that is, the present invention can cover more coverage points, and the verification of the chip is more comprehensive and accurate.

[0011] A preferred solution is to set the class of the random model and define the configuration parameters of the class before creating the random environment; when creating the random environment, create the random model based on the class.

[0012] It can be seen that by creating a new class to define the random model, the creation of the random model can be easily realized, which can avoid the problem of having to define the random model by yourself every time a random environment is created, and improve the efficiency of creating the random environment.

[0013] A further solution is to constrain the configuration parameters based on the application scenario parameters of the device under test when defining the configuration parameters of the class of the random model.

[0014] A further solution is that when a random environment generates configuration information, the configuration information is randomly generated within the constraints of the configuration parameters.

[0015] It can be seen that since the configuration parameters of the random model class are constrained based on the application scenario parameters of the device under test, the configuration parameters will not exceed the boundaries of the constraints, avoiding the generation of unexpected configuration information that affects the accuracy of chip verification.

[0016] A further solution is that when the reference model inputs the test signal to the device under test, the signal value of the test signal in each clock cycle is determined, and the corresponding signal value is sent to the device under test in each clock cycle.

[0017] It can be seen that the test signal is input to the DUT according to the actual situation of each clock cycle, thereby ensuring that the DUT can accurately receive the test signal in each clock cycle, providing accurate data guarantee for subsequent verification.

[0018] A further solution is to determine the signal value of the test signal in each clock cycle according to the delay of the test signal in multiple clock cycles.

[0019] This shows that the delay has been taken into account when sending the test signal, thereby ensuring that the device under test can receive the corresponding test signal at a precise moment, avoiding affecting the accuracy of chip verification due to inaccurate test signal reception time.

[0020] A further solution is that the reference model sends reference data to the checker according to the clock cycle, and the device under test sends operation data to the checker according to the clock cycle. The checker compares the consistency of the reference data and the operation data in each clock cycle.

[0021] It can be seen that the checker compares the reference data and the operating data according to the clock cycle, so that it can accurately find in which clock cycle the abnormal result of the device under test occurs, and then accurately determine the location of the abnormality of the device under test, allowing testers to quickly find the cause of the abnormality.

[0022] A further solution is that the device to be tested includes a data module and an adaptive module, both of which receive test signals from the reference model; the checker includes a data checker and an adaptive checker, the data checker receives the operating data output by the data module and compares it with the reference data output by the reference model, and the adaptive checker receives the operating data output by the adaptive module and compares it with the reference data output by the reference model.

[0023] It can be seen that corresponding checkers are set for the data module and the adaptive module respectively, that is, a data checker and an adaptive checker are set respectively. The operating data output by the data module is compared with the reference data output by the reference model through the data checker, and the operating data output by the adaptive module is compared with the reference data output by the reference model through the adaptive checker. These can respectively detect problems existing in the data module and the adaptive module, thereby improving the accuracy of verification.

[0024] A further solution is that the data module and the adaptive module operate independently of each other and generate their own operating data respectively.

[0025] A further solution is that the data module also receives data output by the adaptive module and generates corresponding operation data; the adaptive module also receives data output by the data module and generates corresponding operation data.

[0026] It can be seen that when the data module and the adaptive module run independently and are tested separately, the accuracy of the operation of the data module and the adaptive module can be verified respectively. When the data module and the adaptive module are connected to each other and verified, it can be verified whether the data interaction between the two modules is correct. Through the above two verification modes, the independent operation of the two modules and the mutual data interaction can be accurately verified, thereby covering the complete operation scenario.

[0027] To achieve the above-mentioned second purpose, the verification system of the maximum likelihood sequence detection chip provided by the present invention includes a random environment, a random model running in the random environment, and the random environment is used to generate random configuration information, which configuration information includes the operation configuration information of the reference model and / or the configuration information of the registers of the device to be tested; a verification environment, a reference model running in the verification environment, the device to be tested running in the verification environment, the reference model is used to receive the configuration information generated by the random environment, and form a test signal according to the configuration information, and input the test signal to the device to be tested; the verification environment is also provided with a checker, the checker receives reference data generated by the reference model according to the configuration information and operation data generated after the device to be tested runs according to the test signal, compares the reference data with the operation data and generates a verification result.

[0028] As can be seen from the above scheme, the configuration information input to the reference model is generated by the random environment, specifically, by the random model running in the random environment. Because the configuration parameters of the random model are constrained based on the application scenario parameters of the device under test, the configuration information generated by running the random environment can avoid potential implicit coupling between the configuration parameters and the verification environment, thereby covering more verification scenarios and improving the coverage and accuracy of chip verification.

[0029] A preferred solution is that the device to be tested includes a data module and an adaptive module, and the checker includes a data checker and an adaptive checker. The data checker is used to receive the operating data output by the data module and compare it with the reference data output by the reference model, and the adaptive checker is used to receive the operating data output by the adaptive module and compare it with the reference data output by the reference model.

[0030] It can be seen that using the data checker and the adaptive checker to verify the data module and the adaptive module respectively can more accurately realize the verification of the two modules and improve the accuracy of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a structural block diagram of the verification system of the maximum likelihood sequence detection chip of the present invention in the first verification state.

[0032] Figure 2 This is a structural block diagram of the verification system of the maximum likelihood sequence detection chip of the present invention in the second verification state.

[0033] Figure 3 It is a flow chart of an embodiment of a verification method of a maximum likelihood sequence detection chip of the present invention.

[0034] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0035] The present invention provides a verification method for a maximum likelihood sequence detection chip for verifying a device under test, particularly a chip under test. This method generates configuration information by creating a random environment running a random model. This configuration information is then output to a reference model within the verification environment to verify the device under test. This allows configuration parameters to cover a wider range of operating environments, improving chip verification accuracy.

[0036] Example of a verification system for a maximum likelihood sequence detection chip: The verification system of this embodiment is used to verify a maximum likelihood sequence detection (MLSD) chip based on a serializer / deserializer (Serdes). A random environment is applied to generate random configuration information for the verification environment. The verification environment generates a test sequence based on the configuration information and sends the test sequence to the device under test. By comparing the data returned by the device under test with the reference data, it is verified whether the device under test meets the expected design requirements.

[0037] See also Figure 1The verification system of this embodiment includes a random environment 10 and a verification environment 20. A random model 11 runs in the random environment 10, a reference model 21 runs in the verification environment 20, and the device under test also runs in the verification environment 20. The random environment 10 is mainly used to generate random configuration information for the verification environment 20, and the verification environment 20 verifies the device under test based on the received configuration information. To this end, a checker needs to be set in the verification environment 20. The checker is used to receive the operating data output by the device under test. In addition, the reference model 21 also generates reference data based on the received configuration information. The checker compares the received reference data with the operating data output by the device under test, for example, comparing the reference data and the operating data in each clock cycle according to the clock cycle, so as to determine whether the device under test meets the preset design requirements.

[0038] In this embodiment, the device under test is a chip that implements the maximum likelihood sequence detection algorithm. For example, the device under test includes a data module (MLSD_DATA) 23 and an adaptive module (MLSD_ADAPT) 26. The two modules each implement their own functions, and data is also transmitted between the two modules. For example, the data module 23 is used to calculate the value of the branch metric, the path accumulation value and the decision value, while the adaptive module 26 is used to calculate the scoring threshold (level value) of the maximum likelihood sequence detection algorithm.

[0039] To verify data module 23 and adaptive module 26, the checker includes a data checker 24 and an adaptive checker 27. Data checker 24 receives reference data output by reference model 21 and operational data output by data module 23, and compares the reference data output by reference model 21 with the operational data output by data module 23 to determine whether data module 23 is operating incorrectly. Adaptive checker 27 receives reference data output by reference model 21 and operational data output by adaptive module 26, and compares the reference data output by reference model 21 with the operational data output by adaptive module 26 to determine whether adaptive module 26 is operating incorrectly.

[0040] During the verification process of the DUT, the reference model 21 receives the configuration information output by the random environment 10 and, based on the configuration information, generates the correct output result that the data module 23 should output. This is the reference data for the data module 23, and this reference data is output to the data checker 24. Furthermore, the reference model 21 also generates the correct output result that the adaptive module 26 should output based on the configuration information. This is the reference data for the adaptive module 26, and this reference data is output to the adaptive checker 27.

[0041] On the other hand, the reference model 21 generates a test signal to be output to the data module 23 based on the received configuration information. The test signal is output to the data module 23 via the data signal input module 22. At the same time, the reference model 21 also generates a test signal to be output to the adaptive module 26. The test signal is output to the adaptive module 26 via the adaptive signal input module 25.

[0042] Since the data module 23 and the adaptive module 26 can operate independently, that is, they operate without data interaction with each other, and the data module 23 and the adaptive module 26 can also operate in association, that is, the data module 23 and the adaptive module 26 exchange data during operation. When the data module 23 and the adaptive module 26 operate independently, the correctness of the operation of the data module 23 and the adaptive module 26 can be verified separately. When the data module 23 and the adaptive module 26 operate in association, the correctness of the data interaction between the data module 23 and the adaptive module 26 can be verified. The contents of the two operating condition verifications are different. Therefore, it is usually necessary to perform the above two verification operations separately, that is, it is necessary to verify whether the data module 23 and the adaptive module 26 operate correctly separately, and it is also necessary to verify whether the data module 23 and the adaptive module 26 exchange data correctly.

[0043] exist Figure 1 In the illustrated connection configuration, data module 23 and adaptive module 26 do not exchange data. In this state, data module 23 and adaptive module 26 operate independently. Data module 23 outputs the results of its independent operation, i.e., the operating data generated during independent operation, to data checker 24, which determines whether any abnormalities have occurred during the independent operation of data module 23. Furthermore, adaptive module 26 also outputs the results of its independent operation, i.e., the operating data generated during independent operation, to adaptive checker 27, which determines whether any abnormalities have occurred during the independent operation of adaptive module 26.

[0044] exist Figure 2In the illustrated connection mode, data module 23 and adaptive module 26 interact with each other. For example, data module 23 needs to output the decision value obtained by calculation to adaptive module 26, and adaptive module 26 outputs the scoring threshold obtained by calculation to data module 23. In this way, data module 23 performs subsequent calculations based on the obtained scoring threshold and outputs operating data. Correspondingly, adaptive module 26 also performs subsequent calculations based on the obtained decision value and outputs corresponding operating data. The operating data output by data module 23 is also output to data checker 24, and the operating data output by adaptive module 26 is also output to adaptive checker 27. It should be noted that when data module 23 and adaptive module 26 interact with each other, the operating data output by data module 23 is different from the operating data output when data module 23 operates independently. Therefore, reference model 21 needs to generate corresponding reference data based on whether data module 23 and adaptive module 26 operate independently or in conjunction with each other to ensure that data checker 24 can accurately judge the actual operating status of data module 23.

[0045] Example of verification method for maximum likelihood sequence detection chip: The following combination Figure 3 The working method of the above-mentioned verification system is introduced. First, execute step S1 to set the class of the random model. For example, define a class named RandModel, define the matlab model in this class, and perform the configuration required for the target algorithm, that is, set the configuration parameters. In this embodiment, the device to be tested is a chip that implements the maximum likelihood sequence detection algorithm. Therefore, the configuration parameters include channel insertion loss, optimized continuous time linear equalizer implementation code (CTLE_code), dc_noise, adaptive mode, gain, simulation seed number, register configuration, etc. When setting the configuration parameters, it is necessary to constrain the configuration parameters. For example, the application scenario parameters of the actual product are constrained by accurately modeling the various configuration requirements under the actual application conditions, so that the values ​​of each configuration parameter are within the pre-set constraint range, thereby ensuring that the subsequently randomly generated configuration information can fully cover the actual working state and boundary conditions of the chip.

[0046] Then, execute step S2 to create an independent random environment, in which the random model runs. It should be noted that the random environment runs independently of the verification environment. That is, the operation of the random environment is not interfered with by the verification environment, nor does it depend on the data output by the verification environment. Thus, the random model in the random environment is created entirely based on the RandModel class defined in step S1.

[0047] The process of creating a random model is also the process of instantiating the random model. Specifically, a specific object is created based on the class defined in step S1. This object is the created random model. Because the configuration parameters of the RandModel class have been constrained in step S1, the configuration parameters of the random model are randomly selected within the set constraints during instantiation. Therefore, the configuration parameters of each generated random model are different, and the resulting configuration information is also different, thus avoiding the problem of outputting fixed configuration information to the verification environment.

[0048] After the random environment runs, random configuration information will be generated. In order to verify the rationality of the configuration information, functional sampling of the configuration information can be performed. For example, the configuration information output by the random model can be obtained, and it can be judged whether the output configuration information meets the expected requirements, such as whether the configuration information exceeds the pre-set constraint range. If it does not exceed the pre-set constraint range, the configuration information is considered reasonable. If it exceeds the pre-set constraint range, it means that there is an abnormality in the generation of the configuration information, and the configuration parameters need to be reset and the configuration information needs to be regenerated. Of course, if the content of the configuration information needs to be increased later, the configuration parameters of the class of the random model can be redefined and new configuration parameters can be added so that the random model can generate new configuration information. In addition, sampling the configuration information can also facilitate the subsequent analysis and supplementation of the coverage of the configuration information.

[0049] Next, step S3 is executed to create a verification environment. A data transmission interface is defined within the verification environment for signal transmission. Data can be transferred between the random environment and the verification environment via the data transmission interface. For example, the random environment outputs configuration information to the verification environment via the data transmission interface. The created verification environment includes a reference model, a checker, and other components, and the device under test also runs on the verification model.

[0050] In this embodiment, the device to be tested includes a data module and an adaptive module, and correspondingly, the checker includes a data checker and an adaptive checker. After creating the verification environment, it is necessary to instantiate the data module, the adaptive module and the data transmission interface, and realize the connection between each module. For example, the data transmission interface can be connected to the reference model, and the reference model receives the configuration information output by the random environment, the data module can be connected to the data checker, and the adaptive module can be connected to the adaptive checker, etc. In addition, it is necessary to generate a clock signal and a reset signal in the verification environment. The reference model, the data module, the adaptive module, the data checker, and the adaptive checker all need to work under the same clock signal, so that the operating data output by the data module and the adaptive module can be verified according to the clock signal.

[0051] Then, step S4 is performed to run the random environment, such as starting the VCS simulator to run the random environment separately. After the random environment is run, the random model will generate configuration information, which is randomly generated within the constraints of the configuration parameters. The random environment generates configuration information including the operation configuration information of the reference model and the configuration information of the registers of the device under test. Specifically, a part of the configuration information is used to control the operation of the matlab reference model, such as the random seed number to control the random generation of the noise of matlab, and a part of the configuration information is used to control the register configuration of the device under test, such as the gain of the adaptive module. The greater the gain of the adaptive module, the slower the adaptive tracking speed, but the better the stability. The smaller the gain, the faster the tracking speed, but the poorer the stability. Since the random model can randomly generate configuration information, the gain of the adaptive module is also randomly generated within the constraints. The configuration information output to the device under test multiple times is not the same and has randomness. Therefore, the operating conditions of the adaptive module under different gains can be verified, thereby judging whether the device under test meets the operating requirements under different gains. Since this embodiment randomly generates configuration information and verifies the device to be tested based on the configuration information, different configuration information actually verifies different performances of the device to be tested. Therefore, this embodiment can cover more coverage points of the device to be tested, thereby verifying the device to be tested more comprehensively and accurately.

[0052] Of course, the configuration information can also be specified by the tester through the plusarg command. In this way, the tester can specify specific configuration information according to the actual test needs to avoid the problem of incomplete test coverage caused by randomly generated configuration information not fully covering specific test conditions, so that the verification of the device to be tested can cover all blind spots and improve the accuracy of verification.

[0053] Because the test signals of this embodiment are not simple random vectors but are generated based on randomly generated configuration information, which includes the operating configuration information of the reference model and the register configuration information of the device under test, randomizing the operating conditions of the reference model and the configuration of the device under test, this embodiment can simulate operating conditions under different operating conditions by randomly generating these configuration conditions. Compared to traditional techniques that only use random test signals composed of random vectors, this embodiment can cover more operating conditions, that is, it can cover more coverage points, and provide more comprehensive and accurate chip verification.

[0054] Then, step S5 is executed to run the verification environment, for example, by launching the VCS simulation tool. After running the reference model, the reference model receives configuration information from the random model via the data transmission interface and generates test signals required by the device under test based on the configuration information. Because the device under test includes a data module and an adaptive module, test signals required by the data module and the adaptive module must be generated separately. These test signals are output according to each clock cycle.

[0055] The verification environment also operates a data signal input module and an adaptive signal input module. The test signals required by the data module, generated by the reference model, are first output to the data signal input module, which then outputs them to the data module at each clock cycle. Furthermore, the test signals required by the adaptive module, generated by the reference model, are first output to the adaptive signal input module, which then outputs them to the adaptive module at each clock cycle. Because the reference model, data signal input module, data module, data checker, adaptive signal output module, adaptive module, and adaptive checker all receive the same clock signal and operate based on it, the reference model sequentially outputs corresponding test signals according to the operating timing requirements of the data and adaptive modules. Specifically, when the reference model sends a test signal, it needs to determine the test signal value for each clock cycle and send the corresponding signal value to the data and adaptive modules at each clock cycle. Because the test signals sent to the data and adaptive modules are different, the reference model needs to generate corresponding test signals separately and send them to the data and adaptive modules at each clock cycle.

[0056] In addition, since signal transmission delays may occur during the operation of the device to be tested, it is necessary to set a reasonable delay in the test signal. That is, when determining the signal value of the test signal under each clock cycle, the signal value corresponding to each clock cycle is determined according to the delay of the test signal under multiple clock cycles, so that the test signal sent to the data module and the adaptive module contains a delay, thereby verifying whether the data module and the adaptive module can correctly output the corresponding data under the corresponding delay conditions.

[0057] Then, step S6 is executed. After receiving the test signal, the data module operates according to the received test signal, generates operating data, and outputs the operating data to the data checker. Simultaneously, the adaptive module also operates according to the received test signal, generates corresponding operating data, and outputs the operating data to the adaptive checker.

[0058] In addition, while the data module and the adaptive module output operating data, the reference model also sends reference data to the checker according to the clock cycle. Specifically, the reference model applies the received configuration information to run and generates corresponding operating results, including the operating results of the data module and the operating results of the adaptive module. The operating results are the reference data. The parameter data corresponding to the data module is sent to the data checker, and the reference data corresponding to the adaptive module is sent to the adaptive checker.

[0059] Finally, step S7 is executed, where the data checker compares the operational data output by the data module with the reference data output by the reference model, thereby generating a verification result. Specifically, since the data module receives the test signal according to clock cycles and therefore outputs operational data according to clock cycles, and the reference model also outputs reference data according to clock cycles, the data checker can receive reference data and operational data for each clock cycle and compare the reference data and operational data in units of clock cycles. This allows the data checker to quickly analyze the clock cycle in which the operational data output by the data module is erroneous, and furthermore, quickly determine the cause of the data module operational error, such as which part of the data module is erroneous during design.

[0060] Similarly, the adaptive checker compares the operational data output by the adaptive module with the reference data output by the reference model, generating a verification result. Specifically, because the adaptive module receives test signals based on clock cycles and therefore outputs operational data based on clock cycles, and the reference model also outputs reference data based on clock cycles, the adaptive checker can receive reference data and operational data for each clock cycle and compare the reference data and operational data in units of clock cycles. This allows the adaptive checker to quickly determine the clock cycle in which the operational data output by the adaptive module is erroneous, and thus quickly identify the cause of the adaptive module's operational error.

[0061] It should be noted that when executing steps S6 and S7, testing can be performed in two situations: when the data module and the adaptive module operate independently, and when the data module and the adaptive module operate in conjunction with each other. When the data module and the adaptive module operate independently, the data module does not send data to the adaptive module, nor does the adaptive module send data to the data module. The data module merely receives test signals from the reference model and operates based on these test signals, thereby outputting operational data. Accordingly, the reference model also generates corresponding reference data based on the condition that the data module operates independently. Therefore, the verification results generated by the data checker are based on the verification results under the condition that the data module operates independently. Similarly, when the adaptive module operates independently, the verification results generated by the adaptive checker are based on the verification results under the condition that the adaptive module operates independently. In this case, it is possible to verify whether the data module and the adaptive module themselves have any abnormalities.

[0062] When the data module and the adaptive module are operating in conjunction with each other, the data module operation process not only receives test signals from the reference model, but also receives data output from the adaptive module. It operates based on the test signals and the data output by the adaptive module, thereby generating operation data. Correspondingly, the reference model also generates corresponding reference data based on the condition that the data module and the adaptive module are operating in conjunction with each other. Therefore, the verification result generated by the data checker is the verification result based on the condition that the data module and the adaptive module are operating in conjunction with each other. Similarly, when the data module and the adaptive module are operating in conjunction with each other, the verification result generated by the adaptive checker is the verification result based on the condition that the data module and the adaptive module are operating in conjunction with each other. In this case, it is possible to verify whether there are any abnormalities in the data interaction between the data module and the adaptive module.

[0063] Typically, chip verification requires both verifying the operation of each module and verifying the data exchange between modules. Therefore, both tests are necessary and complementary. For example, each module's own operation is first verified to determine whether any design anomalies exist. If no design anomalies exist, then the data exchange between modules must also be verified. Therefore, verification can be performed first with each module operating independently, and then with the modules operating in conjunction with each other.

[0064] Since the random model of the random environment can generate random configuration information each time, through multiple verifications, multiple configuration information can cover more random scenarios, avoiding coverage blind spots caused by using fixed configuration information during the verification process, making the chip verification results more accurate.

[0065] In addition, since the configuration information received by the reference model comes from a random model running in a random environment, and the random model runs independently of the verification environment, that is, the verification environment does not interfere with the operation of the random model, and therefore does not cause any interference to the configuration information generated by the random model. Compared with the verification method of generating random numbers by a driver module in a verification environment, the present invention can achieve the decoupling of the generation of configuration information and the verification process, that is, the generation of configuration information is not related to the verification environment, and can effectively prevent the implicit coupling that exists in the verification environment and the configuration information generation process. Moreover, since the class of the random model is predefined and the configuration parameters of the class are constrained, that is, the generation of configuration information is managed independently of the verification environment, thereby ensuring the independence of the configuration information, so that the generation of configuration information is not interfered with by the verification environment, and further preventing the implicit coupling that exists in the verification environment and the configuration information generation process.

[0066] In addition, when generating configuration information, in addition to generating random configuration information through random models, testers are also allowed to make manual settings. For example, for situations not covered by random configuration information, the unverified conditions can be covered by manually setting the configuration information, thereby improving the verification coverage.

[0067] Furthermore, the test signal generated by this embodiment can vary periodically, so the parameter data generated by the reference model should also vary periodically. If the DUT is operating correctly, its output data should also vary periodically. Therefore, by determining whether the DUT output data varies periodically, the checker can further determine whether the data module and adaptive module are operating abnormally, further improving the accuracy of DUT verification.

[0068] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A verification method for a maximum likelihood sequence detection chip, characterized in that: include: creating a random environment, and creating a random model in the random environment; Creating a verification environment, wherein a reference model runs in the verification environment, and the device to be tested runs in the verification environment; Running the random environment, generating random configuration information by the random environment and sending the random configuration information to the reference model, wherein the configuration information generated by the random environment includes running configuration information of the reference model and / or configuration information of registers of the device under test; The reference model forms a test signal according to the received configuration information, and inputs the test signal to the device under test; The reference model generates reference data according to the received configuration information and outputs it to the checker. The device under test generates operation data after running according to the test signal and outputs it to the checker. The checker compares the reference data with the operation data and generates a verification result.

2. The verification method for a maximum likelihood sequence detection chip according to claim 1, characterized in that: Before creating the random environment, setting the class of the random model and defining the configuration parameters of the class; When creating the random environment, the random model is created based on this class.

3. The verification method for a maximum likelihood sequence detection chip according to claim 2, characterized in that: When defining configuration parameters of the class of the random model, constraining the configuration parameters based on application scenario parameters of the device under test; When the random environment generates the configuration information, the configuration information is randomly generated within the constraint range of the configuration parameters.

4. The verification method for a maximum likelihood sequence detection chip according to any one of claims 1 to 3, characterized in that: When the reference model inputs the test signal to the device under test, the reference model determines a signal value of the test signal in each clock cycle, and sends a corresponding signal value to the device under test in each clock cycle; The reference model sends the reference data to the checker according to a clock cycle, the device under test sends the operating data to the checker according to a clock cycle, and the checker compares the consistency of the reference data and the operating data in each clock cycle.

5. The verification method for the maximum likelihood sequence detection chip according to claim 4, characterized in that: When determining the signal value of the test signal in each clock cycle, the signal value corresponding to each clock cycle is determined according to the delay of the test signal in multiple clock cycles.

6. The verification method for a maximum likelihood sequence detection chip according to any one of claims 1 to 3, characterized in that: The device under test includes a data module and an adaptive module, and both the data module and the adaptive module receive a test signal from the reference model; The checker includes a data checker and an adaptive checker. The data checker receives the operating data output by the data module and compares it with the reference data output by the reference model. The adaptive checker receives the operating data output by the adaptive module and compares it with the reference data output by the reference model.

7. The verification method for a maximum likelihood sequence detection chip according to claim 6, characterized in that: The data module and the adaptive module operate independently of each other and generate their own operating data respectively.

8. The verification method for a maximum likelihood sequence detection chip according to claim 6, characterized in that: The data module further receives the data output by the adaptive module and generates corresponding operation data, and the adaptive module further receives the data output by the data module and generates corresponding operation data.

9. A verification system for a maximum likelihood sequence detection chip, characterized in that: include: A random environment, wherein a random model is run in the random environment, and the random environment is used to generate random configuration information, wherein the configuration information generated by the random environment includes running configuration information of a reference model and / or configuration information of registers of a device under test; A verification environment, wherein a reference model runs in the verification environment, and the device under test runs in the verification environment, the reference model is used to receive configuration information generated by the random environment, and form a test signal according to the configuration information, and input the test signal to the device under test; The verification environment is further provided with a checker, which receives reference data generated by the reference model according to the configuration information and operation data generated after the device under test runs according to the test signal, compares the reference data with the operation data and generates a verification result.

10. The verification system for the maximum likelihood sequence detection chip according to claim 9, characterized in that: The device to be tested includes a data module and an adaptive module, and the checker includes a data checker and an adaptive checker. The data checker is used to receive the operating data output by the data module and compare it with the reference data output by the reference model, and the adaptive checker is used to receive the operating data output by the adaptive module and compare it with the reference data output by the reference model.

Images