Analog signal processing chip and fast start device thereof

Abstract

The application discloses a kind of quick starting device and analog signal processing chip, the device includes: default configuration module is used to store the default configuration value of controlling analog signal processing chip quick start;NVM calibration module is used to store the calibration configuration value of optimizing analog signal processing chip control accuracy;Control module is connected with default configuration module and NVM calibration module respectively, when chip power supply VCC is powered, control module obtains default configuration value from default configuration module and outputs to analog signal processing chip working circuit;When receiving parameter switching signal, control module obtains calibration configuration value from NVM calibration module according to parameter switching signal and outputs to analog signal processing chip working circuit.By default configuration module immediately outputs pre-stored configuration value after chip power-on, so that chip can quickly respond to generate rough conversion result without waiting for NVM calibration value to be loaded, which significantly shortens the start-up time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip control, in particular to an analog signal processing chip and a fast starting device thereof. BACKGROUND

[0002] In the manufacturing process of intelligent sensors and analog signal processing chips, the output characteristics often have inconsistencies due to the inherent deviation of semiconductor technology. To improve performance consistency, the existing technology usually calibrates parameters through NVM technology before shipment, that is, optimal configuration parameters are burned into the chip during the test phase. When the chip is powered on, these pre-stored parameters need to be loaded to adjust the working state and ensure the output accuracy of the sensor. However, the loading process of NVM data is limited by the power stabilization time and data length specified by the process manufacturer, usually requiring a delay of tens of microseconds, resulting in a significant extension of the chip startup time. In low-power applications such as magnetic shaft keyboards, the signals of multiple Hall sensors need to be polled quickly, and the delay in startup time directly affects the system response speed, becoming a key bottleneck restricting performance improvement.

[0003] In addition, for sensors and analog signal processing chips that support ENABLE pin control, the power supply (VCC) and enable signal (ENABLE) are designed separately, and the chip power consumption can be reduced to nano-ampere level by controlling the ENABLE pin. In this mode, the digital circuit inside the chip powered by VCC remains powered on and retains the calibration information in NVM. Although this design significantly reduces part of the power consumption and ensures the fast response of the output signal to the enable signal (ENABLE), it does not completely solve the problem of limited system response speed when the power supply (VCC) is powered on due to the NVM data loading time, limiting its application potential in ultra-low power scenarios. Therefore, how to optimize power management while ensuring fast startup has become a technical problem to be solved. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a fast starting device and an analog signal processing chip, which are suitable for various sensors and analog signal processing chips. By default, the configuration module outputs pre-stored configuration values immediately after the chip is powered on, so that the chip can quickly respond to input signals to generate rough conversion results without waiting for the NVM calibration data to be loaded, significantly shortening the startup time to the microsecond level, meeting the real-time requirements of various high-frequency polling scenarios. At the same time, the NVM calibration module seamlessly switches to output after loading accurate calibration values in the background, ensuring the subsequent conversion accuracy, and storing the calibration data with the help of the latch of the control module, realizing low-power management of the digital circuit under the control of the ENABLE pin, balancing fast startup and energy efficiency optimization.

[0005] To solve the above technical problems, the first aspect of the embodiment of the present application provides a fast starting device for an analog signal processing chip, the fast starting device is connected with a chip power supply VCC and an analog signal processing chip working circuit respectively, and the fast starting device comprises a default configuration module, an NVM calibration module and a control module;

[0006] The default configuration module is used for storing a default configuration value for controlling fast starting of the analog signal processing chip.

[0007] The NVM calibration module is used for storing a calibration configuration value for optimizing control precision of the analog signal processing chip.

[0008] The control module is connected with the default configuration module and the NVM calibration module respectively, when the chip power supply VCC is powered on, the control module obtains the default configuration value from the default configuration module and outputs the default configuration value to the analog signal processing chip working circuit, and when a parameter switching signal is received, the control module obtains the calibration configuration value from the NVM calibration module according to the parameter switching signal and outputs the calibration configuration value to the analog signal processing chip working circuit.

[0009] The parameter switching signal is sent by the NVM calibration module to the control module after the calibration configuration value is loaded.

[0010] Further, the default configuration value comprises an oscillator frequency configuration initial value, a bias current initial value, a bias voltage initial value, a gain initial coefficient, a zero point offset compensation initial value, a filter bandwidth initial parameter and an output driving initial parameter.

[0011] The calibration configuration value comprises an oscillator frequency configuration calibration value, a bias current calibration value, a bias voltage calibration value, a gain calibration coefficient, a zero point offset calibration value, a filter bandwidth calibration parameter and an output driving calibration parameter.

[0012] Further, the NVM calibration module comprises a digital control circuit, a level transfer circuit and an NVM circuit.

[0013] The digital control circuit is electrically connected with the chip power supply VCC, obtains the calibration configuration value pre-stored in the NVM circuit after the chip power supply VCC is powered on, and sends the calibration configuration value to the level transfer circuit.

[0014] The level transfer circuit converts the VCC voltage domain signal output by the NVM circuit into a corresponding VDD voltage domain signal of the digital circuit, and sends the VDD voltage domain signal to the control module.

[0015] Further, the level transfer circuit comprises a first level conversion circuit and a VDD power supply digital driving circuit.

[0016] The first level conversion circuit is electrically connected with the digital control circuit and the VDD-powered digital driving circuit, and is configured to convert the calibration configuration value from a high voltage signal in a VCC voltage domain to a low voltage signal in a VDD voltage domain, and send the calibration configuration value to the VDD-powered digital driving circuit.

[0017] The VDD-powered digital driving circuit is configured to perform shaping and enhancement processing on the calibration configuration value converted to the VDD voltage domain signal, and send the processed calibration configuration value to the control module.

[0018] Further, the control module comprises a multiplexer and a latch.

[0019] The multiplexer is electrically connected with the default configuration module, the NVM calibration module, and a working circuit of the analog signal processing chip, respectively.

[0020] After the chip power supply VCC is powered on, the multiplexer acquires the default configuration value in the default configuration module and sends the default configuration value to the working circuit.

[0021] After receiving the configuration switching signal of the NVM calibration module, the multiplexer receives the calibration configuration value of the NVM calibration module, and sends the calibration configuration value to the working circuit and the latch, respectively.

[0022] Further, the control module further comprises a second level conversion circuit.

[0023] The second level conversion circuit is connected with an output end of the VDD-powered digital driving circuit, and is configured to convert the low voltage signal in the VDD voltage domain output by the VDD-powered digital driving circuit to a high voltage signal in the VCC voltage domain, and send the high voltage signal to the latch powered by VCC for storage.

[0024] Further, when the chip power supply VCC and the chip ENABLE pin are powered on at the same time or the time interval is less than a preset time T set , the control module preferentially sends the default configuration value to the working circuit, and switches the output to the calibration configuration value after receiving the calibration configuration value.

[0025] The preset time is a time required for the NVM calibration module to complete configuration loading.

[0026] Further, when the chip ENABLE pin is powered on later than the chip power supply VCC and the time interval between the two is greater than a preset time T setWhen the preset time T is less than the chip ENABLE pin power-on time, the control module performs NVM calibration configuration loading during the chip power supply VCC power-on period, and outputs the calibration configuration value after the signal of the chip ENABLE pin triggers.

[0027] The preset time is the time required for the NVM calibration module to complete configuration loading.

[0028] Further, when the chip ENABLE pin power-on time is later than the preset time T set , the NVM calibration module performs calibration configuration loading during the chip power supply VCC power-on period, and stores the calibration configuration value in the latch of the control module.

[0029] The preset time is the time required for the NVM calibration module to complete configuration loading.

[0030] The second aspect of the embodiment of the application provides a fast start device for starting a chip.

[0031] The above technical solutions of the embodiment of the application have the following beneficial technical effects:

[0032] 1. By default, the configuration module outputs the pre-stored configuration value immediately after the chip is powered on, so that the Hall sensor can quickly respond to the magnetic field signal to generate a rough conversion result without waiting for the NVM calibration configuration loading to be completed, significantly shortening the start-up time to the microsecond level, and meeting the real-time requirements of high-frequency polling scenarios.

[0033] 2. The NVM calibration module seamlessly switches to output after loading the accurate calibration value in the background, ensuring the subsequent conversion accuracy, and storing the calibration data in the latch of the control module, so as to realize low-power management of the digital circuit under the control of the ENABLE pin, and balance the fast start and energy efficiency optimization. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a schematic circuit diagram of a fast start device for an analog signal processing chip provided by the embodiment of the application

[0035] Figure 2 is a schematic circuit implementation diagram of each module provided by the embodiment of the application.

[0036] Figure 3 is a VCC power-on circuit timing diagram provided by the embodiment of the application.

[0037] Figure 4 is an ENABLE power-on circuit timing diagram provided by the embodiment of the application. DETAILED DESCRIPTION

[0038] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application with reference to the specific embodiments and the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present application. In addition, in the following description, the description of the known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present application.

[0039] Please refer to Figure 1 The first aspect of the embodiment of the present application provides a fast start device of an analog signal processing chip. The fast start device is connected with a chip power supply VCC and an analog signal processing chip working circuit respectively. The fast start device specifically comprises a default configuration module, an NVM calibration module and a control module. The default configuration module is used to store a default configuration value for controlling the fast start of the analog signal processing chip. The NVM calibration module is used to store a calibration configuration value for optimizing the control precision of the analog signal processing chip. The control module is connected with the default configuration module and the NVM calibration module respectively. When the chip power supply VCC is powered on, the control module obtains the default configuration value from the default configuration module and outputs the default configuration value to the analog signal processing chip working circuit. When a parameter switching signal is received, the control module obtains the calibration configuration value from the NVM calibration module according to the parameter switching signal and outputs the calibration configuration value to the analog signal processing chip working circuit. The parameter switching signal is sent by the NVM calibration module to the control module after the calibration configuration value is loaded.

[0040] In one specific embodiment of the present application, the default configuration value comprises an oscillator frequency configuration initial value, a bias current initial value, a bias voltage initial value, a gain initial coefficient, a zero point offset compensation initial value, a filter bandwidth initial parameter and an output drive initial parameter. The oscillator frequency calibration value and the calibration configuration value comprise an oscillator frequency configuration calibration value, a bias current calibration value, a bias voltage calibration value, a gain calibration coefficient, a zero point offset calibration value, a filter bandwidth calibration parameter and an output drive calibration configuration.

[0041] In the above device, the default configuration module immediately outputs the pre-stored reasonable default configuration value to the working circuit at the moment when the chip power supply VCC is powered on, so that the Hall sensor can quickly respond to the magnetic field signal based on the simulation-optimized initial parameters without waiting for the NVM calibration data to be loaded. This breaks through the limitation in the traditional scheme that the chip must be started after the NVM is loaded, shortens the initial response time of the chip to the microsecond level, and significantly improves the polling efficiency in high real-time scenarios. The user's perceived start delay is almost zero, and the system can immediately enter the working state.

[0042] The NVM calibration module (Non-Volatile Memory Calibration Module) is a non-volatile memory unit integrated in the chip. Its core function is to store calibration data of chip working parameters through electrical programming, to ensure the precision performance of the chip in different working environments and life cycles. The NVM calibration module loads the high-precision calibration parameters burned out of the factory in parallel after the chip is powered on, and converts the VCC voltage domain signal into a low-voltage VDD domain signal of the digital circuit through a level transfer circuit, to ensure signal compatibility. Although the NVM configuration loading process takes tens of microseconds, the default configuration supports preliminary work, and the user is unaware of the background operation. The control module dynamically switches the configuration source through a multiplexer: it outputs the default configuration value in the initial stage, and seamlessly switches to the calibration configuration value after the NVM calibration data is loaded. The latch stores the calibration data, ensuring the stability of the parameters after switching, and avoiding the loss of calibration configuration data caused by transient interference or chip hibernation. Among them, the factory pre-stored calibration parameters loaded by the NVM calibration module belong to the working characteristic compensation parameters of the analog signal processing circuit, mainly including oscillator frequency configuration, sensitivity adjustment coefficient, zero point offset compensation value, temperature drift correction factor, etc., which are used to correct the output error of the sensor caused by manufacturing process deviation and environmental factors, to ensure its linearity and precision under different working conditions.

[0043] In addition, the working circuit of the analog signal processing chip contains multiple core devices and functional modules, such as bias circuit, signal conditioning circuit, clock circuit, output driving circuit, and calibration compensation circuit. The above circuits work together to achieve the goal of fast start and high-precision output.

[0044] First of all, the bias circuit is responsible for providing stable working current or voltage for sensor elements and other elements inside the chip. Its parameters (such as bias current size, bias voltage value) are dynamically adjusted by the bias current initial value of the default configuration module or the bias current calibration value of the NVM calibration module. This design ensures that the sensor and other elements establish a reliable working point immediately after the power supply is powered on, laying the foundation for fast response to magnetic field signals.

[0045] Secondly, the signal conditioning circuit is composed of a preamplifier, a filter, and an analog-to-digital converter (ADC). The preamplifier initially amplifies or linearly amplishes the original output signal of the Hall element based on the default configuration gain initial coefficient or the calibrated configuration gain calibration coefficient. The clock circuit provides the required clock signal for the dynamic circuit module in the chip based on the default configuration. The filter sets the initial cutoff frequency or the optimized noise suppression characteristic by the default configuration filter bandwidth initial parameter or the calibrated configuration filter bandwidth calibration parameter, balancing the signal response speed and the noise suppression effect. The analog-to-digital converter (ADC) digitizes the analog signal, and the quantization accuracy is compensated by the calibrated configuration zero-point offset calibration value, effectively eliminating static errors.

[0046] The output drive circuit converts the processed signal into a standard interface format (analog voltage, PWM, or digital signal) based on the default configuration output drive initial parameter (such as analog voltage range, PWM duty cycle reference) or the calibrated configuration output drive calibration configuration (such as interface timing optimization parameter), directly driving external systems. This design ensures the compatibility of the sensor with external devices, while adapting to the needs of different application scenarios.

[0047] In addition, the calibration compensation circuit further optimizes the chip performance by dynamically adjusting parameters. The zero-point offset compensation corrects the static output error based on the default configuration zero-point offset compensation initial value or the calibrated configuration zero-point offset calibration value; the sensitivity compensation adjusts the overall gain of the signal link to maintain linearity in combination with the calibrated configuration gain calibration coefficient; and the temperature drift compensation uses the calibrated configuration temperature drift correction factor to real-time offset the influence of environmental temperature changes on the output. These compensation mechanisms collectively ensure the stability and accuracy of the chip under different working conditions.

[0048] The control module adjusts the key parameters of the working circuit by outputting default configuration values or calibrated configuration values. For example, by adjusting the bias current / voltage to control the stability of the working point of the element, optimizing the gain coefficient to expand the signal amplification range and linearity, setting the filter bandwidth to balance the noise suppression and response speed, and configuring the output drive mode to ensure seamless connection with external systems. At the same time, the calibration compensation algorithm dynamically corrects the zero-point offset, sensitivity error, and temperature drift to further improve the accuracy of the output signal. Through the above multi-parameter collaborative adjustment, the analog signal processing chip achieves microsecond-level fast response based on the default configuration value after power-on, and then seamlessly switches to the high-precision parameters of the NVM calibration module, ultimately achieving the collaborative optimization of fast startup and high-precision output. This design not only shortens the system delay, but also ensures long-term stability through the background calibration mechanism, suitable for high real-time and low-power application scenarios.

[0049] In one specific embodiment of the present application, the NVM calibration module adopts various forms such as EFUSE, EEPROM, Flash, MRAM, FRAM, RRAM, and PCM.

[0050] Next, the device principle of the present application is further described by taking the EFUSE form as an example. Please refer to Figure 2 , the NVM calibration module comprises a digital control circuit, a level shift circuit, and an EFUSE circuit; the digital control circuit is electrically connected with the chip power supply VCC, obtains the pre-stored calibration configuration value of the EFUSE circuit after the chip power supply VCC is powered on, and sends it to the level shift circuit; the level shift circuit converts the VCC voltage domain signal output by the EFUSE circuit into the corresponding VDD voltage domain signal of the digital circuit, and sends it to the control module.

[0051] Among them, please refer to Figure 3 , in the power-on timing sequence in the chip power supply VCC power-on circuit timing diagram, the ENABLE signal is not obviously later than the VCC power-on, and the two are simultaneously or the time interval is less than T set , both belong to this case. In this application scenario, T on is defined as from VCC power-on to the first valid data output d1. After the chip is powered on, the conversion can be performed without waiting for the EFUSE reading operation, thus effectively shortening the power-on time. Otherwise, if the conversion is performed after waiting for the EFUSE reading operation, the first valid data is D2, and the power-on time is prolonged. When this scheme is adopted, the precision of the first valid data may be lost because the chip works in the default configuration rather than the calibrated configuration.

[0052] The NVM calibration module actively reads the pre-stored calibration parameters in the EFUSE circuit after the chip is powered on through the digital control circuit, realizing efficient loading of the parameters. Since the EFUSE circuit is directly powered by the VCC voltage domain, the high-level signal output by it needs to be converted into the low-voltage VDD domain signal suitable for the digital circuit through the level shift circuit, ensuring the compatibility and safety of the signal in cross-voltage domain transmission. The level shift circuit adopts the voltage division or MOS tube dynamic switching mechanism to map the high-voltage logic level in the VCC domain to the VDD domain without loss, avoiding the impact of high-voltage signals on low-voltage digital circuits while maintaining data integrity. It not only retains the precision advantage of EFUSE calibration, but also solves the problems of start-up delay and power consumption increase caused by voltage mismatch in the traditional scheme through voltage domain isolation and signal adaptation technology, so that the calibration process is completed seamlessly in the background, the chip can immediately work based on the default configuration, and finally the collaborative optimization of fast response and high-precision output is realized.

[0053] Further, please refer to Figure 2The level transfer circuit includes a first level conversion circuit and a VDD-powered digital driving circuit; the first level conversion circuit is electrically connected with the digital control circuit and the VDD-powered digital driving circuit, reduces the voltage of the calibration configuration value from a high voltage signal in a VCC voltage domain to a low voltage signal in a VDD voltage domain, and sends the calibration configuration value to the VDD-powered digital driving circuit; the VDD-powered digital driving circuit performs shaping and enhancement processing on the calibration configuration value converted into the VDD voltage domain signal, and sends the processed calibration configuration value to the control module.

[0054] The level transfer circuit reduces the VCC high voltage signal (such as 3.3V) output by the NVM module to a VDD low voltage domain (such as 1.8V) matched with the digital circuit through the first level conversion circuit, avoids potential damage of the high voltage signal to the low voltage device, simultaneously realizes lossless adaptation of the voltage domain through a voltage division network or a dynamic MOS switch, and ensures accurate mapping of the logic level of the calibration data. Subsequently, the VDD-powered digital driving circuit performs shaping processing on the reduced signal, eliminates noise or waveform distortion possibly introduced in the transmission process, and enhances the driving capability through a push-pull output structure, thereby ensuring the integrity of the signal under long wiring or load variation. The above implementation manner not only meets the safe transmission of the cross-voltage domain signal, but also improves the reliability of the transmission of the calibration configuration value through signal optimization, so that the control module can realize fast switching based on stable and clean calibration parameters, and finally significantly reduces the risk of misoperation caused by signal distortion while maintaining high precision of the chip.

[0055] Further, referring to Figure 2 The control module includes a multiplexer and a latch; the multiplexer is connected with a default configuration module, an NVM calibration module, and a working circuit of an analog signal processing chip; after the chip is powered on at a VCC, the multiplexer obtains a default configuration value in the default configuration module and sends the default configuration value to the working circuit; after receiving a configuration switching signal of the NVM calibration module, the multiplexer receives a calibration configuration value of the NVM calibration module, and sends the calibration configuration value to the working circuit and the latch respectively.

[0056] The control module preferentially selects the default configuration value output to the working circuit through the multiplexer at the initial stage of the chip power-on, so that the chip can quickly respond to the magnetic field signal without waiting for the calibration data to be loaded, and realizes instantaneous start. At the same time, after the NVM calibration module completes the calibration configuration loading in the background, the multiplexer is triggered to switch to the calibration configuration value input, thereby ensuring the high precision of the subsequent output. The latch captures and stores the calibration value in this process, and even if the internal low-voltage digital circuit is powered off, the data is still stable by VCC power supply, thereby avoiding the delay and power consumption caused by repeated loading. This dynamic switching and data persistence mechanism takes into account the fast response and long-term calibration stability, and optimizes the energy efficiency management in the low-power consumption scenario.

[0057] Further, asFigure 2 As shown, the control module further comprises: a second level conversion circuit; the second level conversion circuit is connected with the output end of the VDD-powered digital driving circuit, boosts the VDD voltage domain low voltage signal output by the VDD-powered digital driving circuit to a VCC voltage domain high voltage signal, and sends it to the storage of the latch powered by VCC.

[0058] The second level conversion circuit restores the low voltage calibration signal (such as 1.8V) processed in the VDD domain to the VCC high voltage domain (such as 3.3V) matched with the power supply of the latch through a dynamic level lifting mechanism, ensuring that the calibration value can be safely received and stably stored by the latch powered by VCC. The circuit adopts a cross-coupled MOS tube or charge pump structure to realize precise lifting of the voltage amplitude under the premise of unchanged signal logic, avoiding data distortion or device damage caused by voltage domain mismatch. The latch is continuously powered by VCC, even if the chip enters low-power mode (VDD power-off), it can still keep the calibration data for a long time, so that the chip can directly call the stored calibration parameters when it wakes up or the ENABLE pin is reactivated, saving time and energy consumption of repeated loading. This design maintains calibration accuracy while significantly optimizing response speed and energy efficiency in low-power scenarios.

[0059] Further, when the chip power VCC and the chip ENABLE pin are powered on at the same time or the time interval is less than a preset time T set , the control module preferentially sends the default configuration value to the working circuit, and switches the output to the calibration configuration value after receiving the calibration configuration value; wherein the preset time is the time required for the NVM calibration module to complete configuration loading.

[0060] Please refer to Figure 4 , in the power-on timing of the ENABLE power-on circuit timing diagram, the ENABLE signal is obviously later than the VCC power-on, and the time interval is greater than T set . In this application scenario, T on is defined as the time from the ENABLE rising to the output of the first valid data D1. After the chip is powered on by VCC, it immediately performs EFUSE reading, and completes the reading operation after T set time. Then, the control circuit is powered off to reduce power consumption, and the EFUSE_FINISH signal is also lowered. When the ENABLE signal rises, the chip can use the calibration data stored in the EFUSE to work in the first conversion process. In this power-on timing, the same power-on time is maintained, and the first conversion result accuracy is improved from the coarse conversion result d1 to the accurate conversion result D1.

[0061] When the chip power VCC and the ENABLE pin are powered on at the same time or the time interval is shorter than the preset time T setWhen the time interval between the power-on time of the chip ENABLE pin and the power-on time of the chip power supply VCC is greater than the preset time Tset, the control module performs EFUSE calibration configuration loading during the power-on of the chip power supply VCC, and outputs the calibration configuration value after the signal trigger of the chip ENABLE pin; wherein the preset time is the time required for the NVM calibration module to complete the configuration loading. set After the preset time Tset ends, the control module seamlessly switches to the calibration configuration value, ensuring the accuracy of the subsequent output signal. This design, through dynamic priority allocation and parallel operation mechanism, not only meets the stringent real-time requirements of magnetic shaft keyboard and other scenarios, but also preserves the accuracy of the calibration parameters. At the same time, through the precise control of the preset time Tset, it avoids the mis-switching or signal jump caused by incomplete calibration, and realizes the efficient cooperation of fast start and high-precision output.

[0062] Further, when the power-on time of the chip ENABLE pin is later than the power-on time of the chip power supply VCC and the time interval between the two is greater than the preset time T set , the control module performs EFUSE calibration configuration loading during the power-on of the chip power supply VCC, and outputs the calibration configuration value after the signal trigger of the chip ENABLE pin; wherein the preset time is the time required for the NVM calibration module to complete the configuration loading.

[0063] When the power-on time of the chip ENABLE pin is significantly later than the VCC power supply and the time interval exceeds the preset time Tset (i.e. the minimum time required for the NVM calibration module to complete the configuration loading), the control module has completed the loading and storage of the calibration configuration in the background during the power-on of VCC. At this time, the calibration value is pre-stored in the latch powered by VCC, and the latch still maintains stable data when VDD is powered off. When the ENABLE pin signal is triggered, the control module does not need to wait for the calibration data loading process, but directly calls the high-precision calibration value stored in the latch to output to the working circuit, so that the chip can output accurate results at the first signal conversion. Through the implementation of "pre-loading-storage-immediate calling", it not only avoids the additional waiting time caused by ENABLE delay in traditional schemes, but also ensures the persistence and fast availability of calibration data in low-power mode, significantly improving the system response efficiency and energy efficiency ratio.

[0064] Further, when the power-on time of the chip ENABLE pin is later than the preset time T set , the NVM calibration module performs calibration configuration loading during the power-on of the chip power supply VCC, and stores the calibration configuration value in the latch of the control module; wherein the preset time is the time required for the NVM calibration module to complete the configuration loading.

[0065] When the power-up time of the chip ENABLE pin is later than the preset time Tset (i.e. the threshold time required for the NVM calibration module to complete the configuration loading), the NVM calibration module has completed the loading of the calibration parameters in advance during the VCC power-up, and stores the calibration configuration value in the latch powered by the VCC continuously through level conversion. The latch is powered independently of the low-voltage digital circuit (VDD domain), so that the integrity of the calibration data can be maintained even when the chip enters the low-power mode (VDD power-off when the ENABLE pin is not activated). When the ENABLE pin is finally triggered, the control module can directly call the calibration value stored in the latch, skip the delay for loading in the traditional scheme, and output the first signal conversion based on the high-precision parameters, while avoiding the additional power consumption caused by repeated calibration. This mechanism, through the coordinated design of "background pre-loading-data persistence-immediate calling", ensures the calibration accuracy while significantly optimizing the startup efficiency and system response speed in the low-power scenario.

[0066] Further, the control module further comprises a latch holding circuit; the latch holding circuit is connected with the output end of the multiplexer, and holds the output digital logic level corresponding to the default configuration value before switching to the calibration configuration value.

[0067] The latch holding circuit in the control module captures the logic level corresponding to the default configuration value output by the multiplexer in real time, and maintains the stability of the level at the moment of switching to the calibration configuration value, avoiding the transient fluctuations or interruptions caused by signal switching. The core lies in that the storage characteristics of the latch circuit are used to temporarily keep the original logic level during the switching gap, ensuring that the chip working circuit continuously receives stable driving signals during the configuration transition. In combination with the sample and hold module in the signal conditioning circuit, the output error or noise interference caused by voltage jump is eliminated. This design is particularly important in high-precision sensors and analog signal chain chips, which not only ensures the continuity of the initial fast response, but also provides a smooth transition for the seamless switching of subsequent calibration values, finally maintaining the real-time performance of the system while improving the overall stability and anti-interference ability of the signal chain.

[0068] In addition, the default configuration module realizes the initial parameter configuration required for fast startup by defining the logic level (0 or 1) in advance during the chip design phase. The core structure includes an input node bound to the chip power VCC or ground GND, and a digital driving circuit powered by VCC. The level of the input node is directly bound to VCC (logic 1) or GND (logic 0) through metal layer connection, and after being enhanced in driving capability by the digital driving circuit, it is output to other functional modules. This binding relationship is realized through the photolithography process in the chip manufacturing process, and the path of the metal layer connection is determined by the design mask layout, so that the default value is fixed as a hardware structure.

[0069] If the default value is found to be deviated from the simulation result in actual test, only the binding path of the input node in the metal layer mask layout needs to be modified (for example, the node originally connected to VCC is changed to be connected to GND), so that the default configuration value can be adjusted without the need of redesigning or manufacturing the chip core circuit. Such flexibility significantly reduces the optimization cost after the chip is mass-produced, is compatible with the standard CMOS process, and avoids introducing additional manufacturing steps. The rationality of the default value is verified in advance through simulation, and the physical binding is realized through the metal layer in the manufacturing stage, so that the default configuration module has both reliability and economy in the fast start scenario.

[0070] The second aspect of the embodiment of the application provides a simulation signal processing chip comprising the fast start device for starting the chip.

[0071] The embodiment of the application aims to protect a simulation signal processing chip and a fast start device thereof. The fast start device is connected to a chip power supply VCC and a simulation signal processing chip working circuit respectively. The fast start device comprises a default configuration module, an NVM calibration module and a control module. The default configuration module is used to store a default configuration value for controlling the fast start of the simulation signal processing chip. The NVM calibration module is used to store a calibration configuration value for optimizing the control precision of the simulation signal processing chip. The control module is connected to the default configuration module and the NVM calibration module respectively. When the chip power supply VCC is powered on, the control module obtains the default configuration value from the default configuration module and outputs the default configuration value to the simulation signal processing chip working circuit. When a parameter switching signal is received, the control module obtains the calibration configuration value from the NVM calibration module according to the parameter switching signal and outputs the calibration configuration value to the simulation signal processing chip working circuit. The parameter switching signal is sent by the NVM calibration module to the control module after the calibration configuration value is loaded. The above technical solution has the following effects:

[0072] 1. The pre-stored configuration value is output by the default configuration module immediately after the chip is powered on, so that the Hall sensor can quickly respond to the magnetic field signal to generate a rough conversion result without waiting for the NVM calibration data to be loaded, the start time is significantly shortened to the microsecond level, and the real-time requirement of the high-frequency polling scene such as the magnetic shaft keyboard is met.

[0073] 2. The NVM calibration module seamlessly switches the output after loading the accurate calibration value in the background, ensures the subsequent conversion precision, stores the calibration data by means of the latch of the control module, and realizes the low-power management of the digital circuit under the control of the ENABLE pin, so that the fast start and energy efficiency optimization are considered.

[0074] It should be understood that the foregoing detailed description of the application, rather than limiting the application, is intended to explain and describe the current implementation of the application. Therefore, any modification, equivalent replacement or improvement made without departing from the spirit and scope of the application should be included in the protection scope of the application. In addition, the appended claims of the application are intended to cover all changes and modifications falling within the scope and boundary of the appended claims, or the equivalent form of such scope and boundary.

Claims

1. A fast startup device for an analog signal processing chip, characterized in that, The fast starting device is connected with a chip power supply VCC and an analog signal processing chip working circuit respectively, and comprises a default configuration module, an NVM calibration module and a control module. The default configuration module is used for storing a default configuration value for controlling fast starting of the analog signal processing chip. The NVM calibration module is used for storing a calibration configuration value for optimizing control precision of the analog signal processing chip. The control module is connected with the default configuration module and the NVM calibration module respectively, and when the chip power supply VCC is powered on, the control module obtains the default configuration value from the default configuration module and outputs the default configuration value to the analog signal processing chip working circuit; when a parameter switching signal is received, the control module obtains the calibration configuration value from the NVM calibration module according to the parameter switching signal and outputs the calibration configuration value to the analog signal processing chip working circuit. The parameter switching signal is sent by the NVM calibration module to the control module after the calibration configuration value is loaded. The NVM calibration module comprises a digital control circuit, a level transfer circuit and a memory circuit. The digital control circuit is electrically connected with the chip power supply VCC, obtains the calibration configuration value pre-stored in the memory circuit after the chip power supply VCC is powered on, and sends the calibration configuration value to the level transfer circuit. The level transfer circuit converts a VCC voltage domain signal output by the memory circuit into a corresponding VDD voltage domain signal of a digital circuit, and sends the VDD voltage domain signal to the control module. The level transfer circuit comprises a first level conversion circuit and a VDD power supply digital driving circuit. The first level conversion circuit is electrically connected with the digital control circuit and the VDD power supply digital driving circuit, reduces the calibration configuration value from a VCC voltage domain high voltage signal to a VDD voltage domain low voltage signal, and sends the calibration configuration value to the VDD power supply digital driving circuit. The VDD power supply digital driving circuit performs shaping and enhancement processing on the calibration configuration value converted into the VDD voltage domain signal, and sends the processed calibration configuration value to the control module. The control module comprises a multiplexer and a latch. The multiplexer is connected with the default configuration module, the NVM calibration module and the working circuit of the analog signal processing chip respectively. After the chip power supply VCC is powered on, the multiplexer obtains the default configuration value in the default configuration module and sends the default configuration value to the working circuit. After receiving a configuration switching signal of the NVM calibration module, the multiplexer receives a calibration configuration value of the NVM calibration module, and sends the calibration configuration value to the working circuit and the latch respectively.

2. The analog signal processing chip fast starting device according to claim 1, wherein the default configuration value comprises an oscillator frequency configuration initial value, a bias current initial value, a bias voltage initial value, a gain initial coefficient, a zero point offset compensation initial value, a filter bandwidth initial parameter and an output driving initial parameter. ​ The calibration configuration values include: an oscillator frequency configuration calibration value, a bias current calibration value, a bias voltage calibration value, a gain calibration coefficient, a zero point offset calibration value, a filter bandwidth calibration parameter and an output drive calibration parameter.

3. The analog signal processing chip quick start apparatus according to claim 1, wherein The control module further comprises a second level conversion circuit; The second level conversion circuit is connected with the output end of the VDD-powered digital driving circuit, boosts the VDD voltage domain low voltage signal output by the VDD-powered digital driving circuit into a VCC voltage domain high voltage signal, and sends the signal to the latch for storage.

4. The analog signal processing chip fast starting device according to claim 1, wherein the preset time is the time required for the NVM calibration module to complete configuration loading. When the chip power supply VCC and the chip ENABLE pin are powered on at the same time or the time interval is less than a preset time T set When the chip power supply VCC and the chip ENABLE pin are powered on at the same time or the time interval is less than a preset time T set , the control module preferentially sends the default configuration value to the working circuit, and switches the output to the calibration configuration value after receiving the calibration configuration value.

5. The analog signal processing chip fast starting device according to claim 1, wherein the preset time is the time required for the NVM calibration module to complete configuration loading.

6. The analog signal processing chip fast starting device according to claim 1, wherein the preset time is the time required for the NVM calibration module to complete configuration loading. When the power-on time of the chip ENABLE pin is later than the power-on time of the chip power supply VCC and the time interval between the two is greater than a preset time T set , the control module loads the NVM calibration configuration during the power-on of the chip power supply VCC and outputs the calibration configuration value after the signal of the chip ENABLE pin triggers. An analog signal processing chip fast starting device comprising any one of the devices according to claims 1-6. ​ When the chip ENABLE pin power-up time is later than the preset time T set The NVM calibration module performs calibration configuration loading during the chip power supply VCC power-up and stores the calibration configuration value in the latch of the control module. ​ 7. An analog signal processing chip, characterized by ​

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