Wafer and system for multi-chip programming

Abstract

The present application relates to the technical field of integrated circuit manufacturing, in particular to a wafer and system for burning of multiple chips, the present application sets metal traces in the scribe groove on the wafer, the interface chip and the corresponding metal traces transmit the burning data from the data burning module to each burning chip on the wafer, each burning chip completes its own burning through a preset communication protocol after receiving the corresponding burning data; by directly burning data to the chip in the wafer manufacturing stage, the inefficient problem of burning after cutting and packaging in the traditional method is avoided, the production efficiency is significantly improved; the step of separate burning after packaging is reduced, and the burning port does not need to be increased in the burning chip due to burning data, the chip area is saved, and the production cost and time cost are reduced; the number and grouping mode of the chip array can be flexibly adjusted according to the demand, and are suitable for chip manufacturing demands of different scales.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a wafer and system for programming multiple chips. Background Technology

[0002] In the integrated circuit manufacturing process, chip data programming is a crucial step. Traditional chip programming methods can only program one or a few dozen chips at a time. For example, programming can be done one chip at a time on a specific fixture, multiple chips can be programmed simultaneously via a one-wire transmission line, or multiple chips can be programmed at once using protocols such as the Serial Peripheral Interface (SPI). However, if further efficiency and cost reduction are desired, these methods are insufficient due to limited driving capabilities, typically supporting only a small number of chips to be programmed simultaneously—at most, a few dozen or a hundred.

[0003] For applications requiring the simultaneous programming of thousands of chips at the wafer level, traditional methods necessitate dicing and packaging the chips before programming each one individually. This method involves mechanically replacing one chip with a fixture after programming it, resulting in low efficiency and high costs. Furthermore, soldering the packaged chips onto a printed circuit board (PCB) introduces significant parasitic capacitance, further limiting the driving capability of the data programming interface.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by this invention is how to solve the problem of low efficiency in programming multiple chips in the prior art.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, a wafer for programming multiple chips is provided, the wafer including at least one interface chip, multiple programming chips and metal traces, the metal traces being disposed in the dicing slots of the wafer;

[0008] The interface chip is connected to different programming chips via the metal traces;

[0009] The interface chip is used to connect to the output end of the data burning module to receive the burning data sent by the data burning module;

[0010] The interface chip is used to transmit the programming data to the programming chip through the metal traces;

[0011] The programming chip is used to complete chip programming according to a preset communication protocol and the programming data.

[0012] Preferably, the metal traces are arranged in a crisscross pattern in the dicing groove, and the layers and spacing of the metal traces are adjusted according to the characteristics and quantity of the required metal traces.

[0013] Metal traces of different functions at the same level in the horizontal and vertical directions can be switched to other levels of metal traces at the intersection of the scribe lines by a punched jumper, so as to achieve staggered convergence of metal traces in two directions at the intersection.

[0014] Metal traces with the same function are connected by drilling holes at the intersection of the dicing grooves.

[0015] Preferably, the interface chip includes a pull-up resistor R1, an output unit, a pull-down switch, at least one pull-down resistor R2, and an input unit;

[0016] The input terminal of the output unit, one end of the pull-up resistor R1, and one end of the pull-down switch are respectively connected to the output terminal of the data programming module; the other end of the pull-up resistor R1 is connected to the programming voltage; the other end of the pull-down switch is grounded; the output terminal of the output unit is connected to different programming chips through the metal traces.

[0017] One end of the pull-down resistor R2 and the input terminal of the input unit are respectively connected to the programming chip through the metal trace; the other end of the pull-down resistor R2 is grounded; the output terminal of the input unit is connected to the control terminal of the pull-down switch.

[0018] Preferably, the output unit includes a first trigger and a first buffer connected in sequence;

[0019] The input terminal of the first trigger is connected to the output terminal of the data programming module; the output terminal of the first buffer is connected to different programming chips through the metal traces.

[0020] Preferably, the input unit includes at least one second trigger and a second buffer connected in sequence;

[0021] The input terminal of the second trigger is connected to the programming chip via the metal trace; the output terminal of the second buffer is connected to the control terminal of the pull-down switch.

[0022] Preferably, the programming chip includes a pull-down resistor R3, a first logic gate, and a second logic gate;

[0023] The input terminal of the first logic gate is connected to one end of the pull-down resistor R3 and the programming voltage, respectively; the output terminal of the first logic gate is connected to the internal control circuit of the programming chip.

[0024] One input of the second logic gate is connected to the programming voltage, and the other input of the second logic gate is connected to the output of the interface chip to receive programming data through the metal trace.

[0025] Preferably, the metal traces include a power line, a ground line, a data transmission line, and at least one data return line;

[0026] The data transmission line is used to transmit the programming data from the data programming module to each programming chip respectively.

[0027] The data return line is used to transmit the programming return data fed back from each programming chip to the interface chip.

[0028] Preferably, the chips located at the four corners of the wafer are configured as interface chips, and the chips on the wafer are divided into four regions, each region including at least one interface chip and multiple programming chips.

[0029] The metal traces include power lines, ground lines, data transmission lines, and four data return lines; each interface chip is connected to the data programming module through the metal traces.

[0030] The programming chip is connected to any interface chip via a power line, a ground line, a data transmission line, and any one of the data return lines.

[0031] Preferably, the size of the programming chips is consistent, and they all meet the preset communication protocol.

[0032] In a second aspect, a system for programming multiple chips is provided, the system comprising a wafer for programming multiple chips as described in the first aspect and a data programming module;

[0033] The data programming module is used to send programming data to the programming chip through the interface chip and the metal trace;

[0034] The chip is programmed according to a preset communication protocol and the programming data.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] This invention places metal traces in dicing slots on a wafer, and the interface chip and corresponding metal traces transmit programming data from the programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its programming through a preset communication protocol. By programming data directly on the chips during the wafer manufacturing stage, the inefficiency of programming after chip dicing and packaging in traditional methods is avoided, significantly improving production efficiency. It reduces the step of separate programming after packaging, and eliminates the need to add programming ports for programming data, saving chip area and reducing production and time costs. In addition, the number and grouping of chip arrays can be flexibly adjusted according to needs, making it suitable for chip manufacturing needs of different scales. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a wafer structure for programming multiple chips according to an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the structure of metal traces on a chip on a wafer provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the structure of an interface chip provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of a programming chip provided in an embodiment of the present invention;

[0042] Figure 5 This is another structural schematic diagram of a programming chip provided in an embodiment of the present invention;

[0043] Figure 6 This is a schematic flowchart of a wafer-level multi-chip data programming method provided in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of a multi-chip programming system provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic flowchart of a wafer-level multi-chip metal wiring method provided in an embodiment of the present invention;

[0046] Figure 9This is an interface schematic diagram of an interface chip provided in an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of a chip array and layered metal wiring provided in an embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram of a mesh layout structure of RX metal wire provided in an embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of a mesh layout structure of VDD metal wire provided in an embodiment of the present invention;

[0050] Figure 13 This is a schematic diagram of a mesh layout structure of TX0 metal wire provided in an embodiment of the present invention;

[0051] Figure 14 This is a schematic diagram of a mesh layout structure of TX1 metal wire provided in an embodiment of the present invention;

[0052] Figure 15 This is a schematic diagram of a mesh layout structure of TX2 metal wire provided in an embodiment of the present invention;

[0053] Figure 16 This is a schematic diagram of a mesh layout structure of TX3 metal wire provided in an embodiment of the present invention;

[0054] Figure 17 This is a schematic diagram of a cross-sectional structure of a metal line near the longitudinal axis of an interface chip provided in an embodiment of the present invention;

[0055] Figure 18 This is a schematic diagram of the structure of a longitudinal axis metal wire cross section and a transverse axis metal wire cross section provided in an embodiment of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0057] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0058] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0059] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0060] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0061] Example 1:

[0062] To address the problem of low programming efficiency caused by the prior chip cutting and packaging followed by programming in existing technologies, in one embodiment, such as... Figure 1 As shown, this embodiment proposes a wafer for multi-chip programming. The wafer includes at least one interface chip, multiple programming chips, and metal traces disposed in dicing slots of the wafer. The interface chip is connected to different programming chips through the metal traces. The interface chip is used to connect to the output of a data programming module to receive programming data sent by the data programming module. The interface chip is used to transmit the programming data to the programming chips through the metal traces. The programming chips are used to complete chip programming according to a preset communication protocol and the programming data.

[0063] It is worth noting that the black dots at the intersections of the metal wires indicate an electrical connection, while the intersections without black dots indicate no electrical connection between the metal wires.

[0064] In one embodiment, metal traces are embedded in the dicing slots reserved during wafer dicing to utilize the space not occupied by the chip for data path layout.

[0065] In one embodiment, the wafer includes multiple blocks, each of which can integrate 1024 chips. At least one of these chips can be configured as an interface chip to facilitate data exchange between the data programming module and the programming chips. To facilitate chip configuration, one or all four chips at the four corners of the wafer can be configured as interface chips, with the remaining chips serving as programming chips. All programming chips maintain a consistent size and conform to a preset communication protocol. The programming chips on the wafer can be of the same type or different types. More details will be provided below.

[0066] The chip programming process includes: the data programming module sends programming data to the interface chip, and then the interface chip and corresponding metal traces transmit the programming data to the programming chip. All programming chips can receive the programming data and write it into their internal storage units according to the preset communication protocol to complete the programming of each programming chip. The preset communication protocol can be the OneWire protocol.

[0067] This embodiment places metal traces in dicing slots on the wafer. The interface chip and corresponding metal traces transmit programming data from the programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its programming through a preset communication protocol. By programming data directly on the chips during the wafer manufacturing stage, the inefficiency of programming after chip dicing and packaging in traditional methods is avoided, significantly improving production efficiency. It reduces the step of programming separately after packaging, and the programming chip does not need to add programming ports for programming data, saving chip area and reducing production and time costs. At the same time, the number and grouping of chip arrays can be flexibly adjusted according to needs, suitable for chip manufacturing needs of different scales.

[0068] In order to position the metal traces within the dicing groove, in one embodiment, reference is made to... Figure 1 The metal traces are arranged horizontally and vertically in the dicing grooves. The layers and spacing of the metal traces are adjusted according to the characteristics and quantity of the required metal traces. For metal traces with different functions at the same layer in the horizontal and vertical directions, the metal trace in one direction is switched to the metal trace in another layer by punching jumpers at the intersection of the dicing grooves, so as to realize the staggered convergence of metal traces in the two directions at the intersection. Metal traces with the same function are connected by punching holes at the intersection of the dicing grooves.

[0069] In one embodiment, metal traces with different functions can be set on different metal layers, and metal lines with the same function in the horizontal and vertical directions can be connected by punching at the intersection of the scribe lines; secondly, metal traces with different functions can also be set on the same metal layer as long as the distance is set appropriately (for example, the spacing is less than a preset value). Metal traces with different functions in the same layer in the horizontal and vertical directions can be switched from one direction to another layer of metal lines by punching jumpers at the intersection of the scribe lines, so that the metal lines in the two directions can intersect at the intersection in a staggered manner and be connected by punching at the intersection.

[0070] Among them, the metal wires in both the horizontal and vertical directions should be selected as high-layer metal wires as much as possible. At the intersection, different wires need to be switched by drilling to achieve staggered intersection, so as to avoid short circuits of metal wires with different functions. At the same time, metal wires with the same function are connected by drilling at this point.

[0071] The metal traces include power lines (VDD and VDD_EXT), ground line (VSS), data transmission line (rx), and at least one data return line (tx0, tx1, tx2, and tx3 in this embodiment); the data transmission line is used to transmit the programming data from the data programming module to each of the programming chips; the data return line is used to transmit the programming return data fed back from each programming chip to the interface chip.

[0072] The crisscrossing arrangement refers to the layout of metal traces in the dicing area of ​​the wafer, where they intersect horizontally and vertically to form a grid-like wiring structure.

[0073] Horizontal routing refers to extending along the horizontal direction (such as the X-axis) of the dicing slot, while vertical routing refers to extending along the vertical direction (such as the Y-axis) of the dicing slot and intersecting perpendicularly with horizontal routing. This maximizes the use of two-dimensional space within the limited width of the dicing slot by crisscrossing horizontal and vertical routing, significantly improving wiring density and avoiding the problem of insufficient space caused by all routing being squeezed in the same direction.

[0074] In one embodiment, the horizontally and vertically intersecting traces are distributed across different metal layers and separated by an insulating layer to achieve functional isolation. Connections between the metal layers are made vias (drilled holes). At the intersections of the horizontal and vertical traces (i.e., the overlapping areas of different metal layers), vias are created using an etching process to connect the upper and lower metal traces, achieving electrical conductivity.

[0075] For example, horizontal traces extend horizontally on layer M1, and vertical traces extend vertically on layer M2. At the intersection, vias connect the traces on layers M1 and M2, forming corresponding conductive paths. In one embodiment, the type (through hole, blind hole, buried hole) and size of the vias need to be designed according to the process precision to ensure reliable connection and not affect the mechanical strength of the dicing groove.

[0076] The specific layout of the metal traces will be described in detail in the following embodiments.

[0077] To ensure that each chip in the wafer edge region can be connected to at least one interface chip, and to avoid the problem of being unable to program chips in areas where wafer blocks are incomplete. In one embodiment, such as Figure 2 As shown, the chips located at the four corners of the wafer are configured as interface chips, and the chips on the wafer are divided into four regions, each region including at least one interface chip and multiple programming chips; the metal traces include power lines, ground lines, data transmission lines and four data return lines; each interface chip is connected to the data programming module through the metal traces; the programming chips are connected to any interface chip through power lines, ground lines, data transmission lines and any one of the data return lines.

[0078] To avoid complex wafer routing due to all programming chips being connected to the same interface chip, this embodiment uses four interface chips on the wafer. Each interface chip connects to a programming chip in its corresponding area, responsible for programming data within that area. In other embodiments, more interface chips can be used to simplify wafer routing; however, further details are not provided in this embodiment.

[0079] Reference Figure 2 1024 chips are integrated into a block of a wafer to form a chip array. The chips at the four corners of the chip array are configured as interface chips (such as...). Figure 2 The remaining 1020 chips (P0, P1, P2, and P3) are the programming chips. C0, C1, C2, and C3 represent programming chips located in four different regions, each containing 255 programming chips. The specific number can be increased or decreased according to requirements. Metal traces are arranged in the dicing slots of the chip array for power lines (VDD_EXT and VDD), ground lines (VSS), data transmission lines (rx), and data return lines (including tx0, tx1, tx2, and tx3). The four interface chips P0, P1, P2, and P3 are connected to VDD_EXT, VDD, VSS, rx, tx0, tx1, tx2, and tx3 in the dicing slot, respectively. The programming chips in regions C0, C1, C2, and C3, in addition to connecting to VDD_EXT, VDD, VSS, and rx, only need to connect one of the corresponding data return lines (tx) from tx0, tx1, tx2, and tx3. That is, the programming chip tx in region C0 connects to tx0, the programming chip tx in region C1 connects to tx1, the programming chip tx in region C2 connects to tx2, and the programming chip tx in region C3 connects to tx3. It is worth noting that black dots at the intersections of metal lines indicate intersections; where there are no black dots, the metal lines do not intersect.

[0080] With this layout, the prober only needs to operate any one of the P0, P1, P2, or P3 interface chips to complete the data programming of all 1020 programming chips in the entire chip array. In actual operation, four probes are required, connecting to the four pads corresponding to the interface chip: VDD_EXT, VDD, VSS, and prog (see [reference]). Figure 3 (As shown).

[0081] In summary, by setting up four interface chips, it is ensured that each programming chip at the wafer edge can be connected to at least one interface chip. Even when the wafer edge area is incomplete, it can still be connected to the interface chip through the metal traces in the dicing slot, ensuring that each programming chip can perform data programming.

[0082] To enable data interaction between the data programming module and the programming chip, in one embodiment, such as... Figure 3 As shown, the interface chip includes a pull-up resistor R1, an output unit, a pull-down switch (i.e., Q1), at least one pull-down resistor R2, and an input unit. The input terminal (i.e., prog) of the output unit, one end of the pull-up resistor R1, and one end of the pull-down switch are respectively connected to the output terminal of the data programming module. The other end of the pull-up resistor R1 is connected to the programming voltage (i.e., VDD_EXT). The other end of the pull-down switch is grounded. The output terminal (i.e., rx) of the output unit is connected to different programming chips through the metal traces. One end of the pull-down resistor R2 and the input terminal of the input unit are respectively connected to the programming chips through the metal traces (i.e., tx0~tx3). The other end of the pull-down resistor R2 is grounded. The output terminal of the input unit is connected to the control terminal of the pull-down switch.

[0083] In one embodiment, refer to Figure 3 The output unit includes a first flip-flop (i.e., smit1) and a first buffer (i.e., buffer1) connected in sequence. The input terminal of the first flip-flop is connected to the output terminal of the data programming module. The output terminal of the first buffer is connected to different programming chips through the metal traces (i.e., rx) to transmit programming data to the programming chips. The input unit includes at least one second flip-flop (i.e., smit2) and a second buffer (i.e., buffer2) connected in sequence. The input terminal of the second flip-flop is connected to the programming chip through the metal traces (tx0, tx1, tx2 or tx3) to receive programming return data. The output terminal of the second buffer is connected to the control terminal of the pull-down switch.

[0084] In one embodiment, with four interface chips provided, the interface chips include four pull-down resistors R2 and four second flip-flops, and the interface chips also include a 4-input OR gate (i.e., OR).

[0085] The programming data from the data programming module is transmitted sequentially from the data receiving end (i.e., prog) of the interface chip to the data transmission line rx via the first trigger and the first buffer. The data transmission line rx transmits the programming data to each programming chip. The programming chips in the four regions C0, C1, C2, and C3 return programming return data via data return lines tx0, tx1, tx2, and tx3, respectively. The programming return data is used to indicate whether the programming chip has been successfully programmed.

[0086] In one embodiment, a low-level return data indicates successful programming; a high-level return data indicates programming failure. The programming return data can be in pulse form; that is, if programming is successful, a high-level signal is output for a preset duration. This preset duration can be in the microsecond or millisecond range, depending on the programming time of the chip, ensuring that the programming return data provides feedback on successful programming without affecting the programming of the next chip.

[0087] In this embodiment, the four data return lines are each connected to a pull-down resistor R2 and then to a second flip-flop. The second flip-flop is connected to a 4-input OR gate. After the second flip-flop increases the driving capability, it controls the on and off of the pull-down switch.

[0088] That is, the 4-input OR gate is connected to each of the 4 data return lines. When the programming chip corresponding to a data return line has no programming return data, the second flip-flop maintains a tri-state output, that is, the second flip-flop outputs 0. When the programming chip corresponding to a data return line has programming return data, the second flip-flop outputs the corresponding programming return data.

[0089] When none of the data return lines return programming data or the returned programming return data is 0, the 4-input OR gate outputs a low level, the pull-down switch is closed, and the level of the prog interface is pulled high by the pull-up resistor R1, allowing programming data to continue to be sent to the programming chip. When any data return line returns programming return data of 1, the 4-input OR gate outputs a high level, the pull-down switch is opened, pulling the level of the prog interface low, and programming data cannot continue to be sent.

[0090] In one embodiment, each programming chip on the wafer is designed with a unique identification sequence. During data programming, all programming chips simultaneously receive commands / data (i.e., programming data) sent by external devices through the prog interface. The programming data carries chip selection information. The programming chip parses the commands / data and compares the chip selection information parsed from the commands / data with the unique identification sequence inside the programming chip. The programming chip that successfully matches is identified as the target chip and communicates with the data programming module (the TX outputs of other programming chips besides the target chip remain in three states). Information is read from the target chip and data is programmed. By sending and parsing different chip selection information in this way, the programming of all programming chips on the entire array is completed in sequence.

[0091] When there is no data transmission to be sent on the corresponding data return line, the pull-down resistor R2 can keep the port in a low state. The value of the pull-down resistor R2 is determined by the requirements, for example, 50kΩ.

[0092] In one embodiment, such as Figure 4 As shown, the programming chip includes a pull-down resistor R3, a first logic gate (i.e., buf), and a second logic gate (i.e., AND). The input terminal of the first logic gate is connected to one end of the pull-down resistor R3 and the programming voltage, respectively. The output terminal of the first logic gate is connected to the internal control circuit of the programming chip. One input terminal of the second logic gate is connected to the programming voltage, and the other input terminal of the second logic gate is connected to the output terminal of the interface chip to receive programming data through the metal trace.

[0093] In one embodiment, refer to Figure 4 The first logic gate can be a buffer gate, and the second logic gate can be an AND gate. For example... Figure 5 As shown, the programming chip also includes a tri-state buffer (i.e., en).

[0094] Further reference Figure 4 and Figure 5 The programming chip also includes a data channel selection module (not shown in the figure). `tx_ic_en` (i.e., data return enable signal), `tx_ic` (data return signal), `rx_ic` (data receive signal), and `prog_en` (programming interface valid signal) are respectively connected to the data channel selection module. `tx_ic_en` and `tx_ic` are also connected to the two input terminals of a tri-state buffer, respectively. The output terminal `tx` of the tri-state buffer is connected to one of the data return lines `tx0`, `tx1`, `tx2`, and `tx3` in the metal traces. Only when `tx_ic_en` is at a valid level (usually high, depending on the specific definition) can the data from `tx_ic` pass through the tri-state buffer to drive the programming return data output; if `tx_ic_en` is invalid, the `tx` terminal is in a high-impedance state.

[0095] Reference Figure 4 One input of the AND gate (i.e., the second logic gate) (rx in the figure) is used to receive the programming data output by the interface chip, and the other input of the AND gate is connected to the programming voltage (i.e., VDD_EXT). The input of the buffer gate (i.e., the first logic gate) is connected to the programming voltage and one end of the pull-down resistor R3, respectively. In one embodiment, when an external voltage is applied to VDD_EXT, the output of the buffer gate is prog_en=1, indicating that the programming chip is enabled to receive signals from the prog terminal of the interface chip. When no external voltage is applied to VDD_EXT, the output of the buffer gate is prog_en=0, indicating that the programming chip does not receive signals from the prog terminal of the interface chip.

[0096] When VDD_EXT is equal to VDD voltage, the circuit structure of the programming chip can be directly as follows: Figure 4 and Figure 5When designing, if the voltages VDD_EXT and VDD are not equal, it is necessary to do so on the corresponding signal line (i.e., on...). Figure 4 At VDD_EXT, a corresponding level conversion circuit is set. When the programming chip is programming data, VDD_EXT and VDD are powered simultaneously, and prog_en=1. The programming chip receives or returns data according to the preset communication protocol to realize data programming. After the array programming data is completed, subsequent production processes such as dicing and packaging will be carried out. At this time, only VDD is powered, and VDD_EXT is not powered. Due to the effect of pull-down resistor R3, prog_en=0, and the programming chip no longer receives or returns data through the corresponding interface chip.

[0097] In one embodiment, power lines, ground lines, and data lines are present in all dicing slots, arranged simultaneously along both the horizontal and vertical axes. Through-holes connect the slots at their intersections to reduce parasitic resistance (due to the large current draw from thousands of chips operating simultaneously), ensuring the stability and uniformity of the power supply. This embodiment includes eight metal traces: VDD_EXT, VDD, VSS, rx, tx0, tx1, tx2, and tx3. Multi-layered metal spacing is used during routing to spatially separate adjacent metal lines.

[0098] In one embodiment, the scale can be adjusted according to actual needs. For example, if a scale of 4096 chips is adopted, the TX data lines can be expanded to 16. At the same time, other signal lines can be added to the dicing slots as needed, provided that the conditions are met. The specifics will not be explained in detail in this embodiment.

[0099] Example 2:

[0100] To further illustrate the wafer for multi-chip programming proposed in Example 1, this example proposes a wafer-level multi-chip data programming method. In one example, such as... Figure 6 As shown, the wafer-level multi-chip data programming method includes:

[0101] Step 101: The interface chip is connected to the output terminal of the data programming module to receive the programming data sent by the data programming module.

[0102] The data programming module establishes an electrical connection with an interface chip via a specific physical interface, such as a prober. The interface chip sends programming data to the programming chips. Through metal traces, data communication between the interface chip and numerous programming chips can be achieved without affecting subsequent wafer dicing and packaging. When the interface chip sends data, electrical signals are transmitted along the metal traces to each programming chip.

[0103] Step 102: The interface chip transmits the programming data to the programming chip through the metal trace; the programming chip is used to complete chip programming according to the preset communication protocol and the programming data.

[0104] The preset communication protocol specifies how the programming chip receives, identifies, and processes the received data. This includes the data format (such as the data frame structure, start bit, data bits, parity bit, stop bit, etc.), transmission rate, timing requirements (when to send data and when to receive data), and error handling mechanisms. After receiving data from the metal traces, the programming chip parses the data according to the preset communication protocol.

[0105] Once the programming chip successfully parses the programming data according to the preset communication protocol, it writes the corresponding programming data to a specific internal storage area, such as flash memory or electrically erasable programmable read-only memory. After programming is complete, the relevant circuitry inside the programming chip configures and initializes the written data, enabling the chip to perform the corresponding functions.

[0106] In one embodiment, the wafer-level multi-chip data programming method further includes:

[0107] During the wafer manufacturing stage, a unique identification sequence (such as a unique ID code) is pre-set inside each programmed chip.

[0108] The data programming module broadcasts commands / data (including chip selection information) to all programming chips on the wafer simultaneously through the shared prog interface.

[0109] All programmed chips receive and parse the received commands / data in real time, extract the chip selection information, and compare the chip selection information with their own unique identification sequence.

[0110] Successfully matched programming chips activate their communication function and send an enable signal to the interface chip via the data return line to notify the interface chip that its own communication function has been activated; the ports connected to the data return lines of unmatched programming chips remain in a high-impedance state to avoid bus conflicts.

[0111] The data programming module establishes a point-to-point communication channel with the activated programming chip. After the communication channel is established, the data programming module reads the status information (such as the storage area address) of the activated programming chip through the interface chip and sends programming data to perform the data programming operation on the activated programming chip and write the specified data.

[0112] After the activated programming chip completes programming, the programming return data is transmitted via the data return line.

[0113] The data programming module updates the chip selection information (the identification sequence pointing to the next chip to be programmed) in the command / data.

[0114] Repeat the above steps until all chips on the wafer have been programmed.

[0115] This invention places metal traces in dicing slots on a wafer, and the interface chip and corresponding metal traces transmit programming data from the programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its programming through a preset communication protocol. By programming data directly on the chips during the wafer manufacturing stage, the inefficiency of programming after chip dicing and packaging in traditional methods is avoided, significantly improving production efficiency. It reduces the step of separate programming after packaging, and eliminates the need to add programming ports for programming data, saving chip area and reducing production and time costs. In addition, the number and grouping of chip arrays can be flexibly adjusted according to needs, making it suitable for chip manufacturing needs of different scales.

[0116] Example 3:

[0117] This embodiment proposes a system for programming multiple chips. In one embodiment, such as... Figure 7 As shown, the system includes a wafer for multi-chip programming as described in Embodiment 1 and a data programming module; the data programming module is used to send programming data to the programming chip through the interface chip and the metal trace; the programming chip completes chip programming according to the preset communication protocol and the programming data.

[0118] This invention places metal traces in dicing slots on a wafer, and the interface chip and corresponding metal traces transmit programming data from the programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its programming through a preset communication protocol. By programming data directly on the chips during the wafer manufacturing stage, the inefficiency of programming after chip dicing and packaging in traditional methods is avoided, significantly improving production efficiency. It reduces the step of separate programming after packaging, and eliminates the need to add programming ports for programming data, saving chip area and reducing production and time costs. In addition, the number and grouping of chip arrays can be flexibly adjusted according to needs, making it suitable for chip manufacturing needs of different scales.

[0119] The structure of the wafer for programming the multiple chips is described in Example 1 and will not be repeated here.

[0120] Example 4:

[0121] This embodiment proposes a wafer-level multi-chip metal wiring method. This method is applicable to the arrangement of metal lines on a wafer where multi-chip programming is performed as described in Embodiment 1. In one embodiment, such as... Figure 8 As shown, the wafer-level multi-chip metal wiring method includes:

[0122] Step 201: Set metal traces in the dicing grooves of the wafer; arrange the metal traces in layers and set a preset spacing for isolation.

[0123] The metal traces may include power lines (VPP, VCC, and VDD), ground lines (VSS), data lines (rx and tx), clock line clk, clock selection signal clk_sel, and power-on reset signal rstn. clk, clk_sel, and rstn can be retained depending on the specific requirements. The width and thickness of the metal traces can be dynamically set according to current density and signal integrity requirements: power lines have a width greater than or equal to 5μm and a thickness greater than or equal to 3μm; data lines have a width greater than or equal to 2μm and a thickness greater than or equal to 0.2μm; clock lines and control signal lines have a width greater than or equal to 1μm and a thickness greater than or equal to 0.2μm.

[0124] Step 202: Connect the metal traces of different metal layers through through holes at the intersection of the dicing slots.

[0125] In one embodiment, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer are sequentially disposed in a dicing groove of a wafer. The first metal layer carries power lines, ground lines, and data lines; the second metal layer is used for jumper connections between different metal layers at the intersection of the dicing grooves; the third metal layer is used for routing data return lines and control signal lines; and the fourth metal layer is used for routing the power lines for programming the chip. In one embodiment, a via layer is disposed between the third and fourth metal layers to achieve vertical isolation between the metal layers. The via layer functions as a through-hole to isolate the metal layers vertically.

[0126] In one embodiment, adjacent metal traces use different metal layers alternately in the horizontal and vertical directions and are isolated by a preset spacing. The horizontal spacing between adjacent metal traces is not less than 0.5 μm. The vertical spacing between different metal layers is set according to preset process parameters, wherein the vertical spacing between the first metal layer and the second metal layer is not less than 3 μm.

[0127] Step 203: The interface chip and corresponding metal traces transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its programming through a preset communication protocol.

[0128] Multiple sets of pads are set at the interface chip, and the pads are respectively connected to the power line, ground line and data line in the dicing slot; the probe is electrically connected to the pads by the probe machine to realize the data programming of the chip on the wafer.

[0129] The data programming module sends the programming data to the interface chip, which then transmits the programming data to the target programming chip via corresponding metal traces. All programming chips receive the programming data and write it into their internal storage units according to the preset communication protocol, thus completing the programming process for each chip. The preset communication protocol can be the OneWire protocol.

[0130] It is worth noting that in this embodiment, because the programming chip has a built-in one-time programming memory, programming data requires a high-voltage power supply VPP of 5V or higher. Whether this power supply is needed or other power supplies should be added should be determined according to actual needs. After dicing, VPP is powered by an internal low-dropout linear regulator. VCC powers the programming interface, and VDD powers the programming chip. When VCC is not powered, the programming interface data lines and backup clock signal lines (rx, tx0, tx1, tx2, tx3, clk, clk_sel, rstn) will fail, but this will not affect the normal operation of the chip. The same applies after dicing. The layout of the metal layers should ensure that VCC, VPP, and VDD are not short-circuited.

[0131] On the one hand, this embodiment sets metal traces in the dicing slots of the wafer, and the interface chip and the corresponding metal traces transmit the programming data from the data programming module to each programming chip on the wafer. After receiving the corresponding programming data, each programming chip completes its own programming through a preset communication protocol. By using the wafer dicing slots to arrange the metal traces before programming the chips, the parasitic capacitance is much lower than that of the capacitance soldered on the PCB after packaging, which improves the reliability of signal transmission.

[0132] On the other hand, in this embodiment, the metal traces are laid out in layers and isolated by setting a preset spacing; at the intersection of the dicing slots, through holes are used to realize jumper connection between metal traces of different metal layers. Multi-layer metal traces realize high-density signal transmission. By setting cross-layer jumpers and spacing isolation for the metal traces, it is possible to prevent two adjacent metal lines from short-circuiting together due to cutting and squeezing during dicing.

[0133] In summary, this embodiment achieves efficient data programming of thousands of chips on a wafer through a layered metal wiring structure and spaced wiring. This method significantly reduces parasitic capacitance and short-circuit risk, while improving wafer utilization and programming efficiency. The number and grouping of the chip array can be flexibly adjusted according to requirements, making it suitable for chip manufacturing needs of different scales.

[0134] If only a single interface chip is placed on the wafer, the distance between the programming chip at the edge and the single interface chip is large (possibly several centimeters), resulting in significant resistance and capacitance effects of the metal traces, leading to signal attenuation, timing delays, and an increased programming failure rate. The chip layout at irregular wafer edges is scattered, making it difficult for a single global interface chip to cover all edge chips through a unified routing network; some corner chips may fail to program correctly. During global unified programming, all programming chips must wait for the same interface chip to process data sequentially, especially for edge chips, where the waiting time accounts for a larger proportion. To program chips located at irregular wafer edges, in one embodiment, the wafer-level multi-chip metal routing method further includes: dividing the chip array into multiple regions, and placing at least one interface chip at the edge of each region; the programming chips in each region are connected to at least one interface chip via data return lines.

[0135] In one embodiment, the chip array on the wafer is divided into multiple regions, each region corresponding to a set of data return lines; each set of data return lines is driven by a buffer in the programmed chip, and only one buffer is allowed to output data at a time, while the buffers in the remaining programmed chips remain in a high-impedance state to avoid bus conflicts. In one embodiment, such as Figure 9 and Figure 10 As shown, each of the four areas has an interface chip (P0, P1, P2 and P3), and the rest are programming chips.

[0136] Deploying interface chips close to the edge areas can significantly improve signal quality. Each interface chip can independently receive data programming commands, greatly improving the overall wafer processing efficiency. Furthermore, interface programming chips located at the wafer edge can be flexibly assigned to corresponding areas according to the actual contour, avoiding wiring difficulties caused by irregular wafer shapes.

[0137] Similarly, to further address the aforementioned wiring challenges, in one embodiment, referring to... Figure 10 In incomplete blocks at the wafer edge, data return lines of edge-located programming chips are connected to the nearest interface chip via metal traces in dicing slots. The wafer can be divided into four regions, with the chips at each of the four corners of each region designated as interface chips, and the remaining chips as programming chips. Each interface chip manages the programming of the corresponding region's programming chips and acts as a data interface for communication with the data programming module. The corner interface chips simplify the metal trace layout, and their location at the edge facilitates connection to the data programming module, thus significantly reducing the complexity of the metal trace layout.

[0138] Due to the incompleteness of wafer edge blocks caused by the dicing contour, some dicing slots are truncated, making it impossible for traditional metal trace networks to form complete pathways. The dispersed chip layout in the edge region and the narrower dicing slot width result in insufficient metal trace quantity or excessive spacing, easily leading to signal dead zones. To address these issues, in one embodiment, redundant metal lines are added to the dicing slots in the edge region to compensate for the wiring gaps caused by the incomplete blocks, ensuring that all programmed chips can be connected to the interface chip through at least one path.

[0139] Specifically, this includes: adding redundant horizontal / vertical traces in the edge dicing slots to ensure at least two paths between any two points, namely the primary path and the backup path. Redundant traces with the same topology are set up on different metal layers, with interconnection between layers achieved through vias. Some of the redundant traces are dedicated to power backup, while others are used for signal transmission, preventing single-point failures from affecting the overall power supply. The interface chip automatically selects the optimal path (lowest resistance, strongest signal) for data transmission by detecting the resistance values ​​of each path. When the primary path fails, the system switches from the primary path to the backup path within a preset time (e.g., 10ns) to ensure uninterrupted communication.

[0140] In one embodiment, independent voltage monitoring units can be set on both the main and backup power paths, and the voltage detection results of the voltage detection units can be acquired in real time. The voltage fluctuations of the main and backup power paths can be compared in real time based on the voltage detection results. When the voltage drop of the main power path exceeds a threshold, the system automatically switches to the backup path, and vice versa. In another embodiment, a miniature resistance sensor (such as a piezoresistive sensor based on CMOS technology) can be integrated into each metal trace to measure the resistance value in real time. The sensor accuracy needs to reach ±0.1Ω to distinguish subtle differences between different paths. A path evaluation unit is built into the interface chip, which periodically (e.g., every 100ms) sends probe pulses to each path. The signal quality is calculated based on the echo signal strength and phase, and the path quality is comprehensively evaluated in conjunction with the resistance value to select the appropriate path for data or voltage transmission.

[0141] Example 5:

[0142] To further illustrate the wafer-level multi-chip metal routing method in Example 4, this example provides a specific illustration. Taking a block of a wafer, comprising 1024 chips, as an example, the metal routing includes VPP, VCC, VDD, VSS, clk_sel, rstn, clk, rx, tx0, tx1, tx2, and tx3.

[0143] In one embodiment, refer to Figure 9This is a schematic diagram of the interface chips, with the internal rectangle representing a PAD. The four interface chips P0, P1, P2, and P3 are all connected to VPP, VCC, VDD, VSS, clk_sel, rstn, clk, rx, tx0, tx1, tx2, and tx3 in the dicing slots. The programming chips in the four chip areas C0, C1, C2, and C3, in addition to being connected to VPP, VCC, VDD, VSS, clk_sel, rstn, clk, and rx, only need to connect to one of the corresponding data return lines tx from tx0, tx1, tx2, or tx3. Therefore, except for tx, all metal lines with the same chip name in the array are connected together. With this layout, the prober only needs to operate any one of P0, P1, P2, or P3 to complete the data programming of all 1020 chips in the array.

[0144] Reference Figure 10 This is a schematic diagram of a chip array and layered metal wiring. Metal traces are arranged in the dicing slots of the chip array, including 3 power lines (VPP, VCC, and VDD), 1 ground line (VSS), 5 data lines (rx, tx0, tx1, tx2, tx3), a clock line (clk), a clock select signal line (clk_sel), and a power-on reset signal line (rstn). The function of each metal line is not elaborated further here. In one embodiment, 1024 chips are integrated in a block of the wafer to form a chip array (there are multiple metal lines in the dicing slots, and the width of the dicing slots and the width and length of the chips are not in a fixed ratio). The chips at the four corners of the chip array are designated as interface chips (P0, P1, P2, P3). The remaining 1020 chips are programming chips. C0, C1, C2 and C3 represent programming chips located in four different areas. They can be the same type of chip or different types of chips (but the chip size must be consistent). Each area has 255 programming chips. The specific number can be increased or decreased according to the needs of the array.

[0145] In one embodiment, refer to Figure 10 To distinguish the different metal lines, color-coded diagrams are used for illustration. Blue metal lines represent the metal traces of the first metal layer, green metal lines represent the metal traces of the second metal layer, orange metal lines represent the metal traces of the third metal layer, and black metal lines represent the metal traces of the fourth metal layer. Via layers are not shown in the diagram.

[0146] In one embodiment, such as Figure 11 The image shows the mesh layout of the data cable rx. Figure 12The power supply line VDD has a mesh layout. Because all metal lines with the same chip name, except for the data lines tx (including tx0, tx1, tx2, and tx3), are connected together, the metal line layouts of both (rx and VDD) are identical except for the metal layers. Figure 11 and Figure 12 It can also represent the arrangement of other metal wires besides tx0, tx1, tx2, and tx3. From Figure 11 and Figure 12 As can be seen, the metal wires are laid out in alternating rows (or columns), with a total of 16 wires in both the horizontal and vertical directions. The intersections of the horizontal and vertical wires are connected by perforations. With this wiring method, even though each individual metal wire is not very thick, the total width is considerable, and the even distribution fully meets the current density requirements.

[0147] In one embodiment, such as Figure 13 The diagram shows the mesh layout of data line TX0, with four interface chips located at the four corners. Within region C0, the metal wires of data line TX0 are routed on the first metal layer at intervals of one row (or one column), totaling eight wires horizontally and vertically. The first and eighth wires (counting from left to right) are jumpered to the third metal layer at the boundary between regions C0 and C1 (i.e., the dashed line X), and then extended into region C1. This allows the first metal wire of data line TX0 to connect to interface chips P0 and P1 in regions C0 and C1, respectively. (Continue referring to...) Figure 13 Six metal lines are arranged on the second metal layer along the horizontal axis, passing through regions C2 and C3 respectively, and connected to the eighth metal line in regions C0 and C1 via through-holes. Metal lines are arranged on the third metal layer in the scribe grooves near the interface chips in regions C2 and C3, and connected to the six metal lines on the horizontal axis via through-holes, allowing connection to interface chips P2 and P3 in regions C2 and C3 respectively. The layout of tx1, tx2, and tx3 is similar, as shown below. Figure 14 , Figure 15 , Figure 16 As shown. This completes the connection (or selective connection) of the four sets of data return lines (tx0, tx1, tx2, and tx3) to one or more of the four interface chips. The array size can be adjusted according to actual needs; for example, with a 4096-chip configuration, the tx bus can be expanded to 16 lines. Additional signal lines can also be added to the slots as needed, provided conditions permit. In short, it creates a buffer-avoidance feature between the t0-t3 data lines.

[0148] In one embodiment, such as Figure 17The image shows a cross-sectional view of the metal lines along the vertical axis of the data line TX0 region near the interface chip's dicing slot. In this example, the metal line width is 2µm, the first metal layer thickness is 3µm, and the thickness of the other metal lines is 0.2µm. The varying heights of the metal lines in the cross-sectional view represent different metal layer thicknesses. (Refer to...) Figure 17 From top to bottom, the layers are: the first metal layer (represented by blue), the second metal layer (represented by green), the third metal layer (represented by orange), the via layer (represented by cyan), and the fourth metal layer (represented by black). The dashed boxes represent the metal lines of the second metal layer and the via layer, respectively, and are used sparingly only at intersections.

[0149] In one embodiment, the vertical distance between the first and second metal layers is 3 μm, the vertical distance between the second and third metal layers is 0.2 μm, the vertical distance between the third metal layer and the via layer is 0.2 μm, and the vertical distance between the via layer and the fourth metal layer is 0.2 μm. Along the vertical axis near the interface chip, such as... Figure 10 As shown by the middle arrow and the dashed box, after the data line tx0 in region C0 reaches the boundary between region C0 and region C1, it needs to be horizontally jumpered to the second metal layer, and then vertically jumpered to the third metal layer before continuing into region C1. That is, a metal line distance needs to be left between data line tx1 and data line rx, so the distance between data line tx1 and data line rx is 3µm, and all other horizontal spacing is 0.5µm.

[0150] In one embodiment, such as Figure 18 The diagram shows cross-sectional views of the metal lines in the vertical and horizontal dicing slots. The cross-sections of the vertical and horizontal metal lines are identical; they are simply data lines TX1, TX2, and TX3 removed from the metal lines in the dicing slots near the interface chip, while everything else remains unchanged. Therefore, within the same dicing slot, excluding the second metal layer and the via layer, the horizontal distance between two metal lines of the same layer is 5.5µm, and the horizontal distance between two adjacent metal lines is 0.5µm. The vertical distance between the first and third metal layers is 3.4µm, and the vertical distance between the third and fourth metal layers is 0.6µm. This multi-layer metal spacing method during routing spatially separates adjacent metal lines, preventing them from short-circuiting due to cutting and compression during dicing.

[0151] The structure of the wafer for programming the multiple chips is described in Example 1 and will not be repeated here.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wafer for programming multiple chips, characterized in that, The wafer includes at least one interface chip, multiple programming chips, and metal traces, which are disposed in the dicing grooves of the wafer. The interface chip is connected to different programming chips via the metal traces; The interface chip is used to connect to the output end of the data burning module to receive the burning data sent by the data burning module; The interface chip is used to transmit the programming data to the programming chip through the metal traces; The programming chip is used to complete chip programming according to a preset communication protocol and the programming data; The chips on the wafer are divided into four regions C0, C1, C2 and C3. The chips located at the four corners of the four regions are set as interface chips P0, P1, P2 and P3 respectively. The remaining chips are programming chips. Each interface chip is responsible for programming the programming chips in the corresponding region and communicates with the data programming module as a data interface. Within region C0, the metal wires of data line tx0 are routed in the first metal layer with an interval of one row, totaling eight wires horizontally and vertically. The first and eighth wires are jumpered to the third metal layer at the boundary between regions C0 and C1, and then extended into region C1 so that the first metal wire of data line tx0 can be connected to the interface chips P0 and P1 in regions C0 and C1, respectively. Six metal wires are arranged on the second metal layer, passing through regions C2 and C3, and connected to the eighth metal wire in regions C0 and C1 through holes. Metal wires are arranged on the third metal layer in the scribe slots near the interface chips in regions C2 and C3, and connected to the six metal wires on the horizontal axis through holes, respectively, and connected to the interface chips P2 and P3 in regions C2 and C3. The layout of data lines tx1, tx2, and tx3 is the same as that of data line tx0.

2. The wafer for programming multiple chips according to claim 1, characterized in that, The metal traces are arranged in a crisscross pattern in the dicing groove, and the layers and spacing of the metal traces are adjusted according to the characteristics and quantity of the required metal traces. Metal traces of different functions at the same level in the horizontal and vertical directions can be switched to other levels of metal traces at the intersection of the scribe lines by a punched jumper, so as to achieve staggered convergence of metal traces in two directions at the intersection. Metal traces with the same function are connected by drilling holes at the intersection of the dicing grooves.

3. The wafer for programming multiple chips according to claim 1, characterized in that, The interface chip includes a pull-up resistor R1, an output unit, a pull-down switch, at least one pull-down resistor R2, and an input unit. The input terminal of the output unit, one end of the pull-up resistor R1, and one end of the pull-down switch are respectively connected to the output terminal of the data programming module; the other end of the pull-up resistor R1 is connected to the programming voltage; the other end of the pull-down switch is grounded; the output terminal of the output unit is connected to different programming chips through the metal traces. One end of the pull-down resistor R2 and the input terminal of the input unit are respectively connected to the programming chip through the metal trace; the other end of the pull-down resistor R2 is grounded; the output terminal of the input unit is connected to the control terminal of the pull-down switch.

4. The wafer for programming multiple chips according to claim 3, characterized in that, The output unit includes a first flip-flop and a first buffer connected in sequence; The input terminal of the first trigger is connected to the output terminal of the data programming module; the output terminal of the first buffer is connected to different programming chips through the metal traces.

5. The wafer for programming multiple chips according to claim 3, characterized in that, The input unit includes at least one second trigger and a second buffer connected in sequence. The input terminal of the second trigger is connected to the programming chip via the metal trace; the output terminal of the second buffer is connected to the control terminal of the pull-down switch.

6. The wafer for programming multiple chips according to claim 1, characterized in that, The programming chip includes a pull-down resistor R3, a first logic gate, and a second logic gate; The input terminal of the first logic gate is connected to one end of the pull-down resistor R3 and the programming voltage, respectively; the output terminal of the first logic gate is connected to the internal control circuit of the programming chip. One input of the second logic gate is connected to the programming voltage, and the other input of the second logic gate is connected to the output of the interface chip to receive programming data through the metal trace.

7. The wafer for programming multiple chips according to claim 1, characterized in that, The metal traces include power lines, ground lines, data transmission lines, and at least one data return line; The data transmission line is used to transmit the programming data from the data programming module to each programming chip respectively. The data return line is used to transmit the programming return data fed back from each programming chip to the interface chip.

8. The wafer for programming multiple chips according to claim 1, characterized in that, The chips located at the four corners of the wafer are configured as interface chips, and the chips on the wafer are divided into four regions, each region including at least one interface chip and multiple programming chips. The metal traces include power lines, ground lines, data transmission lines, and four data return lines; each interface chip is connected to the data programming module through the metal traces. The programming chip is connected to any interface chip via a power line, a ground line, a data transmission line, and any one of the data return lines.

9. The wafer for programming multiple chips according to claim 1, characterized in that, The programmed chips are all the same size and all meet the preset communication protocol.

10. A system for programming multiple chips, characterized in that, The system includes a wafer for multi-chip programming as described in any one of claims 1-9 and a data programming module; The data programming module is used to send programming data to the programming chip through the interface chip and the metal trace; The chip is programmed according to a preset communication protocol and the programming data.

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