Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a pixel circuit and a light emitting device. The pixel circuit comprises a pulse width modulation module and a pulse amplitude modulation module. The pulse width modulation module receives the sweep frequency signal. The drive control circuit comprises a frequency sweep drive circuit which provides frequency sweep signals for the pixel circuit. The frequency sweep driving circuit comprises a first gating module which is electrically connected with the frequency sweep control signal line. The first sweep frequency drive circuit provides a first sweep frequency signal for the first pixel circuit, and the second sweep frequency drive circuit provides a second sweep frequency signal for the second pixel circuit; wherein the first sweep frequency drive circuit is electrically connected with N sweep frequency control signal lines in total, and the second sweep frequency drive circuit is electrically connected with M sweep frequency control signal lines in total; n is not equal to M. The redundancy of the sweep frequency control signal line is reduced, the use efficiency of one sweep frequency control signal line is improved, and the preparation cost of the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The pixel circuit includes a control signal that can be used to control the duration of the light-emitting device's light emission. In terms of the sweep frequency signal required in the pixel circuit, the sweep frequency signal is usually a ramp signal. The sweep frequency drive circuit includes a plurality of cascaded shift register units, and the shift register unit can generate a sweep frequency signal to control the duration of the light-emitting device receiving the light-emitting drive current. The shift register unit in the sweep frequency drive circuit is electrically connected to a sweep frequency control signal line that transmits the sweep frequency control signal, and the sweep frequency control signal includes a ramp signal. When the shift register unit needs to output a sweep frequency signal, it can output the ramp signal transmitted by the sweep frequency control signal line. Among the sweep frequency drive circuits that drive light-emitting devices of different colors, how to reasonably set the sweep frequency drive circuit according to the light-emitting brightness of different light-emitting devices is an issue that needs to be considered urgently. Summary of the Invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0005] The pixel circuit includes a pulse width modulation module and a pulse amplitude modulation module; the pulse width modulation module receives a frequency sweep signal; the pulse width modulation module controls the duration of the light-emitting driving current generated by the pulse amplitude modulation module based on the frequency sweep signal;

[0006] A light-emitting device is electrically connected to the pulse amplitude modulation module; the light-emitting device includes a first light-emitting device and a second light-emitting device, the pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit is electrically connected to the first light-emitting device, and the second pixel circuit is electrically connected to the second light-emitting device;

[0007] A drive control circuit, the drive control circuit includes a sweep frequency drive circuit, the sweep frequency drive circuit provides a sweep frequency signal for the pixel circuit; the sweep frequency drive circuit includes a plurality of first shift register units, the first shift register unit includes a first drive module and a first gating module, a control end of the first gating module is connected to the output end of the first drive module, the first gating module is electrically connected to a sweep frequency control signal line, the sweep frequency control signal line transmits a sweep frequency control signal, and the first gating module outputs a sweep frequency signal based on the sweep frequency control signal and the signal output by the first drive module;

[0008] The sweep frequency driving circuit includes a first sweep frequency driving circuit and a second sweep frequency driving circuit. The first sweep frequency driving circuit provides a first sweep frequency signal for the first pixel circuit, and the second sweep frequency driving circuit provides a second sweep frequency signal for the second pixel circuit. The first sweep frequency driving circuit is electrically connected to N sweep frequency control signal lines, and the second sweep frequency driving circuit is electrically connected to M sweep frequency control signal lines. N≠M.

[0009] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel provided in the first aspect.

[0010] In an embodiment of the present application, the number of sweep control signal lines electrically connected to the first sweep drive circuit and the number of sweep control signal lines electrically connected to the second sweep drive circuit are different, corresponding to the first light-emitting device and the second light-emitting device. This is beneficial for correspondingly setting the number of sweep control signal lines required by the first sweep drive circuit and the number of sweep control signal lines required by the second sweep drive circuit according to the difference in the light-emitting duration of the first light-emitting device and the second light-emitting device. Setting N≠M according to actual light-emitting needs is beneficial for reducing the redundancy of the sweep control signal lines, thereby improving the utilization efficiency of a single sweep control signal line, reducing the power consumption and number of wiring of the display panel, and reducing the number of signal ports required to be set in the display panel corresponding to the sweep control signal lines, thereby reducing the manufacturing cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0013] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0014] Figure 3 This is a working timing diagram of a pixel circuit provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of a first shift register unit provided in an embodiment of the present application;

[0016] Figure 5 A timing diagram of a related technology provided in an embodiment of the present application;

[0017] Figure 6 A working timing diagram provided for an embodiment of the present application;

[0018] Figure 7 A working timing diagram of a first shift register unit provided in an embodiment of the present application;

[0019] Figure 8 A schematic plan view of another display panel provided in an embodiment of the present application;

[0020] Figure 9 A schematic plan view of another display panel provided in an embodiment of the present application;

[0021] Figure 10 A schematic plan view of another display panel provided in an embodiment of the present application;

[0022] Figure 11 A schematic plan view of another display panel provided in an embodiment of the present application;

[0023] Figure 12 A schematic diagram of a second shift register unit provided in an embodiment of the present application;

[0024] Figure 13 This is a working timing diagram of another pixel circuit provided in an embodiment of the present application;

[0025] Figure 14 A timing diagram of the operation of a second shift register unit provided in an embodiment of the present application;

[0026] Figure 15 A schematic plan view of another display panel provided in an embodiment of the present application;

[0027] Figure 16 A schematic plan view of another display panel provided in an embodiment of the present application;

[0028] Figure 17 A timing diagram of another display panel operation provided by an embodiment of the present application;

[0029] Figure 18 A timing diagram of another display panel operation provided by an embodiment of the present application;

[0030] Figure 19 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0032] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a," "an," and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0034] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0035] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0036] It should be understood that although the terms "first", "second", etc. may be used to describe pixel circuits, light-emitting devices, shift register units, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish pixel circuits, light-emitting devices, shift register units, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first pixel circuit may also be referred to as the second pixel circuit, and similarly, the second pixel circuit may also be referred to as the first pixel circuit. Through careful and in-depth research, the applicant of this case found that when some of the sweep control signal lines used provide a sweep control signal to a shift register unit, there is a long waiting period. The waiting period here can be regarded as the time for the sweep control signal line to transmit a non-ramp signal, which causes some of the sweep control signal lines to be unable to continuously provide ramp signals to different shift register units. The multiple sweep control signal lines in the display panel have a waiting period, which indicates that there is redundancy in the sweep control signal lines prepared in the display panel, which is not conducive to improving the utilization rate of the sweep control signal lines, and is likely to increase the power consumption in the display panel, increasing the operating cost of the display panel. A solution is provided for the problems existing in the prior art.

[0037] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application is shown. Figure 2A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown. Figure 3 This is a working timing diagram of a pixel circuit provided in an embodiment of the present application. Figure 4 A schematic diagram of a first shift register unit provided in an embodiment of the present application.

[0038] The embodiment of the present application provides a display panel 100, such as Figure 1 As shown, the display panel 100 includes a pixel circuit 10, combined with Figure 2 As shown, the pixel circuit 10 includes a pulse width modulation module 101 and a pulse amplitude modulation module 102. The pulse width modulation module 101 receives a sweep signal SWEEP, and the pulse width modulation module 101 controls the duration of the light-emitting driving current L1 generated by the pulse amplitude modulation module 102 based on the sweep signal SWEEP. The sweep signal SWEEP is a ramp signal whose voltage varies with time. Figure 2 As shown, in the pulse width modulation module 101, when the pulse width modulation module 101 receives the sweep signal SWEEP, as the voltage of the sweep signal SWEEP gradually changes, the gate voltage of the first driving transistor T1 gradually changes under the coupling effect of the first capacitor C1. When the gate voltage of the first driving transistor T1 changes to a level that causes the first driving transistor T1 to reach the on state, the first driving transistor T1 turns on and generates current. The output end of the first driving transistor T1 is electrically connected to the gate of the second driving transistor T2 in the pulse amplitude modulation module 102. Optionally, taking the first driving transistor T1 and the second driving transistor T2 as P-type transistors, the second driving transistor T2 can generate a light-emitting driving current L1 when it is turned on. After the first driving transistor T1 is turned on, it transmits current to the gate of the second driving transistor T2, causing the second driving transistor T2 to turn off and stop generating the light-emitting driving current L1. In this way, the pulse width modulation module 101 controls the duration of the light-emitting driving current L1 generated by the pulse amplitude modulation module 102 based on the sweep signal SWEEP.

[0039] Further, if Figure 2 As shown, in the pixel circuit 10, the pulse width modulation module 101 further includes a third transistor T3 to a seventh transistor T7, and the pulse amplitude modulation module 102 includes an eighth transistor T8 to a thirteenth transistor T13 and a second capacitor C2, and the second capacitor C2 is a storage capacitor. Optionally, in the embodiment of the present application, the first transistor T1 to the thirteenth transistor T13 in the pixel circuit 10 are all P-type transistors for illustration. Figure 3 As shown, one working cycle of the pixel circuit 10 includes:

[0040] Reset Phase E1: For the pulse width modulation module 101, the gate of the third transistor T3 receives a valid signal transmitted by the first width control signal PWM-S1, causing the third transistor T3 to turn on and transmit the first width reset voltage PWM-REF to the gate of the first driving transistor T1, resetting the gate of the first driving transistor T1 and ensuring the accuracy of the turn-on time of the second driving transistor T2. For the pulse amplitude modulation module 102, the gate of the eighth transistor T8 receives a valid signal transmitted by the first amplitude control signal PAM-S1, causing the eighth transistor T8 to turn on and transmit the first amplitude reset voltage PAM-REF to the gate of the second driving transistor T2, resetting the gate of the second driving transistor T2 and ensuring the accuracy of the light-emitting driving current L1 generated by the second driving transistor T2.

[0041] In the data writing phase E2, for the pulse width modulation module 101, the gates of the fourth transistor T4 and the fifth transistor T5 both receive a valid signal transmitted by the second width control signal PWM-S2. The fourth transistor T4 turns on and transmits the pulse width data signal PWM-DATA to the gate of the first driving transistor T1. The fifth transistor T5 also turns on and compensates the threshold voltage of the first driving transistor T1 to the gate of the first driving transistor T1. For the pulse amplitude modulation module 102, the gates of the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 all receive a valid signal transmitted by the second amplitude control signal PAM-S2. The ninth transistor T9 turns on and transmits the pulse amplitude data signal PAM-DATA to the gate of the second driving transistor T2. The tenth transistor T10 also turns on and compensates the threshold voltage of the second driving transistor T2 to the gate of the second driving transistor T2. The eleventh transistor T11 turns on and transmits the low-level voltage PVEE to the first electrode 2001 of the light-emitting device 20, thereby resetting the light-emitting device 20.

[0042] During the light-emitting phase E3, the pulse width modulation module 101 receives valid signals transmitted by the pulse width emission signal PWM-EM at the gates of the sixth transistor T6 and the seventh transistor T7, and both the sixth transistor T6 and the seventh transistor T7 are turned on. The sixth transistor T6 is turned on and transmits the pulse width voltage PWM-VDD to the input terminal of the first driver transistor T1. Simultaneously, the pulse width modulation module 101 receives a time-varying sweep signal SWEEP. As the sweep signal SWEEP changes, the gate potential of the first driver transistor T1 changes via the first capacitor C1. In this embodiment of the present application, for example, the sweep signal SWEEP pulls down the gate of the first driver transistor T1 via the coupling of the first capacitor C1. When the gate potential of the first driver transistor T1 changes to a point where the potential difference between the gate of the first driver transistor T1 and the input terminal is less than or equal to the threshold voltage of the first driver transistor T1, the first driver transistor T1 is turned on. Once turned on, the first driver transistor T1 generates current, and the seventh transistor T7 transmits the current generated by the first driver transistor T1 to the gate of the second driver transistor T2. In the pulse amplitude modulation module 102, the twelfth transistor T12 and the thirteenth transistor T13 both receive a valid signal transmitted by the pulse amplitude emission signal PAM-EM, and are turned on. The twelfth transistor T12 turns on and transmits the pulse amplitude voltage PAM-VDD to the input terminal of the second driving transistor T2, driving the second driving transistor T2 to turn on and generate a light-emitting driving current L1. The thirteenth transistor T13 turns on and transmits the light-emitting driving current L1 to the first electrode 2001 of the light-emitting device 20, causing the light-emitting device 2001 to emit light.

[0043] In conjunction with the operation of the pulse width modulation module 101 during the light-emitting stage E3, when the second driving transistor T2 generates the light-emitting driving current L1, the sweep signal SWEEP also changes the gate potential state of the first driving transistor T1 through coupling with the first capacitor C1. When the first driving transistor T1 turns on to generate current, the seventh transistor T7 can transmit the current generated by the first driving transistor T1 to the gate of the second driving transistor T2, thereby controlling the second driving transistor T2 to turn off, and the second driving transistor T2 stops generating the light-emitting driving current L1. Therefore, it can be seen that the duration of the pulse amplitude modulation module 102 generating the light-emitting driving current L1 is the period between the moment the pulse amplitude modulation module 102 begins to receive the pulse amplitude lighting signal PAM-EM and the moment the seventh transistor T7 transmits the current to the gate of the second driving transistor T2.

[0044] It should be noted that if Figure 3As shown, in the embodiment of the present application, in the light-emitting stage E3, the pulse width modulation module 101 optionally starts receiving the pulse width light-emitting signal PWM-EM earlier than the pulse amplitude modulation module 102 starts receiving the pulse amplitude light-emitting signal PAM-EM. Since, when a black grayscale is required, the seventh transistor T7 needs to immediately transmit current to the gate of the second driving transistor T2 upon entering the light-emitting stage E3, so that the second driving transistor T2 does not generate the light-emitting driving current L1. However, it takes a certain amount of time for the seventh transistor T7 to transmit current to the second driving transistor T2. If the pulse width modulation module 101 and the pulse amplitude modulation module 102 receive the corresponding light-emitting signals at the same time, then when the second driving transistor T2 generates the light-emitting driving current L1, the first driving transistor T1 may not be turned on or the seventh transistor T7 may be transmitting current to the gate of the second driving transistor T2, and the second driving transistor T2 may not be turned off immediately. Therefore, setting the time when the pulse width modulation module 101 starts receiving the pulse width light-emitting signal PWM-EM earlier than the time when the pulse amplitude modulation module 102 starts receiving the pulse amplitude light-emitting signal PAM-EM is beneficial for achieving a black grayscale.

[0045] The display panel 100 further includes a light emitting device 20, which is electrically connected to a pulse amplitude modulation module 102. The pulse amplitude modulation module 102 can transmit a light emitting driving current L1 to the light emitting device 20. Figure 1 、 Figure 2 As shown, the light-emitting device 20 includes a first light-emitting device 20A and a second light-emitting device 20B, and the pixel circuit 10 includes a first pixel circuit 10A and a second pixel circuit 10B. The first pixel circuit 10A is electrically connected to the first light-emitting device 20A, and the second pixel circuit 10B is electrically connected to the second light-emitting device 20B. In the embodiment of the present application, the first light-emitting device 20A and the second light-emitting device 20B are taken as two light-emitting devices 20 with different light-emitting durations at least at the maximum grayscale. In addition, the circuit structures of the first pixel circuit 10A and the second pixel circuit 10B can refer to Figure 2 The structure of the pixel circuit 10 is shown.

[0046] The display panel 100 further includes a driving control circuit 30, which may include a circuit for transmitting a gate control signal to the pixel circuit 10. For example, the driving control circuit 30 includes a circuit for transmitting a first width control signal PWM-S1, a first amplitude control signal PAM-S1, etc. Figure 1As shown, the driving control circuit 30 includes a sweep frequency driving circuit 30A, which provides a sweep frequency signal SWEEP to the pixel circuit 10. The sweep frequency driving circuit 30A includes a plurality of first shift register units VSR1, and the output ends of the plurality of first shift register units VSR1 can output the sweep frequency signal SWEEP to provide to the pixel circuits 10 in different rows.

[0047] Combine Figure 1 、 Figure 4 As shown, the first shift register unit VSR1 includes a first driving module 401 and a first gating module 402. A control terminal of the first gating module 402 is connected to the output terminal of the first driving module 401. Optionally, the first gating module 402 can choose to output a constant potential signal or a sweep signal SWEEP. The signal output from the first driving module 401 to the first gating module 402 can be used to control whether the first gating module 402 outputs the sweep signal SWEEP. The first gating module 402 is electrically connected to the sweep control signal line L-SWEEP. The sweep control signal line L-SWEEP can transmit the sweep control signal SWEEP-IN to the first gating module 402. Optionally, as shown in FIG. Figure 3 As shown in the timing diagram shown, the sweep control signal line L-SWEEP can continuously transmit a periodic sweep control signal SWEEP-IN, and both the sweep control signal SWEEP-IN and the sweep signal SWEEP include a ramp signal. Here, the pulse width of the sweep control signal SWEEP-IN in one cycle provided by the sweep control signal line L-SWEEP is equal to the pulse width of the sweep signal SWEEP that the pixel circuit 10 needs to receive. The first gating module 402 outputs the sweep signal SWEEP based on the sweep control signal SWEEP-IN and the signal output by the first driving module 401. When the first gating module 402 is controlled by the first driving module 401 to output the sweep signal SWEEP, the first gating module 402 outputs the sweep control signal SWEEP-IN transmitted by the sweep control signal line L-SWEEP in the current period as the sweep signal SWEEP.

[0048] Continue to refer Figure 1As shown, the swept-frequency driving circuit 30A includes a first swept-frequency driving circuit 30A1 and a second swept-frequency driving circuit 30A2. The first swept-frequency driving circuit 30A1 provides a first swept-frequency signal SWEEP1 to the first pixel circuit 10A, and the second swept-frequency driving circuit 30A2 provides a second swept-frequency signal SWEEP2 to the second pixel circuit 10B. Generally, different swept-frequency signals SWEEP can control the pixel circuit 10 to generate a light-emitting driving current L1 for different durations. The first pixel circuit 10A can adjust the duration of the light-emitting device 20A receiving the light-emitting driving current L1 based on the received first swept-frequency signal SWEEP1, and the second pixel circuit 10B can adjust the duration of the light-emitting device 20B receiving the light-emitting driving current L1 based on the received second swept-frequency signal SWEEP2.

[0049] In the embodiment of the present application, the first sweep-frequency driving circuit 30A1 is electrically connected to N sweep-frequency control signal lines L-SWEEP, and the second sweep-frequency driving circuit 30A2 is electrically connected to M sweep-frequency control signal lines L-SWEEP; N ≠ M. That is, for the first light-emitting device 20A and the second light-emitting device 20B having different light-emitting durations, the corresponding sweep-frequency driving circuits 30A are electrically connected to different numbers of sweep-frequency control signal lines L-SWEEP.

[0050] The sweep drive circuit 30A includes multiple first shift register units VSR1. The first selection module 402 of each first shift register unit VSR1 is electrically connected to a sweep control signal line L-SWEEP. The output of each first shift register unit VSR1 is electrically connected to multiple pixel circuits 10 located in the same row of pixel circuits 10. In other words, the same sweep signal SWEEP is provided to the multiple pixel circuits 10 in the same row of pixel circuits. Typically, the pixel circuits 10 in the same row of pixel circuits driving the same color light-emitting devices 20 are electrically connected to the output of the same first shift register unit VSR1. In a frame of the display panel 100, the multiple rows of pixel circuits are refreshed row by row. During the process of the sweep frequency driving circuit 30A outputting the sweep frequency signal SWEEP to multiple rows of pixel circuits, the first shift register unit VSR1 electrically connected to a row of pixel circuits outputs the sweep frequency signal SWEEP to the pixel circuits 10. The multiple pulse width modulation modules 101 in the pixel circuits in the row are in the stage of receiving the sweep frequency signal SWEEP. At this time, the sweep frequency signal SWEEP is provided by the sweep frequency control signal line L-SWEEP electrically connected to the first selection module 302 of the first shift register unit VSR1. While the multiple pulse width modulation modules 101 in the pixel circuits in the row are still in the stage of receiving the sweep frequency signal SWEEP, the first selection module 402 of the first shift register unit VSR1 electrically connected to the pixel circuits in the row remains on. At least until the sweep signal SWEEP provided to the row of pixel circuits reaches a specified duration, the first gating module 402 of the first shift register unit VSR1 electrically connected to the pixel circuits in that row is turned off, and the first gating modules 402 of the first shift register units VSR1 electrically connected to the pixel circuits in other rows are turned on. Only then can the sweep control signal line L-SWEEP provide the sweep control signal SWEEP-IN to the first shift register units VSR1 electrically connected to the pixel circuits in other rows. In the above process, one sweep control signal line L-SWEEP can only provide the sweep control signal SWEEP-IN to one first shift register unit VSR1 at a time. For example, the time for scanning a row of pixel circuits is H, and the duration of light emission of the light-emitting device 20 is e*H, where e is an integer greater than or equal to 0. Then, the pulse width of the sweep signal SWEEP received by a row of pixel circuits is at least e*H. However, if e>1, when the pixel circuits in the previous row are still in the light-emitting stage E3, the pixel circuits in the next row also need to enter the light-emitting stage E3. At this time, the sweep control signal line L-SWEEP electrically connected to the pixel circuits in the previous row is still providing the sweep control signal SWEEP-IN to the first shift register unit VSR1 of the previous row, and cannot simultaneously provide the complete sweep control signal SWEEP-IN to the first shift register unit VSR1 of the next row.Therefore, using only one sweep control signal line L-SWEEP in the same sweep drive circuit 30A cannot simultaneously provide the sweep control signal SWEEP-IN to the first shift register units VSR1 in multiple rows. Therefore, multiple sweep control signal lines L-SWEEP are typically used in the same sweep drive circuit 30A to ensure that when multiple first shift register units VSR1 are cascaded, there is always one sweep control signal line L-SWEEP providing the sweep control signal SWEEP-IN to only one first shift register unit VSR1.

[0051] Therefore, when setting up several sweep control signal lines L-SWEEP electrically connected in a sweep drive circuit 30A, based on the light-emitting duration required by the light-emitting devices 20 electrically connected to the pixel circuit 10, if the light-emitting duration of the light-emitting devices 20 in the same row is e*H, then the pulse width of the sweep signal SWEEP received by the pixel circuit 10 is at least e*H, and the period of the sweep control signal SWEEP-IN transmitted by the sweep control signal line L-SWEEP is at least e*H. Accordingly, when a sweep drive circuit 30A transmits a complete sweep control signal SWEEP-IN to a first shift register unit VSR1, at least the scanning time of e rows of pixel circuits will pass, and therefore at least e sweep control signal lines L-SWEEP electrically connected in a sweep drive circuit 30A are required.

[0052] In related art, a display panel typically includes red, green, and blue light-emitting devices. Within a row of pixel circuits, multiple pixel circuits electrically connected to the red light-emitting devices are electrically connected to the same first shift register unit that outputs a sweep signal; multiple pixel circuits electrically connected to the green light-emitting devices are electrically connected to the same first shift register unit that outputs a sweep signal; and multiple pixel circuits electrically connected to the blue light-emitting devices are electrically connected to the same first shift register unit that outputs a sweep signal. Generally, red light-emitting devices emit greater brightness, so the required duration of illumination for these devices is longer. Accordingly, the pulse width of the sweep signal output by the first shift register unit electrically connected to the pixel circuits corresponding to the red light-emitting devices is the largest. Consequently, the sweep drive circuit, where the first shift register unit electrically connected to the pixel circuits driving the red light-emitting devices resides, requires the largest number of sweep control signal lines, for example, N. Green and blue light-emitting devices emit lower brightness, and their corresponding durations of illumination are shorter than those for the red light-emitting devices. However, the number of sweep control signal lines L-SWEEP required for the pixel circuit that drives the green light emitting device and the blue light emitting device and is electrically connected to the sweep driving circuit where the first shift register unit is located is also set to N.

[0053] Figure 5 A timing diagram in a related technology provided in an embodiment of the present application.

[0054] In view of the above analysis, the number of sweep control signal lines L-SWEEP required by the sweep drive circuit where the first shift register unit electrically connected to the pixel circuit driving the green light emitting device or the blue light emitting device is located can be less. However, in the related art, the number of sweep control signal lines L-SWEEP used in the sweep drive circuit corresponding to the light emitting devices of different colors is equal. Figure 5 As shown, taking the example of a pixel circuit electrically connected to a red light-emitting device requiring a sweep signal of SWEEP-R with a pulse width of N*H, a pixel circuit electrically connected to a green light-emitting device requiring a sweep signal of SWEEP-G with a pulse width of M*H, and a pixel circuit electrically connected to a blue light-emitting device requiring a sweep signal of SWEEP-B with a pulse width of Z*H, N*H is typically larger, and N*H ≠ M*H ≠ Z*H. To match the number of sweep control signal lines, the sweep control signal line electrically connected to the first shift register unit driving the pixel circuits of the green and blue light-emitting devices transmits a period equal to that of the sweep control signal line corresponding to the red light-emitting device, at least N*H. However, the effective ramp signal pulse width within the pulse width of the sweep control signal transmitted by the first shift register unit electrically connected to the pixel circuits driving the green and blue light-emitting devices is less than N*H. Figure 5 EM-IN-R is the sweep control signal received by the first shift register unit connected to the pixel driving the red light-emitting device, EM-IN-G is the sweep control signal received by the first shift register unit connected to the pixel driving the green light-emitting device, and EM-IN-B is the sweep control signal received by the first shift register unit connected to the pixel driving the blue light-emitting device. It can be seen that within a cycle, the sweep control signals corresponding to the green and blue light-emitting devices transmit a relatively long period of constant signal within a period N*H. This constant signal can be considered an ineffective signal for adjusting the gate potential of the first driver transistor T1. For the green light-emitting device, only the M*H period of the sweep control signal cycle transmits a useful ramp signal, while for the blue light-emitting device, only the Z*H period of the sweep control signal cycle transmits a useful ramp signal. The idle period of the sweep control signal corresponds to the waiting period of the sweep control signal line. After completing the transmission of a valid ramp signal, a valid ramp signal cannot be directly transmitted to another first shift register unit, resulting in redundancy of the sweep control signal line. Furthermore, the larger number of frequency sweep control signal lines increases the number of signal transmission terminals and wiring lines required in the display panel, which is not conducive to reducing the power consumption of the display panel, improving the wiring efficiency in the display panel, and reducing the manufacturing cost.

[0055] Therefore, in the embodiment of the present application, the number of sweep control signal lines L-SWEEP electrically connected to the first sweep drive circuit 30A1 and the number of sweep control signal lines L-SWEEP electrically connected to the second sweep drive circuit 30A2 are different, corresponding to the first light-emitting device 20A and the second light-emitting device 20B. This is beneficial for correspondingly setting the number of sweep control signal lines L-SWEEP required by the first sweep drive circuit 30A1 and the number of sweep control signal lines L-SWEEP required by the second sweep drive circuit 30A2 according to the difference in the light-emitting duration of the first light-emitting device 20A and the second light-emitting device 20B. Setting N≠M according to actual light-emitting needs is beneficial for reducing the redundancy of the sweep control signal lines L-SWEEP, thereby improving the utilization efficiency of a single sweep control signal line L-SWEEP, reducing the power consumption and number of wiring of the display panel 100, and reducing the number of signal ports required to be set in the display panel 100 corresponding to the sweep control signal lines L-SWEEP, thereby reducing the manufacturing cost of the display panel 100.

[0056] Figure 6 A working timing diagram provided for an embodiment of the present application.

[0057] In one embodiment of the present application, Figure 6 As shown, the pulse width of the first sweep signal SWEEP1 received by the first pixel circuit 10A is different from the pulse width of the second sweep signal SWEEP2 received by the second pixel circuit 10B. This facilitates achieving different light-emitting durations for the first light-emitting device 20A and the second light-emitting device 20B, and facilitates more accurately achieving the light-emitting brightness of the first light-emitting device 20A and the second light-emitting device 20B. Accordingly, the pulse width of the sweep control signal SWEEP-IN transmitted by the sweep control signal line L-SWEEP in the first sweep drive circuit 30A1 within one cycle can be set to be equal to the pulse width of the first sweep signal SWEEP1. Furthermore, the pulse width of the sweep control signal SWEEP-IN transmitted by the sweep control signal line L-SWEEP in the second sweep drive circuit 30A2 within one cycle can be set to be equal to the pulse width of the second sweep signal SWEEP2. As can be seen from the above embodiments, the number of sweep control signal lines L-SWEEP in the sweep drive circuit 30A can be set with reference to the pulse width of the sweep control signal SWEEP-IN transmitted by the sweep control signal lines L-SWEEP within one cycle. Therefore, the number of sweep control signal lines L-SWEEP in the first sweep drive circuit 30A1 is set to N, and the corresponding pulse width of the sweep control signal SWEEP-IN within one cycle is N*H. The number of sweep control signal lines L-SWEEP in the second sweep drive circuit 30A2 is set to M, and the corresponding pulse width of the sweep control signal SWEEP-IN within one cycle is M*H.

[0058] In one embodiment of the present application, the wavelength of light emitted by the first light emitting device 20A is greater than the wavelength of light emitted by the second light emitting device 20B. This can be understood as the brightness of light emitted by the first light emitting device 20A being greater than the brightness of light emitted by the second light emitting device 20B. In a pixel circuit including a pulse width modulation module 101 and a pulse amplitude modulation module 102, the pulse amplitude modulation module 102 generates a light emitting drive current L1 to drive the light emitting device 20 to emit light, and the pulse width modulation module 101 controls the duration of the light emitting drive current L1 generated by the pulse amplitude modulation module 102 to control the duration of light emission of the light emitting device 20, thereby jointly regulating the brightness of the light emitting device 20. The longer the light emission duration, the higher the brightness of the light emitting device 20. Then, continue to refer to Figure 6 As shown, the light-emitting wavelength of the first light-emitting device 20A is greater than the light-emitting wavelength of the second light-emitting device 20B, which means that the pulse width of the first sweep signal SWEEP1 is greater than the pulse width of the second sweep signal SWEEP2, which is beneficial to extend the light-emitting time of the first light-emitting device 20A and achieve high brightness of the first light-emitting device 20A.

[0059] In the embodiment of the present application, N>M is set, that is, the number of sweep control signal lines L-SWEEP electrically connected in the first sweep drive circuit 30A1 is greater than the number of sweep control signal lines L-SWEEP electrically connected in the second sweep drive circuit 30A2. This facilitates the coordinated operation of the N sweep control signal lines L-SWEEP in the first sweep drive circuit 30A1, allowing one sweep control signal line L-SWEEP to output the sweep control signal SWEEP-IN to one first shift register unit VSR1 for a longer period of time, thereby achieving a larger pulse width of the first sweep signal SWEEP1. Moreover, it is beneficial to realize the coordinated action of the M sweep control signal lines L-SWEEP in the second sweep drive circuit 30A2. Since the time for one sweep control signal line L-SWEEP to output the sweep control signal SWEEP-IN for one shift register unit VSR1 is relatively short, after the sweep control signal line L-SWEEP completes transmitting the sweep control signal SWEEP-IN for one shift register unit VSR1, it immediately transmits the sweep control signal SWEEP-IN to another first shift register unit VSR1, so that it can be electrically connected to a larger number of first shift register units VSR1, thereby improving the utilization efficiency of one sweep control signal line L-SWEEP in the second sweep drive circuit 30A2.

[0060] In one embodiment of the present application, Figure 1 、 Figure 4As shown, in the first sweep frequency driving circuit 30A1, the input end of the driving module 101 in the first stage first shift register unit VSR1 (1) receives the first start signal STV1; in the second sweep frequency driving circuit 30A2, the input end of the driving module 101 in the first stage first shift register unit VSR1 (1) receives the second start signal STV2. It should be noted that the first start signal STV1 is Figure 4 The first shift register unit VSR1 shown in FIG3 is regarded as the first shift register unit VSR1 in the first sweep frequency driving circuit 30A1. Similarly, the other start signals STV mentioned below are also start signals received by the corresponding driving circuits. The first start signal STV1 is the start signal for the multiple first shift register units VSR in the first sweep frequency driving circuit 30A1 to start cascading and outputting the sweep frequency signal SWEEP. The second start signal STV2 is the start signal for the multiple first shift register units VSR in the second sweep frequency driving circuit 30A2 to start cascading and outputting the sweep frequency signal SWEEP.

[0061] For example, the sweep frequency driving circuit 30A provided in the embodiment of the present application can refer to Figure 4The circuit shown. In the sweep frequency driving circuit 30A, the first shift register unit VSR1 includes a first driving module 401 and a first selection module 402, and the first driving module 401 includes an input terminal IN and an output terminal OUT. Take the forward cascade of multiple first shift register units VSR1 in the sweep frequency driving circuit 30A as an example. After the input terminal IN of the first driving module 401 of the first-stage shift register unit VSR1 (1) receives the start signal STV, the multiple first shift register units VSR1 start to cascade. After the cascade, the input terminal IN of the first driving module 401 of the remaining first shift register units VSR1 (1) is connected to the output terminal OUT of the first driving module 401 in the first shift register unit VSR1 of the previous stage. It should be noted that the first driving module 401 is any circuit structure that can realize signal shifting. The first driver module 401 includes transistors M1 and M2. The control terminal of transistor M1 is connected to a first node Q1, and the control terminal of transistor M2 is connected to a second node Q2. Under the control of the potential of the first node Q1, transistor M1 provides a first voltage signal VGH to the output terminal OUT of the first driver module 401. Under the control of the potential of the second node Q2, transistor M2 provides a second voltage signal VGL to the output terminal OUT of the first driver module 401. The first selection module 402 includes transistors M3 and M4. The control terminal of transistor M3 is connected to the output terminal OUT of the first driver module 401, and the control terminal of transistor M4 is connected to the first node Q1. The first terminal of transistor M3 receives the sweep control signal SWEEP-IN, and the first terminal of transistor M4 receives the third voltage signal sweep-V0. The third voltage signal sweep-V0 can be considered as the constant potential signal described above, that is, a signal equal to the starting potential of the sweep signal SWEEP. When the pixel circuit 10 begins to receive the sweep signal SWEEP, the potential of the sweep signal SWEEP begins to change from the potential of the third voltage signal sweep-V0. The second end of transistor M3 and the second end of transistor M4 are connected to the output end of the first selection module 402. When the pixel circuit 10 enters the light emitting stage E3, the transistor M3 in the first selection module 402 is turned on, and the sweep driving circuit 30A starts to output the sweep signal SWEEP.

[0062] Optional, such as Figure 4As shown, the first driver module 401 also includes transistors M5 to M18, which are not described one by one. The first driver module 401 also includes four capacitors, namely a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The first node Q1, the second node Q2, the third node Q3, and the fourth node Q4, as well as the fifth node Q5 to the eighth node Q8 in the driver module 401 are marked. The operation of the driver module 401 requires a reset signal RST, a first clock signal CK, a second clock signal XCK, a first voltage signal VGH, and a second voltage signal VGL. The first voltage signal VGH is a high-level voltage, and the second voltage signal VGL is a low-level voltage.

[0063] The first gating module 402 also includes a transistor M19 and a seventh capacitor C7. The control terminal of the first gating module 402 is connected to the driver module 401. The control terminal of the transistor M3 is connected to the output terminal OUT of the first driver module 401 via the transistor M19. The control terminal of the transistor M4 is connected to the first node Q1. During the process in which the first driver module 401 selectively controls the transistor M3 or the transistor M4 of the first gating module 402 to turn on: when the second node Q2 is at a low potential and the first node Q1 is at a high potential, the transistor M2 of the first driver module 401 is turned on and the transistor M1 is turned off, and the output terminal OUT of the first driver module 401 outputs the second voltage signal VGL. This causes the transistor M3 in the first gating module 402 to turn on and the transistor M4 to turn off. The first gating module 402 then outputs the sweep control signal SWEEP-IN transmitted by the sweep control signal line L-SWEEP during the current period as the sweep signal SWEEP. The output terminal OUT of the first driving module 401 outputs a low-level signal of the second voltage signal VGL; when the first node Q1 is at a low potential and the second node Q2 is at a high potential, the transistor M2 of the driving module 401 is turned off and the transistor M1 is turned on, the output terminal OUT of the first driving module 401 outputs the first voltage signal VGH, the transistor M3 in the first selection module 402 is turned off and the transistor M4 is turned on, and the first selection module 402 outputs the third voltage signal sweep-V0. At this time, the signal potential received by the access terminal of the sweep signal SWEEP of the pixel circuit 10 will not change, and the first capacitor C1 in the pixel circuit 10 will not be coupled to cause the gate potential of the first driving transistor T1 to change.

[0064] Figure 7 This is a working timing diagram of a first shift register unit provided in an embodiment of the present application.

[0065] Combine Figure 4 、 Figure 7As shown, the first driver module 401 is started after the input terminal IN receives the start signal STV or the output signal of the output terminal OUT of the previous driver module 401. In the embodiment of the present application, the transistors in the sweep frequency driving circuit 30A are all P-type transistors. After the input terminal IN of the first driver module 401 outputs a low-level signal, the second node Q2 of the first driver module 401 can be at a low potential, causing the first gating module 402 to output the sweep frequency signal SWEEP. When the input terminal IN of the first driver module 401 outputs a high-level signal, the second node Q2 of the first driver module 401 is also at a high potential, and the first gating module 402 stops outputting the sweep frequency signal SWEEP. Therefore, if the first gating module 402 is required to continuously output the sweep frequency signal SWEEP for a period of time, it is also necessary for the input terminal IN of the first driver module 401 to continuously output a low-level signal for a period of time. Therefore, the pulse width of the sweep frequency signal SWEEP output by the first gating module 402 is also related to the duration of the low level of the start signal STV. For example, if the pulse width of the first sweep signal SWEEP1 that the first pixel circuit 10 needs to receive is N*H, then the width of the low-level signal output in the first start signal STV1 received by the first shift register unit VSR1 in the first sweep driving circuit 30A1 needs to be at least equal to N*H.

[0066] The pulse width of the first start signal STV1 is set to be greater than or equal to the pulse width of the first sweep signal SWEEP1, and the pulse width of the second start signal STV2 is set to be greater than or equal to the pulse width of the second sweep signal SWEEP2. It should be noted that the pulse width of the first start signal STV1 mentioned in the present application is the width of the signal transmitted by the first start signal STV1 that enables the gating module 102 to output the sweep signal SWEEP, and in the technical solution of the present application, it refers to the pulse width when the first start signal STV1 outputs a low-level signal. Similarly, the pulse width of the second start signal STV2 mentioned in the present application is the width of the signal transmitted by the second start signal STV2 that enables the gating module 102 to output the sweep signal SWEEP, and in the technical solution of the present application, it refers to the pulse width when the second start signal STV2 outputs a low-level signal.

[0067] In the embodiment of the present application, the pulse width of the first start signal STV1 is set to be greater than or equal to the pulse width of the first sweep signal SWEEP1, and the pulse width of the second start signal STV2 is set to be greater than or equal to the pulse width of the second sweep signal SWEEP2. This helps ensure the accuracy of the pulse width of the sweep signal SWEEP output by the first sweep drive circuit 30A1 and the second sweep drive circuit 30A2, and avoids the situation where the pulse width of the sweep signal SWEEP is insufficient, causing the first drive transistor T1 of the pulse width modulation module 101 to fail to turn on on time, thereby ensuring the accuracy of the light-emitting time of the light-emitting device 20. Accordingly, if the pulse width of the first sweep signal SWEEP is N*H, the pulse width of the first start signal STV1 can be set to N*H. If the pulse width of the second sweep signal SWEEP is M*H, the pulse width of the second start signal STV2 can also be set to M*H.

[0068] In one embodiment of the present application, continue to combine Figure 1 、 Figure 4 As shown, the output terminal OUT of the driving module 401 in the i-th first shift register unit VSR1(i) is connected to the input terminal IN of the first driving module 401 in the i+1-th first shift register unit VSR1(i+1), where i is an integer. This allows for cascading of multiple first shift register units VSR, and helps ensure uniformity in the sweep signal SWEEP output by the multiple stages of first shift register units VSR1.

[0069] Figure 8 A schematic plan view of another display panel provided in an embodiment of the present application.

[0070] In one embodiment of the present application, Figure 8 As shown, the sweep frequency driving circuit 30A includes P cascaded first shift register units VSR1.

[0071] N sweep control signal lines L-SWEEP are electrically connected in the first sweep drive circuit 301. Each of the multiple cascaded first shift register units VSR1 in the first sweep drive circuit 30A1 is electrically connected to only one of the N sweep control signal lines L-SWEEP. Typically, the display panel 100 has a large number of pixel rows, and accordingly, a large number of first shift register units VSR1 electrically connected to the pixel rows. When a smaller number of sweep control signal lines L-SWEEP are used to achieve electrical connection with a larger number of first shift register units VSR1, the sweep control signal line L-SWEEP electrically connected to the x-th first shift register unit VSR1(x) in the first sweep drive circuit 30A1 is also electrically connected to the N+x-th first shift register unit VSR1(N+x), where 1≤x≤PN. Since the pulse width of the first sweep signal SWEEP1 is N*H, the period of the sweep control signal SWEEP-IN outputted by a sweep control signal line L-SWEEP to a first shift register unit VSR1 can also be set to N*H. Figure 6 As shown in the signal of the sweep control signal SWEEP-IN, the first selection module 402 of a first shift register unit VSR1 needs to output the sweep control signal SWEEP-IN within a complete cycle as the sweep signal SWEEP. Since the time to scan a row of pixels is H, the time difference between the first shift register unit VSR1 starting to transmit the sweep signal SWEEP step by step is also H. Then, after the selection module 402 of the x-th first shift register unit VSR1(x) is turned on, when the electrically connected sweep control signal line L-SWEEP outputs a signal of N*H duration, the pixel rows electrically connected to the x-th first shift register unit VSR1(x) to the N+x-1-th first shift register unit VSR1(N+x-1) have all output the sweep signal SWEEP. Continuing, the gating module 402 of the N+x-th first shift register unit VSR1(N+x) is turned on, and the gating module 402 of the x-th first shift register unit VSR1(x) is turned off. The sweep control signal line L-SWEEP electrically connected to the x-th first shift register unit VSR1(x) can output a sweep control signal SWEEP-IN of N*H duration to the N+x-th first shift register unit VSR1(N+x). Correspondingly, the sweep control signal line L-SWEEP electrically connected to the PN-th first shift register unit VSR1(PN) can be electrically connected to the P-th first shift register unit VSR1(P) at the same time, which is beneficial for making the multiple sweep control signal lines L-SWEEP more reasonably electrically connected to the multiple first shift register units VSR1.

[0072] Continue to refer Figure 8As shown, in the second frequency sweep driving circuit 30A2, the frequency sweep control signal line L-SWEEP electrically connected to the y-th stage shift register unit VSR1(y) is also electrically connected to the M+y-th stage shift register unit VSR1(M+y), 1≤y≤PM. Similarly, in the second frequency sweep driving circuit 30A2, the frequency sweep control signal line L-SWEEP electrically connected to the y-th stage first shift register unit VSR1(y) is also electrically connected to the M+y-th stage first shift register unit VSR1(M+y), 1≤y≤PM. Since the pulse width of the second frequency sweep signal SWEEP2 is M*H, the period length of the frequency sweep control signal SWEEP-IN output by a frequency sweep control signal line L-SWEEP to a first shift register unit VSR1 can also be set to M*H. Reference Figure 6 As shown in the figure, the first selection module 402 of a first shift register unit VSR1 needs to output the sweep control signal SWEEP-IN within a complete cycle as the sweep signal SWEEP. Since the time required to scan a row of pixels is H, the time difference between the first shift register unit VSR1 starting to transmit the sweep signal SWEEP step by step is also H. Therefore, after the selection module 402 of the y-th first shift register unit VSR1(y) is turned on, when the electrically connected sweep control signal line L-SWEEP outputs a signal with a duration of M*H, the pixel rows electrically connected to the y-th first shift register unit VSR1(y) to the M+y-1-th first shift register unit VSR1(M+y-1) have all output the sweep signal SWEEP. Continuing, the gating module 402 of the M+y-th first shift register unit VSR1(M+y) is turned on, and the gating module 402 of the y-th first shift register unit VSR1(x) is turned off. The sweep control signal line L-SWEEP electrically connected to the y-th first shift register unit VSR1(y) can output a sweep control signal SWEEP-IN of M*H duration to the M+y-th first shift register unit VSR1(M+y). Correspondingly, the sweep control signal line L-SWEEP electrically connected to the PM-th first shift register unit VSR1(PM) can be electrically connected to the P-th first shift register unit VSR1(P) at the same time, which is beneficial for making the multiple sweep control signal lines L-SWEEP more reasonably electrically connected to the multiple first shift register units VSR1.

[0073] Figure 9 A schematic plan view of another display panel provided in an embodiment of the present application.

[0074] In one embodiment of the present application, Figure 9As shown, the light-emitting device 20 further includes a third light-emitting device 20C. At least at the maximum grayscale, the light-emitting duration of the third light-emitting device 20C is different from that of the first light-emitting device 20A and the second light-emitting device 20B. The pixel circuit 10 further includes a third pixel circuit 10C, which is electrically connected to the third light-emitting device 20C. The third sweep drive circuit 30A further includes a third sweep drive circuit 30A3, which provides a third sweep signal SWEEP3 to the third pixel circuit 10C. The third sweep drive circuit 30A3 is electrically connected to Z sweep control signal lines L-SWEEP.

[0075] In combination with the above, it can be seen that when setting the number of sweep control signal lines L-SWEEP electrically connected to the sweep drive circuit 30A3, the number can be set with reference to the required light-emitting duration of the light-emitting device 20. In the embodiment of the present application, setting Z≠N and Z≠M is conducive to further achieving different numbers of sweep control signal lines L-SWEEP electrically connected to the sweep drive circuit 30A where the first shift register unit VSR1 is located and electrically connected to the pixel circuits 10 corresponding to different light-emitting devices 20 in the display panel 100. This is conducive to further reducing the number of sweep control signal lines L-SWEEP in the display panel 100, reducing the number of ports required to output the sweep control signal, improving the routing utilization of the sweep control signal lines L-SWEEP, and reducing the power consumption of the display panel 100.

[0076] In one embodiment of the present application, the wavelength of light emitted by the first light-emitting device 20A is greater than the wavelength of light emitted by the second light-emitting device 20B, and the wavelength of light emitted by the second light-emitting device 20B is greater than the wavelength of light emitted by the third light-emitting device 20C. The brightness of light emitted by the first light-emitting device 20A is greater than the brightness of light emitted by the second light-emitting device 20B, and the brightness of light emitted by the second light-emitting device 20B is greater than the brightness of light emitted by the third light-emitting device 20C. The pulse width of the first sweep signal SWEEP1 is greater than the pulse width of the second sweep signal SWEEP2, and the pulse width of the second sweep signal SWEEP2 is greater than the pulse width of the third sweep signal SWEEP3. This allows, within a single frame of the display panel 100, the light-emitting duration of the first light-emitting device 20A is greater than the light-emitting duration of the second light-emitting device 20B, and greater than the light-emitting duration of the third light-emitting device 20C.

[0077] The number of sweep control signal lines L-SWEEP electrically connected to the third sweep drive circuit 30A3 that provides the third sweep signal SWEEP3 is Z. In the embodiment of the present application, the pulse width of the third sweep signal SWEEP3 is Z*H. Based on the above, it can be concluded that the pulse width N*H of the first sweep signal SWEEP1 is greater than the pulse width M*H of the second sweep signal SWEEP2, and the pulse width Z*H of the third sweep signal SWEEP3. Therefore, the period of the ramp signal in the sweep control signal SWEEP-IN output by the sweep control signal lines L-SWEEP electrically connected to the third sweep drive circuit 30A3 that generates the third sweep signal SWEEP3 is at least Z*H.

[0078] In the embodiment of the present application, N>M>Z is set, and the first sweep frequency driving circuit 30A1, the second sweep frequency driving circuit 30A2, and the third sweep frequency driving circuit 30A3 are set as different circuits. The specific differences are at least reflected in the different electrically connected sweep frequency control signal lines L-SWEEP, and the required number of sweep frequency control signal lines L-SWEEP is set accordingly according to the luminous brightness of different light-emitting devices 20, which is beneficial to reducing the power consumption of the sweep frequency driving circuit 30A and reducing the number of signal terminals required to be occupied by the sweep frequency driving circuit 30A, thereby reducing the preparation cost and power consumption of the display panel 100.

[0079] In one embodiment of the present application, the first light emitting device 20A emits red light, the second light emitting device 20B emits green light, and the third light emitting device 20C emits blue light. Generally, the brightness of a red light emitting device is greater than that of a green light emitting device and a blue light emitting device.

[0080] Figure 10 A schematic plan view of another display panel provided in an embodiment of the present application.

[0081] In one embodiment of the present application, N:M:Z=6:3:2 is set. Based on the luminance trends of the first light-emitting device 20A, the second light-emitting device 20B, and the third light-emitting device 20C, the setting ratio of the sweep control signal line L-SWEEP electrically connected to the first sweep drive circuit 30A1, the second sweep drive circuit 30A2, and the third sweep drive circuit 30A3 is proposed. This is helpful to provide a reference for relevant technical personnel and improve the feasibility of the embodiment of the present application. It should be noted that Figure 10 The start signal of the first-stage first shift register unit VSR1 ( 1 ) in the third sweep frequency driving circuit 30A3 included in the embodiment is STV5 .

[0082] In one embodiment of the present application, continue to refer to Figure 10As shown, N=6 is set, that is, the number of sweep control signal lines L-SWEEP electrically connected in common in the first sweep frequency driving circuit 30A1 is 6, the number of sweep control signal lines L-SWEEP electrically connected in common in the second sweep frequency driving circuit 30A2 is 3, and the number of sweep control signal lines L-SWEEP electrically connected in common in the third sweep frequency driving circuit 30A3 is 2. This is conducive to more accurately adjusting the light-emitting duration of different light-emitting devices 20. On the basis of adjusting the duration for the light-emitting device 20 to receive the light-emitting driving current L1, the number of sweep control signal lines L-SWEEP electrically connected in common in the second sweep frequency driving circuit 30A2 and the number of sweep control signal lines L-SWEEP electrically connected in common in the third sweep frequency driving circuit 30A3 corresponding to the green light-emitting devices and the blue light-emitting devices with lower light-emitting brightness is reduced, thereby improving the use efficiency of the sweep control signal lines L-SWEEP, reducing the total number of sweep control signal lines L-SWEEP in the display panel 100, and increasing the available space in the display panel 100.

[0083] Figure 11 A schematic plan view of another display panel provided in an embodiment of the present application is shown. Figure 12 A schematic diagram of a second shift register unit provided in an embodiment of the present application.

[0084] In one embodiment of the present application, Figure 11 As shown, the driving control circuit 30 also includes a light-emitting driving circuit 30B, which provides a light-emitting signal PAM-EM to the pulse amplitude modulation module 102 of the pixel circuit 10. The light-emitting signal here is the same signal as the pulse amplitude light-emitting signal PAM-EM improved in the above content. The light-emitting signal PAM-EM can control the pulse amplitude modulation module 102 to generate a light-emitting driving current L1. Figure 2 As shown, the twelfth transistor T12 and the thirteenth transistor T13 in the pulse amplitude modulation module 102 in the pixel circuit 10 both receive a valid signal transmitted by the light-emitting signal PAM-EM. The twelfth transistor T12 turns on and transmits the pulse amplitude voltage PAM-VDD to the input terminal of the second driving transistor T2, driving the second driving transistor T2 to turn on and generate a light-emitting driving current L1. The thirteenth transistor T13 turns on and transmits the light-emitting driving current L1 to the first electrode 2001 of the light-emitting device 20, causing the light-emitting device 20 to emit light.

[0085] Combine Figure 12As shown, the light-emitting driver circuit 30B includes a plurality of second shift register units VSR2. The second shift register unit VSR2 includes a second driver module 501 and a second selection module 502. A control terminal of the second selection module 502 is connected to the output terminal of the second driver module 501. The second selection module 502 is electrically connected to a light-emitting control signal line L-EM, which transmits a light-emitting control signal EM-IN. The second selection module 502 outputs a light-emitting signal PAM-EM based on the light-emitting control signal EM-IN and the signal output by the second driver module 501. For example, if all transistors in the pixel circuit 10 are P-type transistors, then the valid signal received by the gate of the twelfth transistor T12 and the thirteenth transistor T13, i.e., the signal that turns them on, is a low-level signal. Therefore, the valid signal in the light-emitting signal PAM-EM output by the light-emitting driver circuit 30B is a low-level signal. The second gating module 502 can selectively output a first level signal VGH or a second level signal VGL. When the second driving module 501 controls the second gating module 502 to output the second level signal VGL, the pulse amplitude modulation module 102 starts to generate a light-emitting driving current.

[0086] Continue to refer Figure 11 As shown, the light-emitting driving circuit 30B includes a first light-emitting driving circuit 30B1 and a second light-emitting driving circuit 30B2. The first light-emitting driving circuit 30B1 provides a first light-emitting signal PAM-EM1 to the first pixel circuit 10A, and the second light-emitting driving circuit 30B2 provides a second light-emitting signal PAM-EM2 to the second pixel circuit 10B.

[0087] The first light-emitting driving circuit 30B1 is electrically connected to R light-emitting control signal lines L-EM, and the second light-emitting driving circuit 30B2 is electrically connected to Q light-emitting control signal lines L-EM. R≠Q. That is, for the first light-emitting device 20A and the second light-emitting device 20B having different light-emitting durations, the corresponding light-emitting driving circuits 30B are electrically connected to different numbers of light-emitting control signal lines L-EM.

[0088] In the related art, the light-emitting drive circuit 30B electrically connected to the pixel circuits driving different light-emitting devices typically has the same circuit structure, at least in that the number of electrically connected light-emitting control signal lines is equal. Furthermore, the number of light-emitting control signal lines electrically connected in the light-emitting drive circuit is set based on the maximum number of required lines. This can lead to the light-emitting devices with shorter light-emitting phases having more light-emitting control signal lines in the light-emitting drive circuit than required. Consequently, during a cycle, the light-emitting control signal lines corresponding to the light-emitting devices with shorter light-emitting phases will transmit invalid signals for a longer period of time, meaning that each light-emitting control signal line has a certain waiting period. This results in redundancy in the light-emitting control signal lines, increases the number of light-emitting control signal lines in the display panel, and increases the power consumption of the display panel.

[0089] Therefore, in the embodiment of the present application, the number of light-emitting control signal lines L-EM electrically connected to the first light-emitting device 20A and the second light-emitting device 20B is different, and the number of frequency-sweeping control signal lines L-EM electrically connected to the second light-emitting drive circuit 30B2 is different. This is beneficial for correspondingly setting the number of light-emitting control signal lines L-EM required by the first light-emitting drive circuit 30B1 and the number of light-emitting control signal lines L-EM required by the second light-emitting drive circuit 30B2 according to the difference in the duration of the first light-emitting device 20A and the second light-emitting device 20B in the light-emitting stage E3. Setting R≠Q according to actual light-emitting needs is beneficial for reducing the redundancy of the light-emitting control signal lines L-EM, thereby improving the utilization efficiency of each light-emitting control signal line L-EM, reducing the power consumption and number of wiring of the display panel 100, and reducing the number of signal ports required to be provided in the display panel 100 corresponding to the light-emitting control signal lines L-EM, thereby reducing the manufacturing cost of the display panel 100.

[0090] Figure 13 This is another operating timing diagram of a pixel circuit provided in an embodiment of the present application.

[0091] In one embodiment of the present application, Figure 13As shown, the pulse width of the first light-emitting signal PAM-EM1 received by the first pixel circuit 10A is different from the pulse width of the second light-emitting signal PAM-EM2 received by the second pixel circuit 10B. This facilitates achieving the required different light-emitting phase E3 durations for the first light-emitting device 20A and the second light-emitting device 20B, and facilitates more accurately achieving the light-emitting brightness of the first light-emitting device 20A and the second light-emitting device 20B. It should be noted that the pulse width of the first light-emitting signal PAM-EM1 described in the embodiments of the present application refers to the pulse width when the first light-emitting signal PAM-EM1 transmits a valid signal, that is, a low-level signal. The pulse width of the second light-emitting signal PAM-EM2 refers to the pulse width when the second light-emitting signal PAM-EM2 transmits a valid signal, that is, a low-level signal.

[0092] In one embodiment of the present application, the wavelength of light emitted by the first light-emitting device 20A is greater than the wavelength of light emitted by the second light-emitting device 20B. This means that the brightness of the first light-emitting device 20A is greater than that of the second light-emitting device 20B. In the pixel circuit 10 comprising a pulse width modulation module 101 and a pulse amplitude modulation module 102, the pulse amplitude modulation module 102 generates a light-emitting drive current L1 to drive the light-emitting device 20 to emit light. The duration for which the pulse amplitude modulation module 102 provides the light-emitting drive current L1 to the light-emitting device 20 is related to the brightness of the light-emitting device 20. The longer the light-emitting duration, the higher the brightness of the light-emitting device 20. Therefore, in this embodiment of the present application, setting the pulse width of the first light-emitting signal PAM-EM1 to be greater than the pulse width of the second light-emitting signal PAM-EM2 facilitates achieving a longer light-emitting duration for the light-emitting device E3 in the first light-emitting device 20, thereby achieving high brightness for the first light-emitting device 20A. Furthermore, X>Q is set, that is, the number of light-emitting signal lines L-EM electrically connected in common in the first light-emitting driver circuit 30B1 is greater than the number of light-emitting control signal lines L-EM electrically connected in common in the second light-emitting driver circuit 30B2. This facilitates the coordinated operation of the X light-emitting control signal lines L-EM in the first light-emitting driver circuit 30A1, allowing one light-emitting control signal line L-EM to output the light-emitting control signal EM-IN to one second shift register unit VSR2 for a longer period of time, thereby achieving a longer pulse width of the first light-emitting signal PAM-EM1. Moreover, it is beneficial to realize the coordinated action of the Q scanning frequency control signal lines L-EM in the second light-emitting driving circuit 30B2. Since the time for one light-emitting control signal line L-EM to output the light-emitting control signal EM-IN for one second shift register unit VSR2 is relatively short, after the light-emitting control signal line L-EM completes transmitting the light-emitting control signal EM-IN for one second shift register unit VSR2, it immediately transmits the light-emitting control signal EM-IN to another second shift register unit VSR2, so that it can be electrically connected to a larger number of second shift register units VSR2, thereby improving the utilization efficiency of one light-emitting control signal line L-EM in the second light-emitting driving circuit 30B2.

[0093] In one embodiment of the present application, Figure 11 、 Figure 12As shown, in the first light-emitting driving circuit 30B1, the input end of the driving module 501 in the first-stage second shift register unit VSR2(1) receives the third start signal STV3; in the second light-emitting driving circuit 30B2, the input end of the driving module 501 in the first-stage second shift register unit VSR2(1) receives the fourth start signal STV4. The third start signal STV3 is a start signal for the multiple second shift register units VSR2 in the first light-emitting driving circuit 30B1 to start cascading and outputting the light-emitting signal PAM-EM, and the fourth start signal STV4 is a start signal for the multiple second shift register units VSR2 in the second light-emitting driving circuit 30B2 to start cascading and outputting the light-emitting signal PAM-EM. It should be noted that the first start signal STV1 is Figure 12 The second shift register unit VSR2 shown in FIG. 1 is regarded as the second shift register unit VSR2 in the light emitting driving circuit 30B1 and receives the start signal STV. Similarly, the other start signals STV mentioned below are also start signals received in the corresponding driving circuits.

[0094] For example, the light-emitting driving circuit 30B provided in the embodiment of the present application can refer to Figure 12The circuit shown. In the light-emitting drive circuit 30B, the second shift register unit VSR2 includes a second drive module 501 and a second selection module 502, and the second drive module 501 includes an input terminal IN and an output terminal OUT. Take the forward cascade of multiple second shift register units VSR2 in the light-emitting drive circuit 30B as an example. After the input terminal IN of the second drive module 501 of the first-stage shift register unit VSR2 (1) receives the start signal STV, multiple second shift register units VSR2 begin to cascade. After the cascade, the input terminal IN of the second drive module 501 in the remaining second shift register units VSR2 is connected to the output terminal OUT of the second drive module 501 in the second shift register unit VSR2 of the previous stage. It should be noted that the second drive module 501 is any circuit structure that can realize signal shifting. The second driver module 501 includes transistors M20 and M21. The control terminal of transistor M20 is connected to the ninth node Q9, and the control terminal of transistor M21 is connected to the tenth node Q10. Under the control of the potential of the ninth node Q9, transistor M20 provides a first voltage signal VGH to the output terminal OUT of the second driver module 501. Under the control of the potential of the tenth node Q10, transistor M21 provides a second voltage signal VGL to the output terminal OUT of the second driver module 501. The second selection module 502 includes transistors M22 and M23. The control terminal of transistor M22 is connected to the output terminal OUT of the second driver module 501, and the control terminal of transistor M23 is connected to the ninth node Q9. The first terminal of transistor M22 receives the light-emission control signal EM-IN, and the first terminal of transistor M23 receives the first voltage signal VGH. The second terminals of transistor M22 and transistor M23 are connected to the output terminal of the second selection module 502. When the pixel circuit 10 enters the light-emission phase E3, transistor M22 in the second selection module 502 turns on, and the light-emission driver circuit 30B begins to output the light-emission signal PAM-EM.

[0095] Optional, such as Figure 12 As shown, the second driver module 501 further includes transistors M24 to M37, which are not described one by one. The second driver module 501 also includes four capacitors, namely a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10. The ninth node Q9 to the sixteenth node Q16 in the second driver module 501 are marked. The operation of the second driver module 501 requires a reset signal RST, a first clock signal CK, a second clock signal XCK, a first voltage signal VGH, and a second voltage signal VGL. The first voltage signal VGH is a high-level voltage, and the second voltage signal VGL is a low-level voltage.

[0096] The second gating module 502 also includes a transistor M38 and an eleventh capacitor C11. The control terminal of the second gating module 502 is connected to the second driver module 501. The control terminal of transistor M22 is connected to the output terminal OUT of the second driver module 501 via transistor M38. The control terminal of transistor M23 is connected to the ninth node Q9. During the process in which the second driver module 501 selectively controls the turning on of transistor M22 or transistor M23 of the second gating module 502: when the tenth node Q10 is at a low potential and the ninth node Q9 is at a high potential, transistor M21 of the second driver module 501 is turned on and transistor M20 is turned off. The output terminal OUT of the second driver module 501 outputs the second voltage signal VGL. This causes transistor M22 in the second gating module 502 to turn on and transistor M23 to turn off. The second gating module 502 then outputs the light-emission control signal EM-IN transmitted by the light-emission control signal line L-EM as the light-emission signal PAM-EM. When the ninth node Q9 is at a low potential and the tenth node Q10 is at a high potential, the transistor M21 of the second driving module 501 is turned off and the transistor M20 is turned on, the output terminal OUT of the second driving module 501 outputs the first voltage signal VGH, the transistor M22 in the second gating module 502 is turned off and the transistor M23 is turned on, and the second gating module 502 outputs the first voltage signal VGH.

[0097] Figure 14 This is a working timing diagram of a second shift register unit provided in an embodiment of the present application.

[0098] Combine Figure 11 、 Figure 12 、 Figure 14As shown, the second driver module 501 is activated after receiving the start signal STV or the output signal from the output terminal OUT of the previous second driver module 501. In the embodiment of the present application, assuming that all transistors in the light-emitting driver circuit 30B are P-type transistors, when the input terminal IN of the second driver module 501 outputs a low-level signal, the tenth node Q10 of the second driver module 501 may be at a low potential, causing the second gating module 502 to output the light-emitting signal PAM-EM. When the input terminal IN of the second driver module 501 outputs a high-level signal, the tenth node Q10 of the second driver module 501 also is at a high potential, and the second gating module 502 stops outputting the light-emitting signal PAM-EM. Therefore, if the second gating module 502 needs to continuously output the light-emitting signal PAM-EM for a period of time, the input terminal IN of the second driver module 501 also needs to continuously output a low-level signal for a period of time. Therefore, the pulse width of the light-emitting signal PAM-EM output by the second gating module 502 is also related to the duration of the low-level state of the start signal STV. For example, if the pulse width of the first light-emitting signal PAM-EM1 that the first pixel circuit 10A needs to receive is R*H, then the width of the low-level signal output in the third start signal STV3 received by the second shift register unit VSR2 in the first light-emitting driving circuit 30B1 needs to be at least equal to R*H.

[0099] The pulse width of the third start signal STV3 is set to be greater than or equal to the pulse width of the first light-emitting signal PAM-EM1, and the pulse width of the fourth start signal STV4 is set to be greater than or equal to the pulse width of the second light-emitting signal PAM-EM2. It should be noted that the pulse width of the third start signal STV3 mentioned in this application is the width of the signal transmitted by the third start signal STV3 that enables the second selection module 502 to output a valid first light-emitting signal PAM-EM1. In the technical solution of this application, it represents the pulse width when the third start signal STV3 outputs a low-level signal. Similarly, the pulse width of the fourth start signal STV4 mentioned in this application is the width of the signal transmitted by the fourth start signal STV4 that enables the second selection module 502 to output a valid second light-emitting signal PAM-EM2. In the technical solution of this application, it represents the pulse width when the fourth start signal STV4 outputs a low-level signal. Setting the pulse width of the third start signal STV3 to be greater than or equal to the pulse width of the first light-emitting signal PAM-EM1, and the pulse width of the fourth start signal STV4 to be greater than or equal to the pulse width of the second light-emitting signal PAM-EM2, helps ensure the accuracy of the pulse widths of the light-emitting signals PAM-EM output by the first light-emitting driver circuit 30B1 and the second light-emitting driver circuit 30B2, thereby ensuring the accuracy of the light-emitting timing of the light-emitting device 20. Accordingly, if the pulse width of the first light-emitting signal PAM-EM1 is R*H, the pulse width of the third start signal STV3 can be set to R*H. If the pulse width of the second light-emitting signal PAM-EM2 is Q*H, the pulse width of the fourth start signal STV4 can also be set to Q*H.

[0100] In one embodiment of the present application, continue to combine Figure 11 、 Figure 12 As shown, the output terminal OUT of the second driver module 501 in the i-th second shift register unit VSR2(i) is connected to the input terminal IN of the second driver module 501 in the i+1-th second shift register unit VSR2(i+1), where i is an integer. This allows for cascading of multiple second shift register units VSR2, and helps ensure uniformity of the luminescence signals PAM-EM output by the multiple stages of second shift register units VSR2.

[0101] Figure 15 A schematic plan view of another display panel provided in an embodiment of the present application.

[0102] In one embodiment of the present application, Figure 15 As shown, the light emitting driving circuit 30B includes P cascaded second shift register units VSR2.

[0103] R light control signal lines L-EM are electrically connected in common in the first light driving circuit 30B1. Each of the multiple cascaded second shift register units VSR2 in the first light driving circuit 30B1 is electrically connected to only one of the R light control signal lines L-EM. Typically, the display panel 100 has a large number of pixel rows, and accordingly, a large number of second shift register units VSR2 are electrically connected to the pixel rows. When a smaller number of light control signal lines L-EM are used to achieve electrical connection with a larger number of second shift register units VSR2, in the first light driving circuit 30B1, the light control signal line L-EQ electrically connected to the a-th second shift register unit VSR2(a) is also electrically connected to the R+a-th second shift register unit VSR2(R+a), where 1≤a≤PR. Since the pulse width of the first light-emitting signal PAM-EM1 is R*H, a light-emitting control signal line L-EM can be configured to output a light-emitting control signal EM-IN with a pulse width of R*H to a second shift register unit VSR2, and then the transistor M22 of the second selection module 502 is turned off. As mentioned in the above embodiment, the time for scanning a row of pixels in the display panel 100 can be set to H. Therefore, the time difference between the second shift register units VSR2 turning on and transmitting the light-emitting signal PAM-EM in each stage is also H. Therefore, after the second selection module 502 of the a-th second shift register unit VSR2(a) is turned on, and the electrically connected light-emitting control signal line L-EM outputs a signal with a duration of R*H, the pixel rows electrically connected to the a-th second shift register unit VSR2(a) through the R+a-1-th second shift register unit VSR2(R+a-1) have all output the light-emitting signal PAM-EM. Continuing, the second selection module 502 of the second shift register unit VSR2(R+a) of the R+a-th stage is turned on, and the second selection module 502 of the second shift register unit VSR2(a) of the a-th stage is turned off. The light-emitting control signal line L-EM electrically connected to the second shift register unit VSR2(a) of the a-th stage can output the light-emitting control signal EM-IN of the R*H duration to the second shift register unit VSR2(R+a) of the R+a-th stage. Correspondingly, the light-emitting control signal line L-EM electrically connected to the second shift register unit VSR2(PR) of the PR-th stage can be electrically connected to the second shift register unit VSR2(P) of the P-th stage at the same time, which is conducive to making the multiple light-emitting control signal lines L-EM more reasonably electrically connected to the multiple second shift register units VSR2.

[0104] Continue to refer Figure 15As shown, in the second light-emitting driver circuit 30B2, the light-emission control signal line L-EM electrically connected to the b-th shift register unit VSR2(b) is also electrically connected to the Q+b-th shift register unit VSR2(Q+b), with 1≤b≤PQ. Similarly, in the second light-emitting driver circuit 30B2, the light-emission control signal line L-EQ electrically connected to the b-th second shift register unit VSR2(b) is also electrically connected to the Q+b-th second shift register unit VSR2(Q+b), with 1≤b≤PQ. Since the pulse width of the second light-emission signal PAM-EM2 is Q*H, it can be configured that after a light-emission control signal line L-EM outputs a light-emission control signal EM-IN with a pulse width of Q*H to a second shift register unit VSR2, the transistor M22 of the second selection module 502 is turned off. Since the time required to scan a pixel row is H, the time difference between the second shift register units VSR2 turning on and transmitting the light-emission signal SWEEP stage by stage is also H. Then, after the second gating module 502 of the b-th second shift register unit VSR2(b) is turned on and the light-emission control signal line L-EM electrically connected thereto outputs a signal of Q*H duration, the pixel rows electrically connected to the b-th second shift register unit VSR2(b) through the Q+b-1-th second shift register unit VSR2(Q+b-1) have all output the light-emission signal PAM-EM. Continuing, the second gating module 502 of the Q+b-th second shift register unit VSR2(Q+b) is turned on, and the second gating module 502 of the b-th second shift register unit VSR2(b) is turned off. The light-emission control signal line L-EM electrically connected to the b-th second shift register unit VSR2(b) can continue to output the light-emission control signal EM-IN of Q*H duration to the Q+b-th second shift register unit VSR2(Q+b). Correspondingly, the light-emitting control signal line L-EM electrically connected to the PQ-th level second shift register unit VSR2(PQ) can be electrically connected to the P-th level second shift register unit VSR2(P) at the same time, which is conducive to making the multiple light-emitting control signal lines L-EM more reasonably electrically connected to the multiple second shift register units VSR2.

[0105] Figure 16 A schematic plan view of another display panel provided in an embodiment of the present application.

[0106] In one embodiment of the present application, Figure 16As shown, the light-emitting device 20 further includes a third light-emitting device 20C. At least at the maximum grayscale, the light-emitting duration of the third light-emitting device 20C is different from that of the first light-emitting device 20A and the second light-emitting device 20B. The pixel circuit 10 further includes a third pixel circuit 10C, which is electrically connected to the third light-emitting device 20C. The third light-emitting driver circuit 30B further includes a third light-emitting driver circuit 30B3, which provides a third light-emitting signal PAM-EM3 to the third pixel circuit 10C. The third light-emitting driver circuit 30B3 is electrically connected to S light-emitting control signal lines L-EM.

[0107] In combination with the above, it can be seen that when setting the number of light-emitting control signal lines L-EM electrically connected in common to the light-emitting drive circuit 30B3, the number can be set with reference to the duration of the light-emitting phase required by the light-emitting device 20. In the embodiment of the present application, setting S≠R and S≠Q facilitates further achieving different numbers of light-emitting control signal lines L-EM electrically connected in common to the light-emitting drive circuit 30B where the second shift register unit VSR2 is located, which is electrically connected to the pixel circuits 10 corresponding to different light-emitting devices 20 in the display panel 100. This facilitates further reducing the number of light-emitting control signal lines L-EM in the display panel 100, reducing the number of ports required to output light-emitting control signals, improving the routing efficiency of the light-emitting control signal lines L-EM, and reducing the power consumption of the display panel 100.

[0108] In one embodiment of the present application, the wavelength of light emitted by the first light-emitting device 20A is greater than the wavelength of light emitted by the second light-emitting device 20B, and the wavelength of light emitted by the second light-emitting device 20B is greater than the wavelength of light emitted by the third light-emitting device 20C. The brightness of light emitted by the first light-emitting device 20A is greater than the brightness of light emitted by the second light-emitting device 20B, and the brightness of light emitted by the second light-emitting device 20B is greater than the brightness of light emitted by the third light-emitting device 20C. The pulse width of the first light-emitting signal PAM-EM1 is greater than the pulse width of the second light-emitting signal PAM-EM2, and the pulse width of the second light-emitting signal PAM-EM2 is greater than the pulse width of the third light-emitting signal PAM-EM3. This allows, within a single frame of the display panel 100, the light-emitting duration of the first light-emitting device 20A is greater than the light-emitting duration of the second light-emitting device 20B, and greater than the light-emitting duration of the third light-emitting device 20C.

[0109] The third light driving circuit 30B3, which provides the third light signal PAM-EM3, is electrically connected to Z light control signal lines L-EM. In this embodiment, the pulse width of the third light signal PAM-EM3 is Z*H. Based on the above, it can be concluded that the pulse width R*H of the first light signal PAM-EM1 is greater than the pulse width Q*H of the second light signal PAM-EM2, and the pulse width Z*H of the third light signal PAM-EM3. Therefore, the turn-on time of the transistor M22 in the second gating module 502 in the third light driving circuit 30B3 that generates the third light signal PAM-EM3 is Z*H.

[0110] In the embodiment of the present application, R>Q>Z is set, and the first light-emitting driving circuit 30B1, the second light-emitting driving circuit 30B2, and the third light-emitting driving circuit 30B3 are set as different circuits. The specific difference is at least reflected in the different number of electrically connected light-emitting control signal lines L-EM, and the required number of light-emitting control signal lines L-EM is set accordingly according to the light-emitting brightness of different light-emitting devices 20. This is beneficial to reducing the power consumption of the light-emitting driving circuit 30B and reducing the number of signal terminals required to be occupied by the light-emitting driving circuit 30B, thereby reducing the preparation cost and power consumption of the display panel 100.

[0111] The first light emitting device 20A emits red light, the second light emitting device 20B emits green light, and the third light emitting device 20C emits blue light.

[0112] In one embodiment of the present application, continue to refer to Figure 16 As shown, R:Q:Z=6:3:2 is set, and the setting ratio of the light control signal lines L-EM electrically connected to the first light-emitting device 20A, the second light-emitting device 20B, and the third light-emitting device 20C is proposed, based on the light luminance trends of the first light-emitting device 20A, the second light-emitting device 20B, and the third light-emitting device 20C. This is helpful to provide a reference for relevant technical personnel and improve the feasibility of the embodiments of the present application. It should be noted that Figure 16 The start signal of the first-stage second shift register unit VSR2(1) in the third light-emitting driving circuit 30B3 shown in FIG is STV6.

[0113] In one embodiment of the present application, continue to refer to Figure 16As shown, R=6 is set, that is, the number of light-emitting control signal lines L-EM electrically connected in common in the first light-emitting driving circuit 30B1 is 6, the number of light-emitting control signal lines L-EM electrically connected in common in the second light-emitting driving circuit 30B2 is 3, and the number of light-emitting control signal lines L-EM electrically connected in common in the third light-emitting driving circuit 30B3 is 2. This is beneficial to reducing the number of light-emitting control signal lines L-EM electrically connected in common in the second light-emitting driving circuit 30B2 and the number of light-emitting control signal lines L-EM electrically connected in common in the third light-emitting driving circuit 30B3 corresponding to green light-emitting devices and blue light-emitting devices with lower luminance, thereby improving the use efficiency of the light-emitting control signal lines L-EM, reducing the total number of light-emitting control signal lines L-EM in the display panel 100, and increasing the available space in the display panel 100.

[0114] Figure 17 This is another working timing diagram of a display panel provided in an embodiment of the present application. Figure 18 This is another operating timing diagram of a display panel provided in an embodiment of the present application.

[0115] In one embodiment of the present application, it is set that R≤N, Q≤M.

[0116] For the first light-emitting device 20A, the number of light-emitting control signal lines L-EM electrically connected in the first light-emitting drive circuit 30B1 is less than or equal to the number of sweep control signal lines L-SWEEP electrically connected in the first sweep drive circuit 30B1. Therefore, when R light-emitting control signal lines L-EM are used in the entire display panel 100, the maximum output of the first light-emitting signal PAM-EM1 with a pulse width of R*H can be achieved. When N sweep control signal lines L-SWEEP are used in the entire display panel 100, the maximum output of the first sweep signal SWEEP1 with a pulse width of N*H can be achieved. Thus, setting R=N, as Figure 17 As shown, the pulse width of the output first sweep signal SWEEP1 can be equal to the pulse width of the first light-emitting signal PAM-EM, which is conducive to achieving that after the pixel circuit 10 enters the light-emitting stage E3, the pulse width modulation module 101 and the pulse amplitude modulation module 102 simultaneously receive the first sweep signal SWEEP1 and the first light-emitting signal PAM-EM1, so that when the pulse amplitude modulation module 102 starts to generate the light-emitting driving current L1, the first sweep signal SWEEP1 is coupled to the gate potential of the first driving transistor T1 through the first capacitor C1, thereby ensuring the accuracy of the pulse width modulation module 101 controlling the pulse amplitude modulation module 102 to output the light-emitting driving current L1. Alternatively, set R<N, as shown in FIG. Figure 18As shown, the pulse width R*H of the output first light-emitting signal PAM-EM1 can be smaller than the pulse width N*H of the first frequency sweep signal SWEEP1, which is conducive to achieving that after the pixel circuit 10 enters the light-emitting stage E3, the pulse width modulation module 101 first receives the first frequency sweep signal SWEEP1, and after a period of time, the pulse amplitude modulation module 102 starts to receive the first light-emitting signal PAM-EM. This is because when the first light-emitting device 20A needs to achieve a black grayscale, the seventh transistor T7 needs to immediately transmit current to the gate of the second driving transistor T2 when entering the light-emitting stage E3, so that the second driving transistor T2 does not generate the light-emitting driving current L1. However, it takes a certain amount of time for the first sweep signal SWEEP1 to couple the gate potential of the first driving transistor T1 to turn it on, and for the seventh transistor T7 to transmit current to the second driving transistor T2. If the pulse width modulation module 101 and the pulse amplitude modulation module 102 receive the corresponding light-emitting signals at the same time, then when the second driving transistor T2 generates the light-emitting driving current L1, the first driving transistor T1 may not be turned on or the seventh transistor T7 may be transmitting current to the gate of the second driving transistor T2, and the second driving transistor T2 cannot be turned off immediately. Therefore, the time when the pulse width modulation module 101 uses the first sweep signal SWEEP1 to adjust the gate potential of the first driving transistor T1 is advanced by a certain amount. This is beneficial for ensuring that when the pulse amplitude modulation module 102 starts to generate the light-emitting driving current L1, the first sweep signal SWEEP1 has already adjusted the gate potential of the first driving transistor T1 through the first capacitor C1. The second driving transistor T2 can be turned off in time, so that the first light-emitting device 20A does not receive the light-emitting driving current L1, thereby achieving the first light-emitting device 20A being in a black grayscale. It should be noted that the pulse widths of the first sweep signal SWEEP1 received in the pulse width modulation module 101 and the pulse width of the pulse width lighting signal PWM-EM can be set to be equal. The pulse width of the pulse width lighting signal PWM-EM proposed in the embodiment of the present application is the time for the pulse width light-emitting device PWM-EM to transmit a low-level signal.

[0117] For the second light-emitting device 20B, the number of light-emitting control signal lines L-EM electrically connected in the second light-emitting driving circuit 30B2 is less than or equal to the number of sweep control signal lines L-SWEEP electrically connected in the second sweep drive circuit 30B1. Therefore, when Q light-emitting control signal lines L-EM are used in the entire display panel 100, the maximum output of the second light-emitting signal PAM-EM1 with a pulse width of Q*H can be achieved. When M sweep control signal lines L-SWEEP are used in the entire display panel 100, the maximum output of the second sweep signal SWEEP1 with a pulse width of M*H can be achieved. Thus, setting Q=M, continue to refer to Figure 17As shown, the pulse width of the output second sweep signal SWEEP2 can be equal to the pulse width of the second light-emitting signal PAM-EM2, which is conducive to achieving that after the pixel circuit 10 enters the light-emitting stage E3, the pulse width modulation module 101 and the pulse amplitude modulation module 102 simultaneously receive the second sweep signal SWEEP2 and the second light-emitting signal PAM-EM2, so that when the pulse amplitude modulation module 102 starts to generate the light-emitting driving current L1, the second sweep signal SWEEP1 is simultaneously coupled through the first capacitor C1 to adjust the gate potential of the first driving transistor T1, thereby ensuring the accuracy of the pulse width modulation module 101 controlling the pulse amplitude modulation module 102 to output the light-emitting driving current L1. Alternatively, set Q<M, as shown in FIG. Figure 18 As shown, the pulse width Q*H of the output second light-emitting signal PAM-EM2 can be smaller than the pulse width M*H of the second frequency sweep signal SWEEP2, which is conducive to achieving that after the pixel circuit 10 enters the light-emitting stage E3, the pulse width modulation module 101 first receives the second frequency sweep signal SWEEP2, and after a period of time, the pulse amplitude modulation module 102 starts to receive the second light-emitting signal PAM-EM2. This is because when the second light-emitting device 20B needs to achieve a black grayscale, the seventh transistor T7 needs to immediately transmit current to the gate of the second driving transistor T2 when entering the light-emitting stage E3, so that the second driving transistor T2 does not generate the light-emitting driving current L1. However, it takes a certain amount of time for the second sweep signal SWEEP2 to couple the gate potential of the first driving transistor T1 to turn it on, and for the seventh transistor T7 to transmit current to the second driving transistor T2. If the pulse width modulation module 101 and the pulse amplitude modulation module 102 receive the corresponding light-emitting signals at the same time, then when the second driving transistor T2 generates the light-emitting driving current L1, the first driving transistor T1 may not be turned on or the seventh transistor T7 may be transmitting current to the gate of the second driving transistor T2, and the second driving transistor T2 cannot be turned off immediately. Therefore, the time when the pulse width modulation module 101 uses the second sweep signal SWEEP2 to adjust the gate potential of the first driving transistor T1 is advanced by a certain amount. This helps ensure that when the pulse amplitude modulation module 102 starts to generate the light-emitting driving current L1, the second sweep signal SWEEP2 has already adjusted the gate potential of the first driving transistor T1 through the first capacitor C1. The second driving transistor T2 can be turned off in time, so that the second light-emitting device 20B does not receive the light-emitting driving current L1, thereby achieving the second light-emitting device 20B being in a black grayscale. It should be noted that the pulse widths of the second sweep signal SWEEP2 received in the pulse width modulation module 101 and the pulse width of the pulse width lighting signal PWM-EM can be set to be equal. The pulse width of the pulse width lighting signal PWM-EM proposed in the embodiment of the present application is the time for the pulse width light-emitting device PWM-EM to transmit a low-level signal.

[0118] Figure 19 A schematic diagram of a display device provided in an embodiment of the present application.

[0119] The embodiment of the present application provides a display device 200, such as Figure 19 As shown, the display device 200 includes the display panel 100 provided in any of the above embodiments. Optionally, the display device 200 is a device used for display such as a computer, a television, a mobile phone, etc.

[0120] In the display device 200, the number of sweep control signal lines L-SWEEP electrically connected to the first sweep drive circuit 30A1 and the number of sweep control signal lines L-SWEEP electrically connected to the second sweep drive circuit 30A2 are different, corresponding to the first light-emitting device 20A and the second light-emitting device 20B. This facilitates adjusting the number of sweep control signal lines L-SWEEP required by the first sweep drive circuit 30A1 and the number of sweep control signal lines L-SWEEP required by the second sweep drive circuit 30A2 according to the difference in the light-emitting duration of the first light-emitting device 20A and the second light-emitting device 20B. Setting N≠M based on actual light-emitting needs helps reduce the redundancy of the sweep control signal lines L-SWEEP, thereby improving the utilization efficiency of a single sweep control signal line L-SWEEP, reducing the power consumption and wiring count of the display panel 100, and reducing the number of signal ports required to correspond to the sweep control signal lines L-SWEEP in the display panel 100, thereby reducing the manufacturing cost of the display panel 100.

[0121] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: A pixel circuit, including a pulse width modulation module and a pulse amplitude modulation module; The pulse width modulation module receives a frequency sweep signal; The pulse width modulation module controls the duration of the light-emitting driving current generated by the pulse amplitude modulation module based on the frequency sweep signal; a light-emitting device electrically connected to the pulse amplitude modulation module; the light-emitting device includes a first light-emitting device and a second light-emitting device, the pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit is electrically connected to the first light-emitting device, and the second pixel circuit is electrically connected to the second light-emitting device; A driving control circuit, wherein the driving control circuit includes a sweep frequency driving circuit, wherein the sweep frequency driving circuit provides the sweep frequency signal to the pixel circuit; the sweep frequency driving circuit includes a plurality of first shift register units, wherein the first shift register unit includes a first driving module and a first gating module, wherein a control end of the first gating module is connected to an output end of the first driving module, the first gating module is electrically connected to a sweep frequency control signal line, the sweep frequency control signal line transmits a sweep frequency control signal, and the first gating module outputs the sweep frequency signal based on the sweep frequency control signal and a signal output by the first driving module; The frequency sweep driving circuit includes a first frequency sweep driving circuit and a second frequency sweep driving circuit, wherein the first frequency sweep driving circuit provides a first frequency sweep signal to the first pixel circuit, and the second frequency sweep driving circuit provides a second frequency sweep signal to the second pixel circuit; wherein The first frequency sweep driving circuit is electrically connected to N frequency sweep control signal lines, and the second frequency sweep driving circuit is electrically connected to M frequency sweep control signal lines; N≠M.

2. The display panel according to claim 1, wherein: The pulse width of the first frequency sweep signal is different from the pulse width of the second frequency sweep signal.

3. The display panel according to claim 2, wherein: The light-emitting wavelength of the first light-emitting device is greater than the light-emitting wavelength of the second light-emitting device; the pulse width of the first frequency sweep signal is greater than the pulse width of the second frequency sweep signal, and N>M.

4. The display panel according to claim 2, wherein: In the first frequency sweep driving circuit, an input end of the first driving module in the first-stage first shift register unit receives a first starting signal; in the second frequency sweep driving circuit, an input end of the first driving module in the first-stage first shift register unit receives a second starting signal; The pulse width of the first start signal is greater than or equal to the pulse width of the first frequency sweep signal, and the pulse width of the second start signal is greater than or equal to the pulse width of the second frequency sweep signal.

5. The display panel according to claim 1, wherein: The output end of the first driving module in the first shift register unit of the i-th stage is connected to the input end of the first driving module in the first shift register unit of the (i+1)-th stage, where i is an integer.

6. The display panel according to claim 5, wherein: The frequency sweep driving circuit includes P cascaded first shift register units; In the first frequency sweep driving circuit, the frequency sweep control signal line electrically connected to the first shift register unit of the xth stage is also electrically connected to the first shift register unit of the N+xth stage, 1≤x≤PN; In the second frequency sweep driving circuit, the frequency sweep control signal line electrically connected to the y-th stage first shift register unit is also electrically connected to the M+y-th stage first shift register unit, 1≤y≤PM.

7. The display panel according to claim 1, wherein: The light-emitting device further includes a third light-emitting device; the pixel circuit further includes a third pixel circuit, the third pixel circuit being electrically connected to the third light-emitting device; the frequency sweep driving circuit further includes a third frequency sweep driving circuit, the third frequency sweep driving circuit providing a third frequency sweep signal to the third pixel circuit; the third frequency sweep driving circuit is electrically connected to Z frequency sweep control signal lines; Among them, Z≠N and Z≠M.

8. The display panel according to claim 7, wherein: The light-emitting wavelength of the first light-emitting device is greater than the light-emitting wavelength of the second light-emitting device, and the light-emitting wavelength of the second light-emitting device is greater than the light-emitting wavelength of the third light-emitting device; the pulse width of the first frequency sweep signal is greater than the pulse width of the second frequency sweep signal, and the pulse width of the second frequency sweep signal is greater than the pulse width of the third frequency sweep signal; Among them, N>M>Z.

9. The display panel according to claim 8, wherein: The first light emitting device emits red light, the second light emitting device emits green light, and the third light emitting device emits blue light.

10. The display panel according to claim 8, wherein The N:M:Z=6:3:

2.

11. The display panel according to claim 10, wherein: N＝6。 12. The display panel according to claim 1, wherein The drive control circuit further includes a light-emitting drive circuit, which provides a light-emitting signal to a pulse amplitude modulation module of the pixel circuit; the light-emitting signal can control the pulse amplitude modulation module to generate a light-emitting drive current; the light-emitting drive circuit includes a plurality of second shift register units, each of which includes a second driving module and a second gating module, wherein a control terminal of the second gating module is connected to an output terminal of the second driving module, the second gating module is electrically connected to a light-emitting control signal line, the light-emitting control signal line transmits a light-emitting control signal, and the second gating module outputs the light-emitting signal based on the light-emitting control signal and a signal output by the second driving module; The light-emitting driving circuit includes a first light-emitting driving circuit and a second light-emitting driving circuit, wherein the first light-emitting driving circuit provides a first light-emitting signal for the first pixel circuit, and the second light-emitting driving circuit provides a second light-emitting signal for the second pixel circuit; wherein The first light-emitting driving circuit is electrically connected to R light-emitting control signal lines in common, and the second light-emitting driving circuit is electrically connected to Q light-emitting control signal lines in common; R≠Q.

13. The display panel according to claim 12, wherein: The light emission wavelength of the first light emitting device is greater than the light emission wavelength of the second light emitting device; the pulse width of the first light emitting signal is greater than the pulse width of the second light emitting signal, and R>Q.

14. The display panel according to claim 13, wherein: R≤N, Q≤M.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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