Method for setting read address of memory

Abstract

The embodiment of the invention provides a memory read address setting method, which comprises the following steps that: a digital-to-analog converter can perform parallel sampling on a synchronous signal based on a plurality of phases of clock signals by acquiring the plurality of phases of clock signals to obtain the plurality of phases of synchronous signals; generating a synchronization sequence signal corresponding to each phase synchronization signal according to the multiple phase synchronization signals; according to the synchronization sequence signal and the synchronization signal of the multiple phases, the read address in the memory is set, so that the problem of address setting errors caused by low time delay precision of the multi-phase synchronization signal obtained by performing serial sampling on the synchronization signal by using a clock signal in the related technology is solved, the precision of the synchronization signal is improved, and the user experience is improved. Therefore, the memory can correctly carry out higher-precision setting on the read address.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular, to a method for setting a memory read address. Background Art

[0002] The initialization and reset of the dividers and random access memory in a traditional DAC usually involves sampling the input system reference signal Input Sysref through a PLL clock and transmitting it to the DAC together with the clock. After receiving the system reference synchronization signal, a synchronous reset pulse is generated on its first rising edge to reset the dividers in the DAC and generate a multi-phase, multi-division ratio clock with a fixed phase relationship.

[0003] In order to solve the delay accuracy error caused by clock frequency error, after initialization and reset, the clock rising edge of the reference synchronization signal is usually compared with the 10ms obtained by counting the clock in the random access memory every 10ms to obtain the clock frequency deviation. The clock frequency error is compensated by setting the read address, and finally a high-precision delay is obtained.

[0004] However, the four-phase synchronization signal obtained by serially sampling the 10ms synchronization signal using the clock signal has low delay accuracy. For example, when the rising edge is relatively slow or the jitter is relatively large, there is a situation where different clock rising edges are used to sample the 10ms period synchronization signal, resulting in a non-ideal multi-phase synchronization signal. When the low-precision four-phase synchronization signal is used to directly set the read address of the corresponding phase, it causes the problem of address setting error. Summary of the Invention

[0005] An embodiment of the present application provides a method for setting a memory read address, so as to at least solve the problem in the related art that the four-phase synchronous signal obtained by serially sampling the synchronous signal using a clock signal has low delay accuracy, resulting in address setting errors.

[0006] According to one embodiment of the present application, a method for setting a memory read address is provided, which is applied to a digital-to-analog converter, wherein the digital-to-analog converter includes a memory, and the method includes:

[0007] Acquire clock signals of multiple phases, and perform parallel sampling on the synchronization signal based on the clock signals of the multiple phases to obtain synchronization signals of the multiple phases;

[0008] Generating a synchronization sequence signal corresponding to each phase synchronization signal according to the synchronization signals of the multiple phases;

[0009] A read address in the memory is set according to the synchronization sequence signal and the synchronization signals of the multiple phases.

[0010] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0011] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0012] According to another embodiment of the present application, a computer program product is provided, including a computer program, which implements the steps of any of the above method embodiments when executed by a processor.

[0013] In an embodiment of the present application, the digital-to-analog converter can obtain clock signals of multiple phases and perform parallel sampling of synchronization signals based on the clock signals of multiple phases to obtain synchronization signals of multiple phases; based on the synchronization signals of multiple phases, a synchronization sequence signal corresponding to each phase synchronization signal is generated; based on the synchronization sequence signal and the synchronization signals of multiple phases, a read address in the memory is set, which solves the problem in the related art that the multi-phase synchronization signal obtained by serial sampling of the synchronization signal using the clock signal has low delay accuracy, resulting in address setting errors, improves the accuracy of the synchronization signal, and enables the memory to correctly set the read address with higher accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the system block diagram of a traditional digital-to-analog converter;

[0015] Figure 2 This is the schematic diagram of the circuit for generating four-phase synchronous signals under traditional precision;

[0016] Figure 3 This is a hardware structure block diagram of a mobile terminal for a method for setting a memory read address according to an embodiment of the present application;

[0017] Figure 4 is a flowchart of a memory read address setting method according to an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of a four-phase synchronization signal generating circuit according to an embodiment of the present application;

[0019] Figure 6 This is a block diagram of clock phase initialization under multiple clock domains according to an embodiment of the present application;

[0020] Figure 7 is a schematic diagram of an interface circuit for converting an analog synchronization signal into a digital synchronization signal according to an embodiment of the present application;

[0021] Figure 8 This is a timing diagram of clock phase initialization under multiple clock domains according to an embodiment of the present application;

[0022] Figure 9 is a block diagram of a random access memory read address reset according to an embodiment of the present application;

[0023] Figure 10 This is the timing diagram of the traditional RAM read address setting without synchronous sequence signal logic control;

[0024] Figure 11 This is a timing diagram of the RAM read address setting with synchronous sequence signal control logic according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0027] Figure 1 This is a system block diagram of a traditional digital-to-analog converter. A digital-to-analog converter (DAC) may include a data path, a clock path, and a DAC core circuit. The data path may include an interface circuit, random access memory (RAM), a decoder, a serializer, and a switch driver; the clock path may include a clock and synchronization signal receiver, a divider, and a clock driver (not shown in the figure); and the DAC core circuit may include one or more DAC core slices (not shown in the figure).

[0028] like Figure 1As shown, l-channel low-speed data operating at a frequency of Fs / l in the interface circuit can be transmitted in parallel to the random access memory RAM, and converted into m-channel data under the clock of Fs / m in the RAM. The m-channel data is then output to a decoder with the same clock frequency of Fs / m. Logical operations such as thermometer decoding can be performed in the decoder. Therefore, the input data and input clock of the random access memory RAM are asynchronous, and a synchronization signal is required to set the read address of the random access memory RAM. The input data and clock of the decoder are synchronized. After the decoder completes the code conversion, the m-phase to n-phase data can be merged using double-edge sampling in the serializer, and then the n-phase to k-phase data can be merged in the switch driver, ultimately obtaining data at a rate of Fs / k.

[0029] from Figure 1 As can be seen in the figure, the operating frequency of the entire data link is accelerated from the low-speed modules in the digital domain to the high-speed modules in the analog domain, requiring multiple parallel-to-serial conversions. This results in the existence of multiple clock domains within the data link. To achieve high delay accuracy in the DAC's sine wave output, the multiphase dividers and the read addresses in the random access memory (RAM) must be initialized and reset in each clock domain. Therefore, reset accuracy determines the delay accuracy of the DAC's sine wave output.

[0030] like Figure 1 As shown in the figure, in the clock chain, the phase-locked loop (PLL) can transmit a high-frequency clock signal with a frequency of Fs and a synchronization signal to a clock and synchronization signal receiver, which then transmits the high-frequency clock signal with a frequency of Fs and the synchronization signal to a frequency divider. The PLL output synchronization signal can be a system reference synchronization signal with an adjustable period and duty cycle after being sampled by the PLL.

[0031] After receiving a high-frequency clock signal with a frequency of Fs, the frequency divider of the analog domain can perform frequency division processing on the high-frequency clock signal. For example, the high-frequency clock signal can be divided by 4, and a synchronization signal can be used to generate a reset pulse signal to reset the frequency divider of the analog domain. The synchronization signal can be serially sampled using the divided clock to obtain a four-phase synchronization signal with an accuracy of 4 / Fs. The four-phase synchronization signal with an accuracy of 4 / Fs can be transmitted together with the divided clock to the random access memory to set its read address.

[0032] Figure 2This is the schematic diagram of the four-phase synchronization signal generation circuit under traditional precision. Taking the four-phase divided-by-four clock as an example, the trigger DFF can use the four-phase divided-by-four clock (such as 0, 1, 2, and 3) to serially sample the synchronization signal in sequence: use the divided-by-four clock of phase 0 to sample the synchronization signal sync with a period of 10ms and output sync p0; then reset the DFF based on the read address synchronization reset signal of phase 0, and use the divided-by-four clock of phase 1 to sample sync p0 and output sync p1; reset the DFF based on the read address synchronization reset signal of phase 1, and use the divided-by-four clock of phase 2 to sample sync p1 and output sync p2; then reset the DFF based on the read address synchronization reset signal of phase 2, and use the divided-by-four clock of phase 3 to sample sync p2 and output sync p3, thereby obtaining the four-phase synchronization signals sync p0, sync p1, sync p2, and sync p3.

[0033] After obtaining the four-phase synchronization signal, the four-phase synchronization signal and the four-divided clock are transmitted to the random access memory RAM. After receiving the four-phase synchronization signal, the random access memory RAM initializes and sets the read address of the corresponding phase; through the above method, the initialization and setting of the DAC internal divider and the random access memory are completed.

[0034] However, this read address setting method has the following problems:

[0035] First, if the rising edge of the synchronization signal input to the system is slow or the jitter is large, a clock frequency error will occur. When the clock with a frequency of Fs samples it, there is a situation where different clock rising edges are used to sample the 10ms period synchronization signal. This causes the synchronization signal in the system to be a non-ideal 10ms period signal, and after sampling by the internal divided clock of the DAC, the minimum accuracy deviation of the four-phase synchronization signal is 4 / Fs, introducing a time delay error of 4 / Fs; second, if the clock frequency error causes the 10ms count in the random access memory to deviate, similar problems to those mentioned above will also occur; third, due to the low operating frequency of the digital domain, the four-phase synchronization signal directly sets the read address of the corresponding phase. Providing a four-phase synchronization signal with an accuracy exceeding 4 / Fs will result in address setting errors.

[0036] Currently, there is no solution to how to generate a higher-precision four-phase synchronization signal and how to interact the high-precision synchronization signal with the digital domain operating at a low frequency to improve the delay accuracy of the entire system.

[0037] In response to the technical problems existing in the above-mentioned prior art, an embodiment of the present application proposes a method for setting a memory read address. The technical concept is to perform parallel sampling of the synchronization signal based on a multi-phase clock signal to obtain a multi-phase synchronization signal with an accuracy of 1 / FS, and generate a corresponding synchronization sequence signal. Based on the synchronization sequence signal and the synchronization signal of multiple phases, the read address in the memory is controlled to be set, thereby improving the accuracy of the synchronization signal, so that the memory can correctly set the read address with higher accuracy.

[0038] The memory read address setting method of the embodiment of the present application can be used not only in DAC circuits, but also in other circuits that require high-precision reset, and the embodiment of the present application is not limited here.

[0039] The memory read address setting method of the embodiment of the present application can be used not only for random access memory, but also for other devices or apparatuses where data and clock are asynchronous and need to be synchronized or reset, and the embodiment of the present application does not limit this.

[0040] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 3 This is a hardware structure block diagram of a mobile terminal of a method for setting a memory read address according to an embodiment of the present application. Figure 3 As shown, the mobile terminal may include one or more ( Figure 3 Only one is shown) a processor 302 (the processor 302 may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices) and a memory 304 for storing data, wherein the mobile terminal may also include a transmission device 306 and an input and output device 308 for communication functions. It will be understood by those skilled in the art that Figure 3 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 3 More or fewer components than shown, or with Figure 3 Different configurations shown.

[0041] The memory 304 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the memory read address setting method in the embodiment of the present application. The processor 302 executes various functional applications and data processing by running the computer program stored in the memory 304, that is, implementing the above method. The memory 304 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 304 may further include a memory remotely located relative to the processor 302, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0042] Transmission device 306 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, transmission device 306 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, transmission device 306 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0043] In this embodiment, a setting method for a read address of a memory of the mobile terminal is provided, which is applied to a digital-to-analog converter. The digital-to-analog converter includes a memory, Figure 4 : is a flowchart of a memory read address setting method according to an embodiment of the present application. Figure 4 As shown, the process includes the following steps:

[0044] Step S401 : Acquire clock signals of multiple phases, and perform parallel sampling on the synchronization signal based on the clock signals of multiple phases to obtain synchronization signals of multiple phases.

[0045] The embodiment of the present application uses clock signals of multiple phases to sample the synchronization signal in parallel to obtain synchronization signals of multiple phases.

[0046] In an exemplary embodiment, the digital-to-analog converter further includes a frequency divider, and obtaining clock signals of multiple phases includes:

[0047] receiving a high-frequency clock signal;

[0048] The high-frequency clock signal is divided by the frequency divider to obtain the clock signals of the multiple phases.

[0049] As an example, a frequency divider can receive a high-frequency (Fs) clock signal and generate a clock signal with multiple phases at a lower frequency. The divided clock can be used to drive subsequent parallel sampling.

[0050] Figure 5 : is a schematic diagram of a four-phase synchronous signal generating circuit according to an embodiment of the present application, taking a four-phase four-frequency division as an example. Figure 5 As shown, the trigger DFF can perform parallel sampling of 10ms synchronization signals based on four-phase divided-by-four clock signals (such as divided-by-four phase zero clock, divided-by-four phase one clock, divided-by-four phase two clock, and divided-by-four phase three clock): use the divided-by-four phase zero clock signal to sample the synchronization signal sync with a period of 10ms and output the phase zero synchronization signal sync p0 for read address setting, use the divided-by-four phase one clock signal to sample the synchronization signal sync with a period of 10ms and output the phase one synchronization signal sync p1 for read address setting, use the divided-by-four phase two clock signal to sample the synchronization signal sync with a period of 10ms and output the phase two synchronization signal sync p2 for read address setting, use the divided-by-four phase three clock signal to sample the synchronization signal sync with a period of 10ms and output the phase three synchronization signal sync p3 for read address setting, thereby obtaining four-phase synchronization signals sync p0, sync p1, sync p2, and sync p3 with an accuracy of 1 / Fs.

[0051] The four-phase synchronization signal generation method of the present application can not only be used to achieve a time delay with an accuracy of 1 / Fs, but can also be used in other scenarios that require control or reset accuracy that is much higher than the operating frequency of the circuit itself.

[0052] In an exemplary embodiment, dividing the high-frequency clock signal by the frequency divider to obtain the clock signals of the multiple phases includes:

[0053] Obtaining a reset pulse of the synchronization signal, and initializing and resetting the frequency divider according to the reset pulse;

[0054] The high-frequency clock signal is divided by the initialized and reset frequency divider to obtain the clock signals of the multiple phases.

[0055] As an example, the first edge of the synchronization signal can be used to generate a reset pulse to initialize and reset the divider, and the high-frequency clock signal can be divided by the initialized and reset divider. The multi-phase clock after division can then be used to sample the first edge of the synchronization signal. The synchronization signal obtained based on the sampling of the first edge of the synchronization signal can be used to initialize and reset the random access memory read address.

[0056] For example, Figure 6 This is a block diagram of clock phase initialization under multiple clock domains according to an embodiment of the present application, such as Figure 6 As shown, a clock path and a synchronization pulse can be generated based on the input synchronization signal, high-frequency (Fs) clock signal, and pulse enable signal, and a reset pulse can be generated based on the first edge of the synchronization pulse. A clock signal with a frequency of Fs is extracted based on the clock path, and the reset pulse and the clock signal with a frequency of Fs are input into an m-divided frequency divider (div m), and a four-phase clock signal with a frequency of Fs / m output by the divider can be obtained.

[0057] As an example, the sampling accuracy of the synchronization signal can be varied based on the frequency division number of the frequency divider, for example, Figure 6 The four-phase m-frequency divider is used for frequency division to generate a synchronization signal with an accuracy of m / 4*Fs. It can also be used in conjunction with any other multi-phase frequency divider according to actual usage requirements to generate multi-phase synchronization signals with an accuracy of any integer multiple of 1 / Fs.

[0058] In an exemplary embodiment, the sampling the synchronization signal in parallel based on the clock signals of the multiple phases to obtain the synchronization signals of the multiple phases includes:

[0059] Sampling the first rising edge of the synchronization signal respectively according to the clock signals of the multiple phases to determine the phase relationship of the synchronization signal;

[0060] determining a rising edge subsequent to the first rising edge of the synchronization signal according to a phase relationship of the synchronization signal;

[0061] The rising edges subsequent to the first rising edge are sampled in parallel based on the clocks of the multiple phases to obtain synchronization signals of the multiple phases.

[0062] As an example, the synchronization signals of multiple phases in the embodiment of the present application can be obtained by parallel sampling based on the rising edges after the first rising edge of the synchronization signal.

[0063] Step S402: Generate a synchronization sequence signal corresponding to each phase synchronization signal according to the synchronization signals of the multiple phases.

[0064] For example, Figure 6 As shown, the synchronization signal can be sampled based on a multi-phase clock signal with a frequency of Fs / m to obtain a four-phase synchronization signal. According to the phase sequence of the four-phase synchronization signal, a corresponding 2-bit synchronization sequence signal can be generated, and the 2-bit synchronization sequence signal and the four-phase synchronization signal can be transmitted to a random access memory. The 2-bit synchronization sequence signal can be used to indicate the phase sequence of the multi-phase synchronization signal.

[0065] In an exemplary embodiment, before generating a synchronization sequence signal corresponding to each phase synchronization signal according to the phase sequence of the synchronization signals of the multiple phases, the method further includes:

[0066] Obtaining a falling edge of the synchronization signal, and generating a synchronization sequence reset pulse according to the falling edge;

[0067] Resetting is performed according to the synchronous sequence reset pulse.

[0068] For example, Figure 6 As shown, the falling edge of the synchronization pulse can be used to generate a synchronization sequence reset pulse (syncorder rst pulse). Before generating the synchronization sequence signal, the analog-to-digital converter can be reset based on the synchronization sequence reset pulse to ensure that the synchronization sequence signal is independent of the previous synchronization sequence signal level.

[0069] In an exemplary embodiment, generating a synchronization sequence signal corresponding to each phase synchronization signal according to the multiple phase synchronization signals includes:

[0070] determining a phase combination order of the synchronization signals of the multiple phases according to each phase synchronization signal of the synchronization signals of the multiple phases;

[0071] According to the phase combination sequence, the synchronization sequence signal corresponding to each phase synchronization signal in the synchronization signals of the multiple phases is generated; wherein the synchronization sequence signal is used to indicate the phase sequence of the corresponding phases of the synchronization signals of the multiple phases.

[0072] As an example, the synchronization signals of multiple phases obtained by parallel sampling may have multiple combination orders, and the synchronization sequence signal corresponding to each phase synchronization signal may be generated for each group of phase combination orders of the synchronization signals of multiple phases.

[0073] For example, Figure 7 FIG. 1 is a schematic diagram of an interface circuit for converting an analog synchronization signal into a digital synchronization signal according to an embodiment of the present application. Figure 7 As shown, this interface circuit can be used to convert a 2-bit synchronous sequential pulse signal into a 2-bit synchronous sequential signal, preventing the digital domain's low-frequency clock from failing to sample the narrow pulses. The analog-to-digital conversion circuit that converts the pulse signal into the synchronous sequential signal operates on the same principle as a frequency divider. Therefore, the analog-to-digital conversion circuit needs to be reset. The falling edge of the 10ms synchronous signal can be used to generate a reset pulse. This reset pulse resets the previous synchronous sequence information, thereby generating a correct synchronous sequence signal.

[0074] like Figure 7As shown, a 10ms synchronization signal can be sampled using a divided-by-four clock signal to obtain a synchronization sequence signal and a four-phase synchronization signal, and the divided-by-four clock signal, the synchronization sequence signal and the four-phase synchronization signal are transmitted to the trigger together.

[0075] For example, the trigger can use a divided-by-four clock signal to sample the synchronization signal, generating a four-phase synchronization signal with an accuracy of 1 / Fs. The four-phase synchronization signal with an accuracy of 1 / Fs is then transmitted to the RAM as a read address set signal. During the transmission process, the four-phase synchronization signal can also be buffered in a buffer.

[0076] After sampling, the pulse signal is connected to the trigger port of the trigger, and the pulse signal is converted into a synchronous sequence signal, and transmitted to the RAM to control the read address setting; since the circuit that converts the pulse signal into a synchronous sequence signal is similar to a frequency divider, it needs to be reset. The reset pulse is generated by the falling edge of the 10ms synchronous signal, which can reset the previous synchronous sequence information of the trigger, thereby generating a correct synchronous sequence signal.

[0077] As an example, there are many ways to generate and reset the synchronous sequence signal, for example, Figure 8 In the process, the synchronous sequential pulse is connected to the trigger clock terminal and reset with a 10ms falling edge to generate a 2-bit signal with a long pulse width that is sufficient for the random access memory RAM to correctly identify. In addition, a higher divided clock frequency (the clock frequency is lower than the random access memory RAM operating frequency) can also be used to directly sample the synchronous sequential signal without a reset signal.

[0078] Figure 8 This is a timing diagram of clock phase initialization under multiple clock domains according to an embodiment of the present application, such as Figure 8 As shown, (1) is the phase-locked loop output clock signal, (2) is the 10 millisecond input synchronization signal, (3) is the 10 millisecond synchronization signal after sampling the phase-locked loop output clock, (4) is the synchronization reset pulse, (5) is the quarter-frequency phase zero clock after reset, (6) is the quarter-frequency phase one clock after reset, (7) is the quarter-frequency phase two clock after reset, (8) is the quarter-frequency phase three clock after reset, (9) is the synchronization signal for resetting the RAM phase zero read address, (10) is the synchronization signal for resetting the RAM phase one read address, (11) is the synchronization signal for resetting the RAM phase two read address, (12) is the synchronization signal for resetting the RAM phase three read address, (13) is the phase zero synchronization sequence reset pulse, (14) is the phase one synchronization sequence reset pulse, (15) is the phase two synchronization sequence reset pulse, and (16) is the phase three synchronization sequence reset pulse.

[0079] like Figure 8As shown, after the phase-locked loop PLL samples the synchronous signal, when the phase zero (i.e., phase 0) is hereinafter referred to as phase zero p0, phase 1 p1, phase 2 p2, and phase 3 p3. Figure 8 As shown, the four-phase divided-by-four clock signal is sampled into the four-phase synchronous reset signal in the order of p0, p1, p2, and p3; when the synchronous signal is at p1 after PLL sampling, the four-phase divided-by-four clock is sampled into the four-phase synchronous signal in the order of p1, p2, p3, and p0; when the synchronous signal is at p2 after PLL sampling, the four-phase divided-by-four clock signal can be sampled into the four-phase synchronous reset signal in the order of p2, p3, p0, and p1; when the synchronous signal is at p3 after PLL sampling, the four-phase divided-by-four clock signal can be sampled into the four-phase synchronous reset signal in the order of p3, p0, p1, and p2.

[0080] According to the combination sequence of the four phases of the four-phase synchronous reset signal, a 4-bit synchronization pulse corresponding to each combination sequence is generated, that is, when the synchronization signal is p0, the synchronization pulse sync pulse<3:0>=0001; when the synchronization signal is p1, sync pulse<3:0>=0010; when the synchronization signal is p2, sync pulse<3:0>=0100; when the synchronization signal is p3, sync pulse<3:0>=1000; according to the thermometer code of the 4-bit synchronization pulse corresponding to each combination sequence, the thermometer code can be converted into a binary code, and the pulse signal is converted into a synchronization sequence signal.

[0081] The number of bits and the corresponding phase relationship of the synchronous sequence signal can be varied in many ways, as shown in the attached figure. Figure 8 The four possible phase relationship information is converted into 2-bit data, and can also be converted into other bits of data according to the number of other possible phase relationships. For example, if there are 8 possible phase relationships, it can be converted into 3-bit data. This embodiment of the present application does not limit this.

[0082] Step S403: setting a read address in the memory according to the synchronization sequence signal and the synchronization signals of the multiple phases.

[0083] The embodiment of the present application can set the read address in the memory based on the synchronization sequence signal and the synchronization signals of multiple phases.

[0084] For example, Figure 9 is a block diagram of a random access memory read address reset according to an embodiment of the present application, such as Figure 9As shown, RAM can be used to implement corresponding read functions (such as read enable, read clock, read address, read data, etc.) and write functions (such as write enable, write clock, write address, write data, etc.), and the read address reset module can be used to reset the read address of the RAM according to the read clock signal and the four-phase synchronization signal.

[0085] After receiving a four-phase synchronization signal (4phase sync), the random access memory controls the sequential setting of the read address according to the synchronization sequence signal corresponding to the synchronization signal, regardless of which phase of the synchronization signal is received first, rather than directly setting the read address of the corresponding phase after receiving the synchronization signal.

[0086] In an exemplary embodiment, setting the read address in the memory according to the synchronization sequence signal and the synchronization signals of the multiple phases includes:

[0087] Transmitting the synchronization sequence signal and the synchronization signals of the multiple phases to the memory, and obtaining a corresponding relationship between each phase of the synchronization signals of the multiple phases and the read address;

[0088] According to the synchronization sequence signal, the synchronization signals of the multiple phases and the corresponding relationship, the memory is controlled to set the read address in sequence.

[0089] Exemplarily, each phase of the multiple-phase synchronization signal has a corresponding relationship with the RAM read address, and the read address corresponding to each phase of the multiple-phase synchronization signal can be controlled to be set according to the synchronization sequence signal and the multiple-phase synchronization signal.

[0090] For example, Figure 10 This is the timing diagram of the traditional RAM read address setting without synchronous sequence signal logic control, such as Figure 10 As shown, A is the phase zero synchronous reset signal p0, B is the phase one synchronous reset signal p1, C is the phase two synchronous reset signal p2, D is the phase three synchronous reset signal p3, E is the RAM read address of p0, F is the RAM read address of p1, G is the RAM read address of p2, and H is the RAM read address of p3.

[0091] like Figure 10 As shown, the phase order of the random access memory receiving the four-phase synchronization signal for the first time can be p0, p1, p2, and p3, and the read addresses of the corresponding phases are set respectively. The set value can be configured according to requirements. Taking the set value of 41 as an example, when initializing and resetting, the four-phase read addresses are all set to 41.

[0092] After 10ms, the random access memory receives the four-phase synchronization signal again. Figure 10The synchronization signal is transmitted to the random access memory RAM in the order of p1, p2, p3, and p0. The interval between the synchronization signals of p1, p2, and p3 and the synchronization signal at the time of initialization and reset is 10ms. Since 10ms is an integer multiple of the read address depth multiplied by the clock period, the read address 41 of the p1, p2, and p3 phases is the same as the read address set value 41 of the synchronization signal. As for p0, since p0 is in the order after p3, its read address set value 10ms ago is 42. After 10ms, the read address set value should be 42. However, since the preset read address corresponding to p0 is 41, 10ms later, when the read address corresponding to p0 is set, the read address is directly set to 41. This causes the four-phase read address values ​​to be misaligned, resulting in data errors in the subsequent parallel-to-serial conversion synthesis, and the DAC outputs an incorrect waveform.

[0093] Figure 11 is a timing diagram of the RAM read address setting with synchronous sequence signal control logic according to an embodiment of the present application, such as Figure 11 As shown, a is the phase zero synchronous reset signal p0, b is the phase one synchronous reset signal p1, c is the phase two synchronous reset signal p2, d is the phase three synchronous reset signal p3, e is the RAM read address of p0, f is the RAM read address of p1, g is the RAM read address of p2, and h is the RAM read address of p3.

[0094] When the received synchronization sequence signal is 0, the synchronization signal sets the read address of the corresponding phase to 41; when the received synchronization sequence signal is 1, the synchronization signal sets the read address of the p0 phase to 42, and the read addresses of other phases to 41; when the received synchronization sequence signal is 2, the synchronization signal sets the read address of the p0 and p1 phases to 42, and the read addresses of other phases to 41 (not shown in the figure); when the received synchronization sequence signal is 3, the synchronization signal sets the read address of the p0, p1, and p2 phases to 42, and the read addresses of other phases to 41 (not shown in the figure); through the above method, the random access memory can achieve address setting with 1 / Fs accuracy, and ultimately achieve a system delay with 1 / Fs accuracy.

[0095] In an embodiment of the present application, the digital-to-analog converter can obtain clock signals of multiple phases and perform parallel sampling of synchronization signals based on the clock signals of multiple phases to obtain synchronization signals of multiple phases; based on the synchronization signals of multiple phases, a synchronization sequence signal corresponding to each phase synchronization signal is generated; based on the synchronization sequence signal and the synchronization signals of multiple phases, a read address in the memory is set, which solves the problem in the related art that the multi-phase synchronization signal obtained by serial sampling of the synchronization signal using the clock signal has low delay accuracy, resulting in address setting errors, improves the accuracy of the synchronization signal, and enables the memory to correctly set the read address with higher accuracy.

[0096] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0097] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0098] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0099] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0100] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0101] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0102] An embodiment of the present application further provides a computer program product, including a computer program, which implements the steps of any of the above method embodiments when executed by a processor.

[0103] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0104] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for setting a memory read address, characterized in that: Applied to a digital-to-analog converter, the digital-to-analog converter includes a memory, and the method includes: Acquire clock signals of multiple phases, and perform parallel sampling on the synchronization signal based on the clock signals of the multiple phases to obtain synchronization signals of the multiple phases; Generating a synchronization sequence signal corresponding to each phase synchronization signal according to the synchronization signals of the multiple phases; A read address in the memory is set according to the synchronization sequence signal and the synchronization signals of the multiple phases.

2. The method according to claim 1, characterized in that The step of sampling the synchronization signal in parallel based on the clock signals of the multiple phases to obtain the synchronization signals of the multiple phases includes: Sampling the first rising edge of the synchronization signal respectively according to the clock signals of the multiple phases to determine the phase relationship of the synchronization signal; determining a rising edge subsequent to the first rising edge of the synchronization signal according to a phase relationship of the synchronization signal; The rising edges subsequent to the first rising edge are sampled in parallel based on the clocks of the multiple phases to obtain synchronization signals of the multiple phases.

3. The method according to claim 1, characterized in that Generating a synchronization sequence signal corresponding to each phase synchronization signal according to the synchronization signals of the multiple phases includes: determining a phase combination order of the synchronization signals of the multiple phases according to a phase order of each synchronization signal of the synchronization signals of the multiple phases; According to the phase combination sequence, the synchronization sequence signal corresponding to each phase synchronization signal in the synchronization signals of the multiple phases is generated; wherein the synchronization sequence signal is used to indicate the phase sequence of the corresponding phases of the synchronization signals of the multiple phases.

4. The method according to claim 1, wherein The step of setting a read address in the memory according to the synchronization sequence signal and the synchronization signals of the multiple phases includes: Transmitting the synchronization sequence signal and the synchronization signals of the multiple phases to the memory, and obtaining a corresponding relationship between each phase of the synchronization signals of the multiple phases and the read address; According to the synchronization sequence signal, the synchronization signals of the multiple phases and the corresponding relationship, the memory is controlled to set the read address in sequence.

5. The method according to claim 1, wherein The digital-to-analog converter further includes a frequency divider, and the step of obtaining clock signals of multiple phases includes: receiving a high-frequency clock signal; The high-frequency clock signal is divided by the frequency divider to obtain the clock signals of the multiple phases.

6. The method according to claim 5, characterized in that The frequency-dividing the high-frequency clock signal by the frequency divider to obtain the clock signals of the multiple phases includes: Obtaining a reset pulse of the synchronization signal, and initializing and resetting the frequency divider according to the reset pulse; The high-frequency clock signal is divided by the initialized and reset frequency divider to obtain the clock signals of the multiple phases.

7. The method according to claim 1, characterized in that Before generating a synchronization sequence signal corresponding to each phase synchronization signal according to the phase sequence of the synchronization signals of the multiple phases, the method further includes: Obtaining a falling edge of the synchronization signal, and generating a synchronization sequence reset pulse according to the falling edge; Resetting is performed according to the synchronous sequence reset pulse.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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