A memory and an operating method of the memory

Abstract

The application discloses a memory and an operating method of the memory. The memory comprises a storage array and a peripheral circuit. The peripheral circuit comprises a plurality of gating switch units, a plurality of equalization switches and a plurality of discharge switch units. One end of each gating switch unit is connected to a bit line end of a storage unit structure. The gating switch unit is configured to control an operating state of the storage unit structure. Two ends of each equalization switch are respectively connected to two adjacent gating switch units. Each discharge switch unit is connected to the other end of the gating switch unit. The discharge switch unit is configured to provide a reset voltage signal to one end of the equalization switch in an initialization operation process and to provide a direct current signal to the other end of the gating switch unit in a discharge operation process. In the technical feature, the conduction of the discharge switch unit can reduce the number of voltage changes and improve the read power consumption caused by frequent voltage changes.

Description

Technical Field

[0001] This application relates to the field of phase-change memory technology, specifically to a memory and a method for operating the memory. Background Technology

[0002] PCM (Phase Change Memory) is a type of non-volatile memory that uses the resistance difference of phase change materials to represent data state. During data reading, the storage state of the memory cell is typically determined by the charge sharing between the BL (bit line) and DL (data line).

[0003] In related technologies, the DL voltage needs to be adjusted before, during, and after reading the storage cell structure, and this adjustment process consumes a lot of power. Summary of the Invention

[0004] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by this application is how to improve the power consumption during the reading process of the memory cell structure.

[0005] To address at least one of the aforementioned technical problems, this application discloses a memory and a method for operating the memory.

[0006] According to one aspect of this application, a memory is provided, the memory including a memory array and peripheral circuitry, the memory array including multiple memory cell structures, and the peripheral circuitry electrically connected to the memory cell structures, the peripheral circuitry including:

[0007] Multiple gating switch units, each gating switch unit includes a first terminal and a second terminal, the first terminal is connected to the bit line terminal of any memory cell structure, and the gating switch unit is configured to control the operating state of the memory cell structure;

[0008] Multiple equalizers, each of which has its two ends connected to the second end of two adjacent gating switch units;

[0009] Multiple discharge switch units, each connected to the second terminal of any selector switch unit, are configured as follows:

[0010] During the initialization process, a reset voltage signal is provided to one end of the equalization switch connected to the selected memory cell structure.

[0011] During the discharge operation, a DC signal is provided to the second terminal of the selection switch unit connected to the selected memory cell structure.

[0012] Optionally, the discharge switch unit includes:

[0013] A voltage switch, one end of which is connected to the second terminal of the gating switch unit, and the other end connected to a negative voltage signal, is configured as follows:

[0014] During the initialization process of the selected memory cell structure, the voltage switch is turned on to provide a reset voltage signal to one end of the equalization switch;

[0015] During the discharge operation of the selected memory cell structure, the voltage switch is turned on for a period of time to provide a reset voltage signal to the second terminal of the selection switch unit.

[0016] Optionally, the discharge switch unit further includes:

[0017] A current switch, one end of which is connected to the second terminal of the gating switch unit, and the other end connected to a negative voltage signal, is configured as follows:

[0018] During the discharge operation of the selected memory cell structure, the current switch is turned on to provide a DC signal to the second terminal of the gating switch unit.

[0019] Optionally, the gating switch unit includes:

[0020] The first bit line switch has a fifth terminal and a sixth terminal. The fifth terminal is connected to the bit line terminal of the memory cell structure, and the sixth terminal is connected to the local bit line of the memory array.

[0021] The second line switch has a seventh terminal and an eighth terminal. The seventh terminal is connected to the sixth terminal of the first line switch, and the eighth terminal is connected to the discharge switch unit.

[0022] The gating switch unit is configured such that the first line switch and the second line switch are simultaneously turned on or off.

[0023] Optionally, the equalizer switch has a third terminal and a fourth terminal, and the equalizer switch is configured as follows:

[0024] The third terminal is connected to the selected memory cell structure, and a reference voltage is obtained at the fourth terminal during the discharge operation of the selected memory cell structure.

[0025] Optionally, the peripheral circuit also includes a compensation capacitor, one end of which is connected to the fourth terminal of the equalization switch, and the other end is connected to the discharge switch unit.

[0026] The compensation capacitor is configured to adjust the reference voltage value by adjusting the capacitance value of the compensation capacitor;

[0027] Among them, the reference voltage value is negatively correlated with the opening time of the equalization switch and positively correlated with the capacitance value of the compensation capacitor.

[0028] Optionally, the discharge switching unit includes a voltage switch and a current switch, and the peripheral circuitry of the memory also includes:

[0029] The signal control structure is configured as follows:

[0030] Perform initialization operations, during which the control voltage switch is turned on;

[0031] After the initialization operation, a discharge operation is performed. During the discharge operation phase, the control gating switch unit and the current switch are turned on.

[0032] The read operation is performed after the discharge operation. During the read operation phase, the selected memory cell structure remains on, the voltage switch is off, and the current switch is turned on for a short period of time before being turned off.

[0033] According to a second aspect of this application, a method for operating a memory as described in any of the above-mentioned embodiments is provided, comprising:

[0034] Turn on the discharge switch unit to provide a reset voltage signal to the third terminal of the equalization switch;

[0035] Perform initialization operations to activate the gating switch unit in order to control the operating state of the memory cell structure;

[0036] After the initialization operation, a discharge operation is performed to turn on the discharge switch unit to provide a DC signal to the second terminal of the gating switch unit;

[0037] A read operation is performed after the discharge operation to enable the selected memory cell structure.

[0038] Optionally, the discharge switching unit includes a voltage switch and a current switch; the discharge operation includes a first operation stage and a second operation stage.

[0039] The method includes:

[0040] A voltage switch is turned on to provide a reset voltage signal to the third terminal of the equalization switch; wherein the voltage switch is continuously turned on and turned off during the second operating phase of the discharge operation.

[0041] Optionally, the discharge operation also includes:

[0042] In the first operational phase of the discharge operation, the equalization switch is turned on to generate a reference voltage at its fourth terminal; wherein the on-time of the equalization switch is not greater than the time corresponding to the first operational phase; and,

[0043] In the first phase of the discharge operation, the current switch is turned on to provide a DC signal to the second terminal of the gating switch unit;

[0044] During the second phase of the discharge operation, the voltage switch is turned off, the equalization switch is turned off, and the current switch remains on.

[0045] The peripheral circuit of the memory disclosed in the embodiments of this application can improve the power consumption of the reading process of the memory cell structure.

[0046] Specifically, a discharge switch unit is set in the peripheral circuit, and the discharge switch unit is configured to provide a reset voltage signal to one end of the equalization switch connected to the selected memory cell structure during the initialization operation. This ensures that the voltage at one end of the equalization switch remains at the reset voltage signal before and after reading the selected memory cell structure, reducing the number of voltage changes and thus improving power consumption during the reading process of the selected memory cell structure.

[0047] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of this application, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0049] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0050] Figure 1 A schematic diagram of the structure corresponding to the memory provided for an exemplary embodiment of this disclosure;

[0051] Figure 2 A circuit diagram corresponding to the peripheral circuitry of the memory provided for an exemplary embodiment of this disclosure;

[0052] Figure 3 A voltage variation timing diagram provided for an exemplary embodiment of this disclosure;

[0053] Figure 4 A switching control timing diagram provided for an exemplary embodiment of this disclosure;

[0054] Figure 5 A flowchart illustrating a memory operation method provided for an exemplary embodiment of this disclosure.

[0055] Explanation of reference numerals in the attached figures:

[0056] 1-Memory array, 2-Peripheral circuit, 3-Word line unit, 4-Circuit control structure, 5-Signal control structure, 6-Memory cell structure, 7-Selected memory cell structure;

[0057] 10-Gating switch unit, 11-Local bit line, 20-Discharge switch unit, 30-Compensation capacitor, 40-Comparator;

[0058] S0 - Equalization switch, S1 - Voltage switch, S2 - Current switch, S3 - First position line switch, S4 - Second position line switch;

[0059] Vneg - negative voltage signal, Vref - reference voltage. Detailed Implementation

[0060] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0062] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0063] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0064] In this document, the term "and / or" describes a relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0065] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0066] As described in the background section, the reading process of the memory cell structure requires DL voltage adjustment at different stages, and the voltage adjustment process requires a lot of power consumption.

[0067] Figure 1 This is a schematic diagram of a memory embodiment, such as... Figure 1 The memory includes a storage array 1 and peripheral circuits 2, wherein the storage array 1 has multiple storage cell structures 6, and the peripheral circuits 2 are connected to the storage array 1.

[0068] In some embodiments, the storage array 1 corresponds to at least a portion of the phase-change memory and includes a plurality of word lines (WL), a plurality of bit lines, and a plurality of storage cell structures 6. The storage cell structures 6 are located at the intersection of the WL and BL, and binary data can be written to or read from the storage cell structures 6.

[0069] The memory cell structure 6 can include crystalline and amorphous states, each corresponding to a different voltage threshold. The transition between these states is achieved by applying different forms of heat to the memory cell structure 6. The crystalline state is defined as 1, corresponding to a lower threshold voltage, while the amorphous state is defined as 0, corresponding to a higher threshold voltage. A programming operation to write a "1" to the memory cell structure 6 is defined as a set operation, and a programming operation to write a "0" is defined as a reset operation. By applying a voltage greater than the set state but less than the reset state threshold voltage to the selected memory cell structure 7, the crystalline state memory cell structure 6 can be opened, but the amorphous state memory cell structure 6 cannot be opened, thus completing the state reading of the memory cell structure 6. The voltage threshold corresponding to each memory cell structure 6 is the intrinsic read voltage corresponding to the BL voltage when reading the selected memory cell structure.

[0070] The peripheral circuit 2 includes a word line unit 3, a circuit control structure 4, and a signal control structure 5. The word line unit 3 is configured to determine the target memory level (WL) corresponding to the target memory cell structure. The signal control structure 5 is configured to perform operations associated with the circuit control structure 4, such as controlling the on / off state of switches corresponding to various components of the circuit control structure 4 during the reading of the memory cell structure 6.

[0071] In the embodiment described above, before and after reading any memory cell structure 6 in the memory array 1, the DL voltage needs to be adjusted from the initial signal to the reset voltage signal. After reading the memory cell structure, the DL voltage needs to be adjusted from the reset voltage signal to the initial signal. This voltage adjustment process consumes a lot of power.

[0072] To address the technical problems existing in the above embodiments, this application proposes a peripheral circuit for a memory. By setting a discharge switch unit in the peripheral circuit and configuring the discharge switch unit to provide a reset voltage signal to one end of the equalization switch connected to the selected memory cell structure during the initialization operation, the voltage corresponding to one end of the equalization switch can always maintain the reset voltage signal before and after reading the selected memory cell structure, reducing the number of voltage changes and thus improving the power consumption during the reading process of the selected memory cell structure.

[0073] Figure 2 The circuit diagram corresponding to the peripheral circuitry of the memory provided for an exemplary embodiment of this disclosure is as follows: Figure 1 and Figure 2 As shown, the peripheral circuit 2 of the memory includes a circuit control structure 4.

[0074] Circuit control structure 4 includes:

[0075] Multiple gating switch units 10, each gating switch unit 10 includes a first end and a second end, the first end is connected to the bit line end of any memory cell structure 6, and the gating switch unit 10 is configured to control the operating state of the memory cell structure 6;

[0076] Multiple equalization switches S0, each having a third terminal and a fourth terminal, with the two ends of each equalization switch S0 connected to the second terminals of two adjacent gating switch units 10, respectively.

[0077] Multiple discharge switch units 20, each discharge switch unit 20 being connected to the second terminal of any selector switch unit 10, are configured as follows:

[0078] During the initialization process, a reset voltage signal is provided to one end of the balanced switch S0 connected to the selected memory cell structure 7.

[0079] During the discharge operation, a DC signal is provided to the second terminal of the selection switch unit 10 connected to the selected memory cell structure 7.

[0080] In some embodiments, the peripheral circuit 2 includes a circuit control structure 4, a word line unit 3, and a signal control structure 5. The circuit control structure 4 is configured to select and read a target memory cell structure from a plurality of memory cell structures 6 of the memory array 1 to determine the storage state of the target memory cell structure. The components of the circuit control structure 4 can be equivalent to, for example, Figure 2 The circuit diagram shown is shown. The circuit control structure 4 includes multiple gating switch units 10, multiple equalizing switches S0, and multiple discharging switch units 20. The first end of each gating switch unit 10 is connected to a storage cell structure 6, and the second end is connected to a discharging switch unit 20. The second ends of two adjacent gating switch units 10 are connected to an equalizing switch S0. It can be assumed that the number of storage cell structures 6 is the same as the number of gating switch units 10 and discharging switch units 20, and is greater than the number of equalizing switches S0.

[0081] When the turn-on switch unit 10 is turned on, the corresponding storage cell structure 6 can be considered as the selected storage cell structure 7, i.e., the aforementioned target storage cell structure. When binary data needs to be read from the selected storage cell structure 7, the corresponding operation state is "read," and when binary data needs to be written to the selected storage cell structure 7, the corresponding operation state is "write." This application uses the "read" operation state of the selected storage cell structure 7 as an example for explanation.

[0082] In some embodiments, the gating switch unit 10 includes:

[0083] The first bit line switch S3 has a fifth terminal and a sixth terminal. The fifth terminal is connected to the bit line terminal of the memory cell structure 6, and the sixth terminal is connected to the local bit line 11 of the memory array 1.

[0084] The second line switch S4 has a seventh terminal and an eighth terminal. The seventh terminal is connected to the sixth terminal of the first line switch S3, and the eighth terminal is connected to the discharge switch unit 20.

[0085] The gating switch unit 10 is configured such that the first line switch S3 and the second line switch S4 are simultaneously turned on or off.

[0086] In some embodiments, the selection switch unit 10 includes a first bit line switch S3 connected to the bit line terminal of any memory cell structure 6, and a second bit line switch S4 connected to the first bit line switch S3 and the discharge switch unit 20, respectively. The fifth terminal of the first bit line switch S3 is the first terminal of the selection switch unit 10, and the eighth terminal of the second bit line switch S4 is the second terminal of the selection switch unit 10. The first bit line switch S3 and the second bit line switch S4 remain synchronously turned on or off during the reading process of the selected memory cell structure 7, so that their corresponding voltage signals change synchronously.

[0087] Figure 3 A voltage variation timing diagram provided for an exemplary embodiment of this disclosure. Figure 4 A switching control timing diagram provided for an exemplary embodiment of this disclosure. Combined with... Figure 3 and Figure 4 It can be seen that the conduction or opening of the first line switch S3 is synchronized with the conduction or opening of the second line switch S4, and the BL voltage corresponding to the first line switch S3 and the LBL voltage corresponding to the second line switch S4 change synchronously during the reading process of the selected memory cell structure 7.

[0088] In some embodiments, the discharge switch unit 20 is connected to the gating switch unit 10, and the discharge switch unit 20 is turned on after the gating switch unit 10 is turned on, so as to provide a DC signal to the gating switch unit 10.

[0089] Specifically, such as Figure 2 As shown, the discharge switch unit 20 includes:

[0090] Voltage switch S1, one end of which is connected to the second terminal of gating switch unit 10, and the other end of which is connected to the negative voltage signal Vneg, is configured as follows:

[0091] During the initialization operation of the selected memory cell structure 7, the voltage switch S1 is turned on to provide a reset voltage signal to one end of the equalization switch S0.

[0092] During the discharge operation of the selected memory cell structure 7, the voltage switch S1 is turned on for a period of time to provide a reset voltage signal to the second terminal of the selection switch unit 10.

[0093] In some embodiments, the discharge switch unit 20 includes a voltage switch S1, one end of which is connected to the eighth terminal of the second bit line switch S4, and the other end is connected to the negative voltage signal Vneg. During the reading of the selected memory cell structure 7, the voltage switch S1 is configured to perform different functions at different operation stages.

[0094] Please see Figure 2 as well as Figure 4 In the inactive phase p1 and the initialization phase p2, when the voltage switch S1 is turned on, the voltage switch S1 can provide a reset voltage signal to the third terminal of the equalization switch S0, so that the voltage value of the DL voltage corresponding to the third terminal remains unchanged.

[0095] During the discharge operation phases p3-p4, voltage switch S1 is turned on in phase p3 and turned off in phase p4. Voltage switch S1 provides a reset voltage signal to the first line switch S3 and the second line switch S4, so that the BL voltage and LBL voltage can change from 0V to the voltage value corresponding to the reset voltage signal. The voltage value of the reset voltage signal is equal to the voltage value of the negative voltage signal Vneg.

[0096] The discharge switch unit 20 also includes:

[0097] The current switch S2 has one end connected to the second terminal in the gating switch unit 10, and the other end connected to the negative voltage signal Vneg. The current switch S2 is configured as follows:

[0098] During the discharge operation of the selected memory cell structure 7, the current switch S2 is turned on to provide a DC signal to the second terminal of the gating switch unit 10.

[0099] In some embodiments, one end of the current switch S2 is connected to the eighth terminal of the second bit line switch S4, and the other end is connected to the negative voltage signal Vneg. When the current switch S2 is turned on, it can provide a DC signal to the first bit line switch S3 and the second bit line switch S4. This DC signal can be a DC current. By introducing a DC signal, it can be ensured that the voltage value of BL remains at the value corresponding to the reset voltage signal until the selected memory cell structure 7 is turned on.

[0100] In some embodiments, please refer to Figures 3 to 4 Because voltage switch S1 is continuously conducting from stage p1 to p3, the DL voltage corresponding to the third terminal of equalization switch S0 and the UnselDL voltage corresponding to the fourth terminal of equalization switch S0 are both maintained at the reset voltage signal. When the first line switch S3 and the second line switch S4 are turned on in stage p2, the BL voltage and LBL voltage change synchronously from 0V to the reset voltage signal due to the conduction of the first line switch S3 and the second line switch S4. At the same time, in stage p3, current switch S2 is also turned on, providing a DC signal to the first line switch S3 and the second line switch S4, so that the BL voltage is unaffected and always remains stable at the reset voltage signal before the selected memory cell structure 7 is turned on.

[0101] Please continue reading. Figure 2The equalization switch S0 is configured such that its third terminal is connected to the selected memory cell structure 7, and during the discharge operation of the selected memory cell structure 7, a reference voltage Vref is obtained at its fourth terminal.

[0102] In some embodiments, the equalization switch S0 is connected to the second end of two adjacent gating switch units 10, that is, to the eighth end of the second bit line switch S4 of the two adjacent gating switch units 10. One end of the equalization switch S0 is connected to the selected memory cell structure 7 through the gating switch unit 10, and the other end is connected to the unselected memory cell structure 7 through the gating switch unit 10.

[0103] In some embodiments, the equalization switch S0 includes a third terminal and a fourth terminal. The third terminal is connected to the selected memory cell structure 7, and the fourth terminal is connected to the unselected memory cell structure 7. The third terminal corresponds to the DL voltage, and the fourth terminal corresponds to the Unsel DL voltage. During the p5-p7 phase of the read operation, the Unsel DL voltage value is the reference voltage Vref.

[0104] In some embodiments, by introducing a DC signal through the current switch S2, the equalization switch S0 can be equivalent to a finite resistor, the effective resistance value of which is related to the size of the selected memory cell structure 7. The discharge process after the equalization switch S0 is turned on can be equivalent to:

[0105] I*Δt=C*ΔV

[0106] Where Δt is the conduction time of the equalization switch S0, C is the capacitance value during the discharge process, and I is the current flowing through the equalization switch S0, then the Unsel DL voltage, i.e., the reference voltage Vref, is:

[0107] Vref=ΔV=-I*Δt / C

[0108] In this context, positive and negative can represent the direction of current. Charging a capacitor can be considered as positive current, and discharging a capacitor as negative current.

[0109] Please continue reading. Figure 2 The circuit control structure also includes a compensation capacitor 30, one end of which is connected to the fourth terminal of the equalization switch S0, and the other end is connected to the discharge switch unit 20.

[0110] The compensation capacitor 30 is configured to adjust the voltage value of the reference voltage Vref by adjusting the capacitance value of the compensation capacitor 30.

[0111] In some embodiments, one end of the compensation capacitor 30 is connected to the fourth terminal of the equalization switch S0 corresponding to the selected memory cell structure 7, and the other end is connected to the discharge switch unit 20 corresponding to the unselected memory cell structure 7.

[0112] In some embodiments, the first line switch S3 corresponds to a first parasitic capacitance, the second line switch S4 corresponds to a second parasitic capacitance, and the third terminal of the equalization switch S0 corresponds to a third parasitic capacitance. The capacitance value during the discharge process may include the sum of the first parasitic capacitance, the second parasitic capacitance, the third parasitic capacitance, and the capacitance value of the compensation capacitor 30.

[0113] In some embodiments, as shown in the above formula, the reference voltage Vref is positively correlated with the on-time of the equalization switch S0 and negatively correlated with the capacitance value during the discharge process. Therefore, a compensation capacitor 30 is introduced at the fourth terminal of the equalization switch S0, and the reference voltage Vref is adjusted by adjusting the capacitance value of the compensation capacitor 30. Alternatively, the reference voltage Vref can also be adjusted by adjusting the on-time of the equalization switch S0.

[0114] Please continue reading. Figure 2 The circuit control structure 4 also includes a comparator 40, whose input terminals are connected to the third and fourth terminals of the equalization switch S0, respectively, and whose output terminal outputs a read signal.

[0115] In some embodiments, the circuit control structure 4 further includes a comparator 40 connected to both ends of the equalization switch S0. The comparator 40 acquires and compares the DL voltage and the UnselDL voltage, and outputs the comparison result as the read signal corresponding to the selected memory cell structure 7. The read signal represents the storage state corresponding to the selected memory cell structure 7.

[0116] In some embodiments, the third terminal of the equalization switch S0 is connected to the eighth terminal of the second bit line switch S4, and the second bit line switch S4 and the first bit line switch S3 are synchronously turned on, so that the voltage values ​​of DL voltage, BL voltage, and LBL voltage are equal and change synchronously. The fourth terminal of the equalization switch S0 corresponds to the Unsel DL voltage, and the voltage value of the Unsel DL voltage is equal to the reference voltage Vref during the read operation. Therefore, the comparator 40 connected to both ends of the equalization switch S0 can acquire the DL voltage and the Unsel DL voltage respectively. By comparing the DL voltage and the Unsel DL voltage, the relationship between the BL voltage and the reference voltage Vref can be determined, and then a read signal can be output to determine the storage state corresponding to the selected storage cell structure 7. The storage state includes a "0" state and a "1" state.

[0117] Please continue reading. Figure 3It can be seen that when the selected memory cell structure 7 is in the "0" state, the voltage value of BL remains unchanged from the reset voltage signal and is less than the voltage value of the reference voltage Vref. When the selected memory cell structure 7 is in the "1" state, the voltage value of BL increases from the reset voltage signal and is greater than the voltage value of the reference voltage Vref.

[0118] Figure 3 In the voltage change timing diagram shown, because the current may be too large under non-ideal conditions, when the selected memory cell structure 7 is in the "1" state, the BL voltage experiences a partial drop during the charging process before stabilizing. If it is considered as an ideal state, the BL voltage will not be affected by the current, will charge up and stabilize, and there will be no drop.

[0119] Please see Figure 1 The peripheral circuit 2 of the memory also includes: a signal control structure 5, configured as follows:

[0120] An initialization operation is performed, during which the voltage switch S1 is turned on.

[0121] After the initialization operation, a discharge operation is performed. During the discharge operation phase, the control gating switch unit 10 and the current switch S2 are turned on.

[0122] After the discharge operation, the read operation is performed. During the read operation phase, the selected memory cell structure 7 remains open, the voltage switch S1 is turned off, and the current switch S2 is turned on for a period of time before being turned off.

[0123] In some embodiments, the signal control structure 5 is configured to control the on and off states of each switch. Please refer to... Figure 3 as well as Figure 4 , Figure 3 as well as Figure 4 In the diagram, stage p1 corresponds to the inactive stage, stage p2 corresponds to the initialization stage, stages p3 and p4 correspond to the discharge stage, and stages p5-p7 correspond to the read stage.

[0124] according to Figure 4 It can be seen that, under the control of signal control structure 5, voltage switch S1 is continuously turned on from stage p1 to stage p3 and turned off from stage p4 to stage p7; current switch S2 is turned on in stage p3 and continuously turned on from stage p3 to stage p6, and turned off in stage p7; first line switch S3 and second line switch S4 are turned on in stage p2 and continuously turned on from stage p2 to stage p7, and turned off in the next stage p1; equalization switch S0 is turned on in stage p3 and turned off in stage p4, and its on-time is less than or equal to the time corresponding to stage p3. The specific on-time can be adaptively adjusted according to the voltage value of reference voltage Vref.

[0125] In some embodiments, the word line unit 33 further includes a word line switch, the specific location of which is not shown in the figure, but it is clear that one end of it is connected to the word line corresponding to the selected memory cell structure 7, and in combination with... Figure 3 as well as Figure 4 It can be seen that the WL switch is turned on in stage p4 and continues to be turned on until stage p6, and is turned off in stage p7, so that the WL voltage increases in stage p4 and decreases in stage p7.

[0126] Accordingly, this application also provides a memory, including:

[0127] Storage array 1, comprising multiple storage cell structures 6;

[0128] like Figure 2 The peripheral circuit 2 shown is connected to the storage array 1. During the reading process of the storage cell structure 6, the signal control structure 5 controls the circuit control structure 4 to obtain the following... Figure 3 and Figure 4 The temporal changes are shown.

[0129] Accordingly, this application also discloses a method for operating a memory, such as... Figure 5 As shown, it includes:

[0130] S10: In the inactive phase p1, the voltage switch S1 is turned on to provide a reset voltage signal Vneg to the third terminal of the equalization switch S0;

[0131] In some embodiments, the inactive phase may correspond to a phase where the selected memory cell structure 7 is not read, or it may correspond to a state where the memory cell structure 6 is not selected. Please refer to [link to documentation]. Figure 3 as well as Figure 4 At this time, voltage switch S1 is turned on and the other switches are turned off, so that the DL voltage and Unsel DL voltage corresponding to the two ends of equalization switch S0 are both maintained at the reset voltage signal Vneg.

[0132] In addition, since the first line switch S3 and the second line switch S4 are turned off in the p1 stage, the BL voltage and LBL voltage can be 0V, preventing the selected memory cell structure 7 from being accidentally turned on in the non-operation stage.

[0133] In other embodiments, the first bit line switch S3 may be turned off and the second bit line switch S4 may be turned on, so that the BL voltage remains at 0V during the p1 phase and the LBL voltage remains at the reset voltage signal Vneg.

[0134] S20: Initialization operation phase p2, turn on the first bit line switch S3 and the second bit line switch S4 to control the operation state of the memory cell structure 6;

[0135] In some embodiments, please refer to Figure 3 as well as Figure 4 The first bit line switch S3 and the second bit line switch S4 are turned on, making memory cell structure 6 the selected memory cell structure 7. Since the voltage switch S1, which provides the reset voltage signal, is already turned on in stage p1, the BL voltage and LBL voltage can change in stage p2, from 0V to the reset voltage signal Vneg.

[0136] Because the bit line BL and the local bit line 11LBL are at different distances from the address decoder, the BL voltage, which is closer to the address decoder, is pulled down first, while the LBL voltage, which is farther from the address decoder, is pulled down later. This disperses the overshoot current's duration. Furthermore, because the BL capacitor is very small, the overshoot current on the power supply is much smaller compared to the traditional method, thereby improving the stability of the read voltage.

[0137] In some embodiments, combined with Figure 3 As can be seen from the voltage changes, the DL voltage and UnselDL voltage are at the reset voltage signal Vneg in stage p1. In stage p2, the BL voltage and LBL voltage change from 0V to the reset voltage signal Vneg due to the conduction of the first bit line switch S3 and the second bit line switch S4. Compared with related technologies that simultaneously adjust the BL voltage, LBL voltage, DL voltage and UnselDL from 0V to the reset voltage signal Vneg, the time for BL to perform charge sharing can be saved, thereby shortening the time for reading the selected memory cell structure 7 and improving the reading efficiency of the memory cell structure 6.

[0138] S30: During the discharge operation phase p3, the current switch S2 is turned on to provide a DC signal to the second terminal of the gating switch unit 10; and the equalization switch S0 is turned on to generate a reference voltage Vref at the fourth terminal of the equalization switch S0.

[0139] S40: During the discharge operation phase p4, the voltage switch S1 and the equalization switch S0 are turned off; and the WL switch is turned on so that the WL voltage increases.

[0140] In some embodiments, please refer to Figure 3 as well as Figure 4 After initialization, a discharge operation is performed. In phase p3, current switch S2 is turned on and provides a DC signal. The introduction of this DC signal ensures that the BL voltage remains constant before the selected memory cell structure 7 is turned on, and the BL voltage is not affected by the subthreshold on-current and capacitance before the selected memory cell structure 7 is turned on.

[0141] In the p3 stage, which is the first operation stage of the discharge operation, the equalization switch S0 is turned on, and the third and fourth terminals of the equalization switch S0 are connected. The equalization switch S0 is equivalent to a finite resistor and generates a reference voltage Vref, so that the voltage value of the Unsel DL voltage at the third terminal is equal to the voltage value of the reference voltage Vref.

[0142] After the BL voltage, DL voltage, and LBL voltage remain stable in stage p3, the WL switch is turned on in stage p4, which is the second operating stage of the discharge operation, and the WL voltage increases.

[0143] S50: During the read operation phase p5-p6, the selected memory cell structure 7 is turned on, and the first bit line switch S3, the second bit line switch S4, and the current switch S2 are continuously turned on.

[0144] S60: During the read operation phase p7, the selected memory cell structure 7 remains on, the current switch S2 and the WL switch are off, and the first bit line switch S3 and the second bit line switch S4 are on.

[0145] In some embodiments, please refer to Figure 3 and Figure 4 The read operation is performed after the discharge operation. During the p5-p6 phase, the WL switch remains on. When the WL voltage stabilizes, the BL voltage is charged high, and the LBL and DL voltages change synchronously with the BL voltage. At this time, the selected memory cell structure 7 is turned on. When cell = 1 (i.e., the selected memory cell structure 7 is in a "1" state), the BL voltage is greater than the reference voltage Vref; when cell = 0 (i.e., the selected memory cell structure 7 is in a "0" state), the BL voltage is less than the reference voltage Vref.

[0146] In some embodiments, during p5 and p6, the current switch S2 remains on while the selected memory cell structure 7 is turned on, providing a DC signal so that the temperature of the selected memory cell structure 7 after being turned on can slowly decrease from a relatively high temperature to the crystallization temperature. The turned-on selected memory cell structure 7 remains in a crystalline state, which helps to improve the read interference problem caused by the large overshoot current when the selected memory cell structure 7 is turned on.

[0147] During the p7 stage, after the reading is completed, the WL switch is turned off, and the WL voltage gradually decreases; the current switch S2 is turned off, and the BL voltage, DL voltage, LBL voltage, and UnselDL voltage return to 0V.

[0148] By employing the aforementioned memory operation method, issues such as read interference, read voltage accuracy, and read success rate during the read process of the selected memory cell structure 7 can be improved, thereby enhancing the reliability of the read process. Simultaneously, since the voltage switch S1 remains continuously conducting during the inactive, initialization, and partial discharge phases, the DL voltage and Unsel DL voltage can be adjusted to the reset voltage signal Vneg before and after operation on the selected memory cell structure 7, reducing the frequency of voltage changes and mitigating read power consumption caused by frequent voltage fluctuations.

[0149] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0150] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0151] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0152] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent variations, or alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the market of the various embodiments, or to enable other persons skilled in the art to understand the various embodiments disclosed herein.

Claims

1. A memory, the memory comprising a memory array and peripheral circuitry, the memory array comprising a plurality of memory cell structures, the peripheral circuitry being electrically connected to the memory cell structures, characterized in that, The peripheral circuit includes: Multiple gating switch units, each gating switch unit including a first terminal and a second terminal, the first terminal being connected to the bit line terminal of any memory cell structure, the gating switch unit being configured to control the operating state of the memory cell structure; Multiple equalization switches, each of which has its two ends connected to the second ends of two adjacent gating switch units; A plurality of discharge switching units, each of which is connected to the second terminal of any of the gating switching units, wherein each discharge switching unit includes a voltage switch and a current switch connected in parallel, and is configured as follows: During the initialization process, the voltage switch is turned on, providing a reset voltage signal to one end of the selected memory cell structure connected to the equalization switch; During the discharge operation, the current switch is turned on, providing a DC signal to the second terminal of the gating switch unit connected to the selected memory cell structure.

2. The memory according to claim 1, characterized in that, The voltage switch has one end connected to the second terminal of the gating switch unit and the other end connected to a negative voltage signal. The voltage switch is configured as follows: During the discharge operation of the selected memory cell structure, the voltage switch is turned on for a portion of the time to provide the reset voltage signal to the second terminal of the selection switch unit.

3. The memory according to claim 2, characterized in that, The current switch has one end connected to the second end of the gating switch unit and the other end connected to the negative voltage signal.

4. The memory according to claim 1, characterized in that, The gating switch unit includes: The first bit line switch has a fifth terminal and a sixth terminal, the fifth terminal being connected to the bit line terminal of the memory cell structure, and the sixth terminal being connected to the local bit line of the memory array; The second position line switch has a seventh terminal and an eighth terminal, the seventh terminal being connected to the sixth terminal of the first position line switch, and the eighth terminal being connected to the discharge switch unit; The gating switch unit is configured such that the first bit line switch and the second bit line switch are synchronously turned on or off.

5. The memory according to claim 1, characterized in that, The equalizer switch has a third terminal and a fourth terminal, and the equalizer switch is configured as follows: The third terminal is connected to the selected memory cell structure, and a reference voltage is obtained at the fourth terminal during the discharge operation of the selected memory cell structure.

6. The memory according to claim 5, characterized in that, The peripheral circuit also includes a compensation capacitor, one end of which is connected between the fourth terminal of the equalization switch and the discharge switch unit, and the other end is connected to a voltage signal. The compensation capacitor is configured to adjust the voltage value of the reference voltage by adjusting the capacitance value of the compensation capacitor. The reference voltage value is negatively correlated with the opening time of the equalization switch and positively correlated with the capacitance value of the compensation capacitor.

7. The memory according to claim 1, characterized in that, The peripheral circuit also includes: The signal control structure is configured as follows: An initialization operation is performed, during which the voltage switch is turned on. After the initialization operation, a discharge operation is performed. During the discharge operation, the gating switch unit and the current switch are controlled to be turned on. A read operation is performed after the discharge operation. During the read operation phase, the selected memory cell structure remains on, the voltage switch is off, and the current switch is turned off after being turned on for a partial time.

8. A method of operating a memory as described in any one of claims 1-7, characterized in that, include: Turn on the voltage switch to provide a reset voltage signal to the third terminal of the equalization switch; An initialization operation is performed to activate the gating switch unit, thereby controlling the operating state of the memory cell structure; After the initialization operation, a discharge operation is performed to turn on the current switch to provide a DC signal to the second terminal of the gating switch unit; A read operation is performed after the discharge operation to enable the selected memory cell structure.

9. The method of operating the memory according to claim 8, characterized in that, The discharge operation includes a first operation phase and a second operation phase; The equalization switch has a third terminal; The method includes: The voltage switch is turned on to provide a reset voltage signal to the third terminal of the equalization switch; wherein the voltage switch is continuously turned on and turned off during the second operation phase of the discharge operation.

10. The method of operating the memory according to claim 9, characterized in that, The discharge operation also includes: In the first operational phase of the discharge operation, the equalization switch is turned on to generate a reference voltage at its fourth terminal; wherein the on-time of the equalization switch is not greater than the time corresponding to the first operational phase; and, During the first operation phase of the discharge operation, the current switch is turned on to provide the DC signal to the second terminal of the gating switch unit; During the second operation phase of the discharge operation, the voltage switch is turned off, the equalization switch is turned off, and the current switch remains on.

Images