Double-polishing epitaxy process for reducing back defects
By growing an LTO layer on the back of the silicon wafer and combining it with HF and RCA cleaning, the problem of scratches on the back of the silicon wafer is solved and the yield rate of the double-throw epitaxial process is improved.
Patent Information
- Application Number
- CN202510718948.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-05
AI Technical Summary
In the existing double-throw epitaxial growth process, the back side of the silicon wafer is easily scratched during the epitaxial growth, visual inspection, and FTIR processes, resulting in a low yield rate.
After polishing the back of the silicon wafer, an LTO layer is grown, and HF and RCA cleaning are used during epitaxy and subsequent processes to prevent scratches.
It effectively reduces the scratch rate on the back of silicon wafers to below 5%, significantly improving the yield rate.
Smart Images
Figure CN120600623A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of epitaxial silicon wafer preparation, in particular to a double-throw epitaxial process for reducing backside defects. Background Art
[0002] In semiconductor manufacturing and precision materials processing, some silicon wafers require double-sided polishing (DSP). This is primarily due to the wafer's application scenario, performance requirements, and the specificities of subsequent processes. Some single-sided epitaxial silicon wafers also require double-sided polishing. This is primarily because the backside, when etched, is relatively rough and uneven. When the backside contacts the photolithography platform, it can affect the flatness of the front side during photolithography, leading to photolithography failure.
[0003] Existing conventional double-throw epitaxial process such as Figure 2 As shown, first, because epitaxial growth is performed on the front side of a double-sided polished silicon wafer, the furnace's robotic arm contacts the back side of the wafer as the polished wafer is loaded and unloaded. Because the back side is polished and easily scratched, this process results in a certain percentage of scratches. Secondly, the visual inspection station requires a suction pen to contact the back side of the silicon wafer. Finally, the FTIR equipment robotic arm contacts the back side of the silicon wafer, and the ADE robotic arm also contacts the back side of the silicon wafer. All three processes result in varying degrees of scratches, resulting in a backside scratch rate of approximately 80% in the final silicon wafer product, resulting in a very low yield. Summary of the Invention
[0004] The present invention aims to provide a double-throw epitaxial growth process for reducing backside defects, so as to significantly improve the yield rate of double-throw epitaxial silicon wafers.
[0005] In order to solve the above technical problems, the specific solution adopted by the present invention is: a double-polishing epitaxial growth process for reducing back-side defects, first polishing the back of the silicon wafer and then growing a layer of LTO layer, then polishing the front of the silicon wafer and performing RCA cleaning on the silicon wafer, and after cleaning, performing epitaxial treatment on the front of the silicon wafer. After the epitaxial treatment, it is visually inspected, FTIR and ADE, and then HF cleaning and RCA cleaning are performed in sequence.
[0006] Preferably, the thickness of the LTO layer is greater than
[0007] Preferably, the LTO layer is deposited on the back side of the silicon wafer by chemical vapor deposition at 300-500°C.
[0008] Preferably, the reaction gases are silane and oxygen.
[0009] Preferably, in HF cleaning, the ratio of HF to water in the HF aqueous solution is 1:(30-40).
[0010] Preferably, the silicon wafer is immersed in the HF aqueous solution for 8-10 minutes.
[0011] Preferably, in RCA cleaning, first cleaning is performed with a solution prepared from hydrogen peroxide, ammonia and deionized water, wherein the volume ratio of hydrogen peroxide, ammonia and deionized water is 1:1:16-1:1:20; then cleaning is performed with a solution prepared from hydrogen peroxide, hydrochloric acid and deionized water, wherein the volume ratio of hydrogen peroxide, hydrochloric acid and deionized water is 1:1:16-1:1:20.
[0012] Preferably, after RCA cleaning and HF cleaning, the silicon wafer is rinsed with deionized water.
[0013] In the present invention, on the basis of polishing the back side of the silicon wafer, an LTO layer is grown on the back side. The LTO layer can effectively prevent scratches on the back side polished surface caused by the front side epitaxial growth process and post-epitaxial visual inspection, FTIR, ADE and other processes, so that the final back side scratch ratio of the silicon wafer is controlled below 5%, thereby greatly improving the yield rate.
[0014] Furthermore, the LTO layer can be removed by soaking in an aqueous HF solution without negatively impacting the polished surface. HF cleaning is a necessary and routine cleaning step after epitaxial growth and inspection of silicon wafers to remove the oxide layer on the surface of the silicon wafer, expose a clean silicon surface, and prevent re-adsorption of metal ions. In other words, except for growing an LTO layer after polishing the backside of the silicon wafer, the process of the present invention is identical to conventional processes, thus reducing the difficulty of implementation and facilitating its widespread adoption. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a process flow chart of the present invention;
[0016] Figure 2 This is the process flow chart for conventional double-polished outer edge silicon wafers. DETAILED DESCRIPTION
[0017] like Figure 1 As shown in the figure, a double polishing epitaxial process for reducing back defects of the present invention first polishes only the back side of the silicon wafer, then performs back sealing treatment, and grows an LTO layer on the back side with a thickness of The wafer is then polished on the front side, cleaned with RCA, and subjected to epitaxy. Finally, the wafer undergoes visual inspection, FTIR, and ADE, followed by HF cleaning and RCA cleaning to complete the fabrication process. This LTO layer effectively prevents scratches on the polished back side of the wafer during the front epitaxy process and subsequent visual inspection, FTIR, and ADE. The LTO layer can be removed by soaking in HF aqueous solution for 8-10 minutes without any negative impact on the polished back side.
[0018] The LTO layer in this embodiment is deposited on the back of the silicon wafer by chemical vapor deposition at 300-500° C. The reaction gases are silane and oxygen.
[0019] During HF cleaning, the silicon wafer is immersed in an HF aqueous solution for 8-10 minutes. The ratio of HF to water in the HF aqueous solution is 1:30-40.
[0020] In RCA cleaning, first use a solution prepared with hydrogen peroxide, ammonia and deionized water as RCA1 solution for cleaning, and the volume ratio of hydrogen peroxide, ammonia and deionized water is 1:1:16-1:1:20; then use a solution prepared with hydrogen peroxide, hydrochloric acid and deionized water as RCA2 solution for cleaning, and the volume ratio of hydrogen peroxide, hydrochloric acid and deionized water is 1:1:16-1:1:20.
[0021] After the above RCA cleaning and HF cleaning, the silicon wafers are rinsed with deionized water.
Claims
1. A double-throw epitaxial growth process for reducing backside defects, characterized by: First, the back of the silicon wafer is polished and an LTO layer is grown. Then, the front of the silicon wafer is polished and RCA cleaned. After cleaning, the front of the silicon wafer is epitaxially treated. After epitaxial treatment, it is visually inspected, FTIR and ADE are performed, and then HF cleaning and RCA cleaning are performed in sequence.
2. The double-throw epitaxial process for reducing backside defects according to claim 1, wherein: The thickness of the LTO layer is greater than 3. The double-throw epitaxial process for reducing backside defects according to claim 1, wherein: The LTO layer is deposited on the back of the silicon wafer by chemical vapor deposition at 300-500°C.
4. The double-throw epitaxial growth process for reducing backside defects according to claim 3, wherein: The reaction gases are silane and oxygen.
5. The double-throw epitaxial growth process for reducing backside defects according to claim 1, wherein: In HF cleaning, the ratio of HF to water in the HF aqueous solution is 1:(30-40).
6. The double-throw epitaxial growth process for reducing backside defects according to claim 3, wherein: Soak the silicon wafer in HF aqueous solution for 8-10 minutes.
7. The double-throw epitaxial growth process for reducing backside defects according to claim 1, wherein: During RCA cleaning, first use a solution of hydrogen peroxide, ammonia and deionized water for cleaning, with the volume ratio of hydrogen peroxide, ammonia and deionized water being 1:1:16-1:2:20; then use a solution of hydrogen peroxide, hydrochloric acid and deionized water for cleaning, with the volume ratio of hydrogen peroxide, hydrochloric acid and deionized water being 1:1:16-1:1:
20.
8. The double-throw epitaxial growth process for reducing backside defects according to claim 1, wherein: After RCA cleaning and HF cleaning, the silicon wafers were rinsed with deionized water.