Optoelectronic device including light emitting diodes stacked on photodetector

Abstract

An optoelectronic device includes a control circuit, a pixel including a photodetector, a light emitting diode, and an intermediate region between the photodetector and the light emitting diode. The photodetector is sensitive to the detection wavelength lambda2. The light emitting diode includes an active stack having a wavelength shorter than a cutoff wavelength [lambda] c of [lambda] 2, and a buried electrode interposed between the interconnection stack of the circuit and the active stack, and the light emitting diode covers a detection surface of the photodetector. The device further includes a via penetrating the active stack and extending to the interconnect stack; an electric contact portion penetrating through the active stack and contacting the buried electrode; and an electrical path electrically connecting the buried electrode to the control circuit, and including an electrical through contact and a through hole. The intermediate region is free of metal and the buried electrode is transparent to [lambda] 2.

Description

Technical Field

[0001] The field of the invention is optoelectronic devices that combine the functions of emitting light and detecting a light flow. For example, the invention relates to an interactive display screen comprising a matrix of light-emitting diodes controlled by a control circuit and a matrix sensor. The invention also relates to a method for manufacturing such a device. Background Art

[0002] Display screens have benefited from technological advances in light-emitting diodes (LEDs) for lighting. Consequently, screens of various sizes are available, for example, using LEDs based on gallium nitride (GaN). Among these screens, microscreens typically consist of a large number of LEDs, typically less than 10 μm in size, arranged in a matrix. Each LED constitutes a pixel in the microscreen. GaN-based microscreens offer high brightness and good resolution, are compact, and typically consume low current.

[0003] Recently, a new type of screen has emerged, known as an interactive screen. One type of interactive screen combines a matrix of light-emitting diodes with a matrix photon sensor, both powered and controlled by a control circuit. This combination enables new applications that require a response from the interactive screen itself and / or from the system in which it is integrated, based on the light flow detected and / or measured by the matrix sensor. A matrix photon sensor is an optoelectronic component consisting of multiple photodetectors arranged in a matrix. When each photodetector of the photon sensor is arranged opposite a corresponding light-emitting diode, the interactive screen is compact and has good resolution.

[0004] Patent application EP4148810 provides an example of such an interactive screen based on GaN LEDs. In this document, an integrated circuit comprises a first substrate and multiple interconnect layers on the first substrate. The first substrate also incorporates a photon sensor comprising a matrix of photodiodes. On a second substrate, the matrix of LEDs is implemented using epitaxial layers based on AlInGaN and / or InGaN and / or AlGaN and / or GaN. The LEDs are separated from each other by a grid formed of conductive material, each grid being electrically insulated from the LEDs. Thus, the LEDs are independent of each other.

[0005] The first substrate and the second substrate are respectively provided with a first metal bonding pad flush with the surface of the first dielectric layer and a second metal bonding pad flush with the surface of the second dielectric layer. The second substrate is transferred to the first substrate by direct bonding of the first bonding pad and the second bonding pad to the mixture of the first dielectric layer and the second dielectric layer. To this end, the occupancy of the first bonding pad and the second bonding pad on each side is between 60% and 90%. At the end of this step, each light-emitting diode that has been singulated before the transfer is separated from the photodiode by bonding the first bonding pad to the second bonding pad and arranged to face the photodiode, and the second bonding pad itself is in contact with the second electrode of the light-emitting diode. The second electrode is metallic and reflective. The assembly consisting of the first interconnection pad, the second interconnection pad and the second electrode constitutes a single buried electrode of the light-emitting diode. Each buried electrode is the anode electrode of a single light-emitting diode. The light-emitting diode has a common cathode made of indium tin oxide (ITO).

[0006] In this configuration, the photodiode receives incident light flux on a portion of the detection surface that is not vertically aligned with the buried electrode. This incident light flux may originate from an opposing light-emitting diode or from an external scene. Therefore, the photodiode receives only the portion of the incident light flux that is not blocked by the buried electrode. This portion of the incident light flux is received, for example, through an aperture formed in the second electrode, which is concentric with the wider aperture formed in the first and second bonding pads. Increasing the surface area of ​​the second electrode results in an increase in the quantum efficiency of the light-emitting diode, thereby reducing the amount of light reaching the photodiode.

[0007] The end result is a compromise between the sensitivity of the photon sensor and the emission efficiency of the LED matrix. Summary of the Invention

[0008] The present invention aims to at least partially overcome the disadvantages of the prior art and, more particularly, to provide an optoelectronic device comprising a light-emitting diode stacked on a photodetector, the device having improved sensitivity to incident light flux without reducing the emission efficiency of the light-emitting diode. The optoelectronic device of the present invention is particularly advantageous when used in a laboratory-on-chip type system.

[0009] To this end, the present invention relates to an optoelectronic device comprising: a substrate; a control circuit integrated in and / or on the substrate, the control circuit comprising an interconnect stack; and a matrix of at least one pixel. Each pixel comprises a photodetector, a light-emitting diode, and an intermediate region between the photodetector and the light-emitting diode. Each pixel is such that: the photodetector is sensitive to a detection wavelength λ2, and the photodetector comprises a detection surface extending in a plane substantially parallel to the main plane of the substrate. The light-emitting diode comprises: a light having a cut-off wavelength λ c Active stack, cutoff wavelength λ c is shorter than the detection wavelength λ2. The active stack includes a first doping layer and a second doping layer of opposite types. The light emitting diode also includes a buried electrode in contact with the second doping layer. The light emitting diode is arranged so that the buried electrode is between the interconnect stack and the active stack and covers the detection surface. Each pixel is such that: the intermediate region is defined by the detection surface and extends from the detection surface to the active stack. The optoelectronic device also includes: a through-hole that completely passes through the active stack and extends to the interconnect layer of the interconnect stack; an electrical contact that completely passes through the active stack and contacts the buried electrode; an electrical path that electrically connects the buried electrode to the control circuit and includes an electrical through-contact and a through-hole. The intermediate region is free of metal and the buried electrode is transparent to the detection wavelength λ2.

[0010] Some preferred but non-limiting aspects of the optoelectronic device are as follows.

[0011] The optoelectronic device may be such that, for each pixel, the light-emitting diode may include an active region extending between a first doped layer and a second doped layer in a plane substantially parallel to the main plane; a conductive trench may surround the active region and the intermediate region, the conductive trench may completely pass through the active stack and may extend to an interconnect layer of the interconnect stack; and a surface electrode, the surface electrode being in contact with the first doped layer and being electrically connected to the control circuit through the conductive trench.

[0012] The optoelectronic device can be such that, for each pixel, the light-emitting diode includes: an active area, which extends between a first doped layer and a second doped layer in a plane substantially parallel to the main plane; a conductive trench, which surrounds the active area and the intermediate area, can completely pass through the active stack and can extend to the interconnection layer of the interconnection stack; and a surface electrode in contact with the first doped layer, the surface electrode being electrically connected to the control circuit through the conductive trench.

[0013] Optoelectronic devices may be such that the conductive trench is coated with a reflective mirror.

[0014] The matrix may comprise a plurality of pixels, and the surface electrode may be an electrode common to all pixels.

[0015] The conductive trenches of two adjacent pixels may have a common portion.

[0016] The intermediate region may comprise an optically functional intermediate layer extending parallel to the main plane of the substrate.

[0017] For each pixel, the buried electrode can be made of indium tin oxide, zinc oxide doped with aluminum, or tin dioxide.

[0018] For each pixel, the surface electrode can be made of indium tin oxide, zinc oxide doped with aluminum.

[0019] The optoelectronic device may further include an optically functional surface layer disposed on a side of the optoelectronic device opposite to the substrate.

[0020] The optically functional surface layer may be an absorption layer comprising openings facing the detection surface.

[0021] The optoelectronic device may further include a heating element disposed on a face of the optoelectronic device opposite to the substrate, and the heating element may include an opening facing the detection surface.

[0022] The detection wavelength λ2 may belong to the visible spectrum, and the light emitting diode may be capable of emitting a light flux in the long-wave ultraviolet UVA range.

[0023] The present invention also relates to a method for manufacturing an optoelectronic device comprising a light-emitting diode and a photodetector sensitive to a detection wavelength λ2. The method comprises the following steps: providing a first assembly comprising, in this order, a first substrate, a semiconductor stack, and a lower conductive layer, such that the semiconductor stack comprises a first doped layer of a first conductivity type and a second doped layer of a second conductivity type opposite to the first conductivity type, and such that the lower conductive layer is in physical contact with the second doped layer, the second doped layer being interposed between the first doped layer and the first substrate.

[0024] The method includes providing a second assembly including a second substrate, a control circuit, and a photodetector, such that the control circuit is integrated in and / or on the second substrate and includes an interconnect stack.

[0025] The method comprises placing the face of the first component opposite to the first substrate on the face of the second component opposite to the second substrate by direct bonding, thereby realizing a bonding layer that is transparent to the detection wavelength λ2.

[0026] The method comprises exposing the first doped layer, the exposing step comprising removing the first substrate to obtain an active stack comprising the first doped layer and the second doped layer.

[0027] The method includes etching a first hole, aligning the first hole relative to a component of a second assembly such that the first hole passes completely through the active stack and extends to an interconnect layer of the interconnect stack.

[0028] The method includes etching a second hole, aligning the second hole relative to the component of the second assembly so that the second hole passes completely through the active stack and stops on the lower conductive layer.

[0029] The method includes passivating the first hole and the second hole to obtain a first passivation hole and a second passivation hole, respectively.

[0030] The method comprises filling a first passivation hole and a second passivation hole with a metal to obtain a through hole and an electrical contact, respectively.

[0031] The method includes forming a conductive line electrically insulated from the active stack and in contact with the electrical contacts and the vias.

[0032] After the bonding step, the method comprises forming an active area of ​​the light-emitting diode in the active stack, the active area facing the detection surface of the photodetector, achieving alignment of the active area relative to the elements of the second component.

[0033] The step of forming the active area may include a sub-step of etching a trench which may pass completely through the active stack and extend to the interconnect layer of the interconnect stack.

[0034] The bonding layer may include an intermediate layer having an optical function. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other aspects, objects, advantages and features of the present invention will better emerge from the following detailed description of a preferred embodiment given by way of non-limiting example and made with reference to the accompanying drawings, in which:

[0036] Figure 1A is a schematic cross-sectional view of a first assembly comprising a semiconductor stack on a first substrate;

[0037] Figure 1B is a schematic cross-sectional view of a second assembly comprising a second substrate, a control circuit, and a photodetector;

[0038] Figures 2A to 2H is a schematic cross-sectional view of an intermediate step of a first method for manufacturing a first optoelectronic device according to the present invention;

[0039] Figure 2I and Figure 2J 1 are a schematic transverse cross-sectional view and a schematic cross-sectional view viewed from above of a first optoelectronic device;

[0040] Figure 3Ais a schematic cross-sectional view of a first variation of the optoelectronic device according to the present invention;

[0041] Figure 3B is a schematic cross-sectional view of a second variation of the optoelectronic device according to the present invention;

[0042] Figure 3C is a schematic cross-sectional view of a third variation of the optoelectronic device according to the present invention;

[0043] Figure 3D is a schematic cross-sectional view of a fourth variation of the optoelectronic device according to the present invention;

[0044] Figure 3E is a schematic cross-sectional view of a fifth variation of the optoelectronic device according to the present invention;

[0045] Figure 4A is a schematic cross-sectional view of a variation of the second assembly;

[0046] Figure 4B is a schematic cross-sectional view of a sixth variant of the first optoelectronic device obtained at the end of the first manufacturing method applied to a variant of the second assembly;

[0047] Figure 5A and Figure 5B is a schematic cross-sectional view of an intermediate step of a second method for manufacturing a second optoelectronic device according to the present invention;

[0048] Figure 5C and Figure 5D 1 and 2 are respectively a schematic transverse cross-sectional view and a top view of a second optoelectronic device produced by the second manufacturing method. DETAILED DESCRIPTION

[0049] In the drawings and the following description, the same reference numerals represent the same or similar elements. In addition, the various elements are not drawn to scale to facilitate the clarity of the drawings. In addition, the various embodiments and modifications are not mutually exclusive and can be combined with each other. Unless otherwise specified, the terms "substantially", "about", "approximately (of the order of)" mean within 10%, preferably within 5%. In addition, unless otherwise specified, the terms "included between ... and ..." and the like mean including the boundaries.

[0050] The present invention relates to an optoelectronic device comprising a substrate, a control circuit integrated in and / or on the substrate (the control circuit comprising an interconnect stack), a light-emitting diode, and a photodetector. The light-emitting diode is stacked on the photodetector and is powered and / or controlled by the control circuit. The photodetector is arranged and configured to detect a light flow at a detection wavelength λ2 (referred to as incident light flow), which passes through the light-emitting diode and reaches a detection surface of the photodetector. This is possible, in particular, because the light-emitting diode comprises a cutoff wavelength λ c The semiconductor stack is smaller than the detection wavelength λ2. Therefore, the light emitting diode will emit a so-called emission light flux at an emission wavelength λ1 that is smaller than the detection wavelength λ2.

[0051] The light emitting diode comprises a semiconductor layer stack and a buried electrode arranged between the semiconductor layer stack and a detection surface.

[0052] The buried electrode is transparent to wavelength λ2 and has no physical contact with the interconnect layer of the interconnect stack. The buried electrode is electrically connected to the interconnect layer of the interconnect stack via an electrical path, which includes an electrical contact, a through-hole and a conductive line, which covers the face of the semiconductor layer stack opposite to the buried electrode. The electrical path may also be more complex and include a set of electrical interconnects that are electrically connected to the electrical contact and the through-hole and cover the face of the semiconductor layer stack opposite to the buried electrode. Both the electrical contact and the through-hole pass through the semiconductor layer stack. The electrical contact makes physical contact on the upper part of the buried electrode opposite to the interconnect stack. The through-hole extends to the interconnect layer of the interconnect stack. Therefore, the increase in the detection surface of the photodetector increases the detected incident light flux without reducing the lateral size of the buried electrode. In other words, the sensitivity of the photodetector is improved without losing the emission efficiency of the light-emitting diode.

[0053] The present invention also relates to a method for manufacturing such an optoelectronic device. The method includes transferring a first component to a second component. The first component includes, in this order, a first substrate, a semiconductor stack, and a conductive layer. The second component includes a second substrate, a control circuit, and a photodetector. The control circuit is integrated in and / or on the second substrate and includes an interconnect stack. The conductive layer is transparent to a detection wavelength λ2 of the photodetector. After the transfer, the conductive layer is located between the semiconductor stack and the photodetector.

[0054] After the transfer, the method comprises the following steps: forming an active area of ​​the light-emitting diode in the semiconductor stack by alignment on the elements of the second component so that the active area is positioned facing the photodetector. After the transfer, the method further comprises the following steps: forming through-holes and conductive trenches that pass through the semiconductor stack and extend to corresponding bonding pads of the interconnect stack. The through-holes and conductive trenches are used to electrically connect the light-emitting diode to the control circuit. The through-holes and conductive trenches are formed using alignment on the elements of the second component. Therefore, firstly, the alignment of the active area of ​​the light-emitting diode relative to the photodetector is precise, and secondly, the alignment of the through-holes and conductive trenches relative to the bonding pads is also precise. In this way, the effective detection surface of the photodetector is increased, in particular because smaller bonding pads can be used. Therefore, the sensitivity of the photodetector is improved.

[0055] The detection surface of a photodetector defines the smallest planar surface of the photodetector through which all photons of an incident light flux can generate a signal detected by a readout circuit of the photodetector.

[0056] The active region of an optoelectronic device is the portion of the device used to emit or detect optical radiation of interest. The active region of a light-emitting diode is the region or regions within which charge carriers from the diode's electrodes combine to produce photons. The active region of a photodiode is the region or regions within which photons can generate a signal detected by the photodiode's readout circuitry.

[0057] In this description, the term "metal" has its conventional meaning as used in the art to which the present invention pertains. However, for the sake of clarity, it should be noted that metal oxides such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or tin dioxide (SnO2) are not metals.

[0058] In this description, the term "interconnect stack" has its conventional meaning as used in the art to which the present invention pertains. However, for the sake of clarity, it is noted that the interconnect stack includes layers referred to as "interconnect layers," which are separated in pairs by layers referred to as "interlevel layers." The interconnect layers include metal lines separated by electrically insulating material. The interlevel layers include metal vias that electrically connect a metal line of one interconnect layer to another metal line of an adjacent interconnect layer or to the substrate on which the interconnect stack is disposed. Multiple vias are separated by electrically insulating material.

[0059] Here and in the rest of this description, "layer" means a range consisting of one or more sub-layers of material, the thickness of the layer along the axis z being ten or even twenty times smaller than its longitudinal width and length dimensions in a plane (x, y) perpendicular to the axis z. The layer may be structured. When a layer consists of a plurality of sub-layers, these sub-layers may be made of different materials. One or more sub-layers extend in a plane substantially parallel to the plane (x, y). A conformable layer is a special class of layers formed in contact with a non-planar surface, for which the thickness measured perpendicular to the surface is substantially constant, for example within 10%, or even within 5%.

[0060] Cutoff wavelength λ of semiconductor material c is the maximum wavelength of an incident photon that can be absorbed to excite an electron from the valence band to the conduction band of the semiconductor material, thereby generating a free electron and a hole. This absorption occurs when the energy of the incident photon is equal to or greater than the energy of the forbidden band of the semiconductor material (also referred to as the term "gap or gap energy"). The cutoff wavelength λ of the semiconductor stack c Equal to the minimum of the cutoff wavelengths of all semiconductor materials constituting the semiconductor stack.

[0061] A first element is aligned relative to a second element if the formation of the first element includes a photolithography sub-step that achieves the position of the second element, followed by an alignment process based on this position. The second element can be a set of typical alignment marks used by a photolithography tool. When the formation of the first element is achieved through a photolithography sub-step, the alignment is called first-order alignment or primary alignment. When the photolithography sub-step forms part of a step for forming an intermediate element, on which the first element is to be aligned, the alignment is called second-order alignment or secondary alignment. When the alignment is neither primary nor secondary, it is called high-order alignment. Primary alignment is more precise than secondary alignment, i.e., the relative position of the first element relative to the second element and to any other elements formed simultaneously with the second element will be more precise using primary alignment than using secondary alignment. Secondary alignment is more precise than high-order alignment. The first element can be a mask obtained by a supplementary photolithography step. Subsequently, the supplementary photolithography step can be said to be aligned relative to the second element.

[0062] Certain embodiments will be described with reference to an optoelectronic device including a light emitting diode stacked on a photodetector. However, these embodiments can be adapted for use with other optoelectronic devices, such as a multispectral sensor in which a supplemental photodetector is used in place of the light emitting diode.

[0063] Reference below Figures 2A to 2J A first manufacturing method for implementing the first embodiment is described.

[0064] exist Figure 2A In the first component is transferred to the second component. Figure 1A and Figure 1B The first component and the second component are shown in the cross-sectional view in FIG. The first component and the second component may be supplied in whole or in part by a semiconductor foundry company, for example.

[0065] The first assembly 5 includes, in the following order, a first substrate 100, a semiconductor stack 101, a lower conductive layer 102, and an upper bonding layer 103. The semiconductor stack 101 is in physical contact with the first substrate 100 and the lower conductive layer 102. The upper bonding layer 103 is in physical contact with the lower conductive layer 102.

[0066] Semiconductor stack 101 is a stack of semiconductor layers. Semiconductor stack 101 includes a first doped layer 101.2 of a first conductivity type and a second doped layer 101.4 of a second conductivity type opposite to the first conductivity type. First doped layer 101.2 is interposed between second doped layer 101.4 and first substrate 100. Semiconductor stack 101 can be grown by epitaxial growth on first substrate 100. Where applicable, semiconductor stack 101 may include a buffer layer 101.1, which serves to adapt the grid parameters of first doped layer 101.2 to those of first substrate 100.

[0067] Alternatively, semiconductor stack 101 can be grown epitaxially on a temporary substrate and transferred to first substrate 100, for example, by directly bonding first doped layer 101.2 to a face of first substrate 100. For example, a p-type doped layer is grown epitaxially on the temporary layer, intended to become second doped layer 101.4 of semiconductor stack 101; an intrinsic layer is grown epitaxially on the p-type doped layer; and an n-type doped layer is grown epitaxially on the intrinsic layer, intended to become first doped layer 101.2 of semiconductor stack 101. Where applicable, semiconductor stack 101 can include a buffer layer 101.1, which contacts first doped layer 101.2 and first substrate 100 and serves as a bonding layer. For example, buffer layer 101.1 can be an oxide-oxide, silicon-silicon, or silicon nitride-silicon nitride bond. The bonding layer can include a bonding interface. This alternative approach is advantageous, for example, for obtaining a first doped layer 101.2 of p-type gallium nitride (GaN).

[0068] The semiconductor stack 101 comprises a direct-gap crystalline semiconductor material having an energy value enabling emission of a light flux at an emission wavelength λ1.

[0069] The first doped layer 101.2 and the second doped layer 101.4 are made of semiconductor materials. The semiconductor stack 101 may include a semiconductor active layer 101.3, which is interposed between the first doped layer 101.2 and the second doped layer 101.4 and physically contacts both layers. The active layer 101.3 may, for example, include multiple semiconductor sublayers with different energies to form quantum wells. The active layer 101.3 may be unintentionally doped or lightly doped, either p-type or n-type.

[0070] The first doped layer 101.2 and the second doped layer 101.4 as well as the active layer 101.3 may be made of a semiconductor material selected from gallium nitride, gallium phosphide, gallium arsenide and indium phosphide, for example.

[0071] In the specific, non-limiting context of the example of the method described below, the first doped layer 101.2 is an n-type doped layer of gallium nitride (GaN). The second doped layer 101.4 is a p-type doped layer of gallium nitride (GaN). The first substrate 100 is made of silicon, for example a silicon wafer having a diameter of 150 mm, 200 mm, or 300 mm. The buffer layer 101.1 includes an aluminum nitride (AlN) sublayer in physical contact with the first substrate 100 and a series of GaN / AlGaN bilayers, the AlGaN sublayers having a lower aluminum concentration as the AlGaN sublayers are further away from the first substrate 100. The active layer 101.3 includes AlGaN-based quantum wells, the composition of which is suitable for emitting light in the long-wave ultraviolet (UVA) range.

[0072] For the sake of clarity, certain elements in this description are defined by their intended functions, which are achieved by a specific choice of layer doping type. Such definitions should not be construed as limiting in any way. Thus, for example, in the specific case described below, the cathode trench can accommodate a conductive trench connected to the cathode of a light-emitting diode, or, if the first doped layer 101.2 and the second doped layer 101.4 are doped p-type and n-type, respectively, the cathode trench can accommodate a conductive trench connected to the anode of a light-emitting diode.

[0073] The second component 6 comprises a second substrate 200, a control circuit and a photodetector 210. The second substrate 200 is made of silicon, for example. Advantageously, the second substrate 200 has the same dimensions as the first substrate 100. For example, the first substrate and the second substrate can both be 150 mm, 200 mm or 300 mm wafers. The control circuit is integrated on the so-called front face of the second substrate 200 and can optionally be integrated into the second substrate 200. The control circuit can be of CMOS type. The control circuit comprises an interconnect stack 201 located on the front face of the second substrate 200, which interconnect stack 201 is, for example, in contact with the front face.

[0074] The interconnect stack 201 includes at least one interconnect layer. Here, the interconnect stack 201 includes an anode bonding pad 221 and a cathode bonding pad 222, both of which are arranged in an interconnect layer of the interconnect stack 201. The anode bonding pad 221 and the cathode bonding pad 222 are made of metal, for example, copper. In this example, the interconnect layer including the anode bonding pad 221 and the cathode bonding pad 222 is the last interconnect layer of the interconnect stack 201, that is, the interconnect layer farthest away from the second substrate 200. Advantageously, the interconnect stack 201 may include a passivation layer made of a dielectric material, for example, silicon nitride (SiN), which includes the face of the interconnect stack 201 opposite to the second substrate 200. In this case, in Figure 2A Prior to the transfer step, the control circuit and / or the photodetector 210 are preferably not tested.

[0075] The second component 6 further comprises a lower bonding layer 203 located on the interconnect stack 201, on a side of the interconnect stack 201 opposite to the second substrate 200. The lower bonding layer 203 may be a passivation layer of the interconnect stack 201 or a complementary layer deposited on the passivation layer, and may advantageously be pre-polished.

[0076] The photodetector 210 includes a detection surface 211 that is substantially parallel to the front face of the second substrate 200. Preferably, the detection surface 211 faces a metal-free region of the interconnect stack 201, i.e., the interconnect stack 201 has no metal lines or vias vertically above the detection surface. Here, the detection surface is located near the front face of the second substrate 200.

[0077] The photodetector 210 is sensitive to a detection wavelength λ2 (e.g., 630 nm), for example, in the visible or near-infrared spectrum. Furthermore, the photodetector 210 may be sensitive to an emission wavelength λ1. The control circuit is electrically connected to the photodetector 210 and combines the functionality of supplying power to the photodetector 210 and reading the charge generated in the photodetector 210.

[0078] The second component 6 may include a plurality of photodetectors 210, for example, a plurality of photodetectors 210 arranged in a matrix extending parallel to the front face of the second substrate 200. The interconnect stack 201 may also include one or more supplementary bonding pads 223, for example, one or more supplementary bonding pads 223 arranged at the edge of the matrix of photodetectors 210. Figure 1B , two supplementary bonding pads 223 are shown in the same interconnect layer as the anode bonding pad 221 and the cathode bonding pad 222. The supplementary bonding pads 223 (if present) and the anode bonding pad 221 and the cathode bonding pad 222 are collectively referred to as bonding pads 221, 222, 223 hereinafter.

[0079] As shown here, the second component 6 can be, for example, a front side illumination (FSI) image sensor. The second component 6 can also be a back side illumination (BSI) image sensor. In this case, the second substrate 200 is interposed between the interconnect stack 201 and the lower bonding layer 203. The lower bonding layer 203 can be produced by deposition or thermal oxidation of the second substrate 200.

[0080] Figure 2A The transfer step can advantageously be performed in the following manner: directly bonding the upper bonding layer 103, the surface to be assembled opposite to the first substrate 100, and the surface to be assembled opposite to the second substrate 200, of the lower bonding layer 203 by bringing them into contact. The upper bonding layer 103 and the lower bonding layer 203 are transparent to the detection wavelength λ2 and may also be transparent to the emission wavelength λ1. For example, at the detection wavelength λ2 and / or the emission wavelength λ1, the upper bonding layer 103 and the lower bonding layer 203 transmit at least 50% of the incident light incident normally. ， Or preferably at least 90%, or even at least 95%.

[0081] The direct bonding achieved in the context of the present invention can be of any known type. Direct bonding can be the case of direct bonding by molecular adhesion. In this case, bonding is produced by chemical bonds established between the assembly surfaces. There are several types of bonding by molecular adhesion. These several types of bonding differ in particular in the temperature, pressure or air pressure conditions and / or processing steps before the surfaces to be assembled are brought into contact. For example, bonding can be a hydrophilic bonding or a hydrophobic bonding at ambient temperature in the presence or absence of prior activation by plasma of the surfaces to be assembled, optionally followed by a heat treatment to enhance the bonding interface. Bonding can also be the case of atomic fusion bonding (ADB) or surface-activated bonding (SAB).

[0082] exist Figure 2AIn the case of direct bonding during the transfer step, both the upper bonding layer 103 and the lower bonding layer 203 can be made of silicon oxide, silicon nitride or amorphous silicon. Here, the upper bonding layer 103 and the lower bonding layer 203 are made of silicon oxide, and the thickness of both is between 300nm and 600nm. Before the transfer, the surfaces to be assembled of the upper bonding layer 103 and the lower bonding layer 203 are polished to obtain a roughness state that is compatible with direct bonding by molecular adhesion. After the upper bonding layer 103 and the lower bonding layer 203 are brought into contact, a consolidation heat treatment of the bonding interface is applied at a temperature between 300°C and 400°C. Figure 2A At the end of the transfer step, the upper bonding layer 103 and the lower bonding layer 203 form a single bonding layer 303 .

[0083] The lower conductive layer 102 is transparent to the detection wavelength λ2 and may also be transparent to the emission wavelength λ1. For example, at the detection wavelength λ2 and / or the emission wavelength λ1, the lower conductive layer 102 transmits at least 50%, or preferably at least 90%, or even at least 95% of the incident light at normal incidence. The lower conductive layer 102 may be made of a metal oxide, such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or tin dioxide (SnO2). In this example, the lower conductive layer 102 is made of indium tin oxide (ITO) and has a thickness between 40 nm and 120 nm.

[0084] Here and for the rest of this description, an orthogonal three-dimensional direct reference system (X, Y, Z) is defined, wherein the X-axis and the Y-axis form a plane parallel to the main plane of the second substrate 200, the X-axis being Figures 2A to 2J 、 Figures 3A to 3E as well as Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C , and wherein the Z axis is oriented substantially orthogonal to the main plane of the second substrate 200 from the second substrate 200 towards the interconnect stack 201 and the bonding layer 303. In the description below, the terms "vertical / perpendicular" and "vertically / perpendicularly" should be understood as referring to a direction substantially parallel to the Z axis, and the terms "horizontal" and "horizontally" should be understood as referring to a direction substantially parallel to the plane (X, Y). In addition, the terms "lower" and "upper" should be understood as referring to an incremental positioning when moving away from the second substrate 200 in the +Z direction. In the reference frame (X, Y, Z), the layer, stack or substrate extends from the upper face to the lower face, both of the upper face and the lower face being parallel to the plane (X, Y). The upper face and / or the lower face may be structured.

[0085] exist Figure 2BIn the process, the first substrate 100 is removed, for example, by a series of grinding and / or polishing and / or wet etching sub-steps. Figure 2B In the specific example of , a first substrate 100 made of silicon is removed by a series of increasingly fine grinding sub-steps, followed by a selective wet-chemical etch with respect to AlN.

[0086] Next, the optional buffer layer 101.1 is removed, for example by dry etching and / or by electropolishing, to expose the n-doped layer 101.2. At the end of the removal of the first substrate 100 and optionally of the buffer layer 101.1 (if present), the remaining part of the semiconductor stack 101 is the so-called active semiconductor stack 301, which has a cut-off wavelength λ c The thickness of the active stack 301 is typically 1 μm.

[0087] Next, a hard mask 320 is deposited on the n-type doped layer 101.2 of the active stack 301. The hard mask 320 can be made of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). In this particular example, the hard mask 320 is made of silicon oxide and has a thickness between 1 μm and 1.5 μm, for example, a thickness of 1.2 μm.

[0088] In the hard mask 320 vertically above the anode bonding pad 221 and the cathode bonding pad 222, an anode opening 331 and a cathode opening 332 are etched, respectively, so that the anode opening 331 and the cathode opening 332 extend through the hard mask 320. For example, the anode opening 331 and the cathode opening 332 can be defined by a photolithography sub-step aligned (preferably first-order aligned) with respect to an element of the second component 6 (e.g., an alignment mark positioned on the second substrate 200 or in the interconnect stack 201). As a result, the position of the anode opening 331 and the cathode opening 332 relative to the anode bonding pad 221 and the cathode bonding pad 222 is precise, and the horizontal size of the latter can be reduced. The minimum dimension of the bonding pads 221, 222, 223 in a plane parallel to the plane (X, Y) is typically between 500 nm and 5 μm (e.g., between 500 nm and 1 μm).

[0089] exist Figure 2B In the example shown, the optional supplemental openings 333 will be etched in the hard mask 320 vertically above the corresponding supplemental bond pads 223 .

[0090] The cathode opening 332 may have an annular form in a plane parallel to the plane (X, Y), such as a circular ring, a rectangular ring, or a square ring. The anode opening 331 and the supplementary opening 333 may have, for example, a disc shape in a plane parallel to the plane (X, Y). When the cathode opening 332 has an annular form, the ring surrounds the anode opening 331. Here, the cathode opening 332 has an annular form, such as a square ring.

[0091] These openings are produced, for example, by reactive dry etching through the insulating resin during a photolithography sub-step, the reactive dry etching stopping on the n-doped layer 101 . 2 The resin can be removed by applying an oxygen plasma and a chemical solvent.

[0092] exist Figure 2C In the embodiment of the present invention, active stack 301, lower conductive layer 102, bonding layer 303, and optional passivation layer are successively etched through anode opening 331, cathode opening 332, and supplementary opening 333 until they reach bonding pads 221, 222, and 223. For example, one or more reactive dry etching sub-steps are used. The final etching sub-step, for example, selectively etches the passivation layer or bonding layer 303 relative to the metallic material of bonding pads 221, 222, and 223. A chemical cleaning step may advantageously be performed after the etching step.

[0093] exist Figure 2C At the end of the steps in , a first anode hole 341 facing the anode opening 331, a cathode groove 342 facing the cathode opening 332, and a supplementary hole 343 facing the supplementary opening 333 are obtained. The first anode hole 341 has a bottom formed by a portion of the anode bonding pad 221. Similarly, the cathode groove 342 has a bottom formed by a portion of the cathode bonding pad 222, and the supplementary hole 343 has a bottom formed by a portion of the supplementary bonding pad 223. Advantageously, the anode bonding pad 221, the cathode bonding pad 222, and the supplementary bonding pad 223 have similar forms to the first anode hole 341, the cathode groove 342, and the supplementary hole 343, respectively, in a plane parallel to the plane (X, Y), optionally with dimensional differences in this plane, and this dimensional difference can absorb alignment errors during the photolithography sub-step. Hereinafter, the first anode hole 341, the cathode groove 342, and the supplementary hole 343 are collectively referred to as through-grooves 341, 342, and 343.

[0094] exist Figure 2D, an additional opening is etched in the hard mask 320. A second anode hole 345 is then etched in the active stack 301 through the additional opening until the second anode hole reaches the lower conductive layer 102 without exceeding it. The additional opening is defined, for example, by a photolithography sub-step that is aligned (preferably first-order aligned) to an element of the second component 6 (e.g., an alignment mark positioned on the second substrate 200 or in the interconnect stack 201). When the active stack 301 is based on gallium nitride and the lower conductive layer 102 is based on indium tin oxide (ITO), the second anode hole 345 can be etched selectively relative to indium tin oxide (ITO) by a BCl plasma. Therefore, it is easier to stop etching the second anode hole 345 in the lower conductive layer 102. The thickness of the lower conductive layer 102 is preferably greater than or equal to 100 nm to absorb thickness variations experienced by the active stack 301, and is typically less than or equal to 300 nm.

[0095] exist Figure 2E In the embodiment, the passivation layer is uniformly deposited directly on the hard mask 320 and on the corresponding side surfaces and bottoms of the through trenches 341, 342, 343 and the second anode hole 345. The thickness of the passivation layer is substantially the same on the upper surface of the hard mask 320, and on the corresponding side surfaces and bottoms of the through trenches 341, 342, 343 and the second anode hole 345. The thickness variation of the passivation layer is, for example, less than or equal to 10%, preferably less than 5%. Advantageously, the passivation layer can be deposited before chemical etching, such as using TMAH and / or KOH.

[0096] In any cross-section parallel to the plane (X, Y) at the sides of the through trenches 341, 342, 343 and the second anode hole 345, the thickness of the passivation layer is such that any pair of opposing sides will be separated by two different portions of the passivation layer. The passivation layer can be made of, for example, aluminum oxide (Al2O3), silicon nitride (SiN), or aluminum nitride (AlN). In this example, the passivation layer is made of aluminum oxide (Al2O3) and has a thickness between 20 nm and 100 nm.

[0097] Next, the passivation layer is anisotropically etched perpendicular to the plane (X, Y) to obtain a lateral passivation layer 351. The etching can be a reactive dry etch. Preferably, a chemical clean can be performed after the etching. During this etching sub-step, the portion of the passivation layer in contact with the anode bonding pad 221 and the cathode bonding pad 222 as well as the supplementary bonding pad 223 will be completely removed. Similarly, the portion of the passivation layer in contact with the lower conductive layer 102 will be completely removed. Preferably, the passivation layer is completely removed on the upper face of the hard mask 320.

[0098] exist Figure 2FIn the embodiment, the thin layer is uniformly deposited on the upper surface of the hard mask 320, on the lateral passivation layer 351, and on the corresponding sides and bottoms of the through trenches 341, 342, 343 and the second anode hole 345. In any cross-section parallel to the plane (X, Y) at the sides of the through trenches 341, 342, 343 and the second anode hole 345, the thicknesses of the passivation layer and the thin layer are such that any pair of opposing sides is separated by two portions having different thin layers. The thin layer contacts the pads 221, 222, 223 and the lower conductive layer 102. The thin layer is capable of conducting electricity.

[0099] Next, the volume defined by the thin layer within through trenches 341, 342, 343 and the second anode aperture 345 is filled, preferably completely, with a metallic material. This step may, for example, include the following sub-steps: conformal deposition of a conductive seed layer, followed by growth of the metallic material by electrochemical deposition (ECD). The metallic material may be copper (Cu). The seed layer may consist of a titanium nitride (TiN) sublayer between a titanium (Ti) sublayer and a copper (Cu) sublayer. The Ti sublayer is in contact with the micron sublayer and the TiN sublayer. The Cu sublayer is in contact with the TiN layer.

[0100] Next, the portion of the thin layer in contact with the hard mask 320, the portion of the lateral passivation layer 351 in contact with the hard mask, the excess portion of the metal material located in the upper portion extending vertically from the upper face 301.1 of the active stack 301, and the hard mask 320 itself are removed. In this way, the n-type doped layer 101.2 is exposed.

[0101] At the end of this removal sub-step, the remaining portion of the thin layer, the remaining portion of the lateral passivation layer 351 and the remaining portion of the metallic material are flush with the upper face 301.1 of the active stack 301. This removal sub-step may comprise one or more chemical-mechanical polishing steps and, optionally, one or more cleaning steps. The sub-step of filling with metallic material and the subsequent removal sub-step may comprise one or more conventional bricks of the damascene process.

[0102] Advantageously, the thin layer is capable of reflecting light flux at the detection wavelength λ1 and / or at the emission wavelength λ2. The thin layer can be made, for example, of aluminum (Al), aluminum-silicon alloy (AlSi), or copper (Cu). The thickness of the thin layer is, for example, 80 nm on the sides of the through trenches 341, 342, 343 and at the second anode hole 345, and 300 nm on the upper surface of the hard mask 320.

[0103] exist Figure 2FAt the end of the step of forming the first anode hole 341, the remaining portion of the thin layer constitutes the cladding 352. The remaining portion of the metal material within the through-trench 341, 342, 343 and the second anode hole 345 each constitutes a metal fill 353. Each metal fill 353 is associated with a portion of the cladding 352 of the corresponding through-trench 341, 342, 343 and constitutes a conductive via 355, 359 or trench 358 that is in physical contact with one of the bond pads 221, 222, 223. Thus, the anode via 355, the conductive trench 358, and the additional via 359 are respectively housed in the first anode hole 341, the cathode trench 342, and the supplemental hole 343. The metal fill 353 is associated with a portion of the cladding 352 of the corresponding through-trench 341, 342, 343 and constitutes a conductive anode contact 357 that is in physical contact with the lower conductive layer 102.

[0104] When the thin layer is reflective, the portions of the cladding 352 facing the sides of the through trenches 341 , 342 , 343 and the second anode aperture 345 each constitute a mirror.

[0105] exist Figure 2G , an upper passivation layer 360 is formed on the upper face 301.1 of the active stack 301. The upper passivation layer 360 includes openings running through the upper passivation layer. The first opening is arranged to face the detection surface 211 and to face the conductive groove 358, the second opening is arranged to face the anode contact 357, and the third opening is arranged to face the anode through-hole 355. Preferably, the first opening covers the entire detection surface 211. Advantageously, the first opening covers the entire conductive groove 358. The upper passivation layer 360 can be made of silicon nitride (SiN), for example, and have a thickness between 50nm and 100nm. The first opening, the second opening and the third opening and any supplementary openings running through the upper passivation layer 360 are hereinafter collectively referred to as upper openings.

[0106] Next, an upper conductive layer 361 is deposited over upper passivation layer 360 and over a portion of n-doped layer 101.2 exposed in the upper opening. Here, upper conductive layer 361 is continuous and in physical contact with n-doped layer 101.2, anode contact 357, and anode via 355. Upper conductive layer 361 is transparent to both emission wavelength λ1 and detection wavelength λ2. At emission wavelength λ1 and detection wavelength λ2, upper conductive layer 361 transmits, for example, at least 50%, or preferably at least 90%, or even at least 95% of normally incident light. Upper conductive layer 361 can be made of a metal oxide, such as indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or tin dioxide (SnO2). In this example, upper conductive layer 361 is made of indium tin oxide (ITO) and has a thickness between 60 nm and 120 nm. A thickness between 100 nm and 120 nm makes it possible to obtain satisfactory transmittance and good electrical conductivity.

[0107] exist Figure 2H In the embodiment, a portion of upper conductive layer 361 that contacts anode contact 357 and anode via 355 is isolated by etching to produce conductive line 356. Conductive line 356 is electrically insulated from n-type doped layer 101.2 by upper passivation layer 360. Upper conductive layer 361 is etched throughout its entire thickness, preferably throughout its entire thickness in the area completely located above upper passivation layer 360.

[0108] The remaining portion of upper conductive layer 361 in contact with n-type doped layer 101.2 in the first opening constitutes a surface electrode 370 of the LED. Here, surface electrode 370 is cathode electrode 370 of the LED. Cathode electrode 370 extends through a portion of upper conductive layer 361 in contact with conductive trench 358. Preferably, the entire upper surface of conductive trench 358 is flush with upper surface 301.1 of active stack 301. Cathode electrode 370 preferably covers the entire surface of n-type doped layer 101.2 exposed in the first opening. The portion of lower conductive layer 102 in physical contact with anode contact 357 constitutes a buried electrode 380 of the LED. Here, buried electrode 380 is anode electrode 380 of the LED. A portion of cathode electrode 370 (preferably the entire cathode electrode 370) is located vertically above anode electrode 380.

[0109] Figures 2B to 2HThe steps in the above process form the active area of ​​the light-emitting diode arranged in the active layer 101.3. The geometric shape and relative position of the cathode electrode 370 and the anode electrode 380 define the horizontal dimensions of the active area. Here, the anode electrode 380 and the cathode electrode 370 are defined by the conductive groove 358. Therefore, the same applies to the active area. Therefore, the formation of the conductive groove 358 participates in the formation of the active area. The conductive groove 358 is aligned (preferably first-order aligned) relative to the elements of the second component 6, and the positioning of the active area relative to the detection surface 211 is precise. The same applies to the positioning of the anode through-hole 355 and the anode contact portion 357 relative to the detection surface 211 and the interconnect stack 201.

[0110] Figure 2I and Figure 2J The final step of the first manufacturing method is shown.The figures show views of a first embodiment of a first optoelectronic device 1 according to the invention. Figure 2J It is along Figure 2I Plan view of the section along cutting plane BB. Figure 2I It is along Figure 2J Cross-sectional view of cutting plane AA in.

[0111] During the final step, an optional encapsulation layer 375 is deposited on the upper passivation layer 360, the cathode electrode 370, and the conductive electrode 356. The encapsulation layer 375 may include one or more sublayers, for example, one or more sublayers made of a material selected from silicon oxide (SiO) or silicon nitride (SiN). The encapsulation layer 375 may have a flat upper face on a portion opposite the second substrate 200. The final step may include, after depositing the encapsulation layer 375, a substep for thinning the second substrate 200, for example, for exposing a through-hole extending deep into the second substrate 200 from the front side of the second substrate 200.

[0112] The first optoelectronic device 1 comprises a pixel 10. Figure 2I and Figure 2J In the particular case of , the first optoelectronic device 1 comprises a plurality of identical pixels 10 arranged in a matrix. The matrix extends in a plane parallel to the plane (X, Y). Figure 2J Only one pixel 10 is shown above. This pixel is located at the edge of the pixel matrix.

[0113] The pixel 10 comprises a photodetector 210, a light emitting diode and an intermediate region 390 between the photodetector 210 and the light emitting diode. Here, the photodetector 210 is a photodiode, such as a pinned photodiode. The upper face of the doped region of the photodiode defines a detection surface 211.

[0114] The light emitting diode comprises an anode electrode 380 and a portion of the active stack 301 bounded by the cathode trench 342. The anode electrode 380 is also bounded by the cathode trench 342. The light emitting diode further comprises a cathode electrode 370. The cathode electrode 370 is bounded by the cathode trench 342 in the plane of the upper face 301.1 of the active stack 301.

[0115] The intermediate region 390 is an imaginary region extending from the detection surface 211 to the active stack 301. This imaginary region has a base and walls. The base is the detection surface 211, where the detection surface 211 is located near the front surface of the second substrate 200. The walls are parallel to the Z axis. The walls can be right prisms or right elliptical cylinders. The intermediate region 390 includes a portion passing through the interconnect stack 201, a portion passing through the bonding layer 303, and a portion passing through the anode electrode 380. The intermediate region is free of metal elements.

[0116] The first optoelectronic device 1 includes an electrical path that electrically connects the anode electrode 380 to the control circuit. The electrical path includes an anode contact 357, an anode through-hole 355, and a conductive wire 356. The conductive wire 356 is separated from the cathode electrode 370 by an insulating material, which can be air or, as shown herein, a part of the encapsulation layer 375. The conductive wire 356 here has a generally rectangular shape when viewed from above. In this example, the cathode electrode 370 surrounds the conductive wire 356 in all directions parallel to the plane of the plane (X, Y). Alternatively, the conductive wire 356 can extend on a portion insulated from the conductive trench 358 by the upper passivation layer 360 above the cathode trench 342. In this case, the conductive wire 356 can electrically connect the anode contact 357 of the adjacent pixel 10. Preferably, the control circuit has a connecting component or connecting wire arranged below the anode bonding pad 221 and / or below the anode contact 357 and / or below the conductive wire 356. The component can be, for example, a transistor or a doped region.

[0117] The conductive trenches 358 of two adjacent pixels 10 can be different. Alternatively, as in this particular example, the conductive trenches 358 of two adjacent pixels 10 have a common portion. Here, the conductive trenches 358 of the matrix of pixels 10 form an orthogonal line grid in plan view, which is bounded by outer lines forming a rectangular or square frame. Each portion between two adjacent interconnects of the gate constitutes a common portion of the conductive trench 358.

[0118] The cathode electrode 370 of a pixel may be electrically insulated from the cathode electrodes 370 of one or more adjacent pixels. Figure 2J As shown, multiple pixels 10 (preferably all pixels 10) have a common cathode electrode 370, that is, the cathode electrode 370 of one pixel 10 is electrically connected to the cathode electrodes 370 of other pixels 10 (preferably all pixels 10) of the matrix through part of the upper conductive layer 361.

[0119] Now combine Figures 3A to 3E Variants of the first embodiment are described. Only the differences with respect to the first embodiment are explicitly described. These variants include additional features with respect to the first embodiment, all of which can be combined with one another to produce complementary variants falling within the scope of the invention.

[0120] Figure 3A A first useful variant is described, for example, when the region of the interconnect stack 201 facing the detection surface 211 comprises a non-metallic sublayer (e.g. one or more silicon nitride (SiN) sublayers) that absorbs or reflects at the emission wavelength λ1 and / or at the detection wavelength λ2. Figure 2A Prior to the transfer step, a recess 410 has been etched in the interconnect stack 201 facing the detection surface 211 to remove a portion of the absorption sublayer. The size of the recess 410 is sufficient to eliminate all portions of the absorption sublayer vertically above the detection surface 211. Preferably, as shown here, the recess 410 extends through the interconnect stack 201. Advantageously, the entire detection surface 211 faces the recess 410.

[0121] The lower bonding layer 203 is a layer deposited after etching of the recess 410, which completely fills the recess 410. For example, a dielectric layer (e.g., silicon oxide (SiO)) having a thickness strictly greater than the depth of the recess 410 in the Z direction may be deposited, followed by polishing, such as chemical mechanical polishing (CMP).

[0122] Figure 3B A second variant comprising an optically functional surface layer 430 is described. The optically functional surface layer 430 is Figure 2I A layer is deposited on the encapsulation layer 375 at the end of the step.

[0123] The optically functional surface layer 430 may be, for example, an antireflection layer 430 configured to provide an antireflection function at the emission wavelength λ1 and / or the detection wavelength λ2. The antireflection layer 430 may be a single layer or include multiple sublayers. The material and thickness of the layer or the material and thickness of the sublayer may be selected, for example, through simulation, to provide the desired antireflection function.

[0124] For example, antireflection layer 430 can be made of silicon nitride (SiN). For an active stack 301 of gallium nitride (GaN), an upper conductive layer 361 of indium tin oxide (ITO) with a thickness of 100 nm, and an encapsulation layer 375 of silicon oxide (SiO), the thickness of antireflection layer 430 can be between 50 nm and 65 nm, or between 175 nm and 190 nm, or between 295 nm and 310 nm to achieve an antireflection function at an emission wavelength λ1 of 365 nm. Combined with an encapsulation layer 375 thickness of less than 200 nm, the transmittance of the light flux emitted by the light-emitting diode from the upper face 301.1 of the active stack 301 is greater than 90%. The three thickness ranges of the above-mentioned silicon nitride (SiN) anti-reflection layer 430 are respectively combined with the thickness range of the encapsulation layer 375 (between 100nm and 150nm, or between 140nm and 170nm, or between 50nm and 150nm), making it possible to further obtain a transmittance of the incident light flow on the anti-reflection layer 430 in the active stack 301 greater than 90% at a detection wavelength λ2 of 630nm.

[0125] The optically functional surface layer 430 may be a surface layer that absorbs at the emission wavelength λ1. The absorbing surface layer has a through opening ( Figure 3B 375) and extends on the surface of the encapsulation layer 375 facing the area between two adjacent pixels 10. In this particular example, the absorptive surface layer also extends on the surface of the encapsulation layer 375 facing the conductive line 356. Therefore, the light flux emitted by the light-emitting diode of the pixel 10 conducted by the encapsulation layer 375 will be attenuated, and the crosstalk phenomenon can be avoided.

[0126] exist Figure 3B , an optional solder pad 440 is shown. The solder pad 440 passes through the encapsulation layer 375 located vertically above the corresponding additional through-hole 359. The solder pad 440 is made of a conductive material. When there is a surface layer 430 with an optical function, as shown here, the solder pad 440 can pass through the surface layer 430 or be arranged in a through opening formed in the surface layer 430 with an optical function. The number of solder pads 440 can be any number greater than or equal to 1. When the first optoelectronic device 1 includes a matrix of pixels 10, the solder pad 440 can be arranged in the peripheral portion of the matrix of pixels 10. The solder pad 440 can, for example, be used for electrical testing of the first optoelectronic device 1 before singulating the first optoelectronic device 1 by cutting the second substrate 200 (including a plurality of first optoelectronic devices 1).

[0127] Figure 3CA third variation is described in which the bonding layer 303 includes an optically functional intermediate layer 420. The optically functional intermediate layer 420 is a sublayer of the upper bonding layer 103 or a sublayer of the lower bonding layer 203, or it can be a combination of sublayers from the upper bonding layer 103 and the lower bonding layer 203. The third variation is advantageous when the photodetector 210 is sensitive to both the emission wavelength λ1 and the detection wavelength λ2 and is intended to operate simultaneously with a light-emitting diode. Thus, the photodetector 210 is not dazzled by the light-emitting diode.

[0128] The detection surface 211 of at least one pixel 10 (preferably all pixels 10) completely faces the optically functional intermediate layer 420, that is, the intermediate region 390 includes at least a portion of the optically functional intermediate layer 420. When the optically functional intermediate layer 420 is integrated into the lower bonding layer 203, openings can be etched through the optically functional intermediate layer 420 vertically above the detection surface 211 of some pixels 10.

[0129] The optically functional intermediate layer 420 may be an interference filter. The interference filter may, for example, be configured to increase the ratio of the transmission of the light flux at the detection wavelength λ2 to the transmission of the light flux at the emission wavelength λ1. For an emission wavelength λ1 in the UVA range and a detection wavelength λ2 in the visible spectrum, the optically functional intermediate layer 420 may include alternating silicon nitride (SiN) sublayers and silicon oxide (SiO) sublayers, for example, nine SiN / SiO bilayers, the thickness of the silicon nitride (SiN) sublayers being, for example, 44 nm, and the thickness of the silicon oxide (SiO) sublayers being, for example, 62 nm.

[0130] The optically functional intermediate layer 420 may be a reflective layer. The reflective layer may be, for example, a quarter wave plate that is independent of the polarization of light at, for example, the emission wavelength λ1. Thus, the ratio of the transmission of the light flux at the detection wavelength λ2 to the transmission of the light flux at the emission wavelength λ1 is increased. The quarter wave plate may be made of amorphous silicon. Where applicable, the quarter wave plate may be produced by assembling the upper bonding layer 103 and the lower bonding layer 203 comprising amorphous silicon on their surfaces to be assembled during atomic diffusion bonding (ADB). The thickness of the quarter wave plate of amorphous silicon may be, for example, 19.2 nm.

[0131] The optically functional intermediate layer 420 may be, for example, an amorphous silicon absorption layer with a thickness of 100 nm.

[0132] Figure 3D A fourth variant is described which repeats Figure 3BThe invention also includes a modified embodiment of the present invention and further includes an anti-reflection window 435 arranged facing the detection surface 211. The intermediate region 390 includes the anti-reflection window 435. The anti-reflection window 435 is, for example, in contact with the front surface of the second substrate 200. The anti-reflection window 435 includes a layer having an optical function, which has an anti-reflection function at the detection wavelength λ2. The anti-reflection window 435 can be, for example, a structured layer of tantalum oxide (Ta2O5), a structured layer of aluminum oxide (Al2O3), a structured layer of silicon nitride (SiN), or a structured layer of titanium oxide (TiO2). For a detection wavelength λ2 of 630 nm, the photodiode is made of silicon (Si) passivated by a 15 nm thick aluminum oxide (Al2O3) layer, the aluminum oxide layer being between the anti-reflection window 435 and the photodiode and in contact with the anti-reflection window 435 and the photodiode. The anti-reflection window 435 can be, for example, made of tantalum oxide (Ta2O5) and having a thickness greater than 70 nm, for example, equal to 105 nm. The anti-reflection window 435 may also be made of silicon nitride (SiN) and have a thickness between 410 nm and 430 nm.

[0133] Figure 3E Describes the Figure 3D 4 and 5. The anti-reflection window 435 is introduced in FIG. 4 and 5. The anti-reflection window 435 is optional here.

[0134] For this variant, Figure 2I At the end of the step, a through-opening is etched through the encapsulation layer 375, facing the additional through-hole 359. Next, a supplementary conductive layer made of an electrically conductive material is uniformly deposited on the bottom and side surfaces of the opening and on the upper face of the encapsulation layer 375. The supplementary conductive layer is in contact with the additional through-hole 359 and extends continuously from the additional through-hole 359 towards the upper face of the encapsulation layer 375. Next, the supplementary conductive layer is etched over its entire thickness, facing the active area of ​​the light-emitting diode, to obtain the heating element 432.

[0135] The heating element 432 has a through opening that faces the active area of ​​the light-emitting diode, and preferably, the heating element 432 extends on the surface of the encapsulation layer 375 that faces the area between two adjacent pixels 10. In this particular example, the heating element 432 also extends on the surface of the encapsulation layer 375 that faces the conductive line 356.

[0136] The heating element 432 can be heated by the Joule effect when a current passes through the additional through hole 359. The current can be controlled by the control circuit, for example, to stabilize the surface temperature of the first optoelectronic device 1 or to achieve thermal cycling. For example, the temperature of the heating element 432 can be heated to 55°C. The heating element 432 can also achieve Figure 3B The function of the absorbent surface layer.

[0137] The supplementary conductive layer may be made of titanium nitride (TiN), for example, thus making it possible to realize the function of heating by the Joule effect and the function of reducing crosstalk. The thickness of the supplementary conductive layer may be, for example, 100 nm.

[0138] Alternatively, as Figure 3E As shown, the heating element 432 may be electrically connected to the pad 440 through a portion of the supplemental conductive layer that extends the heating element within the openings etched in the encapsulation layer 375 and the upper passivation layer 360 .

[0139] Now combine Figure 4A and Figure 4B A variation of the first method in a sixth variation of realizing the first optoelectronic device 1 is described. Only differences from the first embodiment and the first device will be described. Figure 4B The variant of the first optoelectronic device 1 shown in FIG is repeated here. Figure 3B The additional and optional features of the second variant are shown in FIG. The additional and optional features may be combined with one or more of all the features described with respect to the other variants.

[0140] use Figure 4A The second component in 6 is implemented Figure 2A . The photodetector 210 is here at least partially integrated in and / or on the third substrate 205. The third substrate 205 comprises a supplementary interconnect stack 206 in contact with the front face of the third substrate 205. Here, the photodetector 210 is a photodiode flush with the front face of the third substrate 205. As shown here, the third substrate 205 is transferred to the interconnect stack 201, for example, by metal-oxide hybrid bonding of the supplementary interconnect stack 206 on the interconnect stack 201. The intermediate region 390 extends from the photodiode to the active stack 301 and comprises a portion of the third substrate 205, a portion of the bonding layer 303 and a portion of the lower conductive layer 102. The intermediate region 390 has a base and a wall. The base is the detection surface 211, which is here located in the third substrate 205. The wall is parallel to the Z axis. The wall can be a right prism or a right elliptical cylinder. The intermediate region 390 is free of metal.

[0141] The third substrate 205 preferably has the same size in a plane parallel to the plane (X, Y) as the second substrate 200. The third substrate 205 may be made of a material that is the same as or different from that of the second substrate 200. The material of the third substrate 205 may be, for example, silicon (Si), germanium (Ge), or indium gallium arsenide (InGaAs).

[0142] exist Figure 2BIn the step, the formation of the anode opening 331 and the cathode opening 332 may include a sub-step of performing aligned lithography (preferably first-order aligned lithography) on elements of the second component 6, wherein the alignment marks are arranged, for example, on the front surface of the second substrate 200, in the interconnect stack 201, in the supplementary interconnect stack 206 or on the front surface of the third substrate 205.

[0143] exist Figure 2C At step 341 , 342 , 343 , the through-trench 341 , 342 , 343 extends through the third substrate 205 and the supplementary interconnect stack 206 , up to the bonding pads 221 , 222 , 223 .

[0144] Now combine 5A to 5D A second manufacturing method for implementing a second optoelectronic device 2 is described. Only the differences with respect to the first method and the first device are described. One or more of all features described in connection with the variant of the first optoelectronic device 1 can be combined with this embodiment.

[0145] For the second method, first implement the first method Figures 2A to 2E steps.

[0146] exist Figure 5A , a supplementary cathode opening 336 is etched in the hard mask 320. The supplementary cathode opening 336 passes through the hard mask 320 and exposes the upper part of the n-type doped layer 101.2. The supplementary cathode opening 336 is arranged relative to the second anode hole 345 so that an imaginary line from one to the other has a portion facing the detection surface 211. When the cathode groove 342 has an annular form in a plane parallel to the plane (X, Y), the supplementary cathode opening 336 is arranged in the area surrounded by the cathode groove 342, as is the case here. Regardless of the form of the cathode groove 342, the supplementary cathode opening 336 can have an annular form in a plane parallel to the plane (X, Y), as is the case in this example. Where applicable, the shape of the supplementary cathode opening 336 in the plane can be, for example, elliptical, circular, rectangular or square as is the case here. In case of an n-doped layer 101 . 2 of gallium nitride (GaN), a ring-shaped form of the supplementary cathode opening 336 would be advantageous for large pixels 10 with dimensions, for example, greater than 50 μm or even 100 μm.

[0147] exist Figure 5B In the embodiment, conductive layer 552 is uniformly deposited on the upper surface of hard mask 320, on lateral passivation layer 351, on the bottoms of through-trench 341, 342, 343, in contact with bonding pads 221, 222, 223, and in contact with n-type doped layer 101.2 in supplemental cathode opening 336. Conductive layer 552 is electrically conductive. Advantageously, conductive layer 552 is made of metal. Preferably, conductive layer 552 is reflective with respect to emission wavelength λ1 and / or detection wavelength λ2.

[0148] The conductive layer 552 may be made of aluminum (Al), aluminum-silicon alloy (AlSi), aluminum-copper alloy (AlCu), tungsten (W), or titanium (Ti).

[0149] exist Figure 5C In the embodiment of the present invention, conductive layer 552 is etched through to separate conductive line 356, which contacts the upper surface of hard mask 320, from surface electrode 370, which contacts the exposed portion of n-type doped layer 101.2. Here, surface electrode 370 is cathode electrode 370. Conductive line 356 and cathode electrode 370 are two distinct portions of conductive layer 552 isolated by etching. By definition, cathode electrode 370 is limited to the portion of conductive layer 552 that contacts n-type doped layer 101.2 within supplemental cathode opening 336. At the end of this step, conductive line 356 extends to form anode contact 357, which is disposed in second anode aperture 345 and consists of a portion of conductive layer 552 in contact with lower conductive layer 102. Conductive line 356 also extends to form anode via 355, which is disposed in first anode aperture 341 and consists of a portion of conductive layer 552 in contact with anode bond pad 221. Cathode electrode 370 extends into a conductive trench 358, which is arranged in cathode trench 342 and consists of a portion of conductive layer 552 that contacts cathode bond pad 222. Conductive line 356, anode contact 357, and anode via 355 together form an electrical path that electrically connects the control circuit to anode electrode 380. This electrical path is electrically isolated from active stack 301 by hard mask 320 and lateral passivation layer 351.

[0150] Here, the conductive line 356 has a substantially rectangular shape in a plan view ( Figure 5D ). Still in this example, the conductive line 356 is surrounded by the cathode electrode 370 , which is itself surrounded by the conductive trench 358 .

[0151] In the case where the second optoelectronic device 2 includes solder pads 440, these solder pads 440 can be located on a portion of the conductive layer 552 located above the upper surface of the hard mask 320, electrically isolated by etching from the conductive lines 356, the cathode electrode 370, the anode vias 355, the anode contacts 357, and the conductive trenches 358. Where applicable, the encapsulation layer 375 can fill the empty spaces in the through-trench 341, 342, 343, the supplementary cathode opening 336, and the second anode opening 345.

[0152] Only specific embodiments have been described. Those skilled in the art will appreciate various variations and modifications. For example, when transferring the first component 5 to the second component 6, those skilled in the art can use an organic blue layer 303, such as a silicone layer or a polyimide layer.

Claims

1. A photoelectric device (1, 2), comprising: a substrate (200); a control circuit integrated in and / or on the substrate (200), the control circuit comprising an interconnect stack (201); A matrix of at least one pixel (10), each pixel (10) comprising a photodetector (210), a light emitting diode and an intermediate region (390) between the photodetector (210) and the light emitting diode, and each pixel being such that: The photodetector (210) is sensitive to a detection wavelength λ2 and comprises a detection surface (211) extending in a plane substantially parallel to a main plane of the substrate; The light emitting diode comprises: With cutoff wavelength λ c The active stack (301), the cut-off wavelength λ c shorter than the detection wavelength λ2, the active stack (301) comprises a first doped layer (101.2) and a second doped layer (101.4) of opposite types, a buried electrode (380) in contact with the second doped layer (101.4), The light emitting diodes are arranged such that the buried electrode is between the interconnect stack (201) and the active stack (301) and covers the detection surface, and each pixel is such that: The intermediate region (390) is delimited by the detection surface and extends from the detection surface to the active stack (301), The photovoltaic device (1) is characterized in that it further comprises: a through-hole (355) extending completely through the active stack (301) and extending to an interconnect layer of the interconnect stack (201); an electrical contact (357) extending completely through the active stack (301) and in contact with the buried electrode (380); an electrical path electrically connecting the buried electrode (380) to the control circuit and comprising an electrical through-contact (357) and the through-hole (355); And the photovoltaic device (1) is characterized in that: The intermediate region (390) is free of metal, The embedded electrode is transparent to the detection wavelength λ2.

2. The optoelectronic device (1, 2) according to claim 1, wherein for each pixel, the light emitting diode comprises: an active region extending between the first doped layer (101.2) and the second doped layer (101.4) in a plane substantially parallel to the main plane; a conductive trench (358) surrounding the active region and the intermediate region (390), the conductive trench completely passing through the active stack (301) and extending to an interconnect layer of the interconnect stack (201); as well as A surface electrode (370) is in contact with the first doping layer (101.2) and is electrically connected to the control circuit through the conductive groove (358).

3. The optoelectronic device (1, 2) according to claim 2, wherein: The conductive groove (358) is coated with a reflector.

4. The optoelectronic device (1, 2) according to claim 2 or 3, wherein The matrix includes a plurality of pixels (10), and the surface electrode (370) is an electrode common to all pixels (10).

5. The optoelectronic device (1, 2) according to claim 4, wherein The conductive trenches (358) of two adjacent pixels (10) have a common portion.

6. The optoelectronic device (1, 2) according to any one of the preceding claims, wherein The intermediate region (390) comprises an optically functional intermediate layer (420, 435) extending parallel to the main plane of the substrate.

7. The optoelectronic device (1, 2) according to any one of the preceding claims, wherein For each pixel (10), the buried electrode (380) is made of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), or tin dioxide (SnO).

8. The optoelectronic device (1) according to any one of claims 2 to 7, wherein: For each pixel (10), the surface electrode (370) is made of indium tin oxide ITO, aluminum-doped zinc oxide AZO or tin dioxide SnO.

9. The optoelectronic device (1, 2) according to any one of the preceding claims, further comprising a surface layer (430, 432) having an optical function provided on a side of the optoelectronic device (1) opposite to the substrate (200).

10. The optoelectronic device (1, 2) according to claim 9, wherein The optically functional surface layer (432) is an absorption layer including an opening facing the detection surface (211).

11. The optoelectronic device (1, 2) according to any one of the preceding claims, further comprising a heating element (432) arranged on a face of the optoelectronic device (1, 2) opposite to the substrate (200), the heating element (432) comprising an opening facing the detection surface (211).

12. The optoelectronic device (1, 2) according to any one of the preceding claims, wherein The detection wavelength λ2 belongs to the visible spectrum, and the light emitting diode can emit a light flux within the range of long-wave ultraviolet UVA.

13. A method for manufacturing an optoelectronic device (1, 2) according to any one of claims 1 to 12, the optoelectronic device comprising a light emitting diode and a photodetector (210) sensitive to a detection wavelength λ2, the method comprising the following steps: A first component (5) is provided, the first component (5) comprising a first substrate (100), a semiconductor stack (101) and a lower conductive layer (102) in the following order, such that the semiconductor stack (101) comprises a first doped layer (101.2) of a first conductivity type and a second doped layer (101.4) of a second conductivity type opposite to the first conductivity type, and such that the lower conductive layer (102) is in physical contact with the second doped layer (101.4), the second doped layer (101.4) being interposed between the first doped layer (101.2) and the first substrate (100), providing a second component (6), the second component (6) comprising a second substrate (200), a control circuit and the photodetector (210), such that the control circuit is integrated in and / or on the second substrate (200) and the control circuit comprises an interconnect stack (201), The surface of the first component opposite to the first substrate (100) is placed on the surface of the second component opposite to the second substrate (200) by direct bonding, thereby forming a bonding layer (303), wherein the bonding layer (303) is transparent to the detection wavelength λ2. exposing the first doped layer (101.2), the exposing step comprising removing the first substrate (100) to obtain an active stack (301), the active stack (301) comprising the first doped layer (101.2) and the second doped layer (101.4), etching a first hole (341), achieving alignment of the first hole (341) relative to an element of the second assembly such that the first hole (341) passes completely through the active stack (301) and extends to an interconnect layer of the interconnect stack (201), etching a second hole (345) to achieve alignment of the second hole (342) relative to the elements of the second assembly so that the second hole (345) passes completely through the active stack (301) and stops on the lower conductive layer (102), passivating the first hole (341) and the second hole (345) to obtain a first passivation hole (341) and a second passivation hole (345), respectively; Filling the first passivation hole (341) and the second passivation hole (345) with metal to obtain a through hole (355) and an electrical contact (357), respectively, forming a conductive line (356) electrically insulated from the active stack (301) and in contact with the electrical contact portion (357) and the through hole (355), After the bonding step, an active area of ​​the light-emitting diode is formed in the active stack (301), the active area facing the detection surface (211) of the photodetector (210), achieving alignment of the active area relative to the elements of the second assembly.

14. The method according to claim 13, wherein The step of forming the active area comprises the sub-step of etching a trench (342) which passes completely through the active stack (301) and extends to the interconnect layer of the interconnect stack (201).

15. The method according to claim 13 or 14, wherein: The bonding layer includes an intermediate layer (420, 435) having an optical function.

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