Super-large array multi-chip packaging structure, multi-chip packaging process and detection method thereof

Abstract

The invention relates to the technical field of chip packaging, in particular to a super-large array multi-chip packaging structure, a multi-chip packaging process and a detection method thereof, the packaging structure is used for packaging a plurality of chips on a tube shell, the packaging structure comprises a placing groove formed in the tube shell, the plurality of chips are arranged in the placing groove, and the chip packaging process is used for packaging the plurality of chips on the tube shell. A surface bonding pad used for being electrically connected with the chip is further arranged in the containing groove. Through the distribution mode of combining the tube shell with the bonding pads on the front surface and the back surface, the electrical connection of the chip can be effectively improved, and the connection mode not only ensures that the distance between transition leads on the upper surface and the lower surface is shortest, reduces signal noise and prevents signal distortion, but also facilitates wiring and welding of a flexible board; the problem of chip buckling deformation can be effectively reduced through a step-by-step packaging process, and the mounting position precision of the chip and the lens can be ensured to be within a required range through position precision detection, so that the precision of the chip and the lens during packaging is realized.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and in particular to an ultra-large array multi-chip packaging structure, a multi-chip packaging process and a detection method thereof. Background Art

[0002] VCSELs offer advantages such as small size, high efficiency and reliability, high eye safety, low power consumption, and ease of integration into two-dimensional arrays. 2D addressable products leverage the scalability of VCSEL chip arrays. By designing a two-dimensional VCSEL array and combining it with electronic or optical addressing technology, each VCSEL unit can be individually controlled to emit a dot-matrix multi-beam light source. This allows precise control over which VCSEL units emit laser light and when, thus meeting 2D addressability requirements. These products are widely used in smart cars, consumer electronics, data communications, industrial lasers, and other applications.

[0003] In order to solve the heating problem of high-density and ultra-large array VCSEL arrays, as well as the problems of multi-channel optical path alignment and electrical connection, higher requirements are placed on the packaging structure. It is necessary to design a compact packaging structure with good heat dissipation performance, low stress, high precision, and scalable array quantity to achieve stable operation of VCSEL array chips with good connection and alignment with driving circuits and optical elements. To this end, an ultra-large array multi-chip packaging structure, multi-chip packaging process and its detection method are proposed. Summary of the Invention

[0004] In response to the deficiencies in the prior art, the present invention provides an ultra-large array multi-chip packaging structure, a multi-chip packaging process and a detection method thereof, which solve the technical problems of multi-channel optical path alignment and high requirements for packaging structure.

[0005] To solve the above technical problems, the present invention provides the following technical solutions: an ultra-large array multi-chip package structure, the package structure being used to package multiple chips on a tube shell, the package structure comprising a placement slot defined on the tube shell, the multiple chips being disposed within the placement slot, the placement slot further comprising surface pads for electrically connecting to the chips, the surface pads being divided into multiple groups of horizontal pads and vertical pads, the horizontal pads being electrically connected to the P-level of the chip via gold wire bonding, and the vertical pads being electrically connected to the N-level of the chip via gold wire bonding;

[0006] The packaging structure further includes a lens arranged on the tube shell, the lens is bonded to the tube shell by glue, and the tube shell is provided with an overflow glue groove for intercepting and accommodating excess glue.

[0007] Preferably, the tube shell is further provided with a patch reference line for guiding chip placement;

[0008] Two cross marks are provided on the upper surface of the tube shell, one of which is the product coordinate zero point for later position accuracy measurement, and the other cross mark is the positioning coordinate zero point for high-precision chip mounting and lens installation during the packaging process.

[0009] Preferably, the back of the tube shell is provided with a plurality of back pads electrically connected to the flexible circuit board, the back pads are arranged in a "mouth" shape as a whole, the surface pads are electrically connected to the back pads, and a connector is also provided on the flexible circuit board.

[0010] A super-large array multi-chip packaging process, the packaging process comprising:

[0011] S1. Product clamping: After connecting the tube shell and several flexible circuit boards, use a positioning fixture to limit the overall position of the tube shell and flexible circuit boards;

[0012] S2. Chip installation: several chips are installed in the core area of ​​the tube shell;

[0013] S3. Lens installation: Install the lens on the upper surface of the tube shell to complete the chip packaging.

[0014] Preferably, the positioning fixture is provided with a processing groove, and the depth of the processing groove is greater than the setting height of the flexible circuit board after bending. The positioning fixture is provided with a plurality of assembly holes, and the plurality of assembly holes are symmetrically distributed about the processing groove; the tube shell is provided with mounting holes used for corresponding assembly holes, and the tube shell and the positioning fixture are fixed by connecting bolts.

[0015] Preferably, the chip installation further comprises:

[0016] S21, core area glue dispensing: filling the core area of ​​the tube shell with low-temperature curing flexible conductive glue;

[0017] S22, core area patching: using a nozzle to absorb the chip to be packaged, transfer the chip to be packaged above the core area, and then press down the chip to lower the chip height so that the chip is bonded to the low-temperature curing flexible conductive adhesive in the core area;

[0018] S23, chip position accuracy adjustment;

[0019] S24, the glue is baked and cured.

[0020] Preferably, the lens installation further comprises:

[0021] S31, dispensing of lens area;

[0022] S32, lens placement;

[0023] S33, lens position accuracy adjustment;

[0024] S34, lens glue curing.

[0025] Preferably, the detection method comprises:

[0026] Step 1: Use the cross mark on the upper surface of the tube shell as the coordinate zero point, locate the cross mark as the horizontal axis direction, and measure and record the horizontal / height distance from the zero point to the chip light-emitting hole;

[0027] Step 2: After the lens is mounted, record the horizontal / height distance from the zero point to the center of the lens arc surface, calculate the difference between the two data, and obtain the position deviation. Compensate the mounting data according to the deviation, and mount the lens again. After multiple compensation adjustments, the required accuracy is achieved.

[0028] By means of the above technical solution, the present invention provides an ultra-large array multi-chip packaging structure, a multi-chip packaging process and a detection method thereof, which have at least the following beneficial effects:

[0029] The present invention can effectively improve the electrical connection of the chip by combining the tube shell with the front and back pads in a distributed manner. This connection form not only ensures the shortest distance between the transition leads on the upper and lower sides, reduces signal noise, prevents signal distortion, but also facilitates flexible board wiring and welding; the chip warping and deformation problem can be effectively reduced through a step-by-step packaging process, and the position accuracy of the chip and lens mounting can be ensured to be within the required range through position accuracy detection, thereby achieving accuracy in chip and lens packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] Figure 1 This is a schematic diagram of the overall structure of the chip package of the present invention;

[0032] Figure 2 This is a schematic diagram of the tube shell and chip structure of the present invention;

[0033] Figure 3 This is a schematic diagram of the flexible circuit board and connector structure of the present invention;

[0034] Figure 4 This is a schematic diagram of the upper surface structure of the tube shell of the present invention;

[0035] Figure 5 It is a schematic diagram of the suction nozzle structure of the present invention.

[0036] In the figure: 1. Tube shell; 2. Chip; 3. Lens; 4. Flexible circuit board; 5. Connector; 6. Positioning fixture; 7. Suction nozzle. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] Example 1

[0039] Please refer to Figure 1-Figure 3 A super-large array multi-chip package structure is provided. The package structure is used to package several chips 2 on a tube shell 1. The package structure includes a placement groove 101 opened on the tube shell 1. Several chips 2 are arranged in the placement groove 101. The placement groove 101 also has surface pads 102 for electrically connecting to the chips 2. The surface pads 102 are divided into multiple groups of horizontal pads 1021 and vertical pads 1022. The horizontal pads 1021 are electrically connected to the P-level of the chip 2 through gold wire bonding, and the vertical pads 1022 are electrically connected to the N-level of the chip 2 through gold wire bonding. This electrical connection is electrically connected by flying wires. The specific operation is to achieve conductivity between the surface pads 102 and the chip 2 through gold wire bonding.

[0040] The packaging structure further includes a lens 3 disposed on the tube shell 1. The lens 3 is bonded to the tube shell 1 by glue. The tube shell 1 is provided with a glue overflow groove 103 for intercepting and accommodating excess glue.

[0041] Furthermore, the tube shell 1 is also provided with a patch reference line for guiding the placement of the chip 2; two cross marks are provided on the upper surface of the tube shell 1, one of which is the product coordinate zero point for the later position accuracy measurement, and the other cross mark is the positioning coordinate zero point for the high-precision placement of the chip and lens installation during the packaging process.

[0042] Furthermore, the back of the tube shell 1 is provided with a plurality of back pads 104 for electrical connection with the flexible circuit board 4. The back pads 104 are arranged in an "O" shape as a whole. The surface pads (102) are electrically connected to the back pads 104. The flexible circuit board 4 is also provided with a connector 5. The entire back pad 104 is a ring frame composed of four "L"-shaped connection points. From the overall point of view, the four "L"-shaped connection points are arranged in an "O" shape. This arrangement can make full use of space and solve the problem that too many PINs are difficult to be distributed in a single row. At the same time, the center distance of the pads must be widened to ensure the minimum welding spacing.

[0043] The material of the tube shell 1 is alumina. Since the thermal expansion coefficient of alumina is close to that of the chip material, it reduces stress. The surface pads 102 are connected to the back pads 104 of the tube shell 1 using the existing mature high-temperature co-fired ceramic multi-layer sintering process. That is, the horizontal pads 1021 and the vertical pads 1022 are electrically connected to the corresponding back pads 104.

[0044] Since the shell 1 is relatively large, it is prone to shrinkage and deformation during the sintering process, resulting in low precision. The same surface metallization process as the surface pad 102 is designed, and the chip reference line is processed with relatively high precision. In addition, cross marks are designed symmetrically in the area outside the lens. Laser marking is used. The left cross mark is the product coordinate zero point for later position accuracy measurement. The right cross mark cooperates with the left cross mark to determine the direction of the horizontal coordinate axis, laying the foundation for high-precision placement of the chip 2 and the lens 3 during the packaging process.

[0045] Back of tube shell 1: Combined with the distribution of surface pads 102 and the wiring and welding positioning requirements of flexible board, array pads are designed to ensure the shortest distance between the transition leads on the upper and lower sides to reduce signal noise and prevent signal distortion, and facilitate wiring and welding of flexible board.

[0046] Since the mounting accuracy of chip 2 and lens 3 is strongly related to the machining accuracy of the assembly support surface on the tube shell 1, it is necessary to ensure the flatness of the chip mounting surface and the lens mounting surface, as well as the parallelism between the two surfaces. Therefore, the two key assembly surfaces are processed in a secondary manner, and the bottom surface of the tube shell is used as the reference surface for machining positioning. In the case of one clamping, a high-precision milling machine is used to perform fine milling on both surfaces based on the rough tube shell forming blank to ensure the machining accuracy and relative parallelism of the two surfaces.

[0047] Flexible circuit board 4: Because the pads of each array chip are distributed on two adjacent edges on its outside, each chip uses a flexible board for electrical connection. The pads adopt the same L-shaped distribution on the tube shell, and the flexible bending characteristics of the flexible board are used to turn the flexible board export interface to the outside of the tube shell, which is convenient for observing the connector assembly effect during plugging and unplugging. In order to prevent the edge pads of the flexible board from being damaged by the tension when the connector is plugged and unplugged, two metal holes are designed on the inside of the bending point for welding and fixing.

[0048] Connector 5: Use the flexible board to PCB hard board connector in the board-to-board connector to achieve high-density connection between the flexible circuit board 4 and the circuit on the PCB board.

[0049] Example 2

[0050] Please refer to Figure 2-Figure 5 This embodiment is basically the same as the first embodiment. This embodiment is made on the basis of the first embodiment and has the same beneficial effects as the first embodiment. The same parts can be referred to each other and will not be described in detail here.

[0051] A super-large array multi-chip packaging process, the packaging process comprising:

[0052] S1. Product clamping: After connecting the tube shell 1 and several flexible circuit boards 4, use a positioning fixture 6 to limit the position of the tube shell 1 and the flexible circuit boards 4;

[0053] S2, chip 2 installation: several chips 2 are installed in the core area of ​​the tube shell 1;

[0054] S3, lens 3 installation: mount the lens 3 on the upper surface of the tube shell 1 to complete the chip 2 packaging.

[0055] Preferably, a processing groove is provided on the positioning fixture 6, and the depth of the processing groove is greater than the setting height of the flexible circuit board 4 after bending. A plurality of assembly holes are provided on the positioning fixture 6, and the plurality of assembly holes are symmetrically distributed about the processing groove; mounting holes corresponding to the assembly holes are provided on the tube shell 1, and the tube shell 1 and the positioning fixture 6 are fixed by connecting bolts.

[0056] From the above, it can be seen that due to the presence of flexible board features on the back of the product and the limited height travel of the patch and bonding equipment, a specific positioning fixture 6 is designed to position the flexible board on the fixture in a bent state, lower the product height, and make way for the grooves processed in the flexible board area of ​​the fixture. The product is locked to the fixture through the assembly holes.

[0057] Preferably, the chip 2 installation further includes:

[0058] S21, core area dispensing; fill the core area of ​​the tube shell 1 with low-temperature curing flexible conductive glue; glue selection: in order to ensure the relative mounting height of the chip 2 and the lens 3, the bottom of the chip and the bottom of the lens are positioned with the same glue to reduce the difference in glue thickness; since the areas of the array chip 2 and the lens 3 are relatively large, the conductive silver glue conventionally used for single chip mounting is prone to stress under large-area bonding and high-temperature baking, which may damage the chip 2 in severe cases. Therefore, a low-temperature curing flexible conductive glue is selected to be filled with flexible epoxy resin. On the basis of good bonding performance, it is cured by low-temperature baking, and at the same time, high thermal conductivity and low stress bonding effects are taken into account.

[0059] S22, core area patch; use the nozzle 7 to adsorb the chip 2 to be packaged, transfer the chip 2 to the top of the core area, and then press down the chip 2 to lower the height of the chip 2 so that the chip 2 is bonded to the low-temperature curing flexible conductive adhesive in the core area;

[0060] S23, chip position accuracy adjustment;

[0061] S24, the glue is baked and cured.

[0062] Dealing with the warping problem of chip 2: Due to heteroepitaxial growth, such as the lattice constant of VCSEL AlGaAs epitaxial layer greater than the GaAs substrate, tensile stress is formed on the VCSEL array chip. If the warping problem is not addressed, a height difference will form between the center and the periphery of chip 2. That is, on the same chip 2, the relative distance between chip 2 and lens 3 will vary greatly, resulting in low packaging accuracy and poor light path emission effect.

[0063] Use the following measures to improve the warping problem:

[0064] 1. Use the surface nozzle and point nozzle together to control the patch effect;

[0065] 2. The laser altimeter monitors and measures the chip surface height in real time, providing feedback on the height difference between different areas;

[0066] 3. High-precision pressure control, the pressure value for compensation adjustment is determined according to the height difference value;

[0067] 4. Real-time horizontal position monitoring to prevent the chip from moving horizontally during adjustment;

[0068] 5. Heating curing system.

[0069] The implementation steps are:

[0070] 1. Use the customized large-area nozzle 7 to attach the chip 2. The nozzle 7 is designed to avoid the light-emitting hole of the chip 2 to reduce damage to the chip 2.

[0071] 2. Switch to a small nozzle and determine the nozzle pressure based on the height difference between the highest and lowest points of the chip measured by a laser altimeter. Simulate the action of placing a chip at the highest point of the chip and press down on the chip to reduce the height difference. The measured effect is good. For example, the chip warpage height is 80μm, which can be controlled within 30μm after adjustment.

[0072] 3. Horizontal position accuracy detection to ensure that the placement position accuracy is within the required range;

[0073] 4. Start the heating and curing system and fix the patch position.

[0074] Panoramic image recording: Since the array chip 2 and lens 3 have many features, it is often necessary to record and confirm the status of each feature. However, existing high-magnification observation and detection equipment can only see local features. If local shooting and recording is done, it will not only be cumbersome and prone to errors, but the boundaries of multiple shots cannot be accurately connected, and the true state of the complete product cannot be restored, which is not conducive to observation and analysis. In addition, the chip at the bottom cannot be observed after the lens is assembled. Therefore, an automatic image stitching function has been developed to present the true state of the complete product, record the complete large-area array features that need to be recorded, such as the array chip, array lens, and gold wire bonding, and realize the observable, analytical, and traceable packaging effect of ultra-large array multi-chips.

[0075] Preferably, the lens 3 installation further comprises:

[0076] S31, glue dispensing in the lens area; the glue dispensing method is as follows: since the area of ​​lens 3 is too large and position compensation adjustment needs to be performed repeatedly during high-precision mounting, in order to prevent excessive glue from overflowing and causing uncontrollable effects, glue is first dispensed on the four corners of the lens, and after baking and curing, glue is then dispensed around the lens 3 to seal and enhance the curing effect; the glue filling is divided into two steps, the first step is to dispense a small amount of glue at the gap between the lens 3 and the tube shell 1 to fill the gap, bake and cure, and then supplement the glue amount based on the first glue dispensing to increase the bonding area and enhance the curing effect, so as to avoid dispensing a large amount of glue at one time and the uncontrollable flow range of glue entering the internal chip area.

[0077] S32, lens placement; placing the lens 3 on the upper surface of the tube shell 1. During placement, it is necessary to continuously adjust the lens 3 according to the cross mark (i.e., the positioning coordinate zero point) so that the lens 3 is placed in the appropriate position;

[0078] S33, lens position accuracy adjustment;

[0079] S34, the lens glue is cured, and the glue between the lens 3 and the tube shell 1 is slowly cured by low-temperature baking.

[0080] Preferably, the detection method comprises:

[0081] Step 1: Use the cross mark on the upper surface of the tube shell 1 as the coordinate zero point, locate the cross mark as the horizontal axis direction, and measure and record the horizontal / height distance from the zero point to the chip light-emitting hole;

[0082] Step 2: After lens 3 is mounted, record the horizontal / height distance from the zero point to the center of the light-passing arc surface of lens 3, calculate the difference between the two data, and obtain the position deviation. Compensate the mounting data according to the deviation, and mount the lens again. After multiple compensation adjustments, the required accuracy is achieved.

[0083] For example, when measuring the horizontal alignment accuracy, first measure and record the distance X and Y between the reference point and the chip's light-emitting hole. After the lens is mounted, measure the distance X1 and Y1 between the reference point and the center of the lens's light-passing surface. X-X1 = lateral deviation, and Y-Y1 = longitudinal deviation.

[0084] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0085] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to in detail. For the above embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For relevant parts, please refer to the partial description of the method embodiments.

[0086] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. An ultra-large array multi-chip packaging structure, characterized by: The packaging structure is used to package a plurality of chips (2) on a tube shell (1), the packaging structure comprises a placement groove (101) provided on the tube shell (1), a plurality of chips (2) are arranged in the placement groove (101), and a surface pad (102) for electrically connecting with the chip (2) is further provided in the placement groove (101), the surface pad (102) is divided into a plurality of groups of horizontal pads (1021) and vertical pads (1022), the horizontal pads (1021) are electrically connected to the P level of the chip (2) through gold wire bonding, and the vertical pads (1022) are electrically connected to the N level of the chip (2) through gold wire bonding; The packaging structure further comprises a lens (3) provided on the tube shell (1); the lens (3) is bonded to the tube shell (1) by glue; and an overflow glue groove (103) for intercepting and accommodating excess glue is provided on the tube shell (1).

2. The ultra-large array multi-chip package structure according to claim 1, wherein: The tube shell (1) is also provided with a patch reference line for guiding the placement of the chip (2); Two cross marks are provided on the upper surface of the tube shell (1), one of which is the product coordinate zero point for later position accuracy measurement, and the other is the positioning coordinate zero point for high-precision chip mounting and lens installation during the packaging process.

3. The ultra-large array multi-chip package structure according to claim 2, wherein: The back of the tube shell (1) is provided with a plurality of back solder pads (104) electrically connected to the flexible circuit board (4); the back solder pads (104) are arranged in an overall "mouth" shape; the surface solder pads (102) are electrically connected to the back solder pads (104); and a connector (5) is also provided on the flexible circuit board (4).

4. A super-large array multi-chip packaging process, characterized by: The ultra-large array multi-chip packaging structure according to any one of claims 1 to 3, wherein the packaging process comprises: S1. Product clamping: After connecting the tube shell (1) and a plurality of flexible circuit boards (4), a positioning fixture (6) is used to limit the position of the entire tube shell (1) and the flexible circuit boards (4); S2, chip (2) installation: installing a plurality of chips (2) in the core area of ​​the tube shell (1); S3, lens (3) installation: the lens (3) is installed on the upper surface of the tube shell (1) to complete the chip (2) packaging.

5. The ultra-large array multi-chip packaging process according to claim 1, characterized in that: The positioning fixture (6) is provided with a processing groove, and the depth of the processing groove is greater than the setting height of the flexible circuit board (4) after bending. The positioning fixture (6) is provided with a plurality of assembly holes, and the plurality of assembly holes are symmetrically distributed about the processing groove; the tube shell (1) is provided with mounting holes used for corresponding assembly holes, and the tube shell (1) and the positioning fixture (6) are fixed by connecting bolts.

6. The ultra-large array multi-chip packaging process according to claim 1, characterized in that: The chip (2) installation further comprises: S21, core area glue dispensing; filling the core area of ​​the tube shell (1) with low temperature curing flexible conductive glue; S22, core area patching; using a suction nozzle (7) to absorb the chip (2) to be packaged, transferring the chip (2) to be packaged above the core area, and then pressing down the chip (2) to lower the height of the chip (2) so that the chip (2) is bonded to the low-temperature curing flexible conductive adhesive in the core area; S23, chip position accuracy adjustment; S24, the glue is baked and cured.

7. The ultra-large array multi-chip packaging process according to claim 1, characterized in that: The lens (3) installation also includes: S31, dispensing of lens area; S32, lens placement; S33, lens position accuracy adjustment; S34, lens glue curing.

8. The ultra-large array multi-chip packaging process according to claim 1, characterized in that: The detection method comprises: Step 1: Using the coordinate zero point cross mark on the upper surface of the tube shell (1) as the coordinate zero point, positioning the coordinate zero point cross mark as the horizontal axis direction, and measuring and recording the horizontal / height direction distance from the zero point to the chip light-emitting hole; Step 2: After the lens (3) is mounted, the horizontal / height distance from the zero point to the center of the light-passing arc surface of the lens (3) is recorded, the difference between the two data is calculated, and the position deviation is obtained. The mounting data is compensated according to the deviation, and the lens (3) is mounted again. After multiple compensation adjustments, the required accuracy is achieved.

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