Linear charging chip and detection circuit thereof

Abstract

The embodiment of the invention provides a linear charging chip and a detection circuit thereof. The detection circuit comprises an adjusting module and a time length detection module, when the non-constant-current charging loop works, the adjusting module generates an adjusting current according to a differential voltage of a feedback voltage and a first reference voltage, the first reference voltage is a reference voltage of the constant-current charging loop, and the time length detection module detects the time length of the constant-current charging loop. The duration detection module adaptively adjusts the safe timing duration according to the adjusting current, detects whether the constant-current charging duration exceeds the safe timing duration, and generates a constant-current charging timeout indication signal when the constant-current charging duration exceeds the safe timing duration so as to indicate the linear charging chip to stop charging the battery; the safe timing duration can be adaptively increased when the non-constant current charging loop works, so that the problem of false triggering of the safe timing function is solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a linear charging chip and a detection circuit thereof. Background Art

[0002] When the lithium battery enters the constant current charging stage, the linear charging chip with a safety timer function (Safety Timer Function) starts timing internally (usually on the order of 5-10 hours). Once the timing exceeds the internal preset safety timer, and the chip determines that the constant current charging has not ended, it is necessary to forcibly terminate the continued charging of the lithium battery to avoid continuous charging affecting the battery life. It can also reduce the safety risks caused by "dead batteries" not being fully charged for a long time.

[0003] Linear charging chips typically have a dedicated pin that allows users to connect different external resistors to this pin to set the appropriate safety timer duration. This prevents high-capacity lithium batteries from being triggered and disabling charging before they are fully charged. However, linear charging chips are typically controlled by multiple loops. When a non-constant current charging loop controls a low-dropout linear regulator (LDO), the charging current may be lower than the user's desired current value, potentially causing the safety timer to be falsely triggered. Summary of the Invention

[0004] The present disclosure provides a detection circuit for a linear charging chip and a linear charging chip, which can adaptively increase the safety timing duration when a non-constant current charging loop is operating, thereby improving false triggering of the safety timing function.

[0005] In a first aspect, the present disclosure provides a detection circuit for a linear charging chip, wherein the linear charging chip includes a constant current charging loop and a non-constant current charging loop. In a constant current charging stage, one of the constant current charging loop and the non-constant current charging loop is in a working state, and the detection circuit includes an adjustment module and a duration detection module.

[0006] The regulation module is configured to, when the non-constant current charging loop is operating, generate a regulated current based on the differential voltage between a feedback voltage and a first reference voltage, where the first reference voltage is the reference voltage of the constant current charging loop. The duration detection module is configured to, when the non-constant current charging loop is operating, adaptively adjust the safety timer duration based on the regulated current, detect whether the constant current charging duration exceeds the safety timer duration, and generate a constant current charging timeout indication signal when the constant current charging duration exceeds the safety timer duration, thereby instructing the linear charging chip to stop charging the battery.

[0007] In some embodiments of the present disclosure, the regulation module includes a first conversion unit and a current generating unit. A first input terminal of the first conversion unit is connected to the first reference voltage, a second input terminal of the first conversion unit is connected to the feedback voltage, an output terminal of the first conversion unit is connected to an input terminal of the current generating unit, and an output terminal of the current generating unit is connected to an input terminal of the duration detection module.

[0008] The first conversion unit is configured to convert the first reference voltage into a second reference voltage with drive capability, and convert the differential voltage between the feedback voltage and the second reference voltage into a bias current, wherein the second reference voltage has a voltage value equal to that of the first reference voltage. The current generation unit is configured to determine the regulation current based on the bias current.

[0009] In some embodiments of the present disclosure, the regulation module includes a second conversion unit and a current generating unit. A first input terminal of the second conversion unit is connected to the first reference voltage, a second input terminal of the second conversion unit is connected to the feedback voltage, an output terminal of the second conversion unit is connected to the input terminal of the current generating unit, and an output terminal of the current generating unit is connected to the input terminal of the duration detection module.

[0010] The second conversion unit is configured to generate a first voltage based on the feedback voltage, generate a second voltage based on the first reference voltage, and convert a differential voltage between the first voltage and the second voltage into a bias current, wherein the differential voltage between the first voltage and the second voltage is equal to the differential voltage between the feedback voltage and the first reference voltage. The current generation unit is configured to determine the regulation current based on the bias current.

[0011] In some embodiments of the present disclosure, the first conversion unit includes a first operational amplifier, a first transistor, a first current source, a second operational amplifier, and a first resistor. A non-inverting input terminal of the first operational amplifier is connected to the first reference voltage, an inverting input terminal of the first operational amplifier is connected to a first terminal of the first transistor and a first terminal of the first resistor, an output terminal of the first operational amplifier is connected to a control terminal of the first transistor, a first terminal of the first transistor is grounded via the first current source, and a second terminal of the first transistor is connected to a power supply voltage.

[0012] The second end of the first resistor is connected to the non-inverting input end of the second operational amplifier and the input end of the current generating unit, the inverting input end of the second operational amplifier is connected to the feedback voltage, and the output end of the second operational amplifier is connected to the control end of the current generating unit.

[0013] In some embodiments of the present disclosure, the second conversion unit includes a second current source, a third current source, a second transistor, a third transistor, a third operational amplifier and a second resistor, wherein the second transistor and the third transistor operate in a subthreshold region, and the current provided by the third current source is greater than the bias current.

[0014] The power supply voltage is connected to the first end of the second transistor and the inverting input end of the third operational amplifier through the second current source, the power supply voltage is connected to the first end of the third transistor and the first end of the second resistor through the third current source, the control end of the second transistor is connected to the feedback voltage, the control end of the third transistor is connected to the first reference voltage, the second end of the second transistor and the second end of the third transistor are grounded, the second end of the second resistor is connected to the non-inverting input end of the third operational amplifier and the input end of the current generating unit, and the output end of the third operational amplifier is connected to the control end of the current generating unit.

[0015] In some embodiments of the present disclosure, the current generating unit includes a fourth transistor and a fifth transistor, and a ratio of a width-to-length ratio of the fourth transistor to a width-to-length ratio of the fifth transistor is M:1, where M is an integer greater than 1.

[0016] The first end of the fourth transistor and the first end of the fifth transistor are grounded, the second end of the fourth transistor is connected to the input end of the current generating unit, the control end of the fourth transistor is connected to the control end of the current generating unit and the control end of the fifth transistor, and the second end of the fifth transistor is connected to the input end of the duration detection module.

[0017] In some embodiments of the present disclosure, the duration detection module includes a voltage generating unit and a detection unit. A first output terminal of the voltage generating unit is connected to an inverting input terminal of the detection unit, a second output terminal of the voltage generating unit is connected to a non-inverting input terminal of the detection unit and an output terminal of the regulation module, and an output terminal of the detection unit is connected to a control terminal of the voltage generating unit.

[0018] The voltage generation unit is configured to generate a fixed safety timing voltage; when the non-constant current charging loop is operating, the positive input current of the detection unit is reduced according to the regulated current to increase the safety timing duration. The detection unit is configured to output the constant current charging timeout indication signal when the positive input voltage of the detection unit exceeds the safety timing voltage. The voltage generation unit is also configured to pull the positive input terminal of the detection unit to ground according to the constant current charging timeout indication signal.

[0019] In some embodiments of the present disclosure, the voltage generating unit includes a fourth current source, a fifth current source, a safety timing setting resistor, a capacitor, and a sixth transistor. A power supply voltage is connected to an inverting input terminal of the detection unit and a first terminal of the safety timing setting resistor via the fourth current source. The second terminal of the safety timing setting resistor, the first plate of the capacitor, and the first terminal of the sixth transistor are grounded. The power supply voltage is connected to an output terminal of the regulation module, a second plate of the capacitor, a non-inverting input terminal of the detection unit, and a second terminal of the sixth transistor via the fifth current source. The control terminal of the sixth transistor is connected to the output terminal of the detection unit.

[0020] In some embodiments of the present disclosure, the detection unit includes a comparator, wherein an inverting input terminal of the comparator is connected to a first output terminal of the voltage generating unit, a non-inverting input terminal of the comparator is connected to a second output terminal of the voltage generating unit and an output terminal of the regulating module, and an output terminal of the comparator is connected to a control terminal of the voltage generating unit.

[0021] In a second aspect, the present disclosure provides a linear charging chip, comprising a constant current charging loop, a non-constant current charging loop, and any detection circuit provided in the first aspect.

[0022] In some embodiments of the present disclosure, the constant current charging loop includes a first error amplifier, a first switch tube, a power tube, a sampling tube, a conversion resistor, and a feedback resistor. The first end of the feedback resistor and the first end of the first switch tube are grounded, the first end of the power tube and the first end of the sampling tube are connected to the output end of the linear charging chip, the second end of the power tube is connected to the positive electrode of the battery, the second end of the sampling tube is connected to the second end of the feedback resistor and the non-inverting input end of the first error amplifier, the control end of the power tube is connected to the control end of the sampling tube, the second end of the first switch tube, and the first end of the conversion resistor, the second end of the conversion resistor is connected to the power supply voltage, the control end of the first switch tube is connected to the output end of the first error amplifier, and the inverting input end of the first error amplifier is connected to the first reference voltage.

[0023] The non-constant current charging loop includes a second error amplifier, a second switch tube, the conversion resistor and the power tube, the first end of the second switch tube is grounded, the second end of the second switch tube is connected to the first end of the conversion resistor and the control end of the power tube, the control end of the second switch tube is connected to the output end of the second error amplifier, the non-inverting input end of the second error amplifier is connected to the internal node sampling voltage, and the inverting input end of the second error amplifier is connected to the third reference voltage.

[0024] The technical solution disclosed herein provides a detection circuit for a linear charging chip, including an adjustment module and a duration detection module. When a non-constant current charging loop is operating, the adjustment module generates an adjustment current based on the differential voltage between the feedback voltage and the reference voltage of the constant current charging loop. The duration detection module adaptively adjusts the safety timing duration based on the adjustment current, detects whether the constant current charging duration exceeds the safety timing duration, and generates a constant current charging timeout indication signal when the constant current charging duration exceeds the safety timing duration to instruct the linear charging chip to stop charging the battery. The safety timing duration can be adaptively increased when the non-constant current charging loop is operating, thereby improving the problem of false triggering of the safety timing function. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0026] Figure 1 A circuit diagram of a linear regulator provided by an embodiment of the present disclosure.

[0027] Figure 2 A schematic structural diagram of a detection circuit provided in an embodiment of the present disclosure.

[0028] Figure 3 A circuit diagram of a regulating module provided in an embodiment of the present disclosure.

[0029] Figure 4 A circuit diagram of a duration detection module provided in an embodiment of the present disclosure.

[0030] Figure 5 A circuit diagram of another regulating module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0033] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0034] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0035] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0036] In the description of the present disclosure, unless otherwise specified, "multiple" and "at least two" mean more than two (including two). Similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0038] The linear charging chip provided by the present disclosure includes a linear regulator, for example, the linear regulator is an LDO, and the linear regulator includes a constant current charging loop and a non-constant current charging loop, wherein the constant current charging loop and the non-constant current charging loop both operate in a constant current charging stage, and in the constant current charging stage, only one of the constant current charging loop and the non-constant current charging loop is in an operating state.

[0039] For example, Figure 1A circuit diagram of a linear charging chip provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the linear charging chip includes a linear voltage regulator, which includes a modulation transistor Q1, a power transistor Q2, a sampling transistor Q2_sns, a feedback resistor Rset, a first error amplifier EA1, a second error amplifier EA2, a first switching transistor M1, a second switching transistor M2, a conversion resistor Rs, and an output capacitor Cout. The first error amplifier EA1, the first switching transistor M1, the power transistor Q2, the sampling transistor Q2_sns, the conversion resistor Rs, and the feedback resistor Rset form a constant current charging loop, while the second error amplifier EA2, the second switching transistor M2, the power transistor Q2, and the conversion resistor Rs form part of the non-constant current charging circuit.

[0040] The first end of the feedback resistor Rset, the first plate of the output capacitor Cout, the negative electrode of the battery, the first end of the first switch tube M1 and the first end of the second switch tube M2 are grounded. The input voltage Vin is connected to the first end of the power tube Q2, the first end of the sampling tube Q2_sns, the second plate of the output capacitor Cout and the output end of the linear regulator through the modulation tube Q1. The second end of the power tube Q2 is connected to the positive electrode of the battery, and the second end of the sampling tube Q2_sns is connected to the second end of the feedback resistor Rset and the non-inverting input end of the first error amplifier EA1.

[0041] The control terminal of the power transistor Q2 is connected to the control terminal of the sampling transistor Q2_sns, the second terminal of the first switching transistor M1, the second terminal of the second switching transistor M2, and the first terminal of the conversion resistor Rs. The second terminal of the conversion resistor Rs is connected to the power supply voltage Vbp. The control terminal of the first switching transistor M1 is connected to the output terminal of the first error amplifier EA1, and the control terminal of the second switching transistor M2 is connected to the output terminal of the second error amplifier EA2. The inverting input terminal of the first error amplifier EA1 receives the first reference voltage Vref1, the non-inverting input terminal of the second error amplifier EA2 receives an internal node sampling voltage Vusb_fb, and the inverting input terminal of the second error amplifier EA2 receives a reference voltage different from the first reference voltage Vref1, namely, a third reference voltage Vref'.

[0042] During the constant charging phase, modulation transistor Q1 modulates the input voltage Vin to provide charging current Ibat, which flows through power transistor Q2 to charge the battery. When the constant-current charging loop is operating, power transistor Q2 and sampling transistor Q2_sns form a current mirror structure, with the aspect ratio of power transistor Q2:sampling transistor Q2_sns = N:1, where N is an integer greater than or equal to 1. Sampling transistor Q2_sns can mirror the charging current Ibat flowing through power transistor Q2 into a sampling current Isns, where Isns = Ibat / N.

[0043] After the sampling current Isns flows through the feedback resistor Rset, a voltage drop is generated across the feedback resistor Rset, resulting in a feedback voltage Vset, and Vset = Isns * Rset, where Rset is the resistance of the feedback resistor Rset. The first error amplifier EA1 uses the feedback voltage Vset as the positive input voltage and the first reference voltage Vref1 as the negative input voltage to calculate the error-amplified voltage between the feedback voltage Vset and the first reference voltage Vref1. The first switch tube M1 adjusts the current flowing through the first switch tube M1 based on the error-amplified voltage between the feedback voltage Vset and the first reference voltage Vref1, thereby adjusting the control voltage of the power tube Q2, and further adjusting the charging current Ibat to maintain the charging current Ibat stable. At this time, the current value of the charging current Ibat is a preset current value Ichg, that is, Ibat = Ichg = N * Vref1 / Rsett.

[0044] When the non-constant current charging loop is working, the second error amplifier EA2 uses the internal node sampling voltage Vusb_fb as the positive input voltage and the reference voltage Vref' as the negative input voltage to calculate the error amplification voltage of the internal node sampling voltage Vusb_fb and the reference voltage Vref'. The second switch tube M2 adjusts the current flowing through the second switch tube M2 according to the error amplification voltage of the internal node sampling voltage Vusb_fb and the reference voltage Vref', thereby adjusting the control voltage of the power tube Q2, and then adjusting the charging current Ibat to maintain the charging current Ibat stable. At this time, the current value of the charging current Ibat will be less than the preset current value Ichg, that is, Ibat=Ichg=N*Vref1 / Rsett <Ichg。

[0045] The linear charging chip provided in the present disclosure also includes a detection circuit, which can detect the charging duration of the constant current charging stage and generate a constant current charging timeout indication signal when the charging duration of the constant current charging stage exceeds the safety timing duration. The linear charging chip stops charging the battery according to the constant current charging timeout indication signal to trigger the safety timing function, thereby reducing the safety risks of the charging process.

[0046] Compared to the battery charging speed when the constant current charging loop is operating, the battery charging speed will be slower when the non-constant current charging loop is operating. Therefore, the corresponding safety timer duration should be longer to accurately trigger the safety timer function. However, the current safety timer duration is based on a fixed time duration preset by the resistor. Therefore, when the non-constant current charging loop is operating, the triggering accuracy of the safety timer function is low, resulting in the problem of false triggering of the safety timer function.

[0047] In view of this, the detection circuit provided by the present invention includes an adjustment module and a duration detection module. When the non-constant current charging loop is working, the adjustment module generates an adjustment current based on the differential voltage between the feedback voltage and the first reference voltage. The first reference voltage is the reference voltage of the constant current charging loop. The duration detection module adaptively adjusts the safety timing duration according to the adjustment current, detects whether the constant current charging duration exceeds the safety timing duration, and generates a constant current charging timeout indication signal when the constant current charging duration exceeds the safety timing duration to instruct the linear charging chip to stop charging the battery. It can adaptively increase the safety timing duration when the non-constant current charging loop is working, thereby improving the problem of false triggering of the safety timing function.

[0048] The detection circuit provided by the present disclosure is described in detail below with reference to several specific embodiments.

[0049] Figure 2 A schematic diagram of a detection circuit according to an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the detection circuit 100 includes an adjustment module 110 and a duration detection module 120. A first input terminal of the adjustment module 110 is connected to a first reference voltage Vref1, a second input terminal of the adjustment module 110 is connected to a feedback voltage Vset, an output terminal of the adjustment module 110 is connected to an input terminal of the duration detection module 120, and an output terminal of the duration detection module 120 is connected to an output terminal of the detection circuit 100.

[0050] The regulation module 110 is configured to generate a regulated current Idisc based on the differential voltage Vref1-Vset between the feedback voltage Vset and a first reference voltage Vref1 when the non-constant current charging loop is operating. The first reference voltage Vref1 serves as the reference voltage for the constant current charging loop. The duration detection module 120 is configured to adaptively adjust the safety timer duration based on the regulated current Idisc when the non-constant current charging loop is operating, detect whether the constant current charging duration exceeds the safety timer duration, and generate a constant current charging timeout indication signal Vcc_to when the constant current charging duration exceeds the safety timer duration, thereby instructing the linear charging chip to stop charging the battery.

[0051] For example, Figure 3 This is a circuit diagram of a regulation module provided by an embodiment of the present disclosure, including a first conversion unit 111 and a current generating unit 112. The first input of the first conversion unit 111 is connected to a first reference voltage Vref1, the second input of the first conversion unit 111 is connected to a feedback voltage Vset, the output of the first conversion unit 111 is connected to an input of the current generating unit 112, and the output of the current generating unit 112 is connected to an input of the duration detection module 120.

[0052] Specifically, such as Figure 3As shown, the first conversion unit 111 includes a first operational amplifier OPA1, a first transistor Mn0, a first current source IB1, a second operational amplifier OPA2, and a first resistor R1. The non-inverting input terminal of the first operational amplifier OPA1 is connected to the first reference voltage Vref1, the inverting input terminal of the first operational amplifier OPA1 is connected to the first terminal of the first transistor Mn0 and the first terminal of the first resistor R1, the output terminal of the first operational amplifier OPA1 is connected to the control terminal of the first transistor Mn0, the first terminal of the first transistor Mn0 is grounded via the first current source IB1, and the second terminal of the first transistor Mn0 is connected to the power supply voltage VDD.

[0053] The second end of the first resistor R1 is connected to the non-inverting input end of the second operational amplifier OPA2 and the input end of the current generating unit 112, the inverting input end of the second operational amplifier OPA2 is connected to the feedback voltage Vset, and the output end of the second operational amplifier OPA2 is connected to the control end of the current generating unit 112.

[0054] The first reference voltage Vref1 is typically derived from a bandgap reference resistor divider string. To ensure accurate voltage division, the first reference voltage Vref1 must not be able to sink or source current, meaning it lacks drive capability. A first operational amplifier OPA1 and a first transistor Mn0 form a buffer circuit that converts the first reference voltage Vref1 into a second reference voltage Vref with drive capability. The conversion of the first reference voltage Vref1 only improves the drive capability without changing the voltage value. Consequently, the first reference voltage Vref1 and the second reference voltage Vref2 are equal in value. Specifically, the differential voltage Vref1-Vset between the feedback voltage Vset and the first reference voltage Vref1 is equal to the differential voltage Vref2-Vset between the feedback voltage Vset and the second reference voltage Vref2.

[0055] The second operational amplifier OPA2 clamps its non-inverting input voltage to the feedback voltage Vset, that is, the voltage at the second end of the first resistor R1 is the feedback voltage Vset, and the voltage at the first end of the first resistor R1 is the second reference voltage Vref2. The voltage drop across the first resistor R1 is the differential voltage Vref2-Vset between the feedback voltage Vset and the second reference voltage Vref2. Therefore, the current flowing through the first resistor R2 is (Vref2-Vset) / R1, that is, the bias current Ibias=(Vref2-Vset) / R1, where R1 is the resistance value of the first resistor R1.

[0056] Continue to see Figure 3The current generating unit 112 includes a fourth transistor Mn1 and a fifth transistor Mn2. The ratio of the width-to-length ratio of the fourth transistor Mn1 to the width-to-length ratio of the fifth transistor Mn2 is M:1, where M is an integer greater than 1. A first end of the fourth transistor Mn1 and a first end of the fifth transistor Mn2 are grounded. A second end of the fourth transistor Mn1 is connected to an input end of the current generating unit 112. A control end of the fourth transistor Mn1 is connected to the control end of the current generating unit 112 and the control end of the fifth transistor Mn2. A second end of the fifth transistor Mn2 is connected to an input end of the duration detection module 120.

[0057] The fourth transistor Mn1 and the fifth transistor Mn2 form a current mirror. The current flowing through the fourth transistor Mn1 is the bias current Ibias. The fifth transistor Mn2 can mirror the bias current Ibias to a regulated current Idisc, where Idisc = Ibias / M = (Vref2-Vset) / (M*R1). When the constant current charging loop is operating, Vref1 = Vset, and the regulated current Idisc is zero. When the non-constant current charging loop is operating, Vref1 ≠ Vset, the regulated current Idisc is non-zero, and is injected into the duration detection module 120 as the source current.

[0058] In this way, the first conversion unit 111 can convert the first reference voltage Vref1 into a second reference voltage Vref2 with drive capability, and convert the differential voltage Vref2-Vset between the feedback voltage Vset and the second reference voltage Vref2 into a bias current Ibias. The second reference voltage Vref2 has the same voltage value as the first reference voltage Vref1. The current generation unit 112 can determine the adjustment current bias current Idisc based on the bias current Ibias.

[0059] For example, Figure 4 A current diagram of a duration detection module provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the duration detection module 120 includes a voltage generating unit 121 and a detection unit 122, the first output end of the voltage generating unit 121 is connected to the inverting input end of the detection unit 122, the second output end of the voltage generating unit 121 is connected to the non-inverting input end of the detection unit 122 and the output end of the adjustment module 110, and the output end of the detection unit 122 is connected to the control end of the voltage generating unit 121.

[0060] Specifically, such as Figure 4As shown, the voltage generating unit 121 includes a fourth current source IB4, a fifth current source IB5, a safety timing setting resistor Rtmr, a capacitor C, and a sixth transistor Mn3. The power supply voltage VDD is connected to the inverting input terminal of the detection unit 122 and the first terminal of the safety timing setting resistor Rtmr via the fourth current source IB4. The second terminal of the safety timing setting resistor Rtmr, the first plate of the capacitor C, and the first terminal of the sixth transistor Mn3 are grounded. The power supply voltage VDD is connected to the output terminal of the regulation module 110, the second plate of the capacitor C, the non-inverting input terminal of the detection unit 122, and the second terminal of the sixth transistor Mn3 via the fifth current source IB5. The control terminal of the sixth transistor Mn3 is connected to the output terminal of the detection unit 122.

[0061] The detection unit 122 includes a comparator CMP, an inverting input terminal of the comparator CMP is connected to the first output terminal of the voltage generating unit 121, a non-inverting input terminal of the comparator CMP is connected to the second output terminal of the voltage generating unit 121 and the output terminal of the regulation module 110, and an output terminal of the comparator CMP is connected to the control terminal of the voltage generating unit 121.

[0062] After the safety timing bias current Itmr provided by the fourth current source IB4 flows through the safety timing setting resistor Rtmr, a voltage drop is generated across the safety timing setting resistor Rtmr, resulting in a fixed safety timing voltage Vtmr, where Vtmr = Itmr * Rtmr, where Rtmr is the resistance value of the safety timing setting resistor Rtmr. Therefore, by setting the safety timing setting resistor Rtmr with different resistance values, different safety timing voltages Vtmr can be flexibly set, thereby setting different safety timing durations.

[0063] A fixed bias current Ichg provided by the fifth current source IB5 flows into the second plate of capacitor C, acting as a charging current to charge capacitor C. The voltage Vcap of the second plate of capacitor C gradually increases. The voltage Vcap of the second plate of capacitor C serves as the non-inverting input voltage of the comparator CMP, and the safety timing voltage Vtmr serves as the inverting input voltage of the comparator CMP. When the voltage Vcap of the second plate of capacitor C reaches the safety timing voltage Vtmr, the comparator CMP outputs an indication signal Vcc, which is the constant current charging timeout indication signal Vcc_to. For example, the constant current charging timeout indication signal Vcc_to is a high-level signal.

[0064] At this time, the sixth transistor Mn3 is in the on state, and can pull the non-inverting input terminal of the comparator CMP to the ground, that is, the voltage Vcap of the second plate of the capacitor C is zero. It can be understood that the voltage Vcap of the second plate of the capacitor C is an oscillation signal.

[0065] Continue to see Figure 4The detection unit 122 further includes a control switch K, and the non-inverting input terminal of the detection unit 122 is connected to the output terminal of the current regulating module 110 through the control switch K. When the constant current charging loop is operating, the control switch K is in the off state, and the regulating current Idisc does not flow from the second plate of the capacitor C into the regulating module 110. At this time, the voltage Vcap of the second plate of the capacitor C is only positively correlated with the fixed bias current Ichg, and the oscillation period of the voltage Vcap of the second plate of the capacitor C is (C'*Rtmr*Itmr) / Ichg, where C' is the capacitance of the capacitor C.

[0066] When the non-constant current charging loop is operating, the control switch K is in the on state, and the regulated current Idisc serves as the discharge current of the capacitor C, flowing from the second plate of the capacitor C into the regulation module 110. At this time, the voltage Vcap of the second plate of the capacitor C is positively correlated with Ichg-Idisc, and the oscillation period of the voltage Vcap of the second plate of the capacitor C is (C'*Rtmr*Itmr) / (Ichg-Idisc). Compared to the fixed oscillation period of the voltage Vcap of the second plate of the capacitor C when the constant current charging loop is operating, the oscillation period of the voltage Vcap of the second plate of the capacitor C when the non-constant current charging loop is operating is longer, that is, the safety timing duration can be adaptively increased.

[0067] In other embodiments, the non-inverting input terminal of the detection unit 122 can be directly connected to the output terminal of the current regulation module 110. When the constant current charging loop is operating, the regulated current Idisc is zero, Ichg-Idisc=Ichg, then the voltage Vcap of the second plate of capacitor C is only positively correlated with the fixed bias current Ichg, and the oscillation period of the voltage Vcap of the second plate of capacitor C is (C'*Rtmr*Itmr) / Ichg. When the non-constant current charging loop is operating, the regulated current Idisc is not zero, the voltage Vcap of the second plate of capacitor C is positively correlated with Ichg-Idisc, then the oscillation period of the voltage Vcap of the second plate of capacitor C is (C'*Rtmr*Itmr) / (Ichg-Idisc).

[0068] In this way, the voltage generating unit 121 can generate a fixed safety timing voltage, and when the non-constant current charging loop is working, the positive input current of the detection unit 122 is reduced according to the adjustment current Idisc to increase the safety timing duration. When the positive input voltage of the detection unit 122 exceeds the safety timing voltage Vtmr, the detection unit 122 outputs the constant current charging timeout indication signal Vcc_to. The voltage generating unit 121 can also pull the positive input terminal of the detection unit 122 to the ground through the constant current charging timeout indication signal Vcc_to.

[0069] In some embodiments, Figure 5A circuit diagram of another regulating module provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the regulation module 110 includes a second conversion unit 113 and a current generating unit 112. A first input terminal of the second conversion unit 113 is connected to a first reference voltage Vref1, a second input terminal of the second conversion unit 113 is connected to a feedback voltage Vset, an output terminal of the second conversion unit 113 is connected to an input terminal of the current generating unit 112, and an output terminal of the current generating unit 112 is connected to an input terminal of the duration detection module 120.

[0070] The second conversion unit 113 is configured to generate a first voltage V1 based on the feedback voltage Vset, generate a second voltage V2 based on the first reference voltage Vref1, and convert the differential voltage V1-V2 between the first voltage V1 and the second voltage V2 into a bias current Ibias. The differential voltage V2-V1 between the first voltage V1 and the second voltage V2 is equal to the differential voltage Vref1-Vset between the feedback voltage Vset and the first reference voltage Vref1. The current generation unit 112 is configured to determine a regulation current Idisc based on the bias current Ibias.

[0071] Exemplarily, the second conversion unit 113 includes a second current source IB2, a third current source IB3, a second transistor Mp1, a third transistor Mp2, a third operational amplifier OPA3, and a second resistor R2. The power supply voltage VDD is connected to the first terminal of the second transistor Mp1 and the inverting input terminal of the third operational amplifier OPA3 via the second current source IB2. The power supply voltage VDD is connected to the first terminal of the third transistor Mp2 and the first terminal of the second resistor R2 via the third current source IB3. The control terminal of the second transistor Mp1 is connected to the feedback voltage Vset, the control terminal of the third transistor Mp2 is connected to the first reference voltage Vref1, and the second terminal of the second transistor Mp1 and the second terminal of the third transistor Mp2 are grounded.

[0072] The second end of the second resistor R2 is connected to the non-inverting input end of the third operational amplifier OPA3 and the input end of the current generating unit 112 , and the output end of the third operational amplifier OPA3 is connected to the control end of the current generating unit 112 .

[0073] After the current provided by the second current source IB2 flows through the second transistor Mp1, a voltage drop is generated across the second transistor Mp1, resulting in a first voltage V1, where V1 = Vset + Vth_Mp1, where Vth_Mp1 is the threshold voltage of the second transistor Mp1. After the current provided by the third current source IB3 flows through the third transistor Mp2, a voltage drop is generated across the third transistor Mp2, resulting in a second voltage V2, where V2 = Vref1 + Vth_Mp2, where Vth_Mp2 is the threshold voltage of the third transistor Mp2. The voltage difference across the second resistor R2 is V2-V1. The current flowing through the second resistor R2 is the bias current Ibias, and Ibias = (V2-V1) / R2 = [(Vref1+Vth_Mp2)-(Vset+Vth_Mp1)] / R2, where R2 is the resistance value of the second resistor R2.

[0074] By selecting an appropriate second current source IB2 and third current source IB3 and adjusting the magnitude of the current flowing through the second transistor Mp1 and the third transistor Mp2, the second transistor Mp1 and the third transistor Mp2 can be operated in the subthreshold region. In this case, Vth_Mp1 is approximately equal to Vth_Mp2, and V2-V1 is approximately equal to Vref1-Vset. Therefore, the bias current Ibias is approximately equal to (Vref1-Vset) / R2. The current provided by the third current source needs to be greater than the bias current Ibias to ensure normal operation of the circuit.

[0075] For example, the current provided by the third current source is slightly greater than the bias current Ibias, which can ensure normal operation of the circuit and reduce unnecessary power consumption. The second transistor Mp1 and the third transistor Mp2 only need to match each other on the layout and do not need to be large in size.

[0076] In the embodiment of the present disclosure, the function of the first operational amplifier OPA1 can be realized by the second current source IB2, the third current source IB3, the second transistor Mp1 and the third transistor Mp2, which can reduce the number of operational amplifiers in the circuit and reduce the area and power consumption of the detection circuit 100.

[0077] In some embodiments, as Figure 3 As shown, the first conversion unit 111 further includes a sixth current source IB6 , and the power supply voltage VDD is connected to the second end of the first transistor Mn0 through the sixth current source IB6 .

[0078] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0079] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A detection circuit for a linear charging chip, characterized in that: The linear charging chip includes a constant current charging loop and a non-constant current charging loop. In the constant current charging stage, one of the constant current charging loop and the non-constant current charging loop is in an operating state; the detection circuit includes an adjustment module and a duration detection module; The regulation module is configured to, when the non-constant current charging loop is operating, generate a regulation current according to a differential voltage between a feedback voltage and a first reference voltage, where the first reference voltage is a reference voltage of the constant current charging loop; The duration detection module is configured to, when the non-constant current charging loop is operating, adaptively adjust the safety timing duration according to the regulated current, detect whether the constant current charging duration exceeds the safety timing duration, and generate a constant current charging timeout indication signal when the constant current charging duration exceeds the safety timing duration to instruct the linear charging chip to stop charging the battery.

2. The detection circuit according to claim 1, characterized in that The regulating module includes a first conversion unit and a current generating unit; The first input terminal of the first conversion unit is connected to the first reference voltage, the second input terminal of the first conversion unit is connected to the feedback voltage, the output terminal of the first conversion unit is connected to the input terminal of the current generating unit, and the output terminal of the current generating unit is connected to the input terminal of the duration detection module; The first conversion unit is configured to convert the first reference voltage into a second reference voltage with driving capability, and convert the differential voltage between the feedback voltage and the second reference voltage into a bias current, wherein the second reference voltage has a voltage value equal to that of the first reference voltage; The current generating unit is configured to determine the regulating current according to the bias current.

3. The detection circuit according to claim 1, characterized in that: The regulating module includes a second conversion unit and a current generating unit; A first input terminal of the second conversion unit is connected to the first reference voltage, a second input terminal of the second conversion unit is connected to the feedback voltage, an output terminal of the second conversion unit is connected to the input terminal of the current generating unit, and an output terminal of the current generating unit is connected to the input terminal of the duration detection module; The second conversion unit is configured to generate a first voltage according to the feedback voltage, generate a second voltage according to the first reference voltage, and convert a differential voltage between the first voltage and the second voltage into a bias current, wherein the differential voltage between the first voltage and the second voltage is equal to the differential voltage between the feedback voltage and the first reference voltage; The current generating unit is configured to determine the regulating current according to the bias current.

4. The detection circuit according to claim 2, characterized in that: The first conversion unit includes a first operational amplifier, a first transistor, a first current source, a second operational amplifier and a first resistor; a non-inverting input terminal of the first operational amplifier connected to the first reference voltage, an inverting input terminal of the first operational amplifier connected to the first terminal of the first transistor and the first terminal of the first resistor, an output terminal of the first operational amplifier connected to the control terminal of the first transistor, a first terminal of the first transistor connected to ground via the first current source, and a second terminal of the first transistor connected to a power supply voltage; The second end of the first resistor is connected to the non-inverting input end of the second operational amplifier and the input end of the current generating unit, the inverting input end of the second operational amplifier is connected to the feedback voltage, and the output end of the second operational amplifier is connected to the control end of the current generating unit.

5. The detection circuit according to claim 3, characterized in that: The second conversion unit includes a second current source, a third current source, a second transistor, a third transistor, a third operational amplifier, and a second resistor, wherein the second transistor and the third transistor operate in a subthreshold region, and the current provided by the third current source is greater than the bias current; The power supply voltage is connected to the first end of the second transistor and the inverting input end of the third operational amplifier through the second current source, the power supply voltage is connected to the first end of the third transistor and the first end of the second resistor through the third current source, the control end of the second transistor is connected to the feedback voltage, the control end of the third transistor is connected to the first reference voltage, the second end of the second transistor and the second end of the third transistor are grounded, the second end of the second resistor is connected to the non-inverting input end of the third operational amplifier and the input end of the current generating unit, and the output end of the third operational amplifier is connected to the control end of the current generating unit.

6. The detection circuit according to any one of claims 2 to 5, characterized in that: The current generating unit includes a fourth transistor and a fifth transistor, wherein a ratio of a width-to-length ratio of the fourth transistor to a width-to-length ratio of the fifth transistor is M:1, where M is an integer greater than 1; The first end of the fourth transistor and the first end of the fifth transistor are grounded, the second end of the fourth transistor is connected to the input end of the current generating unit, the control end of the fourth transistor is connected to the control end of the current generating unit and the control end of the fifth transistor, and the second end of the fifth transistor is connected to the input end of the duration detection module.

7. The detection circuit according to any one of claims 1 to 5, characterized in that: The duration detection module includes a voltage generating unit and a detection unit; The first output terminal of the voltage generating unit is connected to the inverting input terminal of the detection unit, the second output terminal of the voltage generating unit is connected to the non-inverting input terminal of the detection unit and the output terminal of the regulation module, and the output terminal of the detection unit is connected to the control terminal of the voltage generating unit; The voltage generating unit is configured to generate a fixed safety timing voltage; When the non-constant current charging loop is operating, reducing the positive phase input current of the detection unit according to the regulated current to increase the safety timing duration; The detection unit is configured to output the constant current charging timeout indication signal when the positive phase input voltage of the detection unit exceeds the safety timing voltage; The voltage generating unit is further configured to pull the non-inverting input terminal of the detection unit to ground according to the constant current charging timeout indication signal.

8. The detection circuit according to claim 7, characterized in that: The voltage generating unit includes a fourth current source, a fifth current source, a safety timing setting resistor, a capacitor and a sixth transistor; The power supply voltage is connected to the inverting input terminal of the detection unit and the first terminal of the safety timing setting resistor through the fourth current source, the second terminal of the safety timing setting resistor, the first plate of the capacitor, and the first terminal of the sixth transistor are grounded, the power supply voltage is connected to the output terminal of the regulation module, the second plate of the capacitor, the non-inverting input terminal of the detection unit, and the second terminal of the sixth transistor through the fifth current source, and the control terminal of the sixth transistor is connected to the output terminal of the detection unit; The detection unit includes a comparator, the inverting input end of the comparator is connected to the first output end of the voltage generating unit, the non-inverting input end of the comparator is connected to the second output end of the voltage generating unit and the output end of the regulation module, and the output end of the comparator is connected to the control end of the voltage generating unit.

9. A linear charging chip, characterized in that: The invention comprises a constant current charging loop, a non-constant current charging loop and the detection circuit according to any one of claims 1 to 8.

10. The linear charging chip according to claim 9, characterized in that: The constant current charging loop includes a first error amplifier, a first switch tube, a power tube, a sampling tube, a conversion resistor and a feedback resistor; The first end of the feedback resistor and the first end of the first switch tube are grounded, the first end of the power tube and the first end of the sampling tube are connected to the output end of the linear charging chip, the second end of the power tube is connected to the positive electrode of the battery, the second end of the sampling tube is connected to the second end of the feedback resistor and the non-inverting input end of the first error amplifier, the control end of the power tube is connected to the control end of the sampling tube, the second end of the first switch tube and the first end of the conversion resistor, the second end of the conversion resistor is connected to the power supply voltage, the control end of the first switch tube is connected to the output end of the first error amplifier, and the inverting input end of the first error amplifier is connected to the first reference voltage; The non-constant current charging loop includes a second error amplifier, a second switch tube, the conversion resistor and the power tube, the first end of the second switch tube is grounded, the second end of the second switch tube is connected to the first end of the conversion resistor and the control end of the power tube, the control end of the second switch tube is connected to the output end of the second error amplifier, the non-inverting input end of the second error amplifier is connected to the internal node sampling voltage, and the inverting input end of the second error amplifier is connected to the third reference voltage.

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