DC-DC converter OOA mode control circuit and method, chip and electronic equipment

Abstract

The invention provides a DCDC converter OOA mode control circuit and method, a chip and electronic equipment, and relates to the technical field of power management chips, and the DCDC converter OOA mode control circuit comprises a logic control circuit, a digital processing circuit and a controlled current source. The first input end and the second input end of the logic control circuit are respectively connected with an inductive current and a trigger signal, and the output end of the logic control circuit is electrically connected with the second input end of the digital processing circuit; the first input end of the digital processing circuit accesses a trigger signal, and the output end of the digital processing circuit is electrically connected with the control end of the controlled current source; the input end of the controlled current source is electrically connected with the switch node, and the output end is grounded; the logic control circuit obtains a driving logic signal according to the inductive current and a preset duration; and the digital processing circuit controls the output current of the controlled current source according to the driving logic signal and the trigger signal. A bleeder current adaptive to load change is introduced into a switch node, so that the problem of double pulses can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a DCDC converter OOA mode control circuit, method, chip and electronic device. Background Art

[0002] For step-down converters (Buck circuits), they achieve higher conversion efficiency by reducing the switching frequency under light load conditions. The human ear can hear frequencies between 2 Hz and 20 kHz. This process can reduce the Buck circuit's switching frequency to within the audible range. To avoid this problem, Out-of-Audio (OOA) technology was proposed. This technology is a light-load operating mode that forces the loop to trigger, controlling the switching frequency to a set value and preventing the Buck circuit's switching frequency from entering the audible range.

[0003] Traditional OOA technologies include two methods: reducing the Ton time (i.e., the upper tube on-time) and timed forced discharge. Reducing the Ton time is not suitable for high-frequency and high-ratio applications because the Ton time is already very small in these applications. Further reducing the Ton time can cause system problems. Timed forced discharge is a common technique, but it can cause large transient jumps at the output node of the buck circuit, resulting in double pulses and wasted power. Summary of the Invention

[0004] The present application provides a DCDC converter OOA mode control circuit, method, chip and electronic device to reduce the double pulse problem caused by a large undershoot of the feedback voltage VFB, and can reduce the power consumption waste caused by the large undershoot of the feedback voltage VFB.

[0005] In a first aspect, the present application provides a DCDC converter OOA mode control circuit, comprising: a logic control circuit, a digital processing circuit, and a controlled current source;

[0006] The first input terminal of the logic control circuit is connected to the inductor current, the second input terminal of the logic control circuit is connected to the trigger signal, the output terminal of the logic control circuit is electrically connected to the second input terminal of the digital processing circuit, the first input terminal of the digital processing circuit is connected to the trigger signal, the output terminal of the digital processing circuit is electrically connected to the control terminal of the controlled current source, the input terminal of the controlled current source is electrically connected to the switch node, and the output terminal of the controlled current source is grounded;

[0007] The logic control circuit is configured to compare a duration during which the inductor current is zero with a preset duration to obtain a drive logic signal, and transmit the drive logic signal to the digital processing circuit, wherein the preset duration is a time interval between two adjacent trigger signals;

[0008] The digital processing circuit is used to control the magnitude of the output current of the controlled current source according to the driving logic signal and the trigger signal, so as to generate the trigger signal with a period of the preset time length.

[0009] In one possible design, the logic control circuit is specifically configured to: when the inductor current is zero, start timing the duration of the inductor current being zero to obtain the timing duration;

[0010] When the timing duration is greater than the preset duration, obtaining the driving logic signal of the first level;

[0011] When the timing duration is less than or equal to the preset duration, obtaining the driving logic signal of the second level;

[0012] When the trigger signal is received, the driving logic signal at the first level is switched to the driving logic signal at the second level.

[0013] In one possible design, the digital processing circuit is specifically configured to: when the driving logic signal is at the first level and when the trigger signal is received, control the current level of the controlled current source to increase gradually, so as to increase the output current of the controlled current source;

[0014] When the driving logic signal is at the second level and the trigger signal is received, the current level of the controlled current source is controlled to decrease gradually, so as to reduce the output current of the controlled current source.

[0015] In one possible design, the output current of the controlled current source is positively correlated with the current range of the controlled current source.

[0016] In one possible design, an input terminal of the controlled current source is electrically connected to an output node.

[0017] In a second aspect, the present application provides a DCDC converter OOA mode control method, which is applied to the DCDC converter OOA mode control circuit according to the first aspect, and the method includes:

[0018] Comparing the duration when the inductor current is zero with a preset duration to obtain a driving logic signal, wherein the preset duration is the time interval between two adjacent trigger signals;

[0019] According to the driving logic signal and the trigger signal, the magnitude of the output current of the controlled current source is controlled to generate the trigger signal with a period of the preset time length.

[0020] In one possible design, the duration during which the inductor current is zero is compared with a preset duration to obtain a driving logic signal, including:

[0021] When the inductor current is zero, start timing the duration of the inductor current being zero to obtain the timing duration;

[0022] When the timing duration is greater than the preset duration, obtaining the driving logic signal of the first level;

[0023] When the timing duration is less than or equal to the preset duration, obtaining the driving logic signal of the second level;

[0024] When the trigger signal is received, the driving logic signal at the first level is switched to the driving logic signal at the second level.

[0025] In one possible design, controlling the magnitude of the output current of the controlled current source according to the driving logic signal and the trigger signal to generate the trigger signal having a period of the preset duration includes:

[0026] When the driving logic signal is at the first level and the trigger signal is received, controlling the current gear of the controlled current source to increase gradually, so as to increase the output current of the controlled current source;

[0027] When the driving logic signal is at the second level and the trigger signal is received, the current level of the controlled current source is controlled to decrease gradually, so as to reduce the output current of the controlled current source.

[0028] In a third aspect, the present application provides a chip comprising: the DCDC converter OOA mode control circuit as described in the first aspect.

[0029] In a fourth aspect, the present application provides an electronic device, comprising: the chip as described in the third aspect.

[0030] Beneficial effects of the embodiments of the present application:

[0031] In the embodiment of the present application, the magnitude of the output current IDIS of the controlled current source is controlled by a logic control circuit and a digital processing circuit, so that the discharge current introduced by the switch node SW can be adaptively adjusted according to the load conditions. By adjusting the discharge current of the switch node SW, the loop is forced to automatically generate a trigger signal with a period of a preset duration, thereby achieving a relatively constant discharge period. Under different load conditions, that is, when the load changes, the time required for the trigger loop to generate the trigger signal SET is equal to the preset duration t OOA , which can reduce the double pulse problem caused by the large undershoot of the feedback voltage VFB when the load changes, so that the Buck circuit can smoothly switch to the OOA working mode when the load switches from heavy load to light load, realize the control of the switching frequency, and reduce the power consumption waste caused by the large undershoot of the feedback voltage VFB. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0033] Figure 1 A schematic diagram of a Buck circuit structure provided for related technologies;

[0034] Figure 2 A traditional OOA model diagram provided for related technologies;

[0035] Figure 3 A schematic diagram of a DCDC converter OOA mode control circuit structure is provided for an embodiment of the present application;

[0036] Figure 4 This is a signal flow chart of a DCDC converter OOA mode control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0038] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0039] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0040] In order to better understand the technical solution of this application, this application uses the Buck circuit as an example for explanation. Figure 1 , Figure 1 A Buck circuit structure diagram provided for related technologies, such as Figure 1 As shown in FIG, when the load RL changes from a heavy load to a light load, the Buck circuit enters the OOA mode. The OOA mode can control the switching frequency of the Buck circuit to a set value.

[0041] See also Figure 2 and Figure 1 , Figure 2 A traditional OOA model diagram provided for related technologies, such as Figure 2and Figure 1 As shown in the figure, after the inductor current IL decreases to zero, the buck circuit provides the voltage required by the load RL through the output capacitor Cout, and the feedback voltage VFB slowly decreases. After a fixed time tm, a bleeder current is introduced to quickly discharge the switch node SW, causing the feedback voltage VFB to drop below the reference voltage VREF. This triggers the loop to generate the trigger signal SET. The trigger signal SET controls the state of the high-side transistor HS, forcing it to turn on, thereby increasing the buck circuit's switching frequency.

[0042] In order to ensure that the trigger loop can accurately generate the trigger signal SET, the magnitude of the bleeder current is usually designed so that when there is no load, after a fixed time tm, the feedback voltage VFB just drops to the reference voltage VREF. However, in actual applications, the magnitude of the bleeder current cannot be adjusted as the load changes. Figure 2 When the load changes, the feedback voltage VFB may have a large undershoot, and a trigger signal SET appears. At this time, the feedback voltage VFB is much lower than the reference voltage VREF. As the trigger signal SET turns on the high-side tube HS, the inductor current IL begins to increase, and the feedback voltage VFB begins to rise. As the cycle ends, the feedback voltage VFB will drop back to the reference voltage VREF, resulting in the rapid generation of a second trigger signal SET, which appears as a double pulse on the waveform. Figure 2 The dotted line portion of the feedback voltage VFB is a schematic diagram showing that in a no-load state, the feedback voltage VFB drops to the reference voltage VREF to generate the trigger signal SET.

[0043] In order to solve the problem of double pulses in the traditional OOA mode when the load changes, and the power consumption problem caused by the large undershoot of the feedback voltage VFB in the related art, the present application embodiment provides a DCDC converter OOA mode control circuit 1000, see Figure 3 , Figure 3 The present invention provides a DCDC converter OOA mode control circuit structure diagram, as shown in FIG. Figure 3 As shown, the DCDC converter OOA mode control circuit 1000 may include: a logic control circuit 100, a digital processing circuit 200 and a controlled current source CS.

[0044] The first input terminal of the logic control circuit 100 is connected to the inductor current IL, the second input terminal of the logic control circuit 100 is connected to the trigger signal SET, the output terminal of the logic control circuit 100 is electrically connected to the second input terminal of the digital processing circuit 200, the first input terminal of the digital processing circuit 200 is connected to the trigger signal SET, the output terminal of the digital processing circuit 200 is electrically connected to the control terminal of the controlled current source CS, the input terminal of the controlled current source CS is electrically connected to the switch node SW, and the output terminal of the controlled current source CS is grounded.

[0045] The logic control circuit 100 is used to compare the zero time length with the preset time length t OOA Compare and obtain the driving logic signal OOA_D, and transmit the driving logic signal OOA_D to the digital processing circuit 200, wherein the preset time length t OOA is the time interval between two adjacent trigger signals SET.

[0046] The digital processing circuit 200 is used to control the output current I of the controlled current source CS according to the driving logic signal OOA_D and the trigger signal SET. DIS The size of the generated cycle is the preset duration t OOA The trigger signal SET.

[0047] In this application, the DCDC converter may be a step-down circuit, ie, a Buck circuit.

[0048] For Buck circuits, see Figure 1 and Figure 2 A Buck circuit operating cycle includes the following stages: the high-side switch HS turns on, the low-side switch LS turns off, and the inductor current IL begins to increase; the high-side switch HS turns off, the low-side switch LS turns on, and the inductor current IL begins to decrease; the high-side switch HS turns off, the low-side switch LS turns off, and the inductor current IL reaches zero; the feedback voltage VFB naturally decreases. When the feedback voltage VFB drops to the reference voltage VREF, the trigger loop generates a trigger signal SET, turning the high-side switch HS on again, and entering the next operating cycle. This is prior art and will not be further described in this application.

[0049] In the OOA operating mode, the traditional timed forced discharge technology starts timing when the inductor current IL is 0. After the timing ends, the discharge current is introduced to force the switch node SW to discharge, causing the feedback voltage VFB to drop to the reference voltage VREF, thereby triggering the loop to generate a trigger signal SET. The trigger signal SET forces the high-side tube HS to turn on, thereby increasing the switching frequency of the Buck circuit. In other words, in the OOA operating mode, the traditional timed forced discharge technology only forces the switch node SW to discharge after the timing ends, reducing the feedback voltage VFB to the reference voltage VREF, causing the trigger loop to generate the trigger signal SET, and does not pay attention to the changes in the feedback voltage VFB with changes in the load. Therefore, the traditional timed forced discharge technology will cause the feedback voltage VFB to have a large undershoot, resulting in the problem of double pulses.

[0050] In order to solve the double pulse problem, the present application needs to ensure that under different load conditions, that is, when the load changes, the time required for the trigger loop to generate the trigger signal SET is equal to the preset time length t OOA , that is, the trigger loop automatically generates a period of preset duration t OOA The preset time length t in this application OOA It can be set according to the needs of the user, but the preset time length needs to be considered when setting the preset time length. OOA The upper limit cannot reach the frequency range that the human ear can hear, such as 2HZ~20KHZ, and the preset duration t OOA The lower limit depends on the power consumption requirement of the Buck circuit. In actual project applications, the preset time t OOA It is pre-set according to design needs, and the preset duration t OOA The value of can be tens of microseconds, for example, the preset time length t OOA 30us or preset time t OOA It is 40us.

[0051] The input end of the controlled current source CS in the present application is electrically connected to the switch node SW, the output end of the controlled current source CS is grounded, and the control end of the controlled current source CS is electrically connected to the output end of the digital processing circuit. This electrical connection structure enables the controlled current source CS to provide a discharge path between the switch node SW and the ground to discharge the switch node SW. The control end of the controlled current source CS is electrically connected to the output end of the digital processing circuit, and the output current I of the controlled current source CS is controlled by the digital processing circuit. DIS In one example, the controlled current source CS can be configured to output a current I of the controlled current source CS by adjusting the gear of the controlled current source CS. DISThat is, in the embodiment of the present application, in the OOA working mode, a controllable discharge current is introduced at the switch node SW, and the size of the discharge current can be adjusted by adjusting the gear of the controlled current source CS.

[0052] The logic control circuit monitors the connected inductor current IL, compares the duration of the inductor current IL being zero with a preset duration, obtains a drive logic signal OOA_D, and uses the drive logic signal OOA_D as the input of the digital processing circuit.

[0053] The digital processing circuit adjusts the gear position i of the controlled current source CS according to the received driving logic signal OOA_D and is triggered by the trigger signal SET to control the output current I of the controlled current source CS. DIS By controlling the size of the discharge current introduced by the switch node SW, the falling speed of the feedback voltage VFB is controlled, and the time required for the feedback voltage VFB to drop to the reference voltage VREF is controlled, so that the trigger loop generates the next trigger signal SET with a preset time interval, that is, a trigger signal with a period of the preset time length. The high tube HS is then forced to be turned on through the trigger signal SET to adjust the switching frequency of the Buck circuit.

[0054] In the embodiment of the present application, the output current I of the controlled current source CS is controlled by the logic control circuit and the digital processing circuit. DIS The size of the switch node SW allows the discharge current introduced by the switch node SW to be adaptively adjusted according to the load conditions. By adjusting the discharge current of the switch node SW, the loop is forced to automatically generate a trigger signal with a time interval of a preset duration, thereby achieving a relatively constant discharge cycle. Under different load conditions, that is, when the load changes, the time required for the trigger loop to generate the trigger signal SET is equal to the preset duration t OOA , which can reduce the double pulse problem caused by a large undershoot of the feedback voltage VFB when the load changes, allowing the Buck circuit to smoothly switch to the OOA operating mode when the load switches from heavy load to light load, achieving control of the switching frequency and reducing the power consumption problem caused by the large undershoot of the feedback voltage VFB. In addition, the OOA mode in this application is not limited by the loop control method and has universal applicability.

[0055] In a possible embodiment, the logic control circuit 100 is specifically configured to: when the inductor current IL is zero, start timing the duration during which the inductor current IL is zero to obtain the timing duration.

[0056] When the timing duration is greater than the preset duration, a driving logic signal of the first level is obtained.

[0057] When the timing duration is less than or equal to the preset duration, a driving logic signal of the second level is obtained.

[0058] When a trigger signal is received, the driving logic signal of the first level is switched to a driving logic signal of the second level.

[0059] The period of the trigger loop generating the trigger signal SET is the preset duration t OOA For one working cycle of the Buck circuit, the duration of the inductor current IL not being zero is only a few hundredths of the duration of the inductor current IL being zero. Therefore, in practical applications, the duration of the inductor current IL being zero is usually calculated by comparing the duration of the inductor current IL being zero with the preset duration t OOA The comparison is performed to obtain a driving logic signal, and then the digital processing circuit adjusts the output current of the controlled current source CS through the driving logic signal and the trigger signal to generate a trigger signal with a period of a preset time length.

[0060] Specifically, the logic control circuit receives the inductor current IL, and when the inductor current IL is zero, triggers the zero-crossing detection (ZCD), starts timing, calculates the duration of the inductor current IL being zero, obtains the timing duration, and compares the timing duration with the preset duration t OOA Compare, when the timing time is longer than the preset time t OOA , a first level driving logic signal OOA_D is obtained, wherein the first level is a high level, that is, when the timing duration is greater than the preset duration t OOA When the timing duration is less than or equal to the preset duration t OOA , a second level driving logic signal OOA_D is obtained, wherein the second level is a low level, that is, when the timing duration is less than or equal to the preset duration t OOA When , the driving logic signal OOA_D is low.

[0061] The trigger signal SET is a narrow pulse signal. Upon receiving the trigger signal SET, the first-level drive logic signal OOA_D is switched to the second-level drive logic signal OOA_D. Specifically, when the narrow pulse signal is active, the drive logic signal OOA_D is switched from the first level to the second level. The trigger signal SET can be considered a reset signal; when the narrow pulse signal is active, the drive logic signal OOA_D is reset to a low level.

[0062] In a possible embodiment, the digital processing circuit 200 is specifically configured to: when the driving logic signal OOA_D is at the first level and a trigger signal SET is received, control the current level i of the controlled current source CS to increase, so as to increase the output current of the controlled current source CS.

[0063] When the driving logic signal OOA_D is at the second level and the trigger signal SET is received, the current level i of the controlled current source CS is controlled to decrease gradually, so as to reduce the output current of the controlled current source CS.

[0064] In one example, during normal operation of the Buck circuit, if the drive logic signal OOA_D is at a high level, upon the arrival of the next trigger signal SET, i.e., upon receiving the trigger signal SET, the current level i of the controlled current source CS is controlled to increase by 1, thereby increasing the output current of the controlled current source CS. If the drive logic signal OOA_D is at a low level, upon the arrival of the next trigger signal SET, i.e., upon receiving the trigger signal SET, the current level i of the controlled current source CS is controlled to decrease by 1, thereby decreasing the output current of the controlled current source CS.

[0065] In one possible embodiment, the output current I of the controlled current source CS is DIS It is positively correlated with the current level i of the controlled current source CS.

[0066] The controlled current source CS can be configured to output a current I of the controlled current source CS by adjusting the gear i of the controlled current source CS. DIS The size of the controlled current source CS is adjusted, and the output current I DIS It is configured to increase as the current level i of the controlled current source CS increases, and to decrease as the current level i of the controlled current source CS decreases. The initial value of the level can be set to 0.

[0067] The working process of the OOA mode control circuit in the embodiment of the present application is as follows: the logic control circuit receives the inductor current IL, monitors the inductor current IL, triggers the zero-crossing detection (ZCD) when the inductor current IL is zero, starts timing, calculates the duration of the inductor current IL being zero, obtains the timing duration, and compares the timing duration with the preset duration t OOA Compare, when the timing time is longer than the preset time t OOA When the driving logic signal OOA_D is high, and the digital processing circuit receives the driving logic signal OOA_D as high, after the next trigger signal SET arrives, that is, when the trigger signal SET is received, the current gear i of the controlled current source CS is controlled to increase, so that the output current of the controlled current source CS increases; when the timing time is less than or equal to the preset time t OOA When the driving logic signal OOA_D is low, and the digital processing circuit receives the driving logic signal OOA_D as low, after the next trigger signal SET arrives, that is, when the trigger signal SET is received, the current gear i of the controlled current source CS is controlled to decrease, so that the output current of the controlled current source CS decreases; when the logic control circuit receives the trigger signal SET, the driving logic signal OOA_D is switched from high to low for reset.

[0068] In this application, the output current I DIS The size of the discharge current introduced by the switch node SW can be adaptively adjusted according to the load conditions, generating a trigger signal with a preset time interval. The core idea of ​​achieving a relatively constant discharge cycle is to calculate the duration of the inductor current IL being zero and compare the timing duration with the preset time length t OOA Compare and realize the detection of the feedback voltage VFB falling speed. When the timing time is longer than the preset time t OOA When the feedback voltage VFB is considered to decrease too slowly, the current gear i of the controlled current source is controlled to increase, so that the output current of the controlled current source CS increases; when the timing duration is less than or equal to the preset duration t OOA When the feedback voltage VFB decreases too quickly, the current level i of the controlled current source CS is controlled to decrease, thereby reducing the output current of the controlled current source CS. It is understood that in actual practice, adjusting the current level i of the controlled current source CS, controlling the magnitude of the output current of the controlled current source CS, and generating a trigger signal with a preset time interval cannot be achieved through a single adjustment. Multiple adjustments are often required over multiple operating cycles, and this application does not specifically limit the number of adjustments.

[0069] In the embodiment of the present application, after the inductor current IL is 0, the controlled current source CS generates a discharge current to discharge the switch node SW, so that the feedback voltage VFB decreases. After the preset time t OOA When the voltage drops to the reference voltage VREF, the trigger loop generates the next trigger signal SET with a preset time interval. This trigger signal SET then forces the high-side transistor HS to turn on, adjusting the switching frequency of the Buck circuit. When the load is light, a dynamically adjustable bleeder current is introduced to adaptively match the load, achieving precise control of the discharge cycle.

[0070] In a possible embodiment, the input terminal of the controlled current source CS is electrically connected to the output node OUT.

[0071] In the above embodiment, the input end of the controlled current source CS is electrically connected to the switch node SW to realize the discharge of the switch node SW. In another embodiment, the input end of the controlled current source CS can also be electrically connected to the output node OUT to realize the discharge of the output node OUT. The discharge of the output node OUT and the discharge of the switch node SW have the same effect, and both can cause the feedback voltage VFB to drop. The method by which the logic control circuit and the digital processing circuit control the controlled current source CS to discharge the output node OUT is the same as the method for discharging the switch node SW in the above embodiment, and will not be repeated here. By controlling the controlled current source CS to discharge the output node OUT, the feedback voltage VFB is caused to drop, and the feedback voltage VFB is reduced after a preset time t OOA When the voltage drops to the reference voltage VREF, the trigger loop generates the next trigger signal SET with a preset time interval, and then the high-side tube HS is forced to be turned on through the trigger signal SET to adjust the switching frequency of the Buck circuit.

[0072] See also Figure 4 , Figure 4 A signal flow chart of an OOA mode control circuit provided in an embodiment of the present application is shown as follows: Figure 4 As shown, when the load is lighter (or smaller), the feedback voltage VFB decreases more slowly. The time for the feedback voltage VFB to decrease is t f , then when the feedback voltage VFB drops slower, the corresponding t f The larger it is, the larger it will be if t f Greater than the preset time t OOA When , the current level i of the controlled current source CS increases by 1, such as Figure 4 As shown in , assuming that the initial i=i n , t f Greater than the preset time t OOA When the current level i of the controlled current source CS increases by 1, then in the next working cycle, i=i n +1. Comparison is performed cycle by cycle until t f Less than the preset time t OOA At this time, the current level i of the controlled current source CS is recorded as i0. In the next working cycle, the current level i of the controlled current source CS will decrease by 1 and become i0-1. If the comparison is continued in each working cycle, t f Greater than the preset time t OOA .

[0073] Please continue to see Figure 4 In the steady state, reducing the current level i of the controlled current source CS by 1 will make the next working cycle t f Greater than the preset time t OOA, when the current level i of the controlled current source CS is increased by 1, the t f Less than the preset time t OOA Therefore, in the steady state, the current level i of the controlled current source CS switches back and forth between i0 and i0-1. Figure 4 , Figure 4 The dashed line in the feedback voltage VFB curve shows the corresponding change in feedback voltage VFB as the current level i of the controlled current source CS switches back and forth between i0 and i0-1 during a stable state. As the load changes, the current level i of the controlled current source CS is incremented or decremented based on the current level until a stable state is restored.

[0074] Figure 4 The signal flow in the control current source CS is controlled by the output current I DIS The size of the feedback voltage VFB can be adjusted adaptively according to the change of the load, accurately triggering the loop to periodically generate the preset duration t OOA The trigger signal SET can reduce the double pulse phenomenon caused by a large undershoot of the feedback voltage VFB when the load changes.

[0075] An embodiment of the present application further provides an OOA mode control method, which is applied to the above-mentioned OOA mode control circuit, and includes:

[0076] S1, comparing the duration when the inductor current is zero with a preset duration to obtain a driving logic signal, wherein the preset duration is the time interval between two adjacent trigger signals.

[0077] S2, controlling the magnitude of the output current of the controlled current source according to the driving logic signal and the trigger signal, so as to generate a trigger signal with a period of a preset duration.

[0078] In a possible embodiment, the above S1 includes:

[0079] S11, when the inductor current is zero, start timing the duration of the inductor current being zero to obtain the timing duration.

[0080] S12, when the timing duration is greater than the preset duration, obtaining a driving logic signal of a first level.

[0081] S13, when the timing duration is less than or equal to the preset duration, obtaining a driving logic signal of a second level.

[0082] S14 , when a trigger signal is received, switching the driving logic signal of the first level to a driving logic signal of the second level.

[0083] In a possible embodiment, the above S2 includes:

[0084] S21 , when the driving logic signal is at the first level and a trigger signal is received, controlling the current level of the controlled current source to increase gradually, so as to increase the output current of the controlled current source.

[0085] S22 , when the driving logic signal is at the second level and a trigger signal is received, controlling the current level of the controlled current source to decrease gradually, so as to reduce the output current of the controlled current source.

[0086] An embodiment of the present application further provides a chip, which includes: the DCDC converter OOA mode control circuit as described above.

[0087] The chip in the embodiment of the present application may be a buck chip, which includes a DCDC converter OOA mode control circuit.

[0088] An embodiment of the present application further provides an electronic device, which includes: the chip as described above.

[0089] In this application, electronic devices may include but are not limited to: adapters, chargers, tablets, smart home devices, vehicles, and wearable devices.

[0090] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A DCDC converter OOA mode control circuit, characterized in that: The DCDC converter OOA mode control circuit includes: a logic control circuit, a digital processing circuit and a controlled current source; The first input terminal of the logic control circuit is connected to the inductor current, the second input terminal of the logic control circuit is connected to the trigger signal, the output terminal of the logic control circuit is electrically connected to the second input terminal of the digital processing circuit, the first input terminal of the digital processing circuit is connected to the trigger signal, the output terminal of the digital processing circuit is electrically connected to the control terminal of the controlled current source, the input terminal of the controlled current source is electrically connected to the switch node, and the output terminal of the controlled current source is grounded; The logic control circuit is configured to compare a duration during which the inductor current is zero with a preset duration to obtain a drive logic signal, and transmit the drive logic signal to the digital processing circuit, wherein the preset duration is a time interval between two adjacent trigger signals; The digital processing circuit is used to control the magnitude of the output current of the controlled current source according to the driving logic signal and the trigger signal, so as to generate the trigger signal with a period of the preset time length.

2. The DCDC converter OOA mode control circuit according to claim 1, wherein: The logic control circuit is specifically configured to: when the inductor current is zero, start timing the duration of the inductor current being zero to obtain the timing duration; When the timing duration is greater than the preset duration, obtaining the driving logic signal of the first level; When the timing duration is less than or equal to the preset duration, obtaining the driving logic signal of the second level; When the trigger signal is received, the driving logic signal at the first level is switched to the driving logic signal at the second level.

3. The DCDC converter OOA mode control circuit according to claim 1, wherein: The digital processing circuit is specifically configured to: when the driving logic signal is at the first level and the trigger signal is received, control the current gear of the controlled current source to increase gradually, so as to increase the output current of the controlled current source; When the driving logic signal is at the second level and the trigger signal is received, the current level of the controlled current source is controlled to decrease gradually, so as to reduce the output current of the controlled current source.

4. The DCDC converter OOA mode control circuit according to claim 3, characterized in that: The output current of the controlled current source is positively correlated with the current range of the controlled current source.

5. The DCDC converter OOA mode control circuit according to claim 1, wherein: The input terminal of the controlled current source is electrically connected to the output node.

6. A DCDC converter OOA mode control method, characterized in that: The method is applied to the DCDC converter OOA mode control circuit according to any one of claims 1 to 5, and the method includes: Comparing the duration when the inductor current is zero with a preset duration to obtain a driving logic signal, wherein the preset duration is the time interval between two adjacent trigger signals; According to the driving logic signal and the trigger signal, the magnitude of the output current of the controlled current source is controlled to generate the trigger signal with a period of the preset time length.

7. The DCDC converter OOA mode control method according to claim 6, wherein: The duration when the inductor current is zero is compared with the preset duration to obtain a driving logic signal, including: When the inductor current is zero, start timing the duration of the inductor current being zero to obtain the timing duration; When the timing duration is greater than the preset duration, obtaining the driving logic signal of the first level; When the timing duration is less than or equal to the preset duration, obtaining the driving logic signal of the second level; When the trigger signal is received, the driving logic signal at the first level is switched to the driving logic signal at the second level.

8. The DCDC converter OOA mode control method according to claim 6, wherein: The step of controlling the magnitude of the output current of the controlled current source according to the driving logic signal and the trigger signal to generate the trigger signal having a period of the preset time length includes: When the driving logic signal is at the first level and the trigger signal is received, controlling the current gear of the controlled current source to increase gradually, so as to increase the output current of the controlled current source; When the driving logic signal is at the second level and the trigger signal is received, the current level of the controlled current source is controlled to decrease gradually, so as to reduce the output current of the controlled current source.

9. A chip, characterized in that: include: The DCDC converter OOA mode control circuit according to any one of claims 1 to 5.

10. An electronic device, characterized in that: include: The chip as claimed in claim 9.

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