Comparator and comparison circuit
By introducing a limiting module into the comparator to limit the voltage swing of the input stage module, the problem of limited comparator speed in the prior art is solved, and faster response speed and lower delay are achieved.
Patent Information
- Application Number
- CN202410245339.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-04
- Publication Date
- 2025-09-05
AI Technical Summary
The response speed of existing comparators is limited by factors such as power consumption, node parasitic capacitance, and bias current, which leads to increased delay.
A limiting module is set between the input stage module and the push-pull amplification module to limit the voltage swing output by the input stage module, so as to speed up the response speed of the comparator.
By limiting the setting of the module, the delay of the comparator is reduced and the response speed is improved while maintaining sufficient gain and driving capability.
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Figure CN120601868A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a comparator and a comparison circuit. Background Art
[0002] The comparator is a commonly used module in integrated circuit design, which is used to compare the sizes of two voltage or current signals and output the corresponding comparison results.
[0003] After long-term research, the applicant in this case found that a major indicator of a comparator is speed, which is limited by various factors, such as power consumption, node parasitic capacitance, bias current, etc., thereby increasing the delay of the comparator and limiting the speed of the comparator. Summary of the Invention
[0004] The comparator and comparison circuit provided in this application can increase the response speed of the comparator.
[0005] In a first aspect, the present application provides a comparator, which includes: an input stage module, wherein the non-inverting input terminal of the input stage module is used to receive a first voltage to be compared, the inverting input terminal of the input stage module is used to receive a second voltage to be compared, and the input stage module is used to output a first target voltage based on the first voltage to be compared and the second voltage to be compared; a push-pull amplification module, wherein the input terminal of the push-pull amplification module is coupled to the coupling point of the input stage module, and is used to output a second target voltage based on the first target voltage; wherein the second target voltage is used to characterize the magnitude of the first voltage to be compared and the second voltage to be compared.
[0006] In which, the input stage module includes: a first transistor, the control end of the first transistor is used to receive a first voltage to be compared; a second transistor, the control end of the second transistor is used to receive a second voltage to be compared; a current mirror, the first end of the current mirror is coupled to the first end of the first transistor, the second end of the current mirror is coupled to the working voltage end, and the third end of the current mirror is coupled to the first end of the second transistor; the coupling point between the third end of the current mirror and the first end of the second transistor serves as the output end of the input stage module; a third transistor, the first end of the third transistor is coupled to the first ends of the first transistor and the second transistor, and the second end of the third transistor is grounded.
[0007] The current mirror includes: a fourth transistor, a first end of the fourth transistor being coupled to the first end of the first transistor as the first end of the current mirror, and a second end of the fourth transistor being coupled to the operating voltage end; a first end of the fourth transistor being coupled to the control end of the fourth transistor; and a fifth transistor, a first end of the fifth transistor being coupled to the first end of the second transistor as the third end of the current mirror, and a second end of the fifth transistor being coupled to the operating voltage end, and a control end of the fifth transistor being coupled to the control end of the fourth transistor.
[0008] The comparator further includes a limiting module coupled to the output end of the input stage module and configured to limit the voltage swing of the first target voltage; and the input end of the push-pull amplification module is further coupled to the limiting module.
[0009] The limiting module includes: a sixth transistor, a first end of the sixth transistor coupled to the operating voltage end, a second end of the sixth transistor coupled to the output end of the input stage module and the control end of the sixth transistor; a seventh transistor, a first end of the seventh transistor coupled to the second end of the sixth transistor and the control end of the seventh transistor, and a second end of the seventh transistor grounded.
[0010] Among them, the push-pull amplification module includes: a first-stage amplification unit, the first end of the first-stage amplification unit is coupled to the working voltage end, the second end of the first-stage amplification unit is grounded, and the control end of the first-stage amplification unit serves as the input end of the push-pull amplification module to couple the limiting module and the input stage module; a second-stage amplification unit, the first end of the second-stage amplification unit is coupled to the working voltage end, the second end of the second-stage amplification unit is grounded, the control end of the second-stage amplification unit is coupled to the output end of the first-stage amplification unit, and the output end of the second-stage amplification unit serves as the output end of the push-pull amplification module to output the second target voltage.
[0011] In which, the first-stage amplification unit includes: an eighth transistor, the first end of the eighth transistor serving as the first end of the first-stage amplification unit coupled to the operating voltage end; a ninth transistor, the first end of the ninth transistor coupled to the second end of the eighth transistor, the second end of the ninth transistor serving as the second end of the first-stage amplification unit being grounded, the control end of the ninth transistor coupled to the control end of the eighth transistor and the coupling point between the limiting module and the input stage module; and the coupling point between the first end of the ninth transistor and the second end of the eighth transistor serving as the output end of the first-stage amplification unit.
[0012] In which, the second-stage amplifying unit includes: a tenth transistor, the first end of the tenth transistor is coupled to the working voltage end as the first end of the second-stage amplifying unit; an eleventh transistor, the first end of the eleventh transistor is coupled to the second end of the tenth transistor, the second end of the eleventh transistor is grounded as the second end of the second-stage amplifying unit, and the control end of the eleventh transistor is coupled to the control end of the tenth transistor and the output end of the first-stage amplifying unit; the coupling point between the first end of the eleventh transistor and the second end of the tenth transistor serves as the output end of the second-stage amplifying unit.
[0013] When no external current flows through the coupling point, the first target voltage output by the coupling point is equal to the threshold voltage of the first-stage amplifying unit.
[0014] The transistors in the limiting module and the transistors in the first-stage amplifying unit are of the same type and have the same size ratio.
[0015] In a second aspect, the present application provides a comparison circuit, which includes the comparator provided in the first aspect.
[0016] The beneficial effect of the present application is that, unlike the prior art, the comparator and comparison circuit provided by the present application utilize a push-pull amplifier module to further amplify and shape the first target voltage, so that the entire comparator has sufficient gain, while ensuring that the output has sufficient driving capability to speed up the response speed of the comparator and reduce the delay of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:
[0018] Figure 1 is a schematic structural diagram of an embodiment of a comparator provided by the present application;
[0019] Figure 2 is a structural diagram of another embodiment of a comparator provided by the present application;
[0020] Figure 3 is a structural diagram of another embodiment of a comparator provided by the present application;
[0021] Figure 4 yes Figure 1 Schematic diagram of the working simulation of the comparator;
[0022] Figure 5 yes Figure 2 or Figure 3 Schematic diagram of the working simulation of the comparator;
[0023] Figure 6 1 is a schematic structural diagram of an embodiment of a comparison circuit provided in this application. DETAILED DESCRIPTION
[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0025] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0026] See Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a comparator according to an embodiment of the present invention. The comparator 100 includes an input stage module 10 and a push-pull amplifier module 20 .
[0027] The positive input terminal of the input stage module 10 is used to receive the first voltage to be compared, the negative input terminal of the input stage module 10 is used to receive the second voltage to be compared, and the input stage module 10 is used to output the first target voltage V1 according to the first voltage to be compared and the second voltage to be compared. Figure 1 As shown, the first voltage to be compared can be represented by VINP, and the second voltage to be compared can be represented by VINN.
[0028] The input terminal of the push-pull amplifier module 20 is coupled to the output terminal of the limiting module 30 of the input stage module 10, and is used to output a second target voltage VOUT according to the first target voltage V1; wherein the second target voltage VOUT is used to represent the magnitude of the first voltage to be compared and the second voltage to be compared.
[0029] Specifically, the input stage module 10 includes: a first transistor MN1 , a second transistor MN2 , a current mirror, and a third transistor MN5 .
[0030] The control terminal of the first transistor MN1 is configured to receive a first voltage to be compared.
[0031] The control terminal of the second transistor MN2 is configured to receive a second voltage to be compared.
[0032] The first end of the current mirror is coupled to the first end of the first transistor MN1, the second end of the current mirror is coupled to the operating voltage end, and the third end of the current mirror is coupled to the first end of the second transistor MN2; the coupling point between the third end of the current mirror and the first end of the second transistor MN2 serves as the output end of the input stage module 10.
[0033] A first terminal of the third transistor MN5 is coupled to the first terminals of the first transistor MN1 and the second transistor MN2 , and a second terminal of the third transistor MN5 is grounded.
[0034] The current mirror includes: a fourth transistor MP1 and a fifth transistor MP2.
[0035] The first terminal of the fourth transistor MP1 is coupled to the first terminal of the first transistor MN1 as the first terminal of the current mirror. The second terminal of the fourth transistor MP1 is coupled to the working voltage terminal. The first terminal of the fourth transistor MP1 is coupled to the control terminal of the fourth transistor MP1.
[0036] A first terminal of the fifth transistor MP2 is coupled to the first terminal of the second transistor MN2 as the third terminal of the current mirror. A second terminal of the fifth transistor MP2 is coupled to the operating voltage terminal. A control terminal of the fifth transistor MP2 is coupled to the control terminal of the fourth transistor MP1.
[0037] The push-pull amplification module 20 includes a first-stage amplification unit and a second-stage amplification unit.
[0038] The first end of the first stage amplifying unit is coupled to the working voltage end, the second end of the first stage amplifying unit is grounded, and the control end of the first stage amplifying unit is coupled to the output end of the input stage module 10 as the input end of the push-pull amplifying module 20 .
[0039] The first end of the second-stage amplifier unit is coupled to the working voltage end, the second end of the second-stage amplifier unit is grounded, the control end of the second-stage amplifier unit is coupled to the output end of the first-stage amplifier unit, and the output end of the second-stage amplifier unit serves as the output end of the push-pull amplifier module 20 to output the second target voltage.
[0040] The first-stage amplifying unit includes an eighth transistor MP3 and a ninth transistor MN3.
[0041] The first terminal of the eighth transistor MP3 serves as the first terminal of the first-stage amplifying unit and is coupled to the working voltage terminal.
[0042] A first end of the ninth transistor MN3 is coupled to the second end of the eighth transistor MP3. The second end of the ninth transistor MN3 is grounded as the second end of the first-stage amplifying unit. A control end of the ninth transistor MN3 is coupled to the control end of the eighth transistor MP3 and a coupling point between the limiting module 30 and the input stage. A coupling point between the first end of the ninth transistor MN3 and the second end of the eighth transistor MP3 serves as the output end of the first-stage amplifying unit.
[0043] The second-stage amplifying unit includes a tenth transistor MP4 and an eleventh transistor MN4.
[0044] The first terminal of the tenth transistor MP4 serves as the first terminal of the second-stage amplifying unit and is coupled to the working voltage terminal.
[0045] The first terminal of the eleventh transistor MN4 is coupled to the second terminal of the tenth transistor MP4. The second terminal of the eleventh transistor MN4 is grounded as the second terminal of the second-stage amplification unit. The control terminal of the eleventh transistor MN4 is coupled to the control terminal of the tenth transistor MP4 and the output terminal of the first-stage amplification unit. The coupling point between the first terminal of the eleventh transistor MN4 and the second terminal of the tenth transistor MP4 serves as the output terminal of the second-stage amplification unit.
[0046] The comparator 100 described above is used to compare the magnitudes of two voltage signals and output corresponding comparison results. As Figure 1 shown, five MOS transistors MN1, MN2, MN5, MP1, and MP2 form the input-stage module 10, which determines the first target voltage V1 output at the output terminal of the input-stage module 10 according to the magnitudes of the input voltages VINP and VINN. MN3 and MP3 form the second stage, and MN4 and MP4 form the third stage. These two stages are single-stage amplifiers with a push-pull structure, whose function is to further amplify and shape the input signal (the first target voltage V1), so that the entire comparator 100 has sufficient gain and at the same time ensures that the output has sufficient driving ability.
[0047] The typical working process of the circuit is as follows:
[0048] The gates of MN1 and MN2 serve as the non-inverting input terminal and the inverting input terminal of the comparator 100 respectively. Assuming that the voltage VINP is higher than VINN, the gate-source voltage of MN1 increases, the current flowing through it increases, and through the mirroring of the current mirrors MP1 and MP2, the current flowing into the output terminal increases. At the same time, since the gate-source voltage of MN2 decreases, the current flowing through it decreases, and the current flowing out of the output terminal decreases. The above two points result in an increase in the net inflow current at the output terminal and an increase in the voltage V1 at the output terminal.
[0049] After the voltage V1 is higher than the threshold voltage of the single-stage push-pull amplifier formed by MN3 and MP3, the voltage V2 at its output terminal starts to decrease.
[0050] Similarly, after the voltage V2 is lower than the threshold voltage of the single-stage push-pull amplifier formed by MN4 and MP4, the second target voltage VOUT output by it starts to increase.
[0051] The structure of cascading the first-stage amplifier with the latter two push-pull amplifiers ensures that the entire comparator 100 has a large DC gain and a very small input error. Its output characteristics can be approximately regarded as: when VINP > VINN, the second target voltage VOUT output is at a high level; when VINP < VINN, the second target voltage VOUT output is at a low level.
[0052] The inventors of the present application have discovered through long-term research that a major indicator of the above-mentioned comparator 100 is speed, which is limited by various factors, such as power consumption and node parasitic capacitance. In particular, for the input stage, the operating current of its two branches is limited by the tail current source MN5. Under the condition of a certain bias current (the bias current is limited by the power consumption indicator), no matter how large the difference between VINP and VINN is, the net inflow or outflow current of V1 will not exceed the bias current of MN5, which limits the slew rate of V1, thereby increasing the delay of the comparator 100 and limiting the speed of the comparator 100.
[0053] Based on this, the present application proposes providing a limiting module between the input stage module 10 and the push-pull amplification module 20. The limiting module is used to limit the voltage swing of the first target voltage output by the input stage module 10. When the input voltage at the inverting input terminal or the non-inverting input terminal of the input stage module 10 changes, the limiting module limits the voltage swing of the first target voltage, thereby reducing the voltage swing. This can speed up the response of the comparator 100 and reduce the delay of the comparator 100. For details, please refer to any of the following embodiments.
[0054] See Figure 2 , Figure 2 FIG. 1 is a schematic diagram of another embodiment of a comparator provided by the present application. The comparator 100 circuit includes an input stage module 10 , a limiting module 30 , and a push-pull amplification module 20 .
[0055] The non-inverting input terminal of the input stage module 10 is used to receive the first voltage to be compared, and the inverting input terminal of the input stage module 10 is used to receive the second voltage to be compared. The input stage module 10 is used to output the first target voltage V1 according to the first voltage to be compared and the second voltage to be compared.
[0056] The limiting module 30 is coupled to the output terminal of the input stage module 10 and is used to limit the voltage swing of the first target voltage V1. That is, the limiting module 30 can limit the first target voltage V1, so the voltage output by the limiting module 30 after limiting can be represented by V1'.
[0057] The input terminal of the push-pull amplifier module 20 is coupled to the coupling point between the limiting module 30 and the input stage. The module is configured to output a second target voltage VOUT based on the first target voltage V1. The second target voltage is used to represent the magnitude of the first and second comparison voltages. The push-pull amplifier module 20 can quickly respond to the voltage V1' and output the second target voltage VOUT.
[0058] In this embodiment, a limiting module 30 is provided between the input stage module 10 and the push-pull amplification module 20. The limiting module 30 is used to limit the voltage swing of the first target voltage output by the input stage module 10. When the input voltage at the inverting input terminal or the non-inverting input terminal of the input stage module 10 changes, the voltage swing is reduced because the limiting module 30 limits the voltage swing of the first target voltage, which can speed up the response speed of the comparator 100 and reduce the delay of the comparator 100.
[0059] See Figure 3 , Figure 3 FIG. 1 is a schematic diagram of another embodiment of a comparator 100 provided in the present application. The comparator 100 circuit includes an input stage module 10 , a limiting module 30 , and a push-pull amplification module 20 .
[0060] The input stage module 10 includes: a first transistor MN1 , a second transistor MN2 , a current mirror and a third transistor MN5 .
[0061] The control terminal of the first transistor MN1 is used to receive a first voltage to be compared; the control terminal of the second transistor MN2 is used to receive a second voltage to be compared.
[0062] The first end of the current mirror is coupled to the first end of the first transistor MN1, the second end of the current mirror is coupled to the operating voltage end, and the third end of the current mirror is coupled to the first end of the second transistor MN2; the coupling point between the third end of the current mirror and the first end of the second transistor MN2 serves as the output end of the input stage module 10.
[0063] A first terminal of the third transistor MN5 is coupled to the first terminals of the first transistor MN1 and the second transistor MN2 , and a second terminal of the third transistor MN5 is grounded.
[0064] The current mirror includes: a fourth transistor MP1 and a fifth transistor MP2.
[0065] The first terminal of the fourth transistor MP1 is coupled to the first terminal of the first transistor MN1 as the first terminal of the current mirror. The second terminal of the fourth transistor MP1 is coupled to the working voltage terminal. The first terminal of the fourth transistor MP1 is coupled to the control terminal of the fourth transistor MP1.
[0066] A first terminal of the fifth transistor MP2 is coupled to the first terminal of the second transistor MN2 as the third terminal of the current mirror. A second terminal of the fifth transistor MP2 is coupled to the operating voltage terminal. A control terminal of the fifth transistor MP2 is coupled to the control terminal of the fourth transistor MP1.
[0067] The limiting module 30 includes a sixth transistor MP6 and a seventh transistor MN6.
[0068] A first terminal of the sixth transistor MP6 is coupled to the operating voltage terminal, and a second terminal of the sixth transistor MP6 is coupled to the output terminal of the input stage module 10 and the control terminal of the sixth transistor MP6 .
[0069] A first terminal of the seventh transistor MN6 is coupled to the second terminal of the sixth transistor MP6 and the control terminal of the seventh transistor MN6 , and a second terminal of the seventh transistor MN6 is grounded.
[0070] The push-pull amplification module 20 includes a first-stage amplification unit and a second-stage amplification unit.
[0071] The first end of the first stage amplifying unit is coupled to the working voltage end, the second end of the first stage amplifying unit is grounded, and the control end of the first stage amplifying unit serves as the input end of the push-pull amplifying module 20 and is coupled to the coupling point between the limiting module 30 and the input stage module 10.
[0072] The first end of the second-stage amplifier unit is coupled to the working voltage end, the second end of the second-stage amplifier unit is grounded, the control end of the second-stage amplifier unit is coupled to the output end of the first-stage amplifier unit, and the output end of the second-stage amplifier unit serves as the output end of the push-pull amplifier module 20 to output the second target voltage.
[0073] The first-stage amplifying unit includes an eighth transistor MP3 and a ninth transistor MN3.
[0074] The first terminal of the eighth transistor MP3 serves as the first terminal of the first-stage amplifying unit and is coupled to the working voltage terminal.
[0075] A first end of the ninth transistor MN3 is coupled to the second end of the eighth transistor MP3. The second end of the ninth transistor MN3 is grounded as the second end of the first-stage amplifying unit. A control end of the ninth transistor MN3 is coupled to the control end of the eighth transistor MP3 and a coupling point between the limiting module 30 and the input-stage module 10. A coupling point between the first end of the ninth transistor MN3 and the second end of the eighth transistor MP3 serves as the output end of the first-stage amplifying unit.
[0076] The second-stage amplifying unit includes a tenth transistor MP4 and an eleventh transistor MN4.
[0077] The first terminal of the tenth transistor MP4 serves as the first terminal of the second-stage amplifying unit and is coupled to the working voltage terminal.
[0078] The first end of the eleventh transistor MN4 is coupled to the second end of the tenth transistor MP4. The second end of the eleventh transistor MN4 serves as the second end of the second-stage amplifying unit and is grounded. The control end of the eleventh transistor MN4 is coupled to the control end of the tenth transistor MP4 and the output end of the first-stage amplifying unit. The coupling point between the first end of the eleventh transistor MN4 and the second end of the tenth transistor MP4 serves as the output end of the second-stage amplifying unit.
[0079] When no external current flows through the coupling point, the first target voltage output by the coupling point is equal to the threshold voltage of the first-stage amplifying unit.
[0080] The transistors in the limiting module 30 and the transistors in the first-stage amplifying unit are of the same type and have the same size ratio. Figure 3 MP6 and MP3 utilize the same device type, and MN6 and MN3 utilize the same device type. Furthermore, the size ratio of MP6 to MN6 is the same as the size ratio of MP3 to MN3. These two points are intended to ensure that when no external current flows into or out of the branch formed by MN6 and MP6 through the coupling point, the output voltage (first target voltage V1) at the coupling point is exactly equal to the threshold voltage of the single-stage push-pull amplifier formed by MN3 and MP3. This condition corresponds to the zero-input state of comparator 100, i.e., VINP = VINN. When VINP is not equal to VINN, the input stage of comparator 100 injects or extracts current from the coupling point (the direction of the current depends on the magnitude relationship between VINP and VINN, and the magnitude of the current depends on the difference between VINP and VINN and the design of the input stage). This current flows into or out of the branch formed by MN6 and MP6, causing the voltage V1 to deviate from the threshold voltage of the single-stage push-pull amplifier formed by MN3 and MP3. The amount of the deviation is determined by the size of MN6 and MP6 and the current flowing in or out.
[0081] Therefore, by properly setting the sizes of MN6 and MP6 and the input stage module 10 (which determines the current flowing into or out of the output terminal of the input stage module), the first target voltage V1 and the threshold voltages of MN3 and MP3 can deviate from appropriate values under different input voltages. When the input voltage changes, the voltage swing of the first target voltage V1 is reduced, thereby accelerating the response speed of the comparator 100.
[0082] Right now, Figure 3 The comparator 100 shown in Figure 1 Based on the comparator 100, two diode-connected MOS transistors (MN6 and MP6) are added to the output end of the input stage module 10 to limit the voltage swing of the first target voltage V1 output at the coupling point. This ensures that under various input conditions, the first target voltage V1 varies around the threshold voltage of the single-stage push-pull amplifier formed by MN3 and MP3. This reduces the voltage swing of the first target voltage V1 when the input changes, thereby reducing the delay of the comparator 100. In other words, by limiting the voltage swing of the intermediate node, the speed of the comparator 100 can be effectively improved without significantly increasing power consumption or circuit scale.
[0083] In one application scenario, combined with Figure 4 and Figure 5 right Figure 1 and Figure 2 ,or Figure 1 and Figure 3 The comparator 100 performs comparison.
[0084] For example, in a 28nm NAND FLASH process, the hspice tool is used to simulate and compare a 0.2V input signal (the difference between VINP and VINN is 0.2V) at a power supply voltage of 3.3V and an ambient temperature of 25°C.
[0085] Figure 1 The simulation waveform of the comparator 100 is as follows Figure 4 As shown in the figure, under the input signal of 0.2V, the voltage of V1 is close to the power supply or ground voltage, resulting in a large swing of V1. The positive and negative phase delays are 1.956ns and 2.867ns respectively.
[0086] Figure 2 or Figure 3 The simulation waveform of the comparator 100 is as follows Figure 5 As shown in the figure, under the same 0.2V input signal, the voltage swing of V1 is limited to about 0.2V, and the positive and negative phase delays are reduced to 0.739ns and 0.862ns respectively, which is significantly lower than Figure 1 comparator 100.
[0087] illustrate Figure 2 or Figure 3 The comparator 100 can effectively improve the speed of the comparator 100 by limiting the voltage swing of the intermediate node without significantly increasing power consumption or circuit scale.
[0088] In some embodiments, the aforementioned MN1, MN2, MN3, MN4, MN5, and MN6 are N-type MOS transistors, and MP1, MP2, MP3, MP4, and MP6 are P-type MOS transistors.
[0089] See Figure 6 , Figure 6 FIG1 is a schematic diagram of a structure of an embodiment of a comparison circuit provided by the present application. The comparison circuit includes a comparator 100. The comparator 100 is the comparator 100 of any of the above embodiments.
[0090] In summary, the comparator 100 and the comparison circuit provided in the present application utilize the limiting module 30 to limit the voltage swing of the first target voltage output by the input stage module 10. When the input voltage of the inverting input terminal or the non-inverting input terminal of the input stage module 10 changes, the voltage swing is reduced because the limiting module 30 limits the voltage swing of the first target voltage, which can speed up the response speed of the comparator 100 and reduce the delay of the comparator 100.
[0091] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.
[0092] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0093] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A comparator, characterized in that: include: an input stage module, wherein a non-inverting input terminal of the input stage module is used to receive a first voltage to be compared, an inverting input terminal of the input stage module is used to receive a second voltage to be compared, and the input stage module is used to output a first target voltage according to the first voltage to be compared and the second voltage to be compared; A push-pull amplifier module, wherein the input end of the push-pull amplifier module is coupled to the coupling point of the input stage module, and is used to output a second target voltage according to the first target voltage; wherein the second target voltage is used to represent the magnitude of the first voltage to be compared and the second voltage to be compared.
2. The comparator according to claim 1, wherein: The input stage module includes: a first transistor (MN1), wherein a control terminal of the first transistor is used for receiving the first voltage to be compared; a second transistor (MN2), wherein a control terminal of the second transistor is used for receiving the second voltage to be compared; a current mirror, wherein a first terminal of the current mirror is coupled to the first terminal of the first transistor, a second terminal of the current mirror is coupled to an operating voltage terminal, and a third terminal of the current mirror is coupled to the first terminal of the second transistor; a coupling point between the third terminal of the current mirror and the first terminal of the second transistor serves as an output terminal of the input stage module; A third transistor (MN5), wherein a first terminal of the third transistor is coupled to the first terminals of the first transistor and the second transistor, and a second terminal of the third transistor is grounded.
3. The comparator according to claim 2, wherein: The current mirror comprises: a fourth transistor (MP1), wherein a first terminal of the fourth transistor is coupled to the first terminal of the first transistor as a first terminal of the current mirror, a second terminal of the fourth transistor is coupled to the operating voltage terminal, and a first terminal of the fourth transistor is coupled to the control terminal of the fourth transistor; a fifth transistor (MP2), wherein a first end of the fifth transistor is coupled to the first end of the second transistor as the third end of the current mirror, a second end of the fifth transistor is coupled to the operating voltage end, and a control end of the fifth transistor is coupled to the control end of the fourth transistor.
4. The comparator according to claim 1, wherein: The comparator further includes: A limiting module is coupled to the output end of the input stage module and is used to limit the voltage swing of the first target voltage; the input end of the push-pull amplification module is also coupled to the limiting module.
5. The comparator according to claim 4, wherein: The restriction module includes: a sixth transistor (MP6), wherein a first terminal of the sixth transistor is coupled to the operating voltage terminal, and a second terminal of the sixth transistor is coupled to the output terminal of the input stage module and the control terminal of the sixth transistor; A seventh transistor (MN6), wherein a first terminal of the seventh transistor is coupled to the second terminal of the sixth transistor and the control terminal of the seventh transistor, and a second terminal of the seventh transistor is grounded.
6. The comparator according to claim 4, wherein: The push-pull amplification module includes: a first-stage amplifying unit, wherein a first terminal of the first-stage amplifying unit is coupled to the working voltage terminal, a second terminal of the first-stage amplifying unit is grounded, and a control terminal of the first-stage amplifying unit serves as an input terminal of the push-pull amplifying module and is coupled to a coupling point between the limiting module and the input stage module; A second-stage amplifying unit, wherein the first end of the second-stage amplifying unit is coupled to the working voltage end, the second end of the second-stage amplifying unit is grounded, the control end of the second-stage amplifying unit is coupled to the output end of the first-stage amplifying unit, and the output end of the second-stage amplifying unit serves as the output end of the push-pull amplifying module to output the second target voltage.
7. The comparator according to claim 6, wherein: The first-stage amplification unit includes: an eighth transistor (MP3), a first terminal of the eighth transistor serving as a first terminal of the first-stage amplifying unit and coupled to the operating voltage terminal; a ninth transistor (MN3), wherein a first end of the ninth transistor is coupled to the second end of the eighth transistor, the second end of the ninth transistor is grounded as the second end of the first-stage amplifying unit, the control end of the ninth transistor is coupled to the control end of the eighth transistor and the coupling point between the limiting module and the input-stage module; and a coupling point between the first end of the ninth transistor and the second end of the eighth transistor serves as the output end of the first-stage amplifying unit.
8. The comparator according to claim 6, wherein: The second-stage amplification unit includes: a tenth transistor (MP4), a first terminal of the tenth transistor serving as a first terminal of the second-stage amplifying unit and coupled to the working voltage terminal; an eleventh transistor (MN4), wherein the first end of the eleventh transistor is coupled to the second end of the tenth transistor, the second end of the eleventh transistor is grounded as the second end of the second-stage amplifying unit, the control end of the eleventh transistor is coupled to the control end of the tenth transistor and the output end of the first-stage amplifying unit; and a coupling point between the first end of the eleventh transistor and the second end of the tenth transistor serves as the output end of the second-stage amplifying unit.
9. The comparator according to claim 6, wherein: When no external current flows through the coupling point, the first target voltage output by the coupling point is equal to the threshold voltage of the first-stage amplifying unit.
10. A comparison circuit, characterized in that: The comparison circuit comprises the comparator according to any one of claims 1 to 9.