Method for adjusting system clock of integrated circuit and integrated circuit

Abstract

The invention relates to a method for adjusting a system clock of an integrated circuit, said integrated circuit comprising an oscillator module, a counter module, a signal input, and a communication interface, said oscillator module being designed to specify the system clock of the integrated circuit. The method comprises the following steps: a) receiving a reference signal at a signal input for a predefined duration; b) incrementing the counter module by one for each system clock of the integrated circuit for the duration of application of the reference signal; c) after the end of the duration, determining a counter value of the counter module; d) receiving a counter setpoint at the communication interface, the counter setpoint corresponding to the number of system clocks over the duration at the set frequency; e) comparing the counter value of the counter module with the counter setpoint and correcting the frequency of the oscillator module based on the deviation of the counter value from the counter setpoint. The invention also relates to an integrated circuit.

Description

Technical Field

[0001] The present invention relates to a method for adjusting a system clock of an integrated circuit. The present invention also relates to an integrated circuit. Background Art

[0002] Embedded oscillators in application-specific integrated circuits (ASICs) are generally known and are used in a large number of applications in a wide variety of fields. In addition, it is generally known that today's ASICs mostly contain functional modules (counter modules) for counting specific events.

[0003] To compensate for process variations caused by production, a method for adjusting the desired target frequency (oscillator trimming) is usually performed after the manufacture of the ASIC. To date, this frequency adjustment has mostly been performed by performing partially individualized frequency measurements using external test equipment, which is time-consuming and therefore cost-intensive.

[0004] Typically, to frequency-calibrate an embedded oscillator, the clock signal is connected via an output pin of an ASIC to external test equipment, which performs frequency measurements. Based on the measurement results, the embedded oscillator's configuration is then modified so that the measured frequency deviates as little as possible from the desired target frequency. This is an iterative method, requiring multiple frequency measurements and configuration changes. Summary of the Invention

[0005] The method according to the invention can be performed in a short time and at low cost. In particular, a very simple test device is used, which is connected to the integrated circuit. Furthermore, no complex calculations are required, so the method is resource-efficient.

[0006] This method is used to set the system clock of an integrated circuit. The integrated circuit includes an oscillator module configured to predetermine the system clock of the integrated circuit, a counter module, a signal input, and a communication interface. The oscillator module is capable of adjusting a frequency, wherein the method is used to set the frequency to a desired value. During operation of the integrated circuit, the frequency of the oscillator module then determines the system clock. The counter module is preferably an event counter. In the simplest case, the counter module can count the number of system clocks within a specified time period.

[0007] The method includes the following steps: first, step a) of receiving a reference signal at a signal input for a predefined duration. Then, step b) of incrementing a counter module by one for each system clock of the integrated circuit during the duration of the reference signal application. Thus, the counter module counts the number of system clocks as long as the reference signal is applied. Knowing the duration of the reference signal application, the actual system clock can be inferred based on the counter module.

[0008] Step c) is performed to determine the counter value of the counter module after the duration (t) has expired. Furthermore, step d) is performed to receive a counter setpoint at the communication interface. The counter setpoint is generated, in particular, by an external device, wherein the counter setpoint corresponds to the number of system clock cycles within the duration at a set frequency. In other words, the external device advantageously generates a reference signal and determines the number of system clock cycles that should occur during the duration of the reference signal. This corresponds to a system clock presetting, wherein the system clock presetting is to be set for the integrated circuit.

[0009] Therefore, step e) is performed to compare the counter value of the counter module with the counter setting value, and based on the deviation between the counter value and the counter setting value, the frequency of the oscillator module is corrected. If the frequency of the oscillator module matches the predetermined set frequency, the system clock of the integrated circuit has the expected value. If this is not the case, it can be detected that the counter module has not counted the correct number of system clocks during the duration of the reference signal. In this case, the frequency of the oscillator module is either too high, causing the system clock to run too fast and the counter module to have a counter value greater than the counter setting value. Alternatively, the frequency of the oscillator module is too low, causing the system clock to run too slow and the counter module to have a counter value less than the counter setting value. In both cases, the incorrect frequency can be identified and corrected.

[0010] This method requires no complex external systems; only reference signals and counter settings are required. System clock settings are primarily performed using the integrated circuit's onboard resources, particularly the counter module. Complex or tedious computations are avoided. This method is fast and low-cost.

[0011] Preferred embodiments of the invention are described below.

[0012] Preferably, after step e) of comparison and correction, the counter reading of the counter module is reset. All steps a) to e) are then repeated to iteratively correct the frequency of the oscillator module. This allows for precise adjustment of the frequency of the oscillator module, so that the system clock of the integrated circuit is adapted as precisely as possible to a predetermined value.

[0013] It is particularly advantageous if, in each repetition of steps a) to e), the duration of the reference signal is longer than in the preceding repetition of these steps. This allows, in particular, a short duration of the reference signal to be used in the first repetition (in which a rough setting can be performed), while a longer duration is set in the subsequent steps. This minimizes the total time required to set the system clock.

[0014] Alternatively, it is preferably provided that the duration is the same in all repetitions. In this case, in particular, step d) of receiving the counter setting value need not be performed multiple times in each repetition of steps a) to e) because the counter setting value is always the same. Therefore, step d) is performed only once and not repeated. This allows for better comparison of the individual iterations. In particular, the repetition that results in the smallest deviation between the counter setting value and the counter value can be stored as the final result.

[0015] The frequency of the oscillator module can advantageously be set using a binary value having N bits. This is common, for example, in application-specific integrated circuits (ASICs). N represents a natural number. The iterative frequency correction preferably starts with a value in the middle of the value range that can be mapped by N bits and is particularly advantageously adjusted more finely with each iteration.

[0016] In a particularly preferred embodiment, the following steps are implemented to adjust the system clock of the integrated circuit: first, step f) is performed, using the highest bit as the bit to be adjusted. Then, step g) is performed, setting the bit to be adjusted to 1. Preferably, all other bits of the N bits, that is, all bits except the highest bit, are set to 0. In this way, a value that is in the middle of the value range that can be mapped by the N bits is preferably set. As step h), steps a) to e) described above are performed, wherein, in step e), when the counter setting value is less than the counter value, the bit to be adjusted is set to 0, and when the counter setting value is greater than or equal to the counter value, it remains at 1. Then, step i) is performed, using the next lower bit (des Bits) are used as the bit to be adjusted. Finally, steps g) to i) are repeated until all N bits have been traversed. Thus, starting with the most significant bit, all bits are adjusted sequentially until the least significant bit has been adjusted. With each repetition of steps a) to e), only the bit to be adjusted is changed. All other bits, especially all higher-order bits, are particularly advantageously left unchanged. This results in an iterative adjustment of the frequency of the oscillator module in order to adjust the system clock of the integrated circuit. By iterating starting with the most significant bit, the adjustment is initially performed coarsely and then more finely with each lower-order bit.

[0017] The present invention also relates to an integrated circuit. The integrated circuit includes an oscillator module configured to predetermine a system clock for the integrated circuit, a counter module, a signal input, and a communication interface. The oscillator module can be frequency-adjusted, wherein the frequency is set to a desired value. During operation of the integrated circuit, the frequency of the oscillator module determines the system clock. The counter module is preferably an event counter. In the simplest case, the counter module can count the number of system clocks within a specific time period.

[0018] The integrated circuit is particularly advantageously configured to implement the method described above. In particular, the integrated circuit is configured to implement the steps explained below. The integrated circuit is configured to first perform step a) of receiving a reference signal at a signal input for a predefined duration. Furthermore, the integrated circuit is configured to perform step b) of incrementing a counter module by one for each system clock of the integrated circuit during the duration of the application of the reference signal. Thus, the counter module counts the number of system clocks as long as the reference signal is applied. Knowing the duration of the application of the reference signal, the actual system clock can be inferred based on the counter module.

[0019] Furthermore, the integrated circuit is configured to perform step c) of determining the counter value of the counter module after the duration has expired. Furthermore, the integrated circuit is configured to output step d) of receiving a counter setpoint at the communication interface. The counter setpoint is generated, in particular, by an external device, wherein the counter setpoint corresponds to the number of system clock cycles within the duration at a set frequency. In other words, the external device advantageously generates a reference signal and determines the number of system clock cycles that should occur during the duration of the reference signal. This corresponds to a system clock specification, wherein the system clock specification is to be set for the integrated circuit.

[0020] Therefore, the integrated circuit is configured to perform step e), compare the counter value of the counter module with the counter setting value, and correct the frequency of the oscillator module based on the deviation between the counter value and the counter setting value. If the frequency of the oscillator module matches the predetermined set frequency, the system clock of the integrated circuit has the expected value. If this is not the case, it can be detected that the counter module has not counted the correct number of system clocks during the duration of the reference signal. In this case, the frequency of the oscillator module is either too high, causing the system clock to run too fast and the counter module to have a counter value greater than the counter setting value. Alternatively, the frequency of the oscillator module is too low, causing the system clock to run too slow and the counter module to have a counter value less than the counter setting value. In both cases, the incorrect frequency can be identified and corrected.

[0021] Preferably, the integrated circuit is configured to reset the counter reading of the counter module after step e) of comparison and correction. Furthermore, the integrated circuit is preferably configured to then repeat all steps a) to e) in order to iteratively correct the frequency of the oscillator module. This allows for precise adjustment of the frequency of the oscillator module, thereby adapting the system clock of the integrated circuit as precisely as possible to a predetermined setting.

[0022] The frequency of the oscillator module can advantageously be set using a binary value having N bits. This is common, for example, in application-specific integrated circuits (ASICs). N represents a natural number. The integrated circuit is preferably configured to iteratively correct the frequency starting from a value in the middle of the range of values ​​that can be mapped by N bits. Particularly advantageously, the integrated circuit is configured to adjust the frequency more finely with each iteration.

[0023] The integrated circuit particularly preferably comprises an alignment module. The alignment module is designed to perform steps a) to e). In particular, an alignment algorithm for performing the above-described method is implemented in the alignment module. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings:

[0025] Figure 1 A schematic diagram of an integrated circuit according to an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of a time course of signals of an integrated circuit according to an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of a process for adjusting a system clock of an integrated circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0028] Preferably, all identical components, elements and / or units are provided with the same reference numerals in all figures.

[0029] Figure 1 An integrated circuit 1 according to an embodiment of the present invention is schematically shown. The integrated circuit is particularly an application-specific integrated circuit, also known as an "application-specific integrated circuit", or ASIC for short.

[0030] Integrated circuit 1 includes an oscillator module 2. Oscillator module 2 is designed to predetermine a system clock 100 of integrated circuit 1. Furthermore, integrated circuit 1 includes a counter module 3, a signal input 4, and a communication interface 5. Furthermore, a calibration module 8 is provided, which is coupled, in particular, to communication interface 5.

[0031] The external device 7 can be connected to the communication interface 5 in order to establish a communication connection 300 with the alignment module 8 . Furthermore, the external device 7 can be connected to the signal input 4 in order to output a reference signal 100 to the integrated circuit 1 .

[0032] Signal input 4 is coupled to synchronization module 6, which is configured to synchronize reference signal 200 with system clock 100. The generated synchronization reference signal 200a is output to counter module 3 and used to start and stop counter module 3. When the level of synchronization reference signal 100a corresponds to a logical 1, the value of counter module 3 is incremented by one with each rising edge of the system clock. Alignment module 8 is coupled to counter module 3 and allows querying the counter value 3a of counter module 3 and resetting 3b of counter module 1. Alignment module 8 is also configured to adjust the frequency of oscillator module 2. To this end, an alignment algorithm is preferably implemented in alignment module 8.

[0033] The frequency of the oscillator module 2 can be adjusted by a binary value having N bits. N is a natural number. An iterative method is used to adjust the frequency, such as Figure 3 To this end, a plurality of iterations 10, 20, 30 are performed, each of which has the same steps.

[0034] The iterative correction of the frequency of the oscillator module 2 starts from a frequency value in the middle of the value range that can be mapped by N bits. The calibration algorithm is designed to perform the following steps:

[0035] First, the most significant bit of the N bits is considered the bit to be set. Each iteration 10, 20, 30 begins by setting the bit to be set to 1. All lower bits are preferably set to the value 0 or kept at that value. Thus, in the first iteration 10, the middle value of the range of values ​​that can be mapped by the N bits is used by setting the most significant bit to 1. The range of values ​​that can be mapped is Figure 3 Schematically shown as a column.

[0036] The calibration algorithm then performs several steps to align the set frequency with the desired frequency. A reference signal 100 is received from an external device 7 at the signal input 4 for a duration t. This means that the reference signal 200 represents a logical 1 for the duration t. As previously described, the counter module 3 is activated so that it increments by one for each system clock pulse of the integrated circuit during the duration t in which the reference signal 200 is applied. After the duration t has expired, the calibration algorithm determines the counter value 3a of the counter module 3. Furthermore, the calibration module 8 receives a counter set value from the external device 7 via the communication interface 5. This counter set value corresponds to the number of system clock pulses at the desired set frequency during the duration t. By comparing the counter value 3a of the counter module 3 with the counter set value, the deviation in the frequency of the oscillator module 2 can be determined. The calibration algorithm corrects the frequency of the oscillator module 2 based on the deviation in the counter value 3a from the counter set value.

[0037] Frequency calibration is based on the principle that, for a duration t during which external reference signal 200 is applied (i.e., corresponds to a logic 1 level), counter module 3 is influenced, wherein counter value 3a of counter module 3 is directly linked to the oscillator frequency via the system clock. Using the signal form of reference signal 100 specified by external device 7 and the desired target frequency f to be set for oscillator module 2, the counter setting value of counter module 3 can be calculated as follows: counter setting value = t*f.

[0038] If the counter setting value is less than the counter value 3a, the bit to be set is set to 0. In this case, the frequency of the oscillator module 2 is too high and the system clock 100 is too fast, so too many increments of the counter module 3 are performed within the duration t. A decrease 12 is performed. Conversely, if the counter setting value is greater than or equal to the counter value 3a, the bit to be set remains at 1. In this case, the frequency of the oscillator module 2 is too low and the system clock 100 is too slow. Therefore, too few increments of the counter module 3 are performed within the duration t. An increase 11 is performed.

[0039] Thus, the corresponding iterations 10, 20, and 30 are completed. The next lower bit is then used as the bit to be adjusted, and the above steps are repeated for the new bit to be adjusted. In this way, the frequency of the oscillator module 2 is adjusted more and more finely until all N bits have been adjusted.

[0040] It is preferably provided that the duration (t) is the same in all repetitions, wherein step d) of receiving the counter setting value is carried out only once and not repeated.

[0041] The alignment algorithm allows the following options:

[0042] Since the oscillator configuration is initially roughly adjusted using the most significant bit and then adjusted more precisely with each iteration 10, 20, 30, the duration t of the reference signal 200 can also be selected to be short initially and to be longer with each iteration 10, 20, 30. Consequently, a new counter setting value for the counter value is generated in each iteration 10, 20, 30, which needs to be transmitted via the communication interface 5. This can further reduce the overall test time.

[0043] Alternatively, the duration t of the reference signal 100 is selected to be identical in each iteration 10, 20, 30. Consequently, the counter setting value for the counter value is always the same and only needs to be transmitted once via the communication interface 5. In this way, the iterations 10, 20, 30 also become comparable. The alignment algorithm can thus store the oscillator configuration that results in the smallest deviation between the counter value 3a and the counter setting value and provide it as the final result after the iterations 10, 20, 30 have been completed.

[0044] The external device's task is limited to providing reference signal 200 and the counter setting value. No individual calculations or configurations are required. The individual calibration of oscillator module 2 is performed by integrated circuit 1 itself. In this way, the same stimulus from external device 7 can be used to calibrate any number of integrated circuits 1 simultaneously.

[0045] Adjusting the oscillator frequency within the integrated circuit 1 , in particular within an ASIC, using the counter module 3 and an external time reference can be performed significantly faster than by otherwise customary iterative frequency measurements on external test equipment.

[0046] Furthermore, the present invention enables simultaneous frequency calibration of multiple ASICs, since external device 7 does not require individual measurement channels to each ASIC. By implementing the calibration algorithm within the ASIC, any number of components can be aligned in parallel using a single external time reference. The resulting savings in test time directly reduces testing costs.

[0047] The additional logic that has to be implemented on the ASIC is of little importance here, in particular since the counter module 3 that is already integrated anyway can be reused.

Claims

1. A method for adjusting a system clock of an integrated circuit (1), wherein: The integrated circuit (1) comprises an oscillator module (2) configured to predetermine a system clock (100) of the integrated circuit (1), a counter module (3), a signal input terminal (4) and a communication interface (5), wherein the method comprises the following steps: a) receiving a reference signal (100) at said signal input (4) for a predefined duration (t); b) incrementing the counter module (3) by one for each system clock (100) of the integrated circuit during the duration (t) of application of the reference signal (200); c) after the time period (t) has expired, determining the counter value (3a) of the counter module (3); d) receiving a counter setting value at the communication interface (5), the counter setting value corresponding to the number of system clocks within the time duration (t) at the set frequency; e) comparing a counter value (3a) of the counter module (3) with the counter setting value, and correcting the frequency of the oscillator module (2) based on a deviation of the counter value (3a) from the counter setting value.

2. The method according to claim 1, characterized in that After step e) of the comparison and the correction, the counter reading of the counter module (3) is reset, wherein all steps a) to e) are repeated in order to iteratively correct the frequency of the oscillator module (2).

3. The method according to claim 2, characterized in that In each repetition of steps a) to e), the duration (t) of the reference signal is longer than its duration in the previously performed repetition of these steps.

4. The method according to claim 2, characterized in that The duration (t) is the same in all repetitions, wherein step d) of receiving the counter setting value is performed only once and not repeated.

5. The method according to any one of claims 2 to 4, characterized in that The frequency of the oscillator module (2) can be set via a binary value having N bits, wherein N is a natural number, and the iterative correction of the frequency starts from a value in the middle of the value range that can be mapped by the N bits.

6. The method according to claim 5, characterized by the following steps: f) Use the most significant bit as the bit to be set; g) setting the bit to be set to 1; h) performing steps a) to e), wherein: In step e), when the counter setting value is less than the counter value (3a), the bit to be set is set to 0; and when the counter setting value is greater than or equal to the counter value (3a), the bit to be set is kept at 1; i) Use the next lower bit as the bit to be set; j) Repeat steps g) to i) until all N bits are traversed.

7. An integrated circuit (1), comprising: - an oscillator module (2) configured to predetermine a system clock (100) of the integrated circuit (1); - Counter module (3); - a signal input terminal (4); - a communication interface (5); - wherein the integrated circuit (1) is configured to: a) receiving a reference signal (200) at said signal input (4) for a predefined duration (t); b) incrementing the counter module (3) by one for each system clock (100) of the integrated circuit during the duration (t) of application of the reference signal (200); c) after the time period (t) has expired, determining the counter value (3a) of the counter module (3); d) receiving a counter setting value at the communication interface (5), the counter setting value corresponding to the number of system clocks within the time duration (t) at the set frequency; e) comparing a counter value (3a) of the counter module (3) with the counter setting value, and correcting the frequency of the oscillator module (2) based on a deviation of the counter value (3a) from the counter setting value.

8. The integrated circuit (1) according to claim 7, characterized in that The integrated circuit (1) is designed to reset the counter reading of the counter module (3) after the comparison and correction step e) and to repeat all steps in order to iteratively correct the frequency of the oscillator module (2).

9. The integrated circuit (1) according to claim 8, characterized in that The frequency of the oscillator module (2) can be set via a binary value having N bits, wherein N is a natural number, wherein the integrated circuit (1) is designed to iteratively correct the frequency starting from a value in the middle of a value range that can be mapped by the N bits.

10. Integrated circuit (1) according to any one of claims 7 to 9, characterized in that An adjustment module (8) is designed to perform steps a) to e).

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