Maximum overshoot detection circuit and maximum overshoot detection method

Abstract

The application discloses a maximum overshoot detection circuit and a maximum overshoot detection method. The maximum overshoot detection circuit is used for response test of a phase-locked loop and comprises a signal acquisition unit, a timing generation unit, a counting unit and a comparison unit. The signal acquisition unit is used for acquiring an error signal representing a phase difference between a reference clock and a feedback clock of the phase-locked loop and providing at least one pulse signal according to the error signal and an oscillator clock. The timing generation unit is used for providing a counting control signal and a comparison control signal according to the reference clock and the oscillator clock. The counting unit is used for providing a counting value of the pulse signal according to the counting control signal. The comparison unit is used for comparing the counting value with a maximum overshoot value of a previous comparison period according to the comparison control signal to obtain a maximum overshoot value of a current comparison period. The maximum overshoot detection circuit has universality, and can reduce detection cost and improve detection efficiency.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop technology, and in particular to a maximum overshoot detection circuit and a maximum overshoot detection method. Background Technology

[0002] Many high-speed wired applications have specific specifications for the bandwidth and performance of PLLs (Phase-Locked Loops) to ensure signal integrity and system stability during high-speed data transmission. However, due to variations in transistor and passive device manufacturing processes, power supply voltage variations, and temperature variations (PVT), it is difficult to guarantee a narrow range of PLL response. Therefore, it is necessary to test the PLL response and adjust parameter configurations based on the test results to improve yield.

[0003] Traditional PLL response is specified by a phase-modulated closed-loop transfer function. Specifically, it can be obtained by modulating a reference clock using a sine wave generator on a test bench and measuring the PLL response using an oscilloscope or spectrum analyzer. This technique may take several seconds or even minutes to complete, resulting in low testing efficiency and high cost.

[0004] Figure 1a The frequency response curve of the PLL is shown, with the horizontal axis representing the phase modulation frequency (Hz) and the vertical axis representing the phase modulation transfer function (dB). Figure 1b The time-domain response curve of the PLL is shown, with the horizontal axis representing time (μs) and the vertical axis representing phase difference (ns). Reference Figure 1a and Figure 1b The frequency domain can be summarized by the closed-loop bandwidth and peak gain, which correspond to the crossover time T in the time domain, respectively. crossover And maximum overshoot. By using the linear inverse relationship between crossover time and bandwidth, and the linear relationship between peak value and maximum overshoot, the measurement results in the time domain can be linked to the bandwidth and peak value in the frequency domain. Therefore, the frequency domain closed-loop bandwidth and peak gain of the PLL can be obtained by measuring the crossover time and maximum overshoot using all-digital circuits, which is more conducive to reducing test costs and improving test efficiency.

[0005] In the prior art, for example, referring to Dennis Metal., “An Embedded All-Digital Circuit to Measure PLL Response”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.45, NO.8, AUGUST 2010, an all-digital circuit for PLL response testing is disclosed. Among these, a maximum overshoot detection circuit is disclosed, which finds the maximum phase overshoot by sampling the counting state inside the feedback divider at the rising edge of each reference clock.

[0006] Figure 2 A schematic diagram of the timing sequence of the maximum overshoot detection circuit is shown. (Reference) Figure 2 At the rising edge of each reference clock RefClk signal RefRise, the internal counting state FbCnt<5:0> of the feedback divider is sampled to obtain the sampling result SmplCnt<5:0>. At the falling edge of each reference clock RefClk signal RefFall, the current SmplCnt<5:0> is compared with the previous MaxOvershoot<5:0>. The maximum overshoot value MaxOvershoot<5:0> is updated according to the data update instruction UpdateOvershoot. That is, the larger of the two values, the current SmplCnt<5:0> and the previous MaxOvershoot<5:0>, is saved to MaxOvershoot<5:0>. The updated value corresponds to the peak characteristic under the current PLL phase response.

[0007] Because the aforementioned maximum overshoot detection circuit relies on a feedback divider for detection, its application scenarios are quite limited. For example, to ensure correct peak detection, a synchronous divider is needed to maintain continuous internal counting states. However, with the increase in PLL speed, an asynchronous divider is required to achieve reliable frequency division. Asynchronous dividers typically consist of multiple cascaded flip-flops, and the state update of the entire counter occurs gradually, rather than changing simultaneously on the same clock edge. This results in some brief intermediate error states, leading to erroneous sampling results smplcnt<5:0>, causing peak detection errors. Furthermore, since the internal state of the feedback divider is sampled using the rising edge RefRise pulse, not the reference clock RefClk itself, the measurement result includes the RefRise delay (measured using the voltage-controlled oscillator's oscillator clock VcoClk). This also requires that the phase step of the inserted feedback clock be greater than the RefRise delay. Summary of the Invention

[0008] In view of the above problems, the purpose of this application is to provide a universal maximum overshoot detection circuit and a maximum overshoot detection method.

[0009] According to one aspect of this application, a maximum overshoot detection circuit for phase-locked loop (PLL) response testing is provided, comprising: a signal acquisition unit for acquiring an error signal characterizing the phase difference between a reference clock and a feedback clock of the PLL, and providing at least one pulse signal based on the error signal and an oscillator clock; a timing generation unit for providing a counting control signal and a comparison control signal based on the reference clock and the oscillator clock; a counting unit for providing a count value of the pulse signal based on the counting control signal; and a comparison unit for comparing the count value with the maximum overshoot value of the previous comparison cycle based on the comparison control signal to obtain the maximum overshoot value of the current comparison cycle.

[0010] Optionally, the signal acquisition unit includes: an error signal generation module, configured to provide a first level of the error signal when there is a phase difference between the reference clock and the feedback clock; and a clock gating module, configured to provide the at least one pulse signal according to the oscillator clock during the first level, wherein the at least one pulse signal has the same number of pulses as the oscillator clock during the first level.

[0011] Optionally, the error signal generation module includes: a frequency and phase detector for comparing the phase difference between the reference clock and the feedback clock, and providing a pulse control pair based on the comparison result; and an XOR gate, with its input connected to the frequency and phase detector to receive the pulse control pair, and its output providing the error signal.

[0012] Optionally, the error signal generation module and the phase-locked loop share the frequency and phase detector.

[0013] Optionally, the clock gating module includes flip-flops and / or logic gates.

[0014] Optionally, the timing generation unit includes: an edge detection module for converting the rising and falling edges of the reference clock to the clock domain of the oscillator clock to generate rising edge signals and falling edge signals; a first flip-flop, whose data input terminal receives the falling edge signal and whose output terminal provides the counting control signal; and a second flip-flop, whose data input terminal receives the rising edge signal and whose output terminal provides the comparison control signal, wherein the clock input terminals of both the first flip-flop and the second flip-flop receive the oscillator clock.

[0015] Optionally, the edge detection module includes: a third flip-flop, with a data input terminal receiving the reference clock and a clock input terminal receiving the oscillator clock; a fourth flip-flop, with a data input terminal connected to the output terminal of the third flip-flop and a clock input terminal receiving the oscillator clock; a first AND gate, with the output terminal of the third flip-flop connected to one input terminal of the first AND gate, and the output terminal of the fourth flip-flop connected to the other input terminal of the first AND gate via a first inverter, the output terminal of the first AND gate providing the rising edge signal; and a second AND gate, with the output terminal of the third flip-flop connected to one input terminal of the second AND gate via a second inverter, and the output terminal of the fourth flip-flop connected to the other input terminal of the second AND gate, the output terminal of the second AND gate providing the falling edge signal.

[0016] Optionally, the counting unit includes: a counter that receives the pulse signal and counts the number of pulses of the pulse signal; and a sixth flip-flop that has a data input terminal connected to the counter, a clock input terminal that receives the counting control signal, and an output terminal that provides the count value.

[0017] Optionally, the timing generation unit further includes: a fifth flip-flop, a data input terminal receiving the counting control signal, a clock input terminal receiving the oscillator clock, and an output terminal providing a reset signal, the reset signal being used to reset the counter.

[0018] Optionally, the comparison unit includes: a comparator, whose input terminals receive the count value and the maximum overshoot value of the previous comparison cycle, the comparator providing a valid enable signal when the count value is greater than the maximum overshoot value of the previous comparison cycle; a selector, whose input terminals receive the count value and the maximum overshoot value of the previous comparison cycle, the selector being enabled by the valid enable signal to output the count value, otherwise outputting the maximum overshoot value of the previous comparison cycle; and a seventh flip-flop, whose data input terminal is connected to the output terminal of the selector, whose clock input terminal receives the comparison control signal, and whose output terminal provides the maximum overshoot value of the current comparison cycle.

[0019] Optionally, the detection circuit is used to detect the maximum overshoot value during the overshoot phase after the crossover time.

[0020] According to another aspect of this application, a method for detecting maximum overshoot in phase-locked loop (PLL) response testing is provided, comprising: providing at least one pulse signal based on an error signal and an oscillator clock, the error signal representing the phase difference between a reference clock and a feedback clock of the PLL; providing a counting control signal and a comparison control signal based on the reference clock and the oscillator clock; providing a count value of the pulse signal based on the counting control signal; and comparing the count value with the maximum overshoot value of the previous comparison cycle based on the comparison control signal to obtain the maximum overshoot value of the current comparison cycle.

[0021] Optionally, the step of providing the counting control signal and the comparison control signal according to the reference clock and the oscillator clock includes: converting the rising edge and falling edge of the reference clock to the clock domain of the oscillator clock to generate a rising edge signal and a falling edge signal; shifting the falling edge signal to provide the counting control signal; and shifting the rising edge signal to provide the comparison control signal.

[0022] Optionally, the maximum overshoot detection method further includes: shifting the counting control signal to provide a reset signal; and resetting the count value according to the reset signal.

[0023] According to the maximum overshoot detection circuit and method provided in this application, when there is a phase difference between the reference clock and the feedback clock, the pulse signal of the oscillator clock during the phase difference period is acquired by the signal acquisition unit. The magnitude of the phase difference can be obtained by quantizing the number of pulses in the pulse signal. Therefore, this application can achieve the detection of the maximum overshoot value through a fully digital circuit, which is more conducive to reducing detection costs and improving detection efficiency. At the same time, since this application uses an independent counting unit to quantize the pulse signal, the requirements for the feedback frequency divider are reduced.

[0024] Furthermore, in this application, the counter directly counts the number of pulses during the phase difference period and samples the counting result based on the counting control signal obtained from the rising edge signal. Therefore, the count value output by the counting unit does not include the delay introduced when generating the rising edge signal, effectively reducing the limitation on the introduced phase step in the test, which makes the maximum overshoot detection circuit of this application more universal. Attached Figure Description

[0025] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1a The frequency response curve of the PLL is shown.

[0027] Figure 1b The response curve of the PLL in the time domain is shown;

[0028] Figure 2 A schematic diagram showing the operating timing of a maximum overshoot detection circuit in the prior art is provided.

[0029] Figure 3 A schematic structural diagram of the maximum overshoot detection circuit according to an embodiment of this application is shown;

[0030] Figure 4 Show Figure 3 A schematic circuit diagram of the signal acquisition unit;

[0031] Figure 5 Show Figure 3 A schematic circuit diagram of the timing generation unit;

[0032] Figure 6 Show Figure 3 A schematic circuit diagram of the counting unit;

[0033] Figure 7 Show Figure 3 A schematic circuit diagram of the intermediate comparator unit;

[0034] Figure 8 A schematic diagram showing the operating timing of the maximum overshoot detection circuit according to an embodiment of this application is provided.

[0035] Figure 9 A schematic flowchart of the maximum overshoot detection method according to an embodiment of this application is shown. Detailed Implementation

[0036] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0037] Furthermore, certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0038] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0039] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0040] Figure 3 A schematic structural diagram of a maximum overshoot detection circuit according to an embodiment of this application is shown. This maximum overshoot detection circuit 100 is used to detect the maximum overshoot value in a PLL response test. Specifically, it can capture the maximum overshoot value of the phase step response process after a phase step is introduced in the PLL feedback clock clk_fb.

[0041] To facilitate understanding of this application, a brief explanation of phase-locked loops (PLLs) will be provided first. (Reference) Figure 3 The phase-locked loop circuit 400 includes a phase-frequency detector (PFD) 11, a charge pump (CP) 12, a loop filter 13, a voltage-controlled oscillator (VCO) 14, and a feedback divider 15.

[0042] The phase and frequency detector 11 compares the phase and frequency differences between the reference clock clk_ref and the feedback clock clk_fb, and generates a pulse control pair based on the comparison result. Specifically, when the phase / frequency of the feedback clock clk_fb lags behind the reference clock clk_ref, a valid charging control signal UP is generated; when the phase / frequency of the feedback clock clk_fb leads the reference clock clk_ref, a valid discharging control signal DN is generated.

[0043] Charge pump 12 converts the pulse control pairs output by frequency and phase detector 11 into current pulses. These current pulses act on the capacitor of loop filter 13 through charging and discharging operations, accumulating to form a control voltage. In other words, charge pump 12 and loop filter 13 convert the pulse control pairs into voltage variations, thereby providing a smooth and continuous control voltage for voltage-controlled oscillator 14. Voltage-controlled oscillator 14 adjusts the oscillation frequency of its oscillator clock clk_vco according to the control voltage. Feedback divider 15 divides the oscillator clock clk_vco and feeds the generated feedback clock clk_fb back to frequency and phase detector 11, thus forming a closed-loop feedback.

[0044] When a momentary phase step is introduced into the PLL's feedback clock, the PLL will adjust the frequency of the oscillator clock clk_vco output by the voltage-controlled oscillator 14 to eliminate the phase difference and relock the PLL. During this process, due to the dynamic characteristics of the loop, the phase difference may initially exceed the target stable value before gradually converging. (Reference) Figure 1b During the gradual convergence of the phase difference, the phase difference may be positive or negative. However, the maximum overshoot value usually occurs in the overshoot phase after the crossover time (the time when the phase difference first reaches a stable value after the phase step is introduced), i.e., the phase difference is positive. Therefore, in a preferred embodiment, the maximum overshoot value can be detected in the overshoot phase after the crossover time.

[0045] The maximum overshoot detection circuit provided in this application captures the maximum overshoot value by quantizing the phase difference between the reference clock clk_ref and the feedback clock clk_fb. (Reference) Figure 3 The maximum overshoot detection circuit 100 includes a signal acquisition unit 110, a timing generation unit 120, a counting unit 130, and a comparison unit 140.

[0046] Figure 4 Show Figure 3 A schematic circuit diagram of the signal acquisition unit; Figure 5 Show Figure 3 A schematic circuit diagram of the timing generation unit; Figure 6 Show Figure 3 A schematic circuit diagram of the counting unit; Figure 7 Show Figure 3 A schematic circuit diagram of the comparator unit is shown below. Figures 3 to 7 The maximum overshoot detection circuit disclosed in this application will be further described.

[0047] The signal acquisition unit 110 is used to acquire an error signal ES that characterizes the phase difference between the reference clock clk_ref and the feedback clock clk_fb, and to provide at least one pulse signal valid based on the error signal ES and the oscillator clock clk_vco. The error signal ES characterizes the absolute value of the phase difference.

[0048] Combination Figure 3 and Figure 4 The signal acquisition unit 110 includes an error signal generation module 111 and a clock gating module 112. The error signal generation module 111 provides a first level of the error signal ES when a phase difference exists between the reference clock clk_ref and the feedback clock clk_fb. In some embodiments, the error signal generation module 111 includes a frequency-phase detector and an XOR gate. The frequency-phase detector compares the phase difference between the reference clock clk_ref and the feedback clock clk_fb, and provides a pulse control pair, namely a charging control signal UP and a discharging control signal DN, based on the comparison result. The input of the XOR gate is connected to the frequency-phase detector to receive the pulse control pair, and the output provides the error signal. In a preferred embodiment, as shown... Figure 3 and Figure 4 As shown, to simplify the circuit, the error signal generation module 111 can share the frequency and phase detector 11 with the phase-locked loop. That is, the input of the XOR gate is connected to the frequency and phase detector 11 of the phase-locked loop to receive pulse control pairs and provide the error signal ES.

[0049] Specifically, the frequency and phase detector 11 can provide a charging control signal UP and a discharging control signal DN based on the phase difference between the effective edges of the reference clock clk_ref and the feedback clock clk_fb. For example, taking the example where both the effective charging control signal UP and the effective discharging control signal DN are high, and the first level of the error signal ES is also high, then during the period when the rising edge of the reference clock clk_ref leads the rising edge of the feedback clock clk_fb, the frequency and phase detector 11 provides a high-level charging control signal UP and a low-level discharging control signal. Correspondingly, the error signal output by the XOR gate is high.

[0050] The clock gating module 112 is used to provide at least one pulse signal valid according to the oscillator clock clk_vco during the first level of the error signal ES. Specifically, the number of pulse signals valid is the same as the number of pulses in the oscillator clock clk_vco during the first level. More specifically, the number of pulse signals valid is the same as the number of pulses in the oscillator clock clk_vco during each segment of the first level. It should be understood that a pulse here refers to a complete pulse including one rising edge and one falling edge.

[0051] In some embodiments, the clock gating module 112 can be implemented using flip-flops. Taking a D flip-flop as an example, its data input terminal can be connected to the error signal ES, its clock output terminal can be connected to the oscillator clock clk_vco, and its output terminal can provide at least one of the aforementioned pulse signals, valid. However, it should be understood that this application is not limited thereto. For example, the clock gating module 112 can also include logic gates. Taking an AND gate as an example, the error signal ES and the oscillator clock clk_vco are logically ANDed to provide at least one of the aforementioned pulse signals, valid. Alternatively, the clock gating module 112 can also be implemented using a combination of flip-flops and logic gates or other circuits, as long as it is ensured that the number of pulses of the pulse signal valid and the oscillator clock clk_vco are the same during each first level period. This application will not list all such implementations.

[0052] The timing generation unit 120 is used to provide a counting control signal samp1, a comparison control signal samp2, and a reset signal rst based on the reference clock clk_ref and the oscillator clock clk_vco.

[0053] Combination Figure 3 and Figure 5 The timing generation unit 120 includes an edge detection module 121, a first flip-flop 122, a fifth flip-flop 123, and a second flip-flop 124. The edge detection module 121 converts the rising and falling edges of the reference clock clk_ref to the clock domain of the oscillator clock clk_vco to generate a rising edge signal ref rise and a falling edge signal ref fall. The data input of the first flip-flop 122 receives the falling edge signal ref fall, its clock input is connected to the oscillator clock clk_vco, and its output provides a counting control signal samp1. The data input of the fifth flip-flop 123 is connected to the output of the first flip-flop 122, its clock input is connected to the oscillator clock clk_vco, and its output provides a reset signal rst. The data input of the second flip-flop 124 receives the rising edge signal ref rise, its clock input is connected to the oscillator clock clk_vco, and its output provides a comparison control signal samp2.

[0054] More specifically, the edge detection module 121 detects the rising / falling edge of the reference clock clk_ref and generates a pulse signal with a width of one oscillator clock cycle as the rising / falling edge signal. Reference Figure 5The edge detection module 121 includes cascaded third flip-flops 121a and fourth flip-flops 121b, as well as a first inverter, a second inverter, a first AND gate AND1, and a second AND gate AND2. The data input of the third flip-flop 121a receives a reference clock clk_ref, and its clock input receives an oscillator clock clk_vco. The input of the fourth flip-flop 121b is connected to the output of the third flip-flop 121a, and its clock input receives the oscillator clock clk_vco. The output of the third flip-flop 121a is connected to one input of the first AND gate AND1, and the output of the fourth flip-flop 121b is connected to the other input of the first AND gate AND1 via the first inverter. The output of the first AND gate AND1 provides a rising edge signal ref rise. The output of the third flip-flop 121a is connected to one input of the second AND gate AND2 via the second inverter, and the output of the fourth flip-flop 121b is connected to the other input of the second AND gate AND2. The output of the second AND gate AND2 provides a falling edge signal ref fall.

[0055] The counting unit 130 is used to provide the count value of the pulse signal valid according to the counting control signal samp1.

[0056] Combination Figure 3 and Figure 6 The counting unit 130 includes a counter 131 and a sixth flip-flop 132. The counter receives the pulse signal valid and counts the number of pulses num in the pulse signal valid, and resets the number of pulses num according to the reset signal rst. The sixth flip-flop 132 samples the number of pulses num according to the counting control signal sample1 to provide the count value cnt_num. Specifically, the data input terminal of the sixth flip-flop 132 is connected to the counter 131 to receive the number of pulses num, the clock input terminal receives the counting control signal sample1, and the output terminal provides the count value cnt_num. Since the counting control signal sample1 is obtained by shifting the falling edge signal ref fall, sampling the number of pulses num according to the counting control signal sample1 can ensure that the number of pulses num at the time of sampling accurately corresponds to the phase difference between the reference clock clk_ref and the feedback clock clk_fb. Furthermore, since the reset signal rst is obtained by delaying the counting control signal sample1, that is, the reset of the number of pulses num must be performed after sampling is completed, thus ensuring the accuracy of the count value cnt_num.

[0057] The comparison unit 140 is used to compare the count value cnt_num with the maximum overshoot value of the previous comparison cycle according to the comparison control signal samp2, so as to obtain the maximum overshoot value of the current comparison cycle.

[0058] Combination Figure 3and Figure 7 The comparison unit 140 includes a comparator 141, a selector MUX, and a seventh flip-flop 142. The inputs of comparator 141 receive a count value cnt_num and the maximum overshoot value of the previous comparison cycle, respectively, and its output provides an enable signal. Specifically, comparator 141 provides a valid enable signal EN when the count value cnt_num is larger. The inputs of selector MUX receive a count value cnt_num and the maximum overshoot value of the previous comparison cycle, respectively. Selector MUX outputs the count value cnt_num based on a valid enable signal EN, and outputs the maximum overshoot value of the previous comparison cycle otherwise. The seventh flip-flop 142 is used to sample the output of selector MUX based on the comparison control signal samp2 to provide the maximum overshoot value of the current comparison cycle. Specifically, the data input of the seventh flip-flop 142 is connected to the output of selector MUX, its clock input receives the comparison control signal samp2, and its output provides the maximum overshoot value of the current comparison cycle. Since the comparison control signal samp2 is obtained from the shift rising edge signal ref rise, it can be ensured that the comparison unit 140 can correctly update the maximum overshoot value.

[0059] It should be noted that the first to seventh flip-flops mentioned above are all D flip-flops as examples. However, it should be understood that other types of flip-flops may be used in some other embodiments.

[0060] Figure 8 A schematic diagram showing the timing of the detection circuit according to an embodiment of this application is provided below. Figures 3 to 8 This section describes the operation of the maximum overshoot detection circuit in the embodiments of this application. Furthermore, in... Figure 8 Specifically, this example uses the phase difference between the rising edges of the reference clock clk_ref and the feedback clock clk_fb as an example. Furthermore, the error signal's first level is high, and each valid pulse of the valid pulse signal includes one rising edge and one falling edge.

[0061] In the response test, changing the parameters of the feedback divider 15 introduces a phase step into the feedback clock clk_fb, resulting in a phase difference between the rising edges of the reference clock clk_ref and the feedback clock clk_fb. The phase detector 11 detects this phase difference and provides pulse control to UP and DN. The XOR gate provides the first level of the error signal ES to UP and DN according to the pulse control. For example, in... Figure 8In this context, the high-level phase of the error signal ES corresponds to a phase difference between the rising edges of the reference clock clk_ref and the feedback clock clk_fb. The clock gating module 112 is enabled by the first level of the error signal ES to obtain a valid pulse in the oscillator clock clk_vco to provide a valid pulse signal. For example, in... Figure 8 In the pulse signal valid, there is one valid pulse in the phase difference T1 stage and two valid pulses in the phase difference T2 stage. Counter 131 counts the number of pulses num in the pulse signal valid and provides a sampled value as the count value cnt_num according to the counting control signal samp1. The number of pulses num is also reset according to the reset signal rst after being sampled. Comparison unit 140 obtains a new maximum overshoot value by comparing the sampled count value cnt_num with the previous maximum overshoot value according to the comparison control signal samp2.

[0062] According to the maximum overshoot detection circuit provided in this application, when there is a phase difference between the reference clock and the feedback clock, the pulse signal of the oscillator clock during the phase difference period is acquired by the signal acquisition unit. The magnitude of the phase difference can be obtained by quantizing the number of pulses in the pulse signal. Therefore, this application can achieve maximum overshoot detection through a fully digital circuit, which is more conducive to reducing detection costs and improving detection efficiency. At the same time, since this application uses an independent counting unit to quantize the pulse signal, the requirements for the feedback frequency divider are reduced.

[0063] Furthermore, in this application, the counter directly counts the number of pulses during the phase difference period and samples the counting result based on the counting control signal obtained from the rising edge signal. Therefore, the count value output by the counting unit does not include the delay introduced when generating the rising edge signal, effectively reducing the limitation on the introduced phase step in the test. The introduced phase step only needs to be greater than the single pulse width of the oscillator clock (i.e., half of the oscillator clock period), which makes the maximum overshoot detection circuit of this application more universal.

[0064] Figure 9 A schematic flowchart illustrating the maximum overshoot detection method of this application is shown. The maximum overshoot detection method provided in this application can be used to detect the maximum overshoot value in PLL response testing. This detection method can be implemented, for example, using the maximum overshoot detection circuit provided in this application. (Reference) Figure 9 The detection method includes:

[0065] Step S11: Provide at least one pulse signal based on the error signal and the oscillator clock, wherein the error signal characterizes the phase difference between the reference clock and the feedback clock of the phase-locked loop;

[0066] Step S12: Provide counting control signals and comparison control signals based on the reference clock and oscillator clock;

[0067] Step S13: Provide the count value of the pulse signal according to the counting control signal; and

[0068] Step S14: Compare the count value with the maximum overshoot value of the previous comparison cycle according to the comparison control signal to obtain the maximum overshoot value of the current comparison cycle.

[0069] According to the maximum overshoot detection method provided in this application, when there is a phase difference between the reference clock and the feedback clock, the pulse signal of the oscillator clock during the phase difference period is acquired by the signal acquisition unit. The magnitude of the phase difference can be obtained by quantizing the number of pulses in the pulse signal. Therefore, this application can achieve maximum overshoot detection through a fully digital circuit, which is more conducive to reducing detection costs and improving detection efficiency. At the same time, since this application uses an independent counting unit to quantize the pulse signal, the requirements for the feedback frequency divider are reduced.

[0070] Further, step S12 may specifically include: converting the rising and falling edges of the reference clock to the clock domain of the oscillator clock to generate rising edge signals and falling edge signals; shifting the falling edge signal to provide a counting control signal; and shifting the rising edge signal to provide a comparison control signal.

[0071] The shifting of the rising and falling edge signals can be achieved using flip-flops. Correspondingly, the counting control signal can lag behind the falling edge signal by one oscillator clock cycle. Similarly, the comparison control signal can also lag behind the rising edge signal by one oscillator clock cycle.

[0072] To simplify the circuit and reduce computational resources, the maximum overshoot detection method provided in this application further includes: a shift counting control signal to provide a reset signal; and resetting the count value according to the reset signal after providing the count value.

[0073] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit this application to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A maximum overshoot detection circuit, wherein, The maximum overshoot detection circuit is used for response test of a phase-locked loop, and the maximum overshoot detection circuit comprises: a signal acquisition unit configured to acquire an error signal representing a phase difference between a reference clock and a feedback clock of the phase-locked loop, and provide at least one pulse signal according to the error signal and an oscillator clock; a timing generation unit configured to provide a count control signal and a comparison control signal according to the reference clock and the oscillator clock; a counting unit configured to provide a count value of the pulse signal according to the count control signal; and a comparison unit configured to compare the count value with a maximum overshoot value of a previous comparison period according to the comparison control signal, to obtain a maximum overshoot value of a current comparison period, wherein the signal acquisition unit comprises: an error signal generation module configured to provide a first level of the error signal when there is a phase difference between the reference clock and the feedback clock; and a clock gating module configured to provide the at least one pulse signal according to the oscillator clock during the first level, the at least one pulse signal being identical to a number of pulses of the oscillator clock during the first level, the timing generation unit comprises: an edge detection module configured to convert rising and falling edges of the reference clock to a clock domain of the oscillator clock to generate a rising edge signal and a falling edge signal; a first flip-flop having a data input end receiving the falling edge signal and an output end providing the count control signal; and a second flip-flop having a data input end receiving the rising edge signal and an output end providing the comparison control signal, clock input ends of the first flip-flop and the second flip-flop both receiving the oscillator clock.

2. The maximum overshoot detection circuit of claim 1, wherein, the error signal generation module comprises: a phase frequency detector configured to compare a phase difference between the reference clock and the feedback clock, and provide a pulse control pair according to a comparison result; and an exclusive-OR gate having input ends connected to the phase frequency detector to receive the pulse control pair, and an output end providing the error signal.

3. The maximum overshoot detection circuit of claim 2, wherein, the error signal generation module and the phase-locked loop share the phase frequency detector.

4. The maximum overshoot detection circuit of claim 1, wherein, the clock gating module comprises a flip-flop and / or a logic gate circuit.

5. The maximum overshoot detection circuit of claim 1, wherein, the edge detection module comprises: a third flip-flop having a data input end receiving the reference clock and a clock input end receiving the oscillator clock; a fourth flip-flop having a data input end connected to an output end of the third flip-flop and a clock input end receiving the oscillator clock; a first AND gate having one input end connected to an output end of the third flip-flop and another input end connected to an output end of the fourth flip-flop via a first inverter, and an output end providing the rising edge signal; and a second AND gate having one input end connected to the output end of the third flip-flop via a second inverter and another input end connected to the output end of the fourth flip-flop, and an output end providing the falling edge signal.

6. The maximum overshoot detection circuit of claim 1, wherein, the counting unit comprises: a counter receiving the pulse signal, the counter being configured to count a number of pulses of the pulse signal; and A sixth flip-flop has a data input coupled to the counter, a clock input receiving the count control signal, and an output providing the count value.

7. The maximum overshoot detection circuit of claim 6, wherein, The timing generation unit further includes: A fifth flip-flop has a data input receiving the count control signal, a clock input receiving the oscillator clock, and an output providing a reset signal for resetting the counter.

8. The maximum overshoot detection circuit of claim 1, wherein, The comparison unit includes: A comparator has inputs receiving the count value and the maximum overshoot value of the previous comparison period, and provides an active enable signal when the count value is greater than the maximum overshoot value of the previous comparison period; A selector has inputs receiving the count value and the maximum overshoot value of the previous comparison period, and is enabled by the active enable signal to output the count value, and otherwise outputs the maximum overshoot value of the previous comparison period; and A seventh flip-flop has a data input coupled to the output of the selector, a clock input receiving the comparison control signal, and an output providing the maximum overshoot value of the current comparison period.

9. The maximum overshoot detection circuit of claim 1, wherein, The detection circuit is configured to detect the maximum overshoot value during an overshoot phase after a crossing time.

10. A maximum overshoot detection method, wherein, The maximum overshoot detection method is configured to test a response of a phase-locked loop, and includes: providing at least one pulse signal according to an error signal and an oscillator clock, the error signal representing a phase difference between a reference clock and a feedback clock of the phase-locked loop; providing a count control signal and a comparison control signal according to the reference clock and the oscillator clock; providing a count value of the pulse signal according to the count control signal; and comparing the count value with a maximum overshoot value of a previous comparison period according to the comparison control signal to obtain a maximum overshoot value of a current comparison period, wherein the step of providing at least one pulse signal according to an error signal and an oscillator clock includes: providing a first level of the error signal when there is a phase difference between the reference clock and the feedback clock; and providing the at least one pulse signal according to the oscillator clock during the first level, the at least one pulse signal having a same number of pulses as the oscillator clock during the first level, the step of providing a count control signal and a comparison control signal according to the reference clock and the oscillator clock includes: converting rising and falling edges of the reference clock to a clock domain of the oscillator clock to generate a rising edge signal and a falling edge signal; shifting the falling edge signal according to the oscillator clock to provide the count control signal; and shifting the rising edge signal according to the oscillator clock to provide the comparison control signal.

11. The maximum overshoot detection method of claim 10, wherein, The maximum overshoot detection method further includes: shifting the count control signal to provide a reset signal; and resetting the count value according to the reset signal.

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