Silicon-based Schottky diode and preparation method thereof

Abstract

The invention discloses a silicon-based Schottky diode with a composite passivation layer and a gradient doped protection ring and a preparation method thereof, the composite passivation structure comprises a first SiO2 layer, the SiO2 layer is arranged above metal and extends to the periphery of the upper surface of the metal; the second layer of Si3N4 is arranged above the SiO2 layer; and the third layer is Al2O3, wherein the Al2O3 layer is arranged above the Si3N4. According to the manufacturing method of the passivation structure, cracking of silicon nitride on the metal substrate due to large expansion coefficient difference can be avoided, and the morphology of the passivation layer can be adjusted by adjusting the thickness and morphology of the oxide layer below the silicon nitride, so that abnormal conditions such as cracking can be avoided. The surface layer is made of a high-K dielectric Al2O3 material, and the problem that reverse leakage current is large due to edge electric field concentration caused by a gradient protection ring structure is controlled. Meanwhile, the composite passivation layer structure can fix movable charges in an oxide layer of a Schottky diode product and isolate adverse effects caused by harsh environment water vapor, and the reliability and stability of the product are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon-based Schottky diode with a composite passivation layer and a gradient doping guard ring, and a preparation method thereof. Background Art

[0002] For silicon-based Schottky products, since low forward voltage drop is an important advantage, when selecting material resistivity, lower materials will be chosen as much as possible. At this time, it is difficult to achieve a reverse breakdown voltage of 300V or above by relying solely on a field plate, and the terminal length requirement is relatively high. When gradient doping technology is used alone, due to the low doping concentration, it is easily affected by external contamination, charge, surface state, etc., resulting in large leakage current.

[0003] In summary, current traditional silicon-based Schottky diodes have the following defects: ①The edge electric field concentration leads to large reverse leakage current; ② A single passivation layer does not provide sufficient control over the surface state; ③The electric field modulation efficiency of conventional field plate structure is low. Summary of the Invention

[0004] The purpose of the present invention is to overcome the defects in the prior art and provide a silicon-based Schottky diode with a composite passivation layer and a gradient doped guard ring and a preparation method thereof, so as to improve the reverse breakdown voltage and forward conduction characteristics of the silicon-based Schottky diode through structural combination innovation.

[0005] To achieve the above objectives, the present invention designs a silicon-based Schottky diode, wherein the bottom of the diode is a substrate, and an epitaxial layer is formed above the substrate. The diode has a composite passivation layer and a gradient doping (e.g., silicon doped with boron) guard ring. At least two mutually adjacent gradient guard rings are provided between the P+ and N- ends of the diode through gradient doping. The thickness of the outer ring of the gradient guard ring is less than that of the inner ring, and the lateral width of the lower end of the guard ring gradually decreases as the thickness increases. The inner center portion of the innermost ring of the gradient guard ring on the upper surface of the epitaxial layer is covered with a barrier layer, wherein the barrier layer is mainly a compound of metals such as platinum and nickel and silicon. The barrier layer is covered with a metal layer. Except for the central area, the outer area of ​​the metal layer is completely covered by a composite passivation layer, and the composite passivation layer continuously covers the UDO layer adjacent to the outer end of the metal layer. The composite passivation layer includes three dielectric layers of SiO2, Si3N4, and Al2O3 stacked in sequence from bottom to top.

[0006] Furthermore, a portion of the outer ring of the gradient protection ring is embedded in the adjacent inner ring. The so-called inner ring and outer ring refer only to the relative relationship between adjacent protection rings, and do not specifically refer to a fixed gradient protection ring. The shape of the lower end of the gradient protection ring includes an arc shape or a trapezoidal shape.

[0007] Furthermore, the gradient guard ring includes a concentration gradient between P+ and N- of 1×10 16 cm -3 →5×10 17 cm -3 The linear transition zone has a total width of 10 to 15 μm.

[0008] Furthermore, the metal layer directly covers the inner part of the innermost gradient protection ring, and the outer part thereof up to the outermost epitaxial layer is covered with an oxide layer; the oxide layer is covered with a UDO layer.

[0009] Furthermore, in the composite passivation layer, the thickness of SiO2 is 500 nm, the thickness of Si3N4 is 30 nm, and the thickness of Al2O3 is 20 nm, with an error of ±2 nm.

[0010] Furthermore, an N+ cut-off ring is provided at the top outer edge of the epitaxial layer and below the oxide layer.

[0011] In another aspect, a method for preparing a silicon-based Schottky diode is provided, the method comprising: S1. Gradient guard ring etching preparation: A combination of photolithography (photoresist masking) and implantation is used on the upper layer of thermal oxide to wet-etch the gradient guard ring pattern and complete the impurity introduction; S2, Gradient Guard Ring Forming: Using a high-temperature oxidation diffusion process in a furnace, the gradient guard ring is pushed and oxidized to form an impurity distribution and a masking layer; S3. Growth of UDO layer: Using PECVD (plasma enhanced chemical vapor deposition) to grow a layer of UDO, and then using photolithography wet etching to form a barrier metal deposition window; S4. Growth of barrier layer and metal layer: Using PVD (Physical Vapor Deposition) process, a Schottky barrier metal layer of a certain thickness is first deposited on the surface, which covers the PN junction voltage divider ring structure, and then a front electrode metal layer of a certain thickness is deposited on the Schottky barrier layer; S5. Forming Schottky contacts: Using a furnace tube low-temperature alloying process, a Schottky barrier metal layer and an epitaxial layer are formed into a Schottky contact; using photolithography (photoresist masking), the electrode metal layer and the Schottky barrier metal layer are etched to form a bonding metal layer as a lead of the finished device; continuing the photolithography method, excess metal is removed; S6. Growth of SiO2 and Si3N4 layers: PECVD is used to grow SiO2 and Si3N4 layers layer by layer; S7. Growth of Al2O3 layer: ALD (Atomic Layer Deposition) is used to grow the Al2O3 layer, and oxygen plasma treatment is performed at the interface; S8. Forming PAD bonding area: Using photolithography, dry-etch the excess Al2O3, Si3N4, and SiO2 to form a PAD (Precision and Accuracy Defined, a highly precise metallization process) bonding area.

[0012] Furthermore, the step S2 includes adopting a high temperature oxidation push-bonding process, with a furnace temperature of 1150° C., a time of 60 min, and a nitrogen flow rate of 10 L / min; The step S3 includes growing a layer of UDO with a thickness of 0.5 μm, and the boundary of the barrier metal deposition window is set inside the PN junction type voltage divider ring, and the voltage divider ring width is 9 μm; In step S4, the thickness of the Schottky barrier metal layer is 50 nm, and the thickness of the front electrode metal layer is 9 μm; In step S6, the thickness of SiO2 is 500nm and the thickness of Si3N4 is 30nm; The thickness of Al2O3 in step S7 is 20 nm.

[0013] The advantages and beneficial effects of the present invention are: The present invention designs a silicon-based Schottky diode with a composite passivation layer and a gradient doped guard ring. The composite passivation structure comprises a first SiO2 layer, disposed above the metal and extending to the periphery of the metal's top surface; a second Si3N4 layer disposed above the SiO2 layer; and a third Al2O3 layer disposed above the Si3N4 layer. This passivation structure prevents cracking of silicon nitride on the metal substrate due to large differences in expansion coefficient. It also adjusts the passivation layer's morphology by adjusting the thickness and morphology of the oxide layer beneath the silicon nitride to prevent cracking and other anomalies. The surface layer utilizes a high-K Al2O3 dielectric material to mitigate the high reverse leakage current caused by the edge electric field concentration associated with the gradient guard ring structure. The interface trap density of the composite passivation layer is two orders of magnitude lower than that of a single-layer structure, thereby reducing threshold voltage drift and leakage current. In particular, the stability and reliability of the device are significantly improved under high temperature and high voltage conditions. At the same time, this composite passivation layer structure can fix the movable charge in the oxide layer of the Schottky diode product and isolate the adverse effects of water vapor in harsh environments, thereby improving product reliability and stability.

[0014] The present invention incorporates a gradient guard ring, which gradually reduces the doping concentration within the guard ring, thereby reducing the electric field concentration at the spherical junction formed by diffusion, thereby improving withstand voltage. Compared to a field plate-only structure with equivalent terminal length and material resistivity, the present invention's field plate plus gradient doped guard ring structure achieves a breakdown voltage approximately 40V higher, while also offering high electric field modulation efficiency and minimal leakage.

[0015] Regarding the control of surface states by the passivation layer, the mainstream single PI (polyimide) passivation or silicon nitride on the market has a certain ability to fix mobile charges. However, when the production environment conditions are affected, it is easily affected by external contamination, resulting in abnormal interface states and breakdown abnormalities. The use of a composite passivation layer can fully utilize the properties of various passivation layers. The high-K dielectric aluminum oxide and silicon nitride can adjust the electric field distribution, thereby controlling the surface state under the influence of the induced electric field. At the same time, the high mechanical strength of silicon nitride can prevent external scratches from affecting the device. Aluminum oxide also has a deep energy level trap, which can capture and control mobile charges. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a cross-sectional view (front cross-sectional view) of a silicon-based Schottky diode of the present invention; Figure 2 yes Figure 1 A partial enlarged view of the gradient protection ring; Figure 3 yes Figure 1 A local enlarged view of the position of the third composite passivation layer; Figure 4 The present invention is a flow chart of a method for preparing a silicon-based Schottky diode.

[0017] Markings in the figure: 1. Substrate; 2. Epitaxial layer; 3. Gradient guard ring; 4. Barrier layer; 5. UDO layer; 6. Metal layer; 7. Composite passivation layer; 8. Oxide layer; 9. N+ cutoff ring; 7.1, first composite passivation layer; 7.2, second composite passivation layer; 7.3, third composite passivation layer; 7.4, fourth composite passivation layer. DETAILED DESCRIPTION

[0018] The following embodiments are further described in conjunction with the accompanying drawings and examples. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0019] Example 1: The present invention designs a silicon-based Schottky diode, such as Figure 1-Figure 3As shown, the bottom of the diode is a substrate 1, and the epitaxial layer 2 is above the substrate. The diode is characterized in that it has a composite passivation layer and a gradient doping (such as silicon doped with boron) guard ring. At least two mutually adjacent gradient guard rings 3 are set between the P+ and N- of the diode through gradient doping. The thickness of the outer ring of the gradient guard ring (the vertical direction is thickness, the left and right direction is width, the direction pointing to the center is called inner, and the direction pointing to the left and right sides is called outer) is less than the thickness of the inner ring, and the lateral width of the lower end of the guard ring gradually decreases as the thickness increases, that is, the width changes continuously with the thickness. This can improve the diode's withstand voltage (reverse breakdown voltage); The inner center part of the innermost ring of the gradient protection ring on the upper surface of the epitaxial layer is covered with a barrier layer 4, which is mainly a compound of metals such as platinum and nickel and silicon. The barrier layer is covered with a metal layer 6. Except for the central area, the outer area of ​​the metal layer 6 is completely covered by a composite passivation layer 7, and the composite passivation layer continuously covers the UDO layer 5 adjacent to the outer end of the metal layer, that is, the composite passivation layer covers all the step areas that are inevitably formed by the dielectric during the processes of photolithography, corrosion, deposition, etc. except the central area of ​​the lower metal layer. The metal layer is shown extending to the periphery to form a Two successively ascending annular steps and a step between the outermost end and the UDO layer are formed. Corresponding to the annular steps, a first composite passivation layer 7.1, a second composite passivation layer 7.2, a third composite passivation layer 7.3, and a fourth composite passivation layer 7.4 are sequentially arranged on the metal layer from the inside out. The fourth composite passivation layer 7.4 is shown outside the third composite passivation layer 7.3 and above the UDO layer 5. Taking a cylindrical Schottky diode as an example, each composite passivation layer is annular. This distinction is based on current conditions. In short, it is necessary to ensure that these steps are covered by the composite passivation layer. The composite passivation layer 7 includes three dielectric layers of SiO2, Si3N4, and Al2O3 stacked in sequence from bottom to top.

[0020] Among them, P+ is highly doped P-type silicon, Figure 1 As shown, the innermost gradient guard ring or the top of the gradient guard ring can be regarded as P+, N+ is highly doped N-type silicon, N- is low doped N-type silicon, and the epitaxial layer can be regarded as N- in the figure.

[0021] The present invention incorporates a gradient guard ring, which gradually reduces the doping concentration within the guard ring, thereby reducing the electric field concentration at the spherical junction formed by diffusion, thereby improving withstand voltage. Compared to a field plate-only structure with equivalent terminal length and material resistivity, the present invention's field plate plus gradient doped guard ring structure achieves a breakdown voltage approximately 40V higher, while also reducing leakage.

[0022] The interface trap density of the composite passivation layer is two orders of magnitude lower than that of a single-layer structure. This composite passivation structure can prevent cracking of silicon nitride on the metal substrate due to large differences in expansion coefficients. It can also adjust the passivation layer morphology by adjusting the thickness and morphology of the oxide layer (SiO2) beneath the silicon nitride to avoid abnormalities such as cracking. The surface layer uses a high-K dielectric Al2O3 material to control the edge electric field concentration caused by the gradient guard ring structure, which leads to large reverse leakage current. Furthermore, this composite passivation layer structure can effectively fix the movable charge in the oxide layer of Schottky diode products and isolate the adverse effects of water vapor in harsh environments, thereby improving product reliability and stability.

[0023] Preferably, Figure 2 As shown, a portion of the outer ring of the gradient protection ring is embedded in the adjacent inner ring. The so-called inner ring and outer ring refer only to the relative relationship between adjacent protection rings, and do not specifically refer to a fixed gradient protection ring. The shape of the lower end of the gradient protection ring includes an arc shape or a trapezoidal shape. In this embodiment, it is an arc shape.

[0024] Preferably, the gradient guard ring includes a concentration gradient between P+ and N- of 1×10 16 cm -3 →5×10 17 cm -3 The linear transition region has a total width of 10 to 15 μm. This design can be used as a JTE structure to reduce the electric field concentration caused by the spherical junction. Here the width is Figure 1 The left and right directions are shown, and the thickness refers to the up and down directions. In this embodiment, three gradient protection rings are designed with a total width of 15um.

[0025] Preferably, the metal layer 6 directly covers (referring to contact coverage) the inner part of the innermost gradient guard ring, and its outer part is covered with an oxide layer 8 up to the outermost epitaxial layer, and the oxide layer is generally silicon dioxide; the oxide layer 8 is covered with a UDO layer 5, corresponding to the positions of the second composite passivation layer 7.2 and the third composite passivation layer 7.3, the UDO layer 5 is located between the metal layer 6 and the oxide layer 8, and forms corresponding steps; corresponding to the position of the fourth composite passivation layer 7.4, the UDO layer is directly covered by the composite passivation layer, and the composite passivation layer also covers the corresponding steps; in this embodiment, the UDO layer is set to increase the field oxygen thickness by depositing an oxide layer, thereby improving the withstand voltage; and the metal layer covers the UDO, forming a field plate structure, which can optimize the electric field and improve the withstand voltage.

[0026] Preferably, the composite passivation layer has a SiO2 thickness of 500nm, a Si3N4 thickness of 30nm, and an Al2O3 thickness of 20nm, with an error of ±2nm. Silicon dioxide lining beneath silicon nitride can prevent cracking of the silicon nitride caused by the large difference in expansion coefficient between silicon nitride and metal. The silicon nitride layer should not be too thick, as this can also easily crack. Silicon nitride also acts as a passivation layer, reducing the impact of external moisture on the device, while the aluminum oxide film can also protect the device from scratches.

[0027] Preferably, an N+ cutoff ring 9 is provided on the top outer edge of the epitaxial layer and below the oxide layer 8. Since high-voltage devices generally use higher resistivity epitaxy, the material is easily inverted to form surface channel leakage under high voltage. The design of the N+ cutoff ring can effectively block the channel.

[0028] Example 2: The difference from Example 1 is that this embodiment designs two gradient guard rings with a total width of 10 μm, the SiO2 thickness in the composite passivation layer is 480 nm, the Si3N4 thickness is 40 nm, and the Al2O3 thickness is 15 nm.

[0029] Example 3: The difference from Example 1 is that this embodiment designs four gradient guard rings with a total width of 20 μm, and the thickness of SiO2 in the composite passivation layer is 550 nm, the thickness of Si3N4 is 50 nm, and the thickness of Al2O3 is 30 nm.

[0030] Example 4: A method for preparing a silicon-based Schottky diode, such as Figure 4 As shown, the preparation method includes: S1. Gradient guard ring etching preparation: A combination of multiple photolithography (photoresist masking) and implantation is used on the 0.1μm thermal oxide upper layer to wet-etch the gradient guard ring pattern and complete the impurity introduction. The gradient guard ring is achieved by adjusting the energy of multiple ion implantations (80keV→20keV). The preparation process or process of other substrates and metal oxide layers is the general process for diode manufacturing. S2, Gradient Guard Ring Forming: Using a high-temperature oxidation diffusion process in a furnace, the gradient guard ring is pushed and oxidized to form an impurity distribution and a masking layer; S3. Growth of UDO layer: Using PECVD (plasma enhanced chemical vapor deposition) to grow a layer of UDO, and then using photolithography wet etching to form a barrier metal deposition window; S4. Growth of barrier layer and metal layer: Using PVD (Physical Vapor Deposition) process, a Schottky barrier metal layer of a certain thickness is first deposited on the surface, which covers the PN junction voltage divider ring structure, and then a front electrode metal layer of a certain thickness is deposited on the Schottky barrier layer; S5. Forming Schottky contacts: Using a furnace tube low-temperature alloying process, a Schottky barrier metal layer and an epitaxial layer are formed into a Schottky contact; using photolithography (photoresist masking), the electrode metal layer and the Schottky barrier metal layer are etched to form a bonding metal layer as a lead of the finished device; continuing the photolithography method, excess metal is removed; S6. Growth of SiO2 and Si3N4 layers: PECVD is used to grow SiO2 and Si3N4 layers layer by layer; S7. Growth of Al2O3 layer: ALD (Atomic Layer Deposition) is used to grow the Al2O3 layer, and oxygen plasma treatment is performed at the interface; S8. Forming PAD bonding area: Using photolithography, dry-etch the excess Al2O3, Si3N4, and SiO2 to form a PAD (Precision and Accuracy Defined, a highly precise metallization process) bonding area.

[0031] Preferably, the step S2 includes adopting a high-temperature oxidation push-bonding process, with a furnace temperature of 1150° C., a time of 60 min, and a nitrogen flow rate of 10 L / min; The step S3 includes growing a layer of UDO with a thickness of 0.5 μm, and the boundary of the barrier metal deposition window is set inside the PN junction type voltage divider ring, and the voltage divider ring width is 9 μm; In step S4, the thickness of the Schottky barrier metal layer is 50 nm, and the thickness of the front electrode metal layer is 9 μm; In step S6, the thickness of SiO2 is 500nm and the thickness of Si3N4 is 30nm; The thickness of Al2O3 in step S7 is 20 nm.

[0032] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical principles of the present invention, they can also make several improvements and modifications, such as re-modifying and combining parameters such as the thickness and width of the product and parameters such as temperature and time in the process flow, etc. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A silicon-based Schottky diode, wherein the bottom of the diode is a substrate (1), and an epitaxial layer (2) is formed on the substrate, characterized in that: At least two mutually adjacent gradient protection rings (3) are provided between the P+ and N- of the diode by gradient doping, the thickness of the outer ring of the gradient protection ring is smaller than the thickness of the inner ring, and the lateral width of the lower end of the protection ring gradually decreases as the thickness increases; The inner center portion of the innermost ring of the gradient protection ring on the upper surface of the epitaxial layer is covered with a barrier layer (4), and the barrier layer is covered with a metal layer (6). Except for the central area, the outer area of ​​the metal layer (6) is completely covered by a composite passivation layer (7), and the composite passivation layer continuously covers the UDO layer (5) adjacent to the outer end of the metal layer; The composite passivation layer (7) comprises three dielectric layers of SiO2, Si3N4, and Al2O3 stacked in sequence.

2. A silicon-based Schottky diode according to claim 1, characterized in that: A portion of the outer ring of the gradient protection ring is embedded in the adjacent inner ring, and the shape of the lower end portion of the gradient protection ring includes an arc shape or a trapezoidal shape.

3. A silicon-based Schottky diode according to claim 1, characterized in that: The gradient guard ring includes a concentration gradient between P+ and N- of 1×10 16 cm -3 →5×10 17 cm -3 The linear transition zone has a total width of 10 to 15 μm.

4. The silicon-based Schottky diode according to claim 1, wherein: The metal layer (6) directly covers the inner part of the innermost gradient protection ring, and the outer part thereof up to the outermost epitaxial layer is covered with an oxide layer (8); the oxide layer (8) is covered with a UDO layer (5).

5. The silicon-based Schottky diode according to claim 1, characterized in that: The thickness of SiO2 in the composite passivation layer is 500 nm, the thickness of Si3N4 is 30 nm, and the thickness of Al2O3 is 20 nm, with an error of ±2 nm.

6. The silicon-based Schottky diode according to claim 1, characterized in that: An N+ cut-off ring (9) is provided at the outer edge of the top of the epitaxial layer and below the oxide layer (8).

7. A method for preparing a silicon-based Schottky diode, characterized in that: The preparation method comprises: S1. Gradient guard ring etching preparation: A combination of photolithography and implantation is used on the upper layer of thermal oxide to wet-etch the gradient guard ring pattern and complete the impurity introduction; S2, Gradient Guard Ring Forming: Using a high-temperature oxidation diffusion process in a furnace, the gradient guard ring is pushed and oxidized to form an impurity distribution and a masking layer; S3. Growth of UDO layer: Using PECVD method, a layer of UDO is grown, and then wet etching using photolithography process is continued to form a barrier metal deposition window; S4. Growth of barrier layer and metal layer: using PVD process to first deposit a Schottky barrier metal layer of a certain thickness on the surface, which covers the PN junction voltage divider ring structure, and then depositing a front electrode metal layer of a certain thickness on the Schottky barrier layer; S5. Forming Schottky contact: Using a furnace tube low-temperature alloying process, the Schottky barrier metal layer and the epitaxial layer form a Schottky contact; using a photolithography method, etching the electrode metal layer and the Schottky barrier metal layer to form a bonding metal layer as a lead of the finished device; S6. Growth of SiO2 and Si3N4 layers: PECVD is used to grow SiO2 and Si3N4 layers layer by layer; S7, growing an Al2O3 layer: using ALD to grow an Al2O3 layer, and performing oxygen plasma treatment on the interface; S8. Forming a PAD bonding area: Using a photolithography method, dry-etch excess Al2O3, Si3N4, and SiO2 to form a PAD bonding area.

8. The method for preparing a silicon-based Schottky diode according to claim 7, wherein: The step S2 includes adopting a high temperature oxidation push-bonding process, with a furnace temperature of 1150° C., a time of 60 minutes, and a nitrogen flow rate of 10 L / min; The step S3 includes growing a layer of UDO with a thickness of 0.5 μm, and the boundary of the barrier metal deposition window is set inside the PN junction type voltage divider ring, and the voltage divider ring width is 9 μm; In step S4, the thickness of the Schottky barrier metal layer is 50 nm, and the thickness of the front electrode metal layer is 9 μm; In step S6, the thickness of SiO2 is 500nm and the thickness of Si3N4 is 30nm; The thickness of Al2O3 in step S7 is 20 nm.

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