Device structure for improving saturation current stability of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and preparation method thereof
By forming specific ion implantation and epitaxial structures in SiC MOSFET devices, the problem of current increase caused by the short channel effect is solved, the current stability and short-circuit resistance at high drain voltage are improved, and the increase in on-resistance is avoided.
Patent Information
- Application Number
- CN202510590207.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-09-05
AI Technical Summary
In existing SiC MOSFET devices, under the short-channel effect, the increase in drain voltage leads to a decrease in threshold voltage, resulting in an increase in current, which affects the device's short-circuit withstand capability and overcurrent detection. Existing methods often increase on-resistance when reducing short-circuit saturation current or fail to effectively suppress current at high temperatures.
Through multiple ion implantations, structures such as the P-bottom region, N-bottom region, Pwell region, JFET region and current extension layer are formed. Combined with a highly doped substrate and multiple epitaxial processes, a device structure that shields the drain side potential is formed, compensating for the decrease in the potential at the left end point of the channel, increasing the electron density and enhancing the stability of the saturation current.
Without increasing the on-resistance, the saturation current at high drain voltage is effectively reduced, the short-circuit tolerance and overcurrent detection of the device are enhanced, and the current stability is ensured not to be affected by high temperature.
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Figure CN120603281A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor devices, and in particular relates to a device structure for improving the saturation current stability of a SiC MOSFET and a preparation method thereof. Background Art
[0002] Currently, SiC MOSFET is a widely used and commercialized SiC power device. As a third-generation wide bandgap power semiconductor device, it has the advantages of fast switching speed, low on-resistance, high breakdown voltage, and high thermal conductivity. It is widely used in the field of power electronics and is expected to replace Si IGBT as a new generation of high-power switching devices. Since the industrialization of SiC MOSFET, in order to reduce the on-resistance, the channel length of SiC MOSFET has been designed to be shorter and shorter. However, due to the shorter channel, the short channel effect is easily generated: as the drain voltage increases, the potential barrier at the channel will decrease, causing the threshold voltage of the device to decrease. During the application of the device, the gate voltage often does not adjust with the drain voltage. Therefore, as can be seen from Equation (1), as the threshold voltage decreases, the current will continue to increase. This is not only not conducive to the short-circuit resistance of the device, but also puts higher requirements on overcurrent detection.
[0003]
[0004] Therefore, it is of great significance to improve the stability of the saturation current and reduce its amplitude increasing with the drain voltage.
[0005] Existing solutions primarily focus on reducing the saturation current during short circuits, such as widening the injection window at the bottom of the pwell and utilizing the thin-diameter JFET at the bottom to create a good pinch-off effect. While such methods can effectively reduce the saturation current, they lack compensation for the current drop when the drain voltage is low, resulting in a significant drop in the current in the linear region and an increase in the on-resistance of the device. Another method involves etching oxidized polysilicon and then injecting impurities into the exposed substrate to form a channel extension, thereby increasing the channel length. This method also has the disadvantage of increasing the on-resistance of the device. Furthermore, since the resistance of the channel region decreases with increasing temperature, the current may not be ideally suppressed when operating at high temperatures. These methods all have adverse effects on the basic performance of the device. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide a device structure and a preparation method for improving the saturation current stability of SiC MOSFET, and through multiple epitaxial growth and ion implantation processes, effectively improve the saturation current stability of the device without sacrificing the on-resistance of the device as much as possible.
[0007] The present invention provides a device structure for improving the saturation current stability of SiC MOSFET, comprising a substrate, a drift layer, a gate oxide layer and gate polysilicon, a field oxide layer, a source and a drain; the drift layer comprises a first N-drift region and a second N-drift region; the first N-drift region is formed by ion implantation to have a P-bottom region (p-type bottom region) and an N-bottom region (n-type bottom region); the second N-drift region is formed by ion implantation to have a Pwell region (p-type base region), a JFET region (junction field effect transistor region) and a current spreading layer (CSL layer); the Pwell region is formed by ion implantation to have a Pplus region (p+ type region) and an Nplus region (n+ type region).
[0008] Preferably, the substrate is a highly doped substrate, and the doping element includes N.
[0009] Preferably, the source is located in the gate oxide layer, and the source metal penetrates the pplus region and connects to the P-bottom region.
[0010] Preferably, the back side of the substrate is connected to the drain.
[0011] Preferably, the field oxide layer comprises silicon dioxide.
[0012] Preferably, the jfet region is connected to a current spreading layer structure, wherein the jfet region is separated by a pwell region, and the current spreading layer is located below the pwell region.
[0013] Preferably, the device structure is a tetragonal cell arrangement structure.
[0014] The present invention provides a method for preparing a device structure for improving the saturation current stability of a SiC MOSFET, comprising the following steps:
[0015] S1. Growing a first N-drift region on a highly doped substrate;
[0016] S2. A P-bottom region and an N-bottom region are formed on the first N-drift region by ion implantation;
[0017] S3. epitaxially growing the first N-drift region to form a second N-drift region;
[0018] S4. A pwell region, a jfet region, and a current expansion layer are formed on the second N- drift region by ion implantation;
[0019] S5. forming a pplus region and an nplus region on the pwell region by ion implantation;
[0020] S6. After annealing, high-temperature oxidation is performed to form a gate oxide layer and gate polysilicon is deposited;
[0021] S7. depositing a field oxide layer on the gate oxide layer;
[0022] S8. Etching silicon dioxide to form a source window, and etching the substrate to form a through hole connecting the P-bottom region;
[0023] S9. Depositing ohmic contact metal to fill the through hole and form a source;
[0024] S10. Depositing metal on the back side of the substrate to form a drain electrode, and finally obtaining a device structure that improves the saturation current stability of the SiC MOSFET.
[0025] Preferably, the ion implantation method for forming the pwell region in step S4 or the pplus region in step S5 is a U-shaped implantation.
[0026] Preferably, the through hole connecting the p-bottom region in step S8 is located at the ion implantation gap.
[0027] The device structure prepared by the present invention is as follows Figure 2 As shown in the figure, if a high voltage is applied to the drain end, the grounded P-bottom layer can shield the potential on the drain side, causing the potential at the left end of the channel, A, to drop significantly, resulting in a decrease in the saturation current. The higher the voltage applied to the drain end, the more obvious the potential shielding effect is, and the more the saturation current drops. Compared with the device without the N-bottom layer, the device with the N-bottom layer has a larger current flow path along the BC line (the current flow path here after normal opening is as shown in the figure). Figure 1 The electron density in the N-bottom layer (shown by the dashed line) can be significantly increased. When the voltage applied to the drain is low, the increased electron density in the N-bottom layer compensates for the slight decrease in the left-end channel potential A caused by the P-bottom layer, thereby preventing the degradation of the on-current in the linear region. The overall Id-Vd variation trend effectively improves the device's saturation current stability without increasing the on-resistance.
[0028] Beneficial effects
[0029] (1) The device structure of the present invention is of great significance to SiC MOSFET in that it reduces the saturation current at high drain voltage without degrading the linear region current and on-resistance.
[0030] (2) The reduction of saturation current in the present invention can enhance the ability to predict short circuits and reduce the requirements for overcurrent detection without affecting the basic performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 This is a cell arrangement diagram of the device structure for improving the saturation current stability of SiC MOSFET in the present invention.
[0032] Figure 2 A three-dimensional structural diagram of a device structure for improving the saturation current smoothness of a SiC MOSFET according to an embodiment of the present invention.
[0033] Figure numerals: 1-substrate, 2-first N-drift region, 3-P-bottom region, 4-N-bottom region, 5-second N-drift region, 6-pwell region, 7-jfet region, 8-current spreading layer, 9-nplus region, 10-pplus region, 11-gate oxide layer, 12-gate polysilicon, 13-field oxide layer, 14-source, 15-drain. DETAILED DESCRIPTION
[0034] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.
[0035] Example
[0036] In this embodiment, the device structure for improving the saturation current stability of SiC MOSFET is arranged in a tetragonal cell, such as Figure 1 As shown, the three-dimensional structure diagram is as follows Figure 2 As shown, it includes a SiC substrate 1, a drift layer, a gate oxide layer 11 and a gate polysilicon 12, a field oxide layer 13, a source 14 and a drain 15; the drift layer includes a first N-drift region 2 and a second N-drift region 5; the first N-drift region 2 is formed with a P-bottom region 3 and an N-bottom region 4 by ion implantation; the second N-drift region 5 is formed with a pwell region 6, a jfet region 7 and a current spreading layer 8 by ion implantation; the pwell region 6 is formed with a pplus region 9 and an nplus region 10 by ion implantation.
[0037] The method for preparing the device structure in this embodiment includes the following steps:
[0038] S1. A first N-drift region 2 is grown on a highly N-doped SiC substrate 1;
[0039] S2. A P-bottom region 3 is formed on the first N-drift region 2 by Al ion implantation, and an N-bottom region 4 is formed by N ion implantation;
[0040] S3. Epitaxially growing the first N-drift region 2 to form a second N-drift region 5;
[0041] S4. On the second N-drift region 5, a pwell region 6 is formed by Al ion back-shaped implantation, and a jfet region 7 and a current expansion layer 8 are formed by N ion implantation;
[0042] S5. Al ion back-shaped implantation is performed on the pwell region 6 to form a pplus region 9, and N ion implantation is performed to form an nplus region 10;
[0043] S6. After annealing, high temperature oxidation is performed to form a gate oxide layer 11 and gate polysilicon 12 is deposited;
[0044] S7. A silicon dioxide field oxide layer 13 is deposited on the gate oxide layer 11;
[0045] S8. Etching the gate oxide layer 11 and the field oxide layer 13 to form a source window, and etching the SiC substrate 1 to form a through hole connecting the p-bottom region 3;
[0046] S9. Depositing ohmic contact metal to fill the through hole and form the source 14;
[0047] S10. Depositing metal on the back side of the SiC substrate 1 to form a drain 15 , and finally obtaining a device structure that improves the saturation current stability of the SiC MOSFET.
Claims
1. A device structure for improving the saturation current stability of SiC MOSFET, characterized in that: It includes a substrate, a drift layer, a gate oxide layer and gate polysilicon, a field oxide layer, a source and a drain; the drift layer includes a first N-drift region and a second N-drift region; the first N-drift region is formed with a P-bottom region and an N-bottom region by ion implantation; the second N-drift region is formed with a Pwell region, a JFET region and a current spreading layer by ion implantation; the Pwell region is formed with a Pplus region and an Nplus region by ion implantation.
2. The device structure for improving the saturation current stability of SiC MOSFET according to claim 1, characterized in that: The substrate is a highly doped substrate, and the doping elements include N.
3. The device structure for improving the saturation current stability of SiC MOSFET according to claim 1, characterized in that: The source metal penetrates the pplus region and connects to the P-bottom region.
4. The device structure for improving the saturation current stability of SiC MOSFET according to claim 1, characterized in that: The back side of the substrate is connected to the drain.
5. The device structure for improving the saturation current stability of SiC MOSFET according to claim 1, characterized in that: The field oxide layer includes silicon dioxide.
6. The device structure for improving the saturation current stability of SiC MOSFET according to claim 1, characterized in that: The jfet region is connected to a current spreading layer structure, wherein the jfet region is separated by a pwell region, and the current spreading layer is located below the pwell region.
7. The device structure for improving the saturation current stability of SiC MOSFET according to claim 1, characterized in that: The device structure is a tetragonal cell arrangement structure.
8. A method for preparing a device structure for improving the saturation current stability of a SiC MOSFET, comprising the following steps: S1. epitaxially growing a first N-drift region on the substrate; S2. A P-bottom region and an N-bottom region are formed on the first N-drift region by ion implantation; S3. epitaxially growing the first N-drift region to form a second N-drift region; S4. A pwell region, a jfet region, and a current expansion layer are formed on the second N- drift region by ion implantation; S5. forming a pplus region and an nplus region on the pwell region by ion implantation; S6. After annealing, high-temperature oxidation is performed to form a gate oxide layer and gate polysilicon is deposited; S7. depositing a field oxide layer on the gate oxide layer; S8. Etching the gate oxide layer and the field oxide layer to form a source window, and etching the substrate to form a through hole connecting the P-bottom region; S9. Depositing ohmic contact metal to fill the through hole and form a source; S10. Depositing metal on the back side of the substrate to form a drain electrode, and finally obtaining a device structure that improves the saturation current stability of the SiC MOSFET.
9. The method for preparing a device structure for improving the saturation current stability of SiC MOSFET according to claim 8, characterized in that: The ion implantation method for forming the pwell region in step S4 or the pplus region in step S5 is a U-shaped implantation.
10. The method for preparing a device structure for improving the saturation current stability of SiC MOSFET according to claim 8, characterized in that: The through hole connecting the p-bottom region in step S8 is located at the ion implantation gap.