Semiconductor device, preparation method, packaging structure and electronic equipment
By inserting an insulating layer between the ionization region of the semiconductor device and the metal layer, forming a MIS structure, the problems of high source and drain voltage and high power consumption of the semiconductor device are solved, and a lower sub-threshold swing and higher current efficiency are achieved.
Patent Information
- Application Number
- CN202410235152.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-09-05
AI Technical Summary
Existing low-power semiconductor devices such as ionization transistors require high source and drain voltages, resulting in high power consumption and large sub-threshold swing, which is difficult to effectively solve in the prior art.
Insulating layers are inserted between the ionization region of the semiconductor device and the metal layer to form a metal-insulator-semiconductor structure, avoiding direct contact between metal and semiconductor, reducing the induced energy gap state of metal, eliminating the Fermi level pinning effect, and reducing subthreshold swing and power consumption.
By inserting the insulating layer, the source and drain voltage and power consumption of the semiconductor device are reduced, the switching characteristics are improved, the leakage current is reduced, and the sub-threshold swing and higher current efficiency are achieved.
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Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method, a packaging structure, and an electronic device. Background Art
[0002] With the continuous development of technology, higher demands are being placed on the energy consumption and power of semiconductor devices. Existing low-power semiconductor devices include tunneling transistors, negative capacitance transistors, cold source transistors, and ionization transistors. Among them, ionization transistors can reduce subthreshold swing to save power, but require very high source-drain voltages. Summary of the Invention
[0003] Embodiments of the present application provide a semiconductor device and a manufacturing method, a packaging structure, and an electronic device for reducing the subthreshold swing and power consumption of the semiconductor device while reducing the source-drain voltage.
[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:
[0005] In a first aspect, a semiconductor device is provided. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer including a source region, an ionization region, and a channel region disposed between the source region and the ionization region; a gate metal layer disposed on the channel region; and a first insulating layer and a first metal layer stacked on the ionization region.
[0006] The semiconductor device in the embodiment of the present application includes a semiconductor layer disposed on a substrate, the semiconductor including a source region, an ionization region, and a channel region disposed between the source region and the ionization region, wherein the ionization region can also be regarded as the drain region of the semiconductor device. Considering that after the first metal layer contacts the semiconductor layer, metal-induced energy gap states will be generated at the interface, resulting in a Fermi level pinning effect. The embodiment of the present application also includes a first insulating layer and a first metal layer stacked on the ionization region. Therefore, by inserting the first insulating layer between the ionization region and the first metal layer to avoid direct contact between the first metal layer and the semiconductor layer, the metal-induced energy gap states MIGS are reduced or eliminated, the pinning effect is eliminated, and the subthreshold swing of the semiconductor device and the power consumption of the semiconductor device are reduced.
[0007] In a possible implementation manner, a second insulating layer and a second metal layer are further stacked on the source region.
[0008] In this embodiment, the second insulating layer and the first insulating layer are formed in the same step, and the second metal layer and the first metal layer are formed in the same step. Since there is no need to remove the second insulating layer and the second metal layer, the preparation process is simplified and the preparation cost is reduced.
[0009] In a possible implementation manner, the thickness of the first insulating layer is 0.2 nm-2 nm.
[0010] In this embodiment, although the first insulating layer provided between the first metal layer and the semiconductor layer can prevent subthreshold swing degradation caused by Fermi level pinning, the on-state current is somewhat reduced. Therefore, the on-state current can be adjusted by adjusting the thickness of the first insulating layer. This makes it easier for majority carriers to tunnel through the first insulating layer, reducing the impact of the first insulating layer on the on-state current.
[0011] In a possible implementation manner, the material of the first insulating layer includes at least one or more combinations of the following: ZnOx, TiOx, and SiOx.
[0012] In one possible implementation, the doping concentration of the ionization region is less than 1e16 cm-3, and the doping concentration of the channel region is 1e15 cm-3-1e20 cm-3.
[0013] In one possible implementation, the doping concentration of the source region is 1e19 cm-3-1e21 cm-3.
[0014] In a possible implementation, the semiconductor device further includes a gate insulating layer, and the gate insulating layer is disposed between the channel region and the gate metal layer.
[0015] In a possible implementation, the semiconductor device further includes a dielectric layer, and the dielectric layer is disposed on a sidewall of the gate metal layer.
[0016] In a possible implementation, the semiconductor device further includes an isolation layer, where the isolation layer covers the semiconductor layer, the first metal layer, and the gate metal layer.
[0017] In a possible implementation, the semiconductor device further includes a conductive structure, which penetrates the isolation layer and contacts the source region, the first metal layer, or the gate metal layer.
[0018] In one possible embodiment, the material of the first metal layer includes at least one or more of the following: Ti, Sc, Al, Au, Pt, Pd, or compounds thereof. Thus, the material of the first metal layer can be used to adjust the majority Schottky barrier height, thereby increasing the minority carrier field emission and thermal emission Schottky barriers.
[0019] In a second aspect, a method for fabricating a semiconductor device is provided. The method comprises: forming a semiconductor layer on a substrate; forming a source region, an ionization region, and a channel region disposed between the source region and the ionization region in the semiconductor layer; forming a gate metal layer on the channel region; and forming a first insulating layer and a first metal layer stacked on the ionization layer.
[0020] In one possible embodiment, forming a source region, an ionization region, and a channel region arranged between the source region and the ionization region in a semiconductor layer includes: injecting first doping ions into one side of the semiconductor layer to form a first doping region and an ionization region on one side of the semiconductor layer; injecting second doping ions into a side of the first doping region away from the ionization region to form a source region on a side of the first doping region away from the ionization region, and the remaining first doping region is a channel region.
[0021] In one possible embodiment, before forming the gate metal layer on the channel region, the preparation method further includes: forming a gate insulating layer covering the semiconductor layer; correspondingly, after forming the gate metal layer, the preparation method further includes: patterning the gate metal layer through a patterning process, and the patterned gate metal layer covers the channel region.
[0022] In a possible implementation, the preparation method further includes: forming an isolation layer covering the semiconductor layer, the first metal layer, and the gate metal layer.
[0023] In a third aspect, a chip packaging structure is provided, which includes a packaging substrate and the semiconductor device according to the first aspect and any possible embodiment thereof; the semiconductor device is electrically connected to the packaging substrate.
[0024] In a fourth aspect, an electronic device is provided, which includes a printed circuit board and the chip packaging structure provided in the third aspect; the chip packaging structure is electrically connected to the printed circuit board.
[0025] Among them, the technical effects brought about by any possible implementation of the second to fourth aspects can refer to the technical effects brought about by different implementations of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application;
[0027] Figure 2 A schematic diagram of the energy band structure of a semiconductor device provided in an embodiment of the present application;
[0028] Figure 3 A schematic structural diagram of a semiconductor device provided in yet another embodiment of the present application;
[0029] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
[0030] Figure 5 A schematic diagram of the energy band structure of a semiconductor device provided in an embodiment of the present application;
[0031] Figures 6-11A schematic diagram of the structure of a semiconductor device at various stages in the manufacturing process provided by another embodiment of the present application;
[0032] Figure 12 A schematic diagram of a switching characteristic curve of a semiconductor device provided in yet another embodiment of the present application;
[0033] Figure 13 A schematic structural diagram of a semiconductor device provided in yet another embodiment of the present application;
[0034] Figure 14 A schematic structural diagram of a semiconductor device provided in yet another embodiment of the present application;
[0035] Figure 15 A schematic diagram of the doping concentration of a semiconductor layer of a semiconductor device provided in yet another embodiment of the present application;
[0036] Figure 16 A schematic diagram of a transfer characteristic curve of a semiconductor device provided in yet another embodiment of the present application;
[0037] Figure 17 A schematic diagram of the energy band structure of a semiconductor device provided in yet another embodiment of the present application;
[0038] Figure 18 A schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;
[0039] Figure 19 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.
[0041] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0042] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0043] Considering that the ionization transistor adopts a PIN structure, it is necessary to use a strong electric field under a high reverse bias voltage to trigger the ionization to open, and the electrons and holes generated by the ionization provide the conduction current, so a very high source-drain voltage (Vds) is required. For this reason, the embodiment of the present application also provides a semiconductor device. Figure 1 As shown, the semiconductor device includes a substrate 10; a semiconductor layer 20, which is disposed on the substrate 10 and includes a source region 201, an ionization region 203, and a channel region 202 disposed between the source region 201 and the ionization region 203; and a gate metal layer 30, which is disposed on the channel region 202 and further includes a first metal layer 40 disposed on the ionization region 203. It will be understood that the semiconductor layer 20 and the first metal layer 40 form a metal-semiconductor (MS) structure. Exemplarily, the first metal layer 40 is a work function metal.
[0044] The semiconductor device in the embodiment of the present application includes a semiconductor layer 20 disposed on a substrate 10. The semiconductor layer 20 includes a source region 201, an ionization region 203, and a channel region 202 disposed between the source region 201 and the ionization region 203. The ionization region 203 can also be considered the drain region of the semiconductor device. To reduce the source-drain voltage of the semiconductor device, a first metal layer 40 is disposed on the ionization region 203. Therefore, by adjusting the metal work function of the material of the first metal layer 40, a higher electric field is generated in the ionization region 203. The majority carriers injected through the electric field region of the ionization region 203 are ionized. The minority carriers generated by the ionization are swept into the channel region 202 by the strong electric field of the ionization region, thereby lowering the majority carrier barrier. The lowered majority carrier barrier in the channel region 202 leads to a larger majority carrier current passing through the channel region 202 and the ionization region 203, generating stronger collision ionization and forming positive feedback, thereby making the switching of the semiconductor device steeper and significantly reducing the subthreshold swing. Since the semiconductor device can generate ionization by utilizing majority-carrying collisions, the source-drain voltage (Vds) can be reduced to 1.0V or below, which can further reduce the power consumption of the semiconductor device.
[0045] However, after the first metal layer 40 contacts the semiconductor layer 20, metal-induced gap states (MIGS) will be generated, that is, Fermi level pinning will occur, resulting in the metal work function effect being shielded by the interface charge energy level, reducing the regulating effect of the work function metal on the semiconductor layer 20, and causing greater leakage and degraded steep switching characteristics.
[0046] Specifically, refer to Figure 2The energy band structure diagram of a semiconductor device is shown, in which, in semiconductor layer 20, electron current flows from source region 201 to ionization region 203, and hole current flows from ionization region 203 to source region 201. Taking an n-type semiconductor device as an example, when the first metal layer 40 is a metal with a moderate work function, the ability of the first metal layer 40 to form a strong electric field is relatively weak. Therefore, the first metal layer 40 is typically a metal with a low work function to enhance the electric field. Under ideal conditions, Fermi level pinning does not occur in semiconductor devices. Therefore, the metal-semiconductor contact barrier of the semiconductor device is determined by the semiconductor affinity and the metal work function. In other words, the electron Schottky barrier of the semiconductor device is small, while the hole Schottky barrier is large, which is conducive to enhancing the electric field in the ionization region when ionization is turned on. However, due to the Fermi level pinning phenomenon in semiconductor devices under actual circumstances, the influence of the metal work function of the semiconductor device on the gold-semiconductor contact barrier is shielded by the interface charge energy level and weakened, that is, the electron Schottky barrier of the semiconductor device becomes larger and the hole Schottky barrier becomes smaller, which leads to the weakening of hole injection and positive feedback, resulting in greater leakage and degraded steep switching characteristics.
[0047] To this end, the present application also provides a semiconductor device. Figure 3 As shown, the semiconductor device includes a substrate 10; a semiconductor layer 20, which is disposed on the substrate 10 and includes a source region 201, an ionization region 203, and a channel region 202 disposed between the source region 201 and the ionization region 203; a gate metal layer 30, which is disposed on the channel region 202; and a first insulating layer 50 and a first metal layer 40 stacked on the ionization region 203. It will be understood that the semiconductor layer 20, the first insulating layer 50, and the first metal layer 40 constitute a metal-insulator-semiconductor (MIS) structure.
[0048] In a specific embodiment, Figure 4 As shown, the process of forming the above-mentioned semiconductor device includes: S11: forming a semiconductor layer 20 on a substrate 10; S21: forming a source region 201, an ionization region 203, and a channel region 202 arranged between the source region 201 and the ionization region 203 in the semiconductor layer 20; S31: forming a gate metal layer 30 on the channel region 202; S41: forming a first insulating layer 50 and a first metal layer 40 stacked on the ionization layer.
[0049] The semiconductor device in the embodiment of the present application includes a semiconductor layer 20 provided on a substrate 10, and the semiconductor layer 20 includes a source region 201, an ionization region 203, and a channel region 202 provided between the source region 201 and the ionization region 203, wherein the ionization region 203 can also be regarded as the drain region of the semiconductor device. Considering that the first metal layer 40 will generate a metal-induced energy gap state after contacting the semiconductor layer 20. The embodiment of the present application also includes a first insulating layer 50 and a first metal layer 40 stacked on the ionization region 203. Therefore, by inserting the first insulating layer 50 between the ionization region 203 and the first metal layer 40 to avoid direct contact between the first metal layer 40 and the semiconductor layer 20, the metal-induced energy gap state is reduced or eliminated, the pinning effect is eliminated, the subthreshold swing (SS) of the semiconductor device is reduced, and the power consumption of the semiconductor device is reduced.
[0050] Specifically, refer to Figure 5 The energy band structure diagram of the semiconductor device shown is shown, wherein in the semiconductor layer 20, the electron current flows from the source region 201 to the ionization region 203, and the hole current flows from the ionization region 203 to the source region 201. Taking an n-type semiconductor device as an example, the barrier energy of the semiconductor device provided by the embodiment of the present application can be adjusted by the metal work function, that is, the electron Schottky barrier of the semiconductor device is small, and the hole Schottky barrier is large. It can be seen from this that the semiconductor device provided by the embodiment of the present application can eliminate the Fermi level pinning phenomenon by providing the first insulating layer 50, form a stronger electric field in the ionization region to enhance positive feedback, and produce steep switching characteristics to reduce the power consumption of the semiconductor device.
[0051] In an optional embodiment, the manufacturing process of the semiconductor device and the device structure formed during the manufacturing process are described in detail below.
[0052] S11 : forming a semiconductor layer 20 on the substrate 10 .
[0053] For example, Figure 6 As shown, a semiconductor layer 20 is formed on a substrate 10 by a deposition process. The deposition process may be a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process, or other suitable processes.
[0054] The materials of the substrate 10 and the semiconductor layer 20 can both be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 10 and the semiconductor layer 20 can include one or more combinations of materials such as silicon, germanium, and III-V semiconductors. In some embodiments, the substrate 10 and the semiconductor layer 20 are made of compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 10 and the semiconductor layer 20 are made of alloys or multi-component compounds, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. It will be understood that the material of the substrate 10 and the material of the semiconductor layer 20 can be the same or different.
[0055] It is understandable that, in some optional examples, a buried oxide layer (BOX) may be further provided between the substrate 10 and the semiconductor layer 20 , whereby the stacked substrate 10 , the buried oxide layer and the semiconductor layer 20 constitute silicon on insulator (SOI).
[0056] S21 : forming a source region 201 , an ionization region 203 , and a channel region 202 disposed between the source region 201 and the ionization region 203 in the semiconductor layer 20 .
[0057] Furthermore, the above S21 includes the following steps:
[0058] S22 : implanting first doping ions into one side of the semiconductor layer 20 to form a first doping region 204 and an ionized region 203 on one side of the semiconductor layer 20 .
[0059] For example, when the semiconductor device is an N-type semiconductor device, the first doping ion may be a P-type ion doping material, and the P-type ion doping material may be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. In some examples of the embodiments of the present application, boron (B) ions may be used as the first doping ion implanted into one side of the semiconductor layer 20, such that Figure 7 As shown in FIG. 1 , a first doped region 204 and an ionized region 203 are formed on one side of the semiconductor layer 20 .
[0060] When the semiconductor device is a P-type semiconductor device, the first impurity ion doping material may be an N-type ion doping material, and the N-type ion doping material may be at least one of phosphorus (P), As, PHx+ and / or P2Hx+ (x=1, 2, 3...) or a combination thereof. In some examples of the embodiments of the present application, phosphorus (P) ions may be used as the first doping ion implanted into one side of the semiconductor layer 20, such as Figure 7 As shown in FIG. 1 , a first doped region 204 and an ionized region 203 are formed on one side of the semiconductor layer 20 .
[0061] S23 : implanting second doping ions into a side of the first doping region 204 away from the ionized region 203 to form a source region 201 on the side of the first doping region 204 away from the ionized region 203 , and the remaining first doping region 204 is the channel region 202 .
[0062] Exemplarily, when the semiconductor device is an N-type semiconductor device, the second impurity ion doping material may be an N-type ion heavily doped material, and the N-type ion heavily doped material may be at least one of phosphorus (P), As, PHx+ and / or P2Hx+ (x=1, 2, 3...) or a combination thereof. In some examples of the embodiments of the present application, phosphorus (P) ions may be used as the second doping ions to be implanted into the side of the first doping region 204 away from the ionization region 203, forming a source region 201 on the side of the first doping region 204 away from the ionization region 203, and the remaining first doping region 204 is the channel region 202. Thus, as Figure 7 As shown in (2) in FIG. 1 , an N++ / P / I structure is formed in the semiconductor layer 20 .
[0063] When the semiconductor device is a P-type semiconductor device, the second doping ion can be a P-type ion heavily doped material, and the P-type ion heavily doped material can be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. In some examples of the present invention, boron (B) ions can be used as the second doping ion implanted into the side of the first doping region 204 away from the ionization region 203, forming the source region 201 on the side of the first doping region 204 away from the ionization region 203, and the remaining first doping region 204 serves as the channel region 202. Thus, a P++ / N / I structure is formed in the semiconductor layer 20.
[0064] Because the concentrations of the first dopant ion and the second dopant ion are different, the doping concentrations of the source region 201, the ionization region 203, and the channel region 202 are all different. In some optional examples, the doping concentration of the ionization region 203 is less than 1e16 cm-3, the doping concentration of the channel region 202 is 1e15 cm-3-1e20 cm-3, and the doping concentration of the source region 201 is 1e19 cm-3-1e21 cm-3.
[0065] S30 : forming a gate insulating layer 31 on the semiconductor layer 20 .
[0066] In some optional embodiments, such as Figure 8As shown, the gate insulating layer 31 can be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), or plasma enhanced chemical vapor deposition (PECVD). The gate insulating layer 31 is made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), HfO2, and other dielectric materials, alone or in combination.
[0067] S31 : forming a gate metal layer 30 on the channel region 202 .
[0068] In this embodiment, if Figure 9 As shown, a gate metal layer 30 can be formed on the gate insulating layer 31 by a patterning process. Exemplarily, the patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.
[0069] It should be noted that the gate metal layer 30 provided in the embodiment of the present application can just completely cover the channel region 202, that is, the projection of the gate metal layer 30 on the substrate 10 basically coincides with the projection of the channel region 202 on the substrate 10. The gate metal layer 30 can also cover part of the source region 201 and the ionization region 203 while covering the channel region 202. The embodiment of the present application does not limit the coverage range of the gate metal layer 30.
[0070] In some optional embodiments, after forming the patterned gate metal layer 30 , the gate insulation layer 31 may be further patterned.
[0071] S32 : forming a dielectric layer 32 , wherein the dielectric layer 32 is disposed on a sidewall of the gate metal layer 30 .
[0072] In this embodiment, a dielectric material may be deposited on the gate insulating layer 31 by a deposition process, and then a portion of the dielectric material may be removed by an etching process to form a gate insulating layer 31. Figure 10The sidewalls of the gate metal layer 30 are shown covered. The etching process can be a dry etching process, which includes using an etching gas such as carbon tetrafluoride (CF4), argon (Ar), nitrogen trifluoride (NF3), chlorine (Cl2), helium (He), hydrogen bromide (HBr), oxygen (O2), nitrogen (N2), fluoromethane (CH3F), methane (CH4), difluoromethane (CH2F2) or a combination thereof.
[0073] S41: forming a first insulating layer 50 and a first metal layer 40 stacked on the ionization layer.
[0074] For example, the stacked first insulating layer 50 and the first metal layer 40 are formed as follows: Figure 11 As shown in (1), the distance between the ionization region 203 covered by the first insulating layer 50 and the channel region 202 is 10-100 nm. That is, neither the first metal layer 40 nor the first insulating layer 50 is in contact with the channel region 202. The first insulating layer 50 includes an insulating material and a wide bandgap semiconductor. For example, the material of the first insulating layer includes at least one or more of the following combinations: ZnOx, TiOx, SiOx. The material of the first metal layer 40 is a work function metal, which can effectively adjust the height of the majority carrier Schottky barrier and increase the minority carrier field emission and thermal emission Schottky barriers. Exemplarily, the material of the first metal layer 40 includes at least one or more of the following combinations: Ti, Sc, Al, Au, Pt, Pd or their compounds.
[0075] In the examples of this application, refer to Figure 12 and Table 1, affected by the Fermi level pinning, Figure 1 The subthreshold swing of the semiconductor device shown degenerates from 31mV / dec in the ideal state to 124mV / dec. When the work function (WF) and source-drain voltage (Vds) of the first metal layer 40 remain unchanged, the degradation of the subthreshold swing (SS) caused by Fermi level pinning can be avoided by providing a first insulating layer 50 between the first metal layer 40 and the semiconductor layer 20. The subthreshold swing (SS) is restored to about 31mV / dec, but the on-state current (Ion) will be reduced to a certain extent. To this end, the on-state current can be adjusted by adjusting the thickness Tins of the first insulating layer 50. As the thickness of the first insulating layer 50 decreases, the on-state current of the semiconductor device provided in this embodiment also increases. Therefore, in some optional embodiments, the thickness of the first insulating layer 50 is 0.2nm-2nm. This makes it easier for the majority carriers to tunnel through the first oxide layer, reducing the influence of the first oxide layer on the on-state current.
[0076] Table 1
[0077]
[0078] It is understood that, in some embodiments, while forming the first insulating layer 50 and the first metal layer 40, a stacked second insulating layer 51 and a second metal layer 41 are also formed on the source region 201. In order to save process and reduce manufacturing cost, in some optional embodiments, the stacked second insulating layer 51 and the second metal layer 41 can be retained, that is, the structure of the semiconductor device is as follows: Figure 11 Alternatively, in order to further increase the on-state current (Ion) of the semiconductor device, the second insulating layer 51 and the second metal layer 41 can be removed, leaving only the first insulating layer 50 and the first metal layer 40, that is, the structure of the semiconductor device is as shown in FIG. Figure 11 As shown in (1).
[0079] S51 : forming an isolation layer 60 covering the semiconductor layer 20 , the first metal layer 40 and the gate metal layer 30 .
[0080] In some embodiments, as Figure 13 As shown, after the isolation layer 60 is formed, the isolation layer 60 may be planarized by a chemical mechanical polishing (CMP) process.
[0081] It can be understood that the first metal layer 40 and the first insulating layer 50 in the embodiment of the present application can be in contact with the dielectric layer 32, or the first metal layer 40 and the first insulating layer 50 can be separated from the dielectric layer 32 by the isolation layer 60, and the present application does not impose any restrictions.
[0082] S52 : forming at least one groove in the isolation layer 60 that penetrates the isolation layer 60 .
[0083] S53 : depositing a conductive material in the groove to form a conductive structure 61 .
[0084] like Figure 14 As shown, there may be multiple conductive structures 61. One of the conductive structures 61 may be a source electrode, i.e., the source electrode penetrates the isolation layer 60 and contacts the source region 201; or one of the conductive structures 61 may be a drain electrode, i.e., the drain electrode penetrates the isolation layer 60 and contacts the ionized region 203; or one of the conductive structures 61 may be a gate electrode, i.e., the gate electrode penetrates the isolation layer 60 and contacts the gate metal layer 30.
[0085] The semiconductor device provided in the embodiment of the present application includes a substrate 10; a semiconductor layer 20, the semiconductor layer 20 is disposed on the substrate 10, and the semiconductor layer 20 includes a source region 201, an ionized region 203, and a channel region 202 disposed between the source region 201 and the ionized region 203; the doping concentrations of the source region (Source) 201, the channel region (Channel) 202, and the ionized region (Intrinsic) 203 in the semiconductor layer 20 are as follows: Figure 15 As shown. A gate insulating layer 31 and a gate metal layer 30 are also provided on the channel region 202, and the gate metal layer 30 is provided on the gate insulating layer 31; a dielectric layer 32 is provided on the sidewall of the gate metal layer 30, and a first insulating layer 50 and a first metal layer 40 are further stacked on the ionization region 203. It can be understood that the semiconductor layer 20, the first insulating layer 50 and the first metal layer 40 constitute a metal-insulator-semiconductor (MIS) structure. An isolation layer 60 covers the semiconductor layer 20, the first metal layer 40 and the gate metal layer 30. A conductive structure 61 penetrates the isolation layer 60 and contacts the source region 201, the first metal layer 40 or the gate metal layer 30.
[0086] See also Figure 16 The transfer output characteristic curve diagram is shown in FIG. , wherein pinnings = 1 means that there is no Fermi level pinning phenomenon in the semiconductor device, and the smaller the pinnings value, the stronger the Fermi level pinning. Figure 1 The device shown exhibits Fermi level pinning. As the Fermi level pinning effect increases, the off-state leakage current of the semiconductor device also increases. However, because the semiconductor device provided by the embodiment of the present application inserts the first insulating layer 50 between the ionized region 203 and the first metal layer 40, direct contact between the first metal layer 40 and the semiconductor layer 20 is avoided, eliminating the Fermi level pinning effect. Therefore, the off-state leakage current of the semiconductor device can be reduced, further reducing the power consumption and energy consumption of the device, and improving the efficiency of the device.
[0087] See also Figure 17 The energy band structure diagram shown in FIG. 1 , wherein pinnings = 1 means that there is no Fermi level pinning phenomenon in the semiconductor device. The smaller the pinnings value, the stronger the Fermi level pinning. Figure 1The device shown has a Fermi level pinning phenomenon. As the Fermi level pinning effect increases, the ability of the metal work function of the semiconductor device to adjust the ionization region band bending weakens, so the electron Schottky barrier becomes larger and the hole Schottky barrier becomes smaller. However, since the semiconductor device provided by the embodiment of the present application adopts an MIS structure, that is, a first insulating layer 50 is inserted between the ionization region 203 and the first metal layer 40, the Fermi level pinning effect is eliminated, and the switching characteristics of the semiconductor device provided by this embodiment are close to those under ideal conditions. Figure 1 The switching characteristics of the semiconductor device shown have a relatively low subthreshold swing, which enables the first metal layer 40 to more significantly adjust the steep switching characteristics, thereby reducing the power consumption of the semiconductor device.
[0088] It is worth noting that the semiconductor device proposed in the embodiment of the present invention is not limited to the specific structure formed by the preparation method of the above embodiment of the present application, and the specific structure of the semiconductor device can also be formed by other processing techniques by those skilled in the art. The semiconductor device in the embodiment of the present application can be a planar device, or a three-dimensional structure such as a fin field-effect transistor (FinFET), a horizontal structure all-around gate transistor (GAAFET) or a vertical structure GAAFET, and the embodiment of the present application does not impose any restrictions.
[0089] The embodiment of the present application also provides a chip packaging structure 300. Figure 18 As shown, the chip packaging structure 300 includes a semiconductor device 100 and a packaging substrate 200 , and the semiconductor device 100 is electrically connected to the packaging substrate 200 .
[0090] In some embodiments, the chip package structure 300 may further include micro bumps (micro bumps, ubumps) 210, and the package substrate may be electrically connected to the semiconductor device 100 via a plurality of micro bumps 210. In addition, in some embodiments, such as Figure 18 As shown, the electronic device may further include a connector 220 ; the package substrate 200 in the chip package structure is electrically connected to other electronic devices, such as a printed circuit board, via the connector 220 . This enables communication between the semiconductor device 100 and other electronic devices. The connector 220 may be a solder ball or a microbump.
[0091] The semiconductor device according to the embodiment of the present application can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (for example, other forms of transistors, etc.), electrically connecting them with a printed circuit board, and thus constructing an electronic device. Therefore, the embodiment of the present application also provides an electronic device, such as Figure 19 As shown, the electronic device may include the chip packaging structure 300 and printed circuit board (PCB) 400 provided in the above embodiment. The electronic device may include a CMOS image sensor, NAND flash memory, high-bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and other electronic products. The embodiments of the present application do not impose any special restrictions on the specific form of the above electronic device.
[0092] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.
Claims
1. A semiconductor device, characterized in that: include: substrate; a semiconductor layer, the semiconductor layer being disposed on the substrate, the semiconductor layer comprising a source region, an ionization region, and a channel region disposed between the source region and the ionization region; a gate metal layer, the gate metal layer being disposed on the channel region; A first insulating layer and a first metal layer are stacked on the ionization region.
2. The semiconductor device according to claim 1, wherein A second insulating layer and a second metal layer are stacked on the source region.
3. The semiconductor device according to claim 1 or 2, wherein: The thickness of the first insulating layer is 0.2 nm-2 nm.
4. The semiconductor device according to any one of claims 1 to 3, wherein: The material of the first insulating layer includes at least one or more of the following combinations: ZnOx, TiOx, and SiOx.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that The doping concentration of the ionization region is less than 1e16 cm -3 The doping concentration of the channel region is 1e15 cm -3 -1e20 cm -3 .
6. The semiconductor device according to any one of claims 1 to 5, characterized in that The doping concentration of the source region is 1e19 cm -3 -1e21cm -3 .
7. The semiconductor device according to any one of claims 1 to 6, characterized in that The semiconductor device further includes a gate insulating layer disposed between the channel region and the gate metal layer.
8. The semiconductor device according to any one of claims 1 to 7, wherein: The semiconductor device further includes a dielectric layer, which is arranged on a sidewall of the gate metal layer.
9. The semiconductor device according to any one of claims 1 to 8, wherein: The semiconductor device further includes an isolation layer covering the semiconductor layer, the first metal layer and the gate metal layer.
10. The semiconductor device according to claim 9, wherein The semiconductor device further includes a conductive structure, which penetrates the isolation layer and contacts the source region, the first metal layer or the gate metal layer.
11. The semiconductor device according to any one of claims 1 to 10, wherein: The material of the first metal layer includes at least one or more of the following combinations: Ti, Sc, Al, Au, Pt, Pd or compounds thereof.
12. A method for preparing a semiconductor device, characterized in that: include: forming a semiconductor layer on a substrate; forming a source region, an ionization region, and a channel region disposed between the source region and the ionization region in the semiconductor layer; forming a gate metal layer on the channel region; A first insulating layer and a first metal layer are stacked and formed on the ionization region.
13. The method according to claim 12, characterized in that Forming a source region, an ionization region, and a channel region disposed between the source region and the ionization region in the semiconductor layer includes: Implanting first dopant ions into one side of the semiconductor layer to form a first doping region and the ionized region on the one side of the semiconductor layer; Second doping ions are implanted into a side of the first doping region away from the ionization region to form a source region on the side of the first doping region away from the ionization region, and the remaining first doping region is a channel region.
14. The method according to claim 12 or 13, characterized in that Before forming a gate metal layer on the channel region, the preparation method further includes: forming a gate insulating layer covering the semiconductor layer; Accordingly, after forming the gate metal layer, the preparation method further includes: The gate metal layer is patterned through a patterning process, and the patterned gate metal layer covers the channel region.
15. The method according to any one of claims 12 to 14, characterized in that The preparation method further comprises: An isolation layer is formed covering the semiconductor layer, the first metal layer and the gate metal layer.
16. A chip packaging structure, characterized in that: The invention comprises a packaging substrate and a semiconductor device according to any one of claims 1 to 11; the semiconductor device is electrically connected to the packaging substrate.
17. An electronic device, characterized in that: The device comprises a printed circuit board and a chip packaging structure as claimed in claim 16; the chip packaging structure is electrically connected to the printed circuit board.