Low-stress packaging method and product thereof

Abstract

The invention discloses a low-stress packaging method and structure. The low-stress packaging method comprises the following steps: manufacturing a polyimide refraction film layer on glass; forming a cofferdam structure on the polyimide refraction film layer; mounting a chip; manufacturing a through hole structure on the chip; manufacturing a passivation layer and an insulating layer on the chip, and arranging a gasket on the surface of the insulating layer; manufacturing an RDL circuit layer; coating a solder mask layer on the RDL layer; and carrying out ball mounting and cutting to finish packaging. The film layer formed by adopting the atomic layer deposition technology has high flatness, high uniformity and high density, can effectively improve the number of light rays reaching a photosensitive area of the chip, enhances the capability of the chip for converting an optical signal into an electric signal, meets the anti-reflection requirement of optical resin glass, and improves the yield of the optical resin glass. The method can effectively improve the problem of generation of film mechanical performance stress such as hole bottom Oxide fracture caused by the traditional chemical deposition technology, and can effectively disperse the interface stress and reduce the problem of passivation layer crake by bonding the gasket on the surface of the insulating layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a low-stress packaging method and a product thereof. Background Art

[0002] With the advancement of semiconductor technology, electronic components are moving towards miniaturization, high frequency, and multifunctionality. Image sensors, particularly CIS (CMOS Image Sensor), utilize the photoelectric conversion function of optoelectronic devices to convert the light image on a photosensitive surface into an electrical signal proportional to the light image. Compared to point-light-source light sensors such as photodiodes and phototransistors, image sensors are functional devices that divide the light image on their photosensitive surface into many small units and convert them into usable electrical signals. Image sensors are categorized as photoconductive tubes and solid-state image sensors. Compared to photoconductive tubes, solid-state image sensors offer advantages such as small size, light weight, high integration, high resolution, low power consumption, long life, and low price, leading to their widespread application across various industries.

[0003] The Chinese utility model patent with publication number CN207052606U discloses a packaging structure for a CIS chip, which bonds a CIS wafer to a glass containing a cavity, and then uses TSV silicon through-via technology to form a circuit redistribution on the back of the Si, and then cuts it into a single package. For the CIS chip prepared using the above packaging technology, when the light reaches the glass surface with non-vertical incidence, that is, it has a certain incident angle, the light will be refracted when passing through the glass, and the effective amount of light that finally reaches the photosensitive area of ​​the CIS chip will be reduced, thereby affecting the ability of the CIS chip to convert optical signals into electrical signals, that is, the signal conversion ability of the CIS chip will be weakened. Therefore, how to effectively enhance the ability of the CIS chip to convert optical signals into electrical signals is gradually becoming a hot topic in the research of CIS chip packaging technology.

[0004] In the TSV industry process, chemically deposited silicon dioxide and silicon nitride are commonly used for thermal insulation and water vapor protection. However, the current chemical deposition has poor density, many pores, and unstable water vapor isolation ability. In addition, the current packaging method of CIS chips has the problem of reliability failure caused by stress. Therefore, it is particularly important to reduce the stress during the packaging process. Summary of the Invention

[0005] In order to solve the technical problems existing in the prior art, the purpose of the present invention is to provide a low-stress packaging method and a product thereof.

[0006] In order to achieve the above-mentioned purpose and the above-mentioned technical effect, the technical solution adopted by the present invention is:

[0007] A low stress packaging method comprises the following steps:

[0008] S1. preparing a polyimide refractive film layer on glass;

[0009] S2, forming a cofferdam structure on the polyimide refractive film layer;

[0010] S3, mounting a chip on the structure obtained in step S2;

[0011] S4, making a through-hole structure on the chip;

[0012] S5. Making a passivation layer and an insulating layer on the chip, and then placing a gasket on the surface of the insulating layer;

[0013] S6, making an RDL circuit layer on the structure obtained in step S5;

[0014] S7, applying a solder mask layer on the RDL circuit layer;

[0015] S8, ball planting, cutting, and chip packaging are completed.

[0016] Furthermore, in step S1, a polyimide refractive film layer is formed on the glass by atomic layer deposition technology. The polyimide refractive film layer is formed by compounding a polyimide polymer with nano-composite particles ZrO, and the refractive index reaches 1.7.

[0017] Furthermore, in step S3, the chip is mounted on the glass by bonding adhesive to form one side of the cofferdam structure.

[0018] Furthermore, in step S4, the back side of the chip is thinned and a through-hole structure is formed.

[0019] Furthermore, in step S5, a passivation layer with a thickness of 1-3 μm is deposited on the back side of the chip by an atomic layer deposition process. In the atomic layer deposition process, the pulse time is 15-130 ms and the deposition temperature is 100±5°C.

[0020] Furthermore, in step S5, a passivation layer is first formed on the chip, and then an insulating layer is formed on the surface of the passivation layer. Then, a spacer with a thickness of 2-5 μm is bonded to the surface of the insulating layer by UV curing adhesive.

[0021] Furthermore, the gasket is a cellulose nanocrystal gradient composite gasket prepared by using cellulose nanocrystals, silver nanoparticles and polyethylene glycol.

[0022] Furthermore, the gasket is a gasket composited with graphene and hexagonal boron nitride.

[0023] Furthermore, in step S6, on the structure obtained in step S5, the bottom of the through-hole structure is opened by exposure and development to expose the chip PAD, and a Ti / Cu composite layer with a thickness of 1-3 μm is deposited by CVD deposition technology, and then the RDL circuit layer is covered on the Ti / Cu composite layer.

[0024] The present invention also discloses a low-stress packaging structure, which is prepared using the low-stress packaging method described above. The structure includes glass, a polyimide refractive film layer is provided on the glass, a cofferdam structure is provided on the polyimide refractive film layer, a chip is mounted on the glass, a through-hole structure is formed on the chip, a passivation layer is provided on the chip, an insulating layer is provided on the passivation layer, a gasket is provided on the insulating layer, a Ti / Cu composite layer is provided on the surfaces of the insulating layer and the gasket, an RDL circuit layer is provided on the Ti / Cu composite layer, a solder resist layer is provided on the RDL circuit layer, and a solder ball is provided on the RDL circuit layer.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1) The present invention uses atomic layer deposition technology to replace traditional chemical deposition technology to form a highly transparent polyimide refractive film layer on glass. The film layer has high flatness, high uniformity, high density, and no pinholes on the surface. Compared with conventional refractive films, it can achieve low stress, ultra-low reflectivity, ultra-high transmittance, and ultra-high refractive index. It can effectively increase the amount of light reaching the photosensitive area of ​​the CIS chip, effectively enhance the CIS chip's ability to convert optical signals into electrical signals, and at the same time solve the anti-reflection requirements of optical resin glass;

[0027] 2) The present invention uses atomic layer deposition technology to deposit the passivation layer. The film layer has high flatness, high uniformity, high density, no pinholes on the surface, and effectively isolates water vapor. It can effectively improve the problems of mechanical stress of thin films such as oxide fracture at the bottom of the hole caused by traditional chemical deposition technology;

[0028] 3) The present invention forms an insulating layer on the surface of the passivation layer, and bonds the gasket to the surface of the insulating layer through UV curing adhesive, which can effectively disperse the interface stress and reduce the crack problem of the passivation layer;

[0029] 4) By optimizing the pad diameter and solder mask opening size, the package stress is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic structural diagram of step S1 of the present invention;

[0031] Figure 2 This is a schematic structural diagram of step S2 of the present invention;

[0032] Figure 3This is a schematic structural diagram of step S3 of the present invention;

[0033] Figure 4 This is a schematic structural diagram of step S4 of the present invention;

[0034] Figure 5 This is a schematic structural diagram of step S5 of the present invention;

[0035] Figure 6 This is a schematic structural diagram of step S6 of the present invention;

[0036] Figure 7 This is a schematic structural diagram of step S7 of the present invention;

[0037] Figure 8 It is a structural diagram of step S8 of the present invention. DETAILED DESCRIPTION

[0038] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0039] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0040] like Figure 1-8 As shown, the present invention discloses a low stress packaging method, comprising the following steps:

[0041] S1, such as Figure 1 As shown, a highly transparent polyimide refractive film layer 2 is formed on the glass 1 by atomic layer deposition technology. The polyimide refractive film layer 2 is prepared by compounding a polyimide polymer with nano ZrO particles (the addition amount is 5-10wt% of the total amount) and adopting atomic layer deposition technology. The deposition temperature is 250°C-350°C, the deposition pressure is 85-100Pa, the pulse time is 1-3s, the number of cycles is 4000-7000 times, the refractive index can reach 1.7, and the film thickness is uniform.

[0042] S2, such as Figure 2 As shown, a dam structure 3 is formed on the polyimide refractive film layer 2 .

[0043] S3, such as Figure 3 As shown, a chip 4 (preferably a CIS chip) is mounted on the glass 1 through a bonding adhesive 5 to form one side of the cofferdam structure 3 .

[0044] S4, such as Figure 4 As shown, the back side of the chip 4 is thinned and a through-hole structure 6 is formed.

[0045] S5, such as Figure 5 As shown, a passivation layer 7 with a thickness of 1-3 μm is deposited on the back of the chip 4 by atomic layer deposition technology. The passivation layer 7 is made of silicon dioxide material. In the atomic layer deposition process, the pulse time is 15-130 ms and the deposition temperature is 100±5°C. Then, an insulating layer 8 with a thickness of 8-15 μm is formed on the surface of the passivation layer 7 using positive photoresist. Then, a gasket 9 with a thickness of 2-5 μm is bonded to the surface of the insulating layer 8 using a UV-curing adhesive with high viscosity (viscosity 4500-6000 mPa·s);

[0046] In this step, the gasket 9 can be a cellulose nanocrystal (CNCs) gradient composite gasket prepared by cellulose nanocrystals, silver nanoparticles and polyethylene glycol. A small volume fraction (no more than 20 vol%) of silver nanoparticles and polyethylene glycol are introduced into the cellulose nanocrystals. During the composite molding process, there is a certain strength of interaction between the cellulose nanocrystals and the silver nanoparticles, so that the cellulose nanocrystals can drive the self-assembly of the silver nanoparticles and achieve uniform dispersion of the silver nanoparticles. Finally, a cellulose nanocrystal (CNCs) gradient composite gasket is formed into a film. The gasket size r = 1.25X, X is the BGA ball diameter, and r is the radius of the gasket. The gasket can adapt to the size change by its own compression deformation when the circuit board expands due to heat, reducing the extrusion stress on the chip, and can effectively reduce the stress by 7%, thereby improving the passivation layer crack problem.

[0047] The gasket 9 can also be a gasket made of a composite of graphene and hexagonal boron nitride. The surface of hexagonal boron nitride is relatively flat, and it has a hexagonal honeycomb crystal structure similar to graphene. It is also a typical layered material with a soft texture and strong machinability, so it is also called white graphite. Since there is only a small lattice mismatch (1.6%) between graphene and hexagonal boron nitride, they have many similar physical properties. The specific preparation steps of the gasket composed of graphene and hexagonal boron nitride are as follows: disperse graphene oxide in an ethanol solution, add an appropriate amount of boric acid and melamine, and disperse it evenly by ultrasonication; then add an appropriate amount of mineralizer and stir evenly to promote the formation of boron nitride. The mixed solution is centrifuged and dried, then ground into powder and placed in a sintering furnace for sintering under a protective atmosphere. Finally, the required gasket is prepared by a melting method. The gasket has an excellent deformation recovery rate and can disperse large stresses. The gasket size r = 1.28X can effectively reduce the stress by 6.5%, thereby improving the crack problem of the passivation layer.

[0048] S6, such as Figure 6As shown, the bottom of the through-hole structure 6 is opened by exposure and development to expose the chip PAD, and a Ti / Cu composite layer with a thickness of 1-3 μm is deposited by CVD deposition technology, and then the RDL circuit layer 10 is covered on the Ti / Cu composite layer.

[0049] S7, such as Figure 7 As shown, a solder resist layer 11 is coated on the RDL circuit layer 10, and the material thereof is a negative photoresist with a thickness of 20-30 μm;

[0050] The pad diameter and the size of the solder mask opening can affect the package stress. Usually, the pad diameter in the packaging process is 0.8X and the solder mask opening is 0.75X. In this case, there will be a greater risk of solder mask breakage. Therefore, the present invention sets the pad diameter to 0.85X and the solder mask opening to 0.73r. By controlling the ratio of the solder mask to the pad opening, the package stress is effectively reduced.

[0051] S8, such as Figure 8 As shown, solder balls 12 are planted on the pads, and finally cutting is performed to complete the chip packaging.

[0052] The present invention also discloses a low-stress packaging structure, which is prepared using the low-stress packaging method described above, and includes glass 1, a polyimide refractive film layer 2 is provided on the glass 1, a cofferdam structure 3 is provided on the polyimide refractive film layer 2, a chip 4 is mounted on the glass 1, a through-hole structure 6 is formed on the chip 4, a passivation layer 7 is provided on the chip 4, an insulating layer 8 is provided on the passivation layer 7, a gasket 9 is provided on the insulating layer 8, a Ti / Cu composite layer is provided on the surface of the insulating layer 8 and the gasket 9, an RDL circuit layer 10 is provided on the Ti / Cu composite layer, a solder resist layer 11 is provided on the RDL circuit layer 10, and a solder ball 12 is provided on the RDL circuit layer 10.

[0053] Example 1

[0054] like Figure 1-8 As shown, a low stress packaging method includes the following steps:

[0055] S1, such as Figure 1 As shown, a highly transparent polyimide refractive film layer 2 is formed on the glass 1 by atomic layer deposition technology. The polyimide refractive film layer 2 is prepared by compounding a polyimide polymer with nano ZrO particles (the addition amount is 10wt% of the total amount) and adopting atomic layer deposition technology. The deposition temperature is 250°C, the deposition pressure is 85Pa, the pulse time is 2s, the number of cycles is 4000 times, the refractive index can reach 1.7, and the film thickness is uniform.

[0056] S2, such as Figure 2 As shown, a dam structure 3 is formed on the polyimide refractive film layer 2 .

[0057] S3, such as Figure 3 As shown, a chip 4 (CIS chip) is mounted on a glass 1 through a bonding adhesive 5 to form one side of the cofferdam structure 3 .

[0058] S4, such as Figure 4 As shown, the back side of the chip 4 is thinned and a through-hole structure 6 is formed.

[0059] S5, such as Figure 5 As shown, a passivation layer 7 with a thickness of 2 μm is deposited on the back of the chip 4 by atomic layer deposition technology. The passivation layer 7 is made of silicon dioxide material. In the atomic layer deposition process, the pulse time is 80 ms and the deposition temperature is 100° C. Then, an insulating layer 8 with a thickness of 8 μm is formed on the surface of the passivation layer 7 using positive photoresist. Then, a spacer 9 with a thickness of 3 μm is bonded to the surface of the insulating layer 8 using a UV-curable adhesive with high viscosity (viscosity 4500 mPa·s);

[0060] In this step, the gasket 9 is a gasket made of a composite of graphene and hexagonal boron nitride. The surface of hexagonal boron nitride is relatively flat, and it has a hexagonal honeycomb crystal structure similar to graphene. It is also a typical layered material with a soft texture and strong machinability, so it is also called white graphite. Since there is only a small lattice mismatch (1.6%) between graphene and hexagonal boron nitride, they have many similar physical properties. The specific preparation steps of the gasket composed of graphene and hexagonal boron nitride are as follows: disperse graphene oxide in an ethanol solution, add an appropriate amount of boric acid and melamine, and disperse it evenly by ultrasonication; then add an appropriate amount of mineralizer and stir evenly to promote the formation of boron nitride. The mixed solution is centrifuged and dried, then ground into powder and placed in a sintering furnace for sintering under a protective atmosphere. Finally, the required gasket is prepared by a melting method. The gasket has an excellent deformation recovery rate and can disperse large stresses. The gasket size r = 1.28X can effectively reduce the stress by 6.5%, thereby improving the crack problem of the passivation layer.

[0061] S6, such as Figure 6 As shown, the bottom of the through-hole structure 6 is opened by exposure and development to expose the chip PAD, and a Ti / Cu composite layer with a thickness of 2 μm is deposited by CVD deposition technology, and then the RDL circuit layer 10 is covered on the Ti / Cu composite layer.

[0062] S7, such as Figure 7 As shown, a solder resist layer 11 is coated on the RDL circuit layer 10, and the material thereof is a negative photoresist with a thickness of 20 μm;

[0063] The pad diameter and the size of the solder mask opening can affect the package stress. Usually, the pad diameter in the packaging process is 0.8X and the solder mask opening is 0.75X. In this case, there will be a greater risk of solder mask breakage. Therefore, the present invention sets the pad diameter to 0.85X and the solder mask opening to 0.73r. By controlling the ratio of the solder mask to the pad opening, the package stress is effectively reduced.

[0064] S8, such as Figure 8 As shown, solder balls 12 are planted on the pads, and finally cutting is performed to complete the chip packaging.

[0065] A low-stress packaging structure is prepared using the low-stress packaging method described above, comprising glass 1, a polyimide refractive film layer 2 is provided on the glass 1, a cofferdam structure 3 is provided on the polyimide refractive film layer 2, a chip 4 is mounted on the glass 1, a through-hole structure 6 is formed on the chip 4, a passivation layer 7 is provided on the chip 4, an insulating layer 8 is provided on the passivation layer 7, a gasket 9 is provided on the insulating layer 8, a Ti / Cu composite layer is provided on the surfaces of the insulating layer 8 and the gasket 9, an RDL circuit layer 10 is provided on the Ti / Cu composite layer, a solder resist layer 11 is provided on the RDL circuit layer 10, and a solder ball 12 is provided on the RDL circuit layer 10.

[0066] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0067] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A low stress packaging method, characterized in that: The following steps are involved: S1. preparing a polyimide refractive film layer on glass; S2, forming a cofferdam structure on the polyimide refractive film layer; S3, mounting a chip on the structure obtained in step S2; S4, making a through-hole structure on the chip; S5. Making a passivation layer and an insulating layer on the chip, and then placing a gasket on the surface of the insulating layer; S6, making an RDL circuit layer on the structure obtained in step S5; S7, applying a solder mask layer on the RDL circuit layer; S8, ball planting, cutting, and chip packaging are completed.

2. A low stress packaging method according to claim 1, characterized in that: In step S1, a polyimide refractive film layer is formed on glass by atomic layer deposition technology. The polyimide refractive film layer is formed by compounding a polyimide polymer with nano-composite particles ZrO, and the refractive index reaches 1.

7.

3. The low stress packaging method according to claim 1, wherein: In step S3, the chip is mounted on the glass by bonding adhesive to form one side of the cofferdam structure.

4. The low stress packaging method according to claim 1, wherein: In step S4, the back side of the chip is thinned and a through-hole structure is formed.

5. The low stress packaging method according to claim 1, wherein: In step S5, a passivation layer with a thickness of 1-3 μm is deposited on the back side of the chip by an atomic layer deposition process. In the atomic layer deposition process, the pulse time is 15-130 ms and the deposition temperature is 100±5°C.

6. The low stress packaging method according to claim 1, wherein: In step S5, a passivation layer is first formed on the chip, and then an insulating layer is formed on the surface of the passivation layer. Finally, a spacer with a thickness of 2-5 μm is bonded to the surface of the insulating layer by UV curing adhesive.

7. The low stress packaging method according to claim 6, characterized in that: The gasket is a cellulose nanocrystal gradient composite gasket prepared by using cellulose nanocrystals, silver nanoparticles and polyethylene glycol.

8. The low stress packaging method according to claim 6, characterized in that: The gasket is a compound of graphene and hexagonal boron nitride.

9. The low stress packaging method according to claim 1, wherein: In step S6, on the structure obtained in step S5, the bottom of the through-hole structure is opened by exposure and development to expose the chip PAD, and a Ti / Cu composite layer with a thickness of 1-3 μm is deposited by CVD deposition technology, and then the RDL circuit layer is covered on the Ti / Cu composite layer.

10. A low stress packaging structure, characterized in that: The low-stress packaging method according to any one of claims 1 to 9 is used to prepare the device, comprising glass, a polyimide refractive film layer is provided on the glass, a cofferdam structure is provided on the polyimide refractive film layer, a chip is mounted on the glass, a through-hole structure is formed on the chip, a passivation layer is provided on the chip, an insulating layer is provided on the passivation layer, a gasket is provided on the insulating layer, a Ti / Cu composite layer is provided on the surface of the insulating layer and the gasket, an RDL circuit layer is provided on the Ti / Cu composite layer, a solder resist layer is provided on the RDL circuit layer, and a solder ball is provided on the RDL circuit layer.

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