Current limiting circuitry with controlled current variation

Abstract

Methods, apparatus, systems, and articles of manufacture correspond to current limiting circuitry with controlled current variation. An example circuit (102) includes a voltage regulator (104) configured to control a first transistor (106) to regulate a supply voltage to a regulated voltage; and current limiting circuitry (108) configured to enable a second transistor (218) to reduce an output current when a voltage at a control terminal of the first transistor (106) meets a threshold.

Description

[0001] This description relates generally to circuits and, more particularly, to current limiting circuitry with controlled current variation. Background Art

[0002] Current limiting circuitry is used to limit the amount of current that can be drawn by a load. Current limiting circuitry can be used in conjunction with a voltage regulator. For example, a voltage regulator can provide a regulated voltage based on a power supply voltage. However, when the current drawn by the load exceeds a threshold, the current limiting circuitry can activate to limit the current. Current limiting circuitry can prevent damage caused by faults (e.g., short circuits, overloads, etc.). Summary of the Invention

[0003] Examples of the present specification include a circuit comprising: a gain stage having a first input terminal, a second input terminal, and an output terminal; a transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal of the transistor being coupled to a supply voltage terminal, the second current terminal of the transistor being structured to be coupled to the second input terminal of the gain stage, and the control terminal of the transistor being coupled to the output terminal of the gain stage; and regulator compensation circuitry having a first terminal and a second terminal, the first terminal of the regulator compensation circuitry being coupled to the output terminal of the first gain stage, and the second terminal of the regulator compensation circuitry being coupled to the second input terminal of the gain stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is an example power management circuitry including example regulator circuitry and current limiting circuitry.

[0005] Figure 2 yes Figure 1 An example of a current limiting circuit system.

[0006] Figure 3A and 3B illustrate Figure 2 An alternative circuit for a diode-connected transistor.

[0007] Figure 4 yes Figure 1 An example of compensation circuitry in a voltage regulator.

[0008] Figure 5 yes Figure 1 Another example of compensation circuitry in a voltage regulator.

[0009] Figure 6 yes Figure 1 Another example of compensation circuitry in a voltage regulator.

[0010] Figure 7 yes Figure 1 Another example of compensation circuitry in a voltage regulator.

[0011] Figure 8 It means that it can be implemented through execution Figure 1 Flowchart of methods and / or operations of power management circuit systems.

[0012] The use of the same reference numbers or other reference designators in the drawings indicates the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0013] The figures are not necessarily drawn to scale. Generally, like reference numerals in the figures and in this specification refer to like or similar parts. Although the figures show regions with distinct lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, the boundaries and / or lines may be unobservable, blended, and / or irregular.

[0014] Voltage regulators (e.g., low-dropout regulators (LDOs), direct current (DC-DC) converters, etc.) are used as part of a power management block in various industries (e.g., automotive, industrial, etc.) to regulate the supply voltage to a regulated voltage. The regulated voltage is used to power a load. A load is any component that consumes power from the voltage regulator. A current limiting circuit can be used in conjunction with a voltage regulator to prevent the load from drawing more than a threshold amount of current. For example, if the load includes an overloaded component and / or a short circuit, the load may draw enough current to damage one or more components of the load and / or one or more components of the voltage regulator. Therefore, the current limiting circuit protects the load and / or the regulator by limiting the current that the regulator can provide to the load.

[0015] Some voltage regulators regulate their output voltage by utilizing negative feedback. Examples of negative feedback mechanisms in some voltage regulator circuits are further described below. Some regulator circuits include a gain stage to compare a voltage proportional to the output voltage with a reference voltage. In such regulator circuits, if the voltage proportional to the output voltage is lower than the reference voltage, the gain stage increases the voltage at the gate terminal of the pass transistor to increase the output voltage. However, if the voltage proportional to the output voltage is greater than the reference voltage, the gain stage decreases the voltage at the gate (e.g., control) terminal of the pass transistor to decrease the output voltage. Using negative feedback, the above process continues until the voltage proportional to the output voltage is closer to the reference voltage. The pass transistor supplies current from the supply voltage to the load. In some examples, the pass transistor operates in the saturation region. The pass transistor is also part of the negative feedback of the voltage regulator. For example, the gate terminal of the pass transistor is controlled by the gain stage based on the output voltage and the current supplied to the load.

[0016] Some current limiting circuits utilize a gain stage, a resistor, and a sense transistor to determine when the load current (e.g., the output current and / or the current drawn from the output of a regulator circuit) is above a threshold. The sense transistor is coupled to a pass transistor of the regulator circuit to sense the gate-source voltage (VGS) of the pass transistor, which corresponds to the load current. The sensed VGS generates a current through the resistor to generate a voltage corresponding to the load current. The gain stage compares the voltage corresponding to the load current to a threshold to determine whether the load current is above the threshold. If the load current is above the threshold, the current limiting circuit is enabled and adjusts the gate voltage of the pull-down transistor. Adjusting the gate voltage of the pull-down transistor causes the pull-down transistor to adjust or control the gate voltage of the pass transistor to a lower value, which limits the current flowing through the pass transistor.

[0017] However, due to the high variation of the resistors, such current limiting circuits correspond to high variations (e.g., in process, voltage, temperature, and mismatch). For example, resistor variations can cause a current limit variation of ±24%. The described examples can reduce the current limit variation of such current limiting circuits by fixing the VGS of the pass transistor to limit the current flowing through the pass transistor. The described examples can reduce the current limit by eliminating and / or reducing the reliance on the resistor to determine whether the load current is above a threshold. Alternatively, some described examples utilize a gain stage, two transistors, and a current source circuit system to fix the VGS of the pass transistor to limit the load current to a predefined amount of current. Because the variation of the current source circuit system is lower than the variation of the resistor, some described examples result in lower variations in the current limit value in process, voltage, temperature, and / or mismatch. For example, using the examples described herein, the variation in the current limit value is reduced to ±15% or less.

[0018] In addition, unlike some current sensing circuits that scale current consumption with the load current to determine whether the load current is above a threshold, the examples described herein can determine whether the load current is above a threshold without scaling current consumption with the load current, thereby achieving increased efficiency. For example, some current sensing circuits can limit the current to 500 milliamperes (mA). In such current sensing circuitry, if the load current is 100 mA, the current drawn by the sensing transistor is 100 microamperes (uA). However, when the load current is 400 mA, the current drawn by the sensing transistor is 400 uA. The examples described herein limit the current drawn to a fixed current (e.g., 50 uA) regardless of the load current.

[0019] Additionally, some regulator circuitry is structured to support a wide range of currents drawn by the load. However, this wide current range causes variations in the poles of the regulator circuitry's feedback loop. The poles can create stability margins, which can cause undesirable ringing (e.g., large voltage variations) at the regulator circuitry's output. Therefore, such regulator circuitry requires frequency compensation circuitry to compensate for the poles to increase the stability of the regulator circuitry, thereby reducing and / or eliminating the undesirable ringing. In some examples, the frequency compensation circuitry includes a capacitor coupled to the output of the regulator's amplifier and to ground. The capacitor compensates for variations in the poles for the desired current range. In some examples, such capacitors must have capacitance in the nanofarad (nF) range. For example, in certain examples, such capacitors have capacitances of hundreds of picofarads (pF) to provide adequate frequency compensation, which corresponds to metal capacitors. Metal capacitors are large and occupy a significant amount of silicon area. For example, a 500 pF metal capacitor requires 539,000 square micrometers (μm), and a 65 pF metal capacitor requires 70,000 square micrometers.

[0020] The examples described herein provide frequency compensation circuitry that enables the use of smaller capacitors than other frequency compensation circuitry. For example, using the examples described herein, frequency compensation can be achieved using one or more capacitors with a capacitance of no greater than 7.5 pF. Because the voltage across the capacitors included in the examples described herein is less than other technologies, metal oxide semiconductor (MOS) capacitors smaller than metal capacitors can be implemented. For example, the amount of silicon area required to implement a 7.5 pF MOS capacitor is 5,500 μm. Therefore, the examples described herein use 9-67 times less silicon area than other technologies to produce frequency compensation.

[0021] Figure 1Example power management circuitry 102 is illustrated having example regulator circuitry 104 and example current limit circuitry 108 . Figure 1 The power management circuitry 102 includes an example regulator circuitry 104, an example transistor 106, an example current limiting circuitry 108, example terminals 110, 112, 114, 116, and an example load 119. Although the current limiting circuitry 108 is Figure 1 Although implemented in the power management circuitry 102 of FIG. 1 , the current limiting circuitry 108 may be implemented separately (eg, in a dedicated circuit or IC) or in any circuit where it is desired to limit current.

[0022] Figure 1 The power management circuitry 102 may be an IC, a portion of a larger IC, or another component. The power management circuitry 102 may be used to power electrical components, components of a processor, components of a motor drive, and / or components of any circuit that benefits from a regulated voltage.

[0023] Figure 1 The regulator circuitry 104 is structured (e.g., configured or configurable) to couple to a supply voltage source to obtain a supply voltage (e.g., VDD) via a supply voltage terminal 110. The regulator 104 is structured to couple to a ground terminal (or a negative voltage supply) via a ground terminal 112 (e.g., also referred to as a VSS terminal). The regulator circuitry 104 regulates (e.g., converts, adjusts, etc.) the output voltage to a desired value for any disturbances at the output, and also regulates supply voltage variations at the output.

[0024] For example, if there is a sudden change in current that causes the output voltage to drop momentarily, the regulator circuitry 104 adjusts the output voltage to a desired value. As another example, the supply voltage may be too high or may be unstable, which may cause problems when used to power one or more electrical components. Therefore, the regulator circuitry 104 may convert the unstable and / or high supply voltage into a stable and / or lower regulated voltage. The regulator circuitry 104 may control the transistor 106 (e.g., a pass transistor) to output the regulated voltage, as described below in conjunction with Figure 2 Regulator circuitry 104 outputs a regulated voltage via output terminal 114. Output terminal 114 is structured or adapted to be connected to any component to power the component (e.g., load 119) with the regulated voltage. Regulator circuitry 104 controls transistor 106 based on a measurement of the output voltage obtained via terminal 116. Although regulator circuitry 104 obtains the output voltage as part of a feedback loop via an external connection through output terminal 114 and terminal 116, regulator circuitry 104 may be connected internally.

[0025] Figure 1 Current limiting circuitry 108 is coupled to regulator circuitry 104, supply voltage terminal 110, and ground terminal 112. Current limiting circuitry 108 uses a diode-connected transistor and a current source to control the VGS of transistor 106. Additionally, current limiting circuitry 108 uses a feedback loop to determine when the current drawn by load 119 via output terminal 114 (e.g., output current or load current) is above a threshold. If current limiting circuitry 108 determines that the output current is above the threshold, current limiting circuitry 108 reduces the output current using a pull-down transistor, as described below in conjunction with Figure 2 Further description.

[0026] Figure 2 yes Figure 1 An example circuit diagram of the power management circuit system 102 is shown in FIG. Figure 2 The regulator circuitry 104 includes an example gain stage 200, an example regulator compensation circuitry 202, example resistors 206, 208, and Figure 1 Example transistor 106. Figure 2 The current limiting circuitry 108 includes example current source circuitry 212 , example transistor 214 , example gain stage 216 , and example transistor 218 . Figure 2 Further includes Figure 1 Example terminals 114, 116, Figure 1 The load 119 and the example decoupling capacitor 220.

[0027] exist Figure 2 In the example of FIG1 , gain stage 200 (also referred to as gain stage circuitry) can be an amplifier, an error amplifier, an operational amplifier, or the like. Gain stage 200 includes a first input terminal, a second input terminal, a positive supply voltage terminal, a negative supply voltage terminal, and an output terminal. A first input terminal (e.g., a non-inverting terminal) of gain stage 200 is coupled to a reference voltage generator (e.g., a bandgap reference circuitry). A second input terminal (e.g., an inverting terminal) of gain stage 200 is coupled to regulator compensation circuitry 202 and resistors 206 and 208. A positive supply terminal of gain stage 200 is coupled to supply voltage terminal 110. A negative supply terminal of gain stage 200 is coupled to ground terminal 112. An output terminal of gain stage 200 is coupled to a second input terminal of a second example gain stage 216, regulator compensation circuitry 202, a first current terminal of transistor 218, and a control terminal of transistor 106.

[0028] Gain stage 200 compares a voltage corresponding to the regulated output voltage at output terminal 114 to a reference voltage. The voltage corresponding to the regulated output voltage may be a scaled-down version of the output voltage (also referred to as a scaled output voltage). If gain stage 200 determines that the scaled output voltage is higher than the reference voltage, gain stage 200 controls (e.g., adjusts, reduces, etc.) the output voltage to reduce the voltage at the control terminal of transistor 106 to a voltage determined by negative feedback. If gain stage 200 determines that the scaled output voltage is lower than the reference voltage, gain stage 200 controls (e.g., adjusts, increases, etc.) the output voltage to increase the voltage at the control terminal of transistor 106 to a voltage determined by negative feedback. Negative feedback is also used to control the voltage at the control terminal of transistor 106 based on the current consumed by load 119. Further operation of gain stage 200 is described below.

[0029] Figure 2 Regulator compensation circuitry 202 includes a first terminal and a second terminal. The first terminal of regulator compensation circuitry 202 is coupled to the output terminal of gain stage 200, the second input terminal of gain stage 216, the first current terminal of transistor 218, and the control terminal of transistor 106. The second terminal of regulator compensation circuitry 202 is coupled to resistors 206 and 208 and the second input terminal of gain stage 200. Regulator circuitry 104 includes a first stage corresponding to gain stage 200 and a second stage corresponding to transistor 106.

[0030] Thus, regulator compensation circuitry 202 performs frequency compensation (e.g., dominant pole compensation and / or any other type of compensation) to achieve feedback stability. In some examples, regulator compensation circuitry 202 is implemented at a different location in voltage regulator circuitry 104 (e.g., coupled to an output terminal of regulator circuitry 104). Because example regulator circuitry 104 supports output currents from 400 uA to 500 mA, the transconductance of regulator circuitry 104 can be varied, resulting in a 100-fold shift of the pole.

[0031] The regulator compensation circuit system 202 is structured to compensate for varying poles while reducing the surface area used to implement the regulator compensation circuit system 202. For example, the regulator compensation circuit system 202 introduces a zero at the feedback loop (e.g., at the second input terminal of the gain stage 200). The zero compensates for the pole to increase the phase margin and increase the stability of the regulator compensation circuit system 202. The output stage poles and zeros track the transconductance (gmpass) of the pass transistor 106. Additionally, the output stage poles and zeros track the capacitance of the decoupling capacitor 220. Because the regulator compensation circuit system 202 is connected to the output of the gain stage 200 and the second input terminal of the gain stage 200, the regulator compensation circuit system 202 introduces an additional fast closed-loop path at high frequencies to create a closed-loop path that is a single-pole system. The regulator compensation circuit system 202 achieves a unity gain bandwidth (UGB) that is independent of the transconductance of the pass transistor 106 and the decoupling capacitor 220. Figure 4-7 The implementation of regulator compensation circuitry 202 is further described.

[0032] Figure 2 1. Transistor 106 is an N-channel metal oxide semiconductor (MOS) field effect transistor (FET) (also referred to as NMOS) that operates as a pass transistor to provide a regulated voltage to load 119, as further described below. However, transistor 106 may be implemented as any type of transistor and / or switch. Transistor 106 includes a first current terminal (e.g., a drain terminal), a second current terminal (e.g., a source terminal), and a control terminal (e.g., a gate terminal). The first current terminal of transistor 106 is coupled to supply voltage terminal 110. The second current terminal of transistor 106 is coupled to output terminal 114. The control terminal of transistor 106 is coupled to a first current terminal of transistor 218, a second input terminal of regulator compensation circuitry 202 and gain stage 216, and an output terminal of gain stage 200.

[0033] Transistor 106 operates in saturation mode to supply a current to load 119 that is proportional to the square of the difference between the gate-source voltage of transistor 106 and the threshold voltage of transistor 106. Additionally, transistor 106 reduces the effects of power supply noise on the regulated output voltage. Voltage regulation at output terminal 114 is controlled by the control terminal of transistor 106. For example, when gain stage 200 increases the VAMP voltage at the gate of pass transistor 106, pass transistor 106 increases the output voltage to achieve the desired output voltage at terminal 114. When gain stage 200 decreases the VAMP voltage at the gate of pass transistor 106, pass transistor 106 decreases the output voltage to achieve the desired output voltage at terminal 114. In some examples, the above circuit operation description provides a simplified description. Pass transistor 106 is part of the negative feedback of voltage regulator circuitry 104. For example, the control terminal of pass transistor 106 is controlled by gain stage 200 based on or in response to the output voltage and the current supplied to load 119.

[0034] Figure 2 Resistor 206 includes a first terminal and a second terminal. The first terminal of resistor 206 is coupled to feedback terminal 116. The second terminal of resistor 206 is coupled to a first terminal of resistor 208 and a second input terminal of gain stage 200. Resistor 208 includes a first terminal and a second terminal. The first terminal of resistor 208 is coupled to the second terminal of resistor 206 and the second input terminal of gain stage 200. The second terminal of resistor 208 is coupled to ground terminal 112. Figure 2 The resistors 206 , 208 are structured or arranged to function or operate as a voltage divider. Thus, the voltage at the terminal between the two resistors 206 , 208 is a scaled version of the output voltage at the output terminal 114 .

[0035] Figure 2Transistor 214 is an NMOS transistor that functions or operates as a diode to allow current from current source circuitry 212 to flow from a first current terminal of transistor 214 to a second current terminal of transistor 214. However, transistor 214 can be any type of transistor. The transistor includes a first current terminal (e.g., a drain terminal), a second current terminal (e.g., a source terminal), and a control terminal (e.g., a gate terminal). The first current terminal of transistor 214 is coupled to current source circuitry 212, a first input terminal of gain stage 216, and a control terminal of transistor 214. The second current terminal of transistor 214 is coupled to the second current terminal of transistor 106 and output terminal 114. The control terminal of transistor 214 is coupled to the first current terminal of transistor 214, current source circuitry 212, and a first input terminal of gain stage 216. The first current terminal of transistor 214 is coupled to the control terminal of transistor 214.

[0036] Thus, transistor 214 is structured or arranged to operate as a diode-connected transistor. Diode-connected transistor 214 allows current to travel from a first current terminal of transistor 214 to a second current terminal of transistor 214. Transistor 214 uses the current generated by current source circuitry 212 to create a voltage drop (e.g., corresponding to the VTRIG voltage and / or the VOUT voltage) across the current terminal of transistor 214. To limit the amount of current drawn by transistor 214, the size (e.g., channel width and / or channel length) of transistor 214 can be much smaller than transistor 106. For example, the size of transistor 214 can be 1000 times smaller than that of transistor 106. Figure 3A and 3B Alternative structures for transistor 214 are further described.

[0037] Figure 2 Current source circuitry 212 can be implemented using P-channel MOS circuitry based on a bandgap reference circuit and / or any other current source circuitry. Current source circuitry 212 includes a first terminal and a second terminal. The first terminal of current source circuitry 212 is coupled to supply voltage terminal 110, and the second terminal of current source circuitry 212 is coupled to a first input terminal of gain stage 216, a first current terminal of transistor 214, and a control terminal of transistor 214. Current source circuitry 212 generates a current that flows to the first current terminal of transistor 214.

[0038] Figure 2Gain stage 216 (also referred to as gain stage circuitry) can be an amplifier, an error amplifier, an operational amplifier, or the like. Gain stage 216 includes a first input terminal, a second input terminal, a positive supply voltage terminal, a negative supply voltage terminal, and an output terminal. A first input terminal (e.g., an inverting terminal) of gain stage 216 is coupled to current source circuitry 212, a first current terminal of transistor 214, and a control terminal of transistor 214. A second input terminal (e.g., a non-inverting terminal) of gain stage 216 is coupled to the output of gain stage 200, regulator compensation circuitry 202, a first current terminal of transistor 218, and a control terminal of transistor 106. A positive supply terminal of gain stage 216 is coupled to supply voltage terminal 110. A negative supply terminal of gain stage 216 is coupled to ground terminal 112. An output terminal of gain stage 216 is coupled to the control terminal of transistor 218.

[0039] Gain stage 216 compares the voltage at the first current terminal of transistor 214 (e.g., VTRIG) to the voltage output by gain stage 200 (e.g., VAMP). The VTRIG voltage at the first current terminal of transistor 214 corresponds to the regulated voltage at the output terminal (e.g., VTRIG is the sum of the regulated voltage (VOUT) and the VGS of transistor 214). If gain stage 216 determines that VAMP is lower than VTRIG, gain stage 216 acts as a comparator and outputs a low voltage (e.g., 0 volts (V)) at the control terminal of transistor 218, thereby disabling the current limit loop. If gain stage 216 determines that VAMP is higher than VTRIG, gain stage 216 outputs a controlled high voltage based on the excess current being drawn from output terminal 114. The controlled high voltage limits the VAMP voltage to the VTRIG voltage. The greater the difference between the VAMP voltage and the VTRIG voltage, the higher the output voltage (VCURR_LIM), which can be set based on the excess load current being drawn from a threshold, the gain of stage 216, and so on. Further operation of gain stage 216 is described further below.

[0040] Figure 2 Transistor 218 is an NMOS transistor that operates as a pull-down transistor, a switch, and / or a current source to lower VAMP when enabled, as further described below. However, transistor 218 can be implemented as any type of transistor and / or switch. Transistor 218 includes a first current terminal (e.g., a drain terminal), a second current terminal (e.g., a source terminal), and a control terminal (e.g., a gate terminal). The first current terminal of transistor 218 is coupled to the output of gain stage 200, the second input terminal of gain stage 216, regulator compensation circuitry 202, and the control terminal of transistor 106. The second current terminal of transistor 218 is coupled to ground terminal 112. The control terminal of transistor 218 is coupled to the output terminal of gain stage 216.

[0041] When the voltage at the output terminal of gain stage 216 is high (e.g., when the VAMP voltage exceeds the VTRIG voltage), transistor 218 is enabled (e.g., turned on, operated as a closed switch, operated as a current source, etc.). When enabled (e.g., in linear and / or saturation modes), transistor 218 draws current from gain stage 200 toward ground. The amount of current drawn toward ground by transistor 218 may depend on the voltage set by gain stage 216. As described above, the voltage set by gain stage 216 depends on the load current intended to be drawn by external load 119, the gain of stage 216, etc. Transistor 218 is disabled (e.g., turned off, operated as an open switch, etc.) in response to the voltage at the output terminal of gain stage 216 being low (e.g., below a threshold). When disabled (e.g., when the VAMP voltage is below the VTRIG voltage), transistor 218 is turned off and does not lower the voltage at the control terminal of pass transistor 106.

[0042] Initially, in example operation, when the power management circuitry 102 is first started, the voltage at the output terminal 114 is low (e.g., 0V). Consequently, because the resistors 206 and 208 operate as a voltage divider, the voltage at the second input terminal of the gain stage 200 is also low (e.g., lower than the reference voltage at the first input terminal of the gain stage 200). Because the voltage at the first input terminal (VREF) is higher than the voltage at the second input terminal, the gain stage 200 outputs a high voltage (VDD), thereby enabling the transistor 106. As described above, in response to enabling the transistor 106, the output voltage at the load 119 increases using the supply voltage via the supply voltage terminal 110. As the output voltage at the output terminal 114 increases, the voltage at the second input terminal of the gain stage 200 increases because the voltage at the second input terminal of the gain stage 200 is a scaled version of the output voltage. As the second input terminal of the gain stage 200 increases closer to the reference voltage, the gain stage 200 adjusts and / or controls (increases, etc.) the gate voltage of the transistor 106 to generate the expected and / or desired output voltage at the output terminal 114. Thus, the second terminal of the example gain stage 200 is prevented from exceeding the reference voltage by negative feedback. Any disturbance in the output voltage causes the second terminal of the gain stage 200 to reach the reference voltage via negative feedback.

[0043] If the current drawn from transistor 106 by load 119 is too high (e.g., above a threshold), the output voltage at output terminal 114 begins to drop to a lower voltage, and gain stage 200 may no longer be able to regulate the output voltage. Therefore, when the output current is too high, current limit circuitry 108 limits the current to ensure that the output current does not exceed the threshold. Current source circuitry 212 generates a bias current that flows through the current terminal of diode-connected transistor 214 to generate a voltage (VTRIG) at the first current terminal of transistor 214. As described above, the VTRIG voltage is a function of the output voltage. For example, the VTRIG voltage corresponds to the sum of the regulated voltage (VOUT) and the VGS of transistor 214. Therefore, when the current drawn by load 119 exceeds the threshold, the VAMP voltage becomes higher than the VTRIG voltage, causing gain stage 216 to generate a control voltage VCURR_LIM to the gate terminal (e.g., control terminal) of pull-down transistor 218.

[0044] The amount of control voltage is based on the difference between the VAMP voltage and the VTRIG voltage, which is set based on the excess current drawn from the threshold, the gain of stage 216, and the like. The control voltage enables pull-down transistor 218. When enabled, pull-down transistor 218 draws current from gain stage 200 to reduce the VAMP voltage closer to the VTRIG voltage through negative feedback. When the current drawn by load 119 is less than the threshold, the VAMP voltage falls below the VTRIG voltage, thereby rendering current limiting circuitry 108 inoperable. Thus, voltage regulator circuitry 104 operates to generate the desired output voltage.

[0045] Figure 3A Description for Figure 2 An alternative diode-connected transistor structure 300 is provided for the diode-connected transistor 214 . Figure 3A The stacked transistors 301, 302, and 304 are comprised of N numbers. As described above, VTRIG is a voltage threshold for limiting current. Therefore, adjusting VTRIG will adjust the current that can be generated by Figure 2 The maximum amount of current drawn by the load 119. The VTRIG voltage can be adjusted by using transistors of different sizes or stacking additional transistors. Figure 3A Three stacked transistors 301, 302, 304 are included, but there may be any number of stacked transistors to achieve a desired VTRIG. In this example, more transistors correspond to a higher VTRIG.

[0046] exist Figure 3A In the diode-connected transistor structure 300, transistors 301, 302, 304 are NMOS transistors that operate as diodes to allow current from the current source circuit system 212 to flow from the current source circuit system 212 to the Figure 2 1 . However, transistors 301, 302, and 304 can be any type of transistor. Transistor 301 includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of transistor 301 is coupled to current source circuitry 212, a first input terminal of gain stage 216, and control terminals of transistors 301, 302, and 304. The second current terminal of transistor 301 is coupled to the first current terminal of transistor 302. The control terminal of transistor 301 is coupled to the first current terminal of transistor 301, control terminals of transistors 302 and 304, current source circuitry 212, and a first input terminal of gain stage 216.

[0047] Transistor 302 includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of transistor 302 is coupled to the second current terminal of transistor 302. The second current terminal of transistor 302 is coupled to the first current terminal of a subsequent transistor (e.g., to transistor 304 if three transistors are stacked). The control terminal of transistor 302 is coupled to the first current terminal of transistor 302, the control terminals of transistors 301 and 304, current source circuitry 212, and a first input terminal of gain stage 216.

[0048] Transistor 304 includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of transistor 304 is coupled to the second current terminal of the previous transistor (e.g., to transistor 302 if three transistors are implemented). The second current terminal of transistor 304 is coupled to Figure 1 The output terminal 114 of transistor 106 and / or transistor 2 and the second current terminal of transistor 106. The control terminal of transistor 304 is coupled to the first current terminal of transistor 304, the control terminals of transistors 301, 302, the current source circuitry 212 and the first input terminal of gain stage 216.

[0049] Because transistor 301 operates as a diode-connected transistor (e.g., operates in the saturation region) and transistors 302, 304 (e.g., operate in the linear region) use the same control terminal voltage, there is a voltage drop across the current terminal of each of transistors 301, 302, 304. Therefore, the VTRIG voltage increases based on the number of stacked transistors 301, 302, 304. Because transistors 301, 302, 304 can be the same size, increasing the number of transistors can increase the VTRIG voltage without drawing additional current, thereby maintaining power efficiency.

[0050] Figure 3B Description for Figure 2 An alternative diode-connected transistor structure 305 to the diode-connected transistor 214 is shown. Figure 3BThe circuit includes N number of stacked transistors 301, 302, 304 and an example resistor 306. As described above, VTRIG is a voltage threshold used to limit current. Therefore, adjusting VTRIG will adjust the current that can be generated by Figure 2 The maximum amount of current drawn by the load 119. Similar to Figure 3B The structure of 300, Figure 3A The structure of can be used to increase and / or otherwise adjust the VTRIG voltage without drawing more current. For example, if VTRIG is to be increased, the example transistors 301, 302, 304 can be stacked to increase the VTRIG voltage without increasing the amount of current drawn. Although Figure 3B Three stacked transistors 301 , 302 , 304 are included, but there may be any number of stacked transistors to achieve a desired VTRIG (eg, more transistors corresponding to a higher VTRIG).

[0051] Figure 3B A small resistor 306 is included to further tune the VTRIG voltage to a desired voltage. As described above, variations in the resistor can introduce variations in the current limit. Resistor 306 creates a voltage drop across its terminals to increase the VTRIG voltage. Resistor 306 includes two terminals. A first terminal of resistor 306 is coupled to current source circuitry 212 and a first input terminal of gain stage 216. A second terminal of resistor 306 is coupled to a first current terminal of transistor 301 and control terminals of transistors 301, 302, and 304.

[0052] Figure 4 An example regulator circuit system 400 is described, which includes Figure 2 The regulator compensation circuit system 202 combines Figure 2 Circuit implementation of the regulator circuit system 102. Figure 4 Include Figure 2 Pass transistor 106 , current limiting circuitry 108 , load 119 , resistors 206 , 208 , and capacitor 220 . Figure 4 Further comprising for implementing Figure 2 Regulator compensation circuitry 401 of the regulator compensation circuitry 202. Regulator compensation circuitry 401 includes example capacitors 402, 404. Although Figure 4 The second terminal of the current transistor 106 and the first terminal of the resistor 206 are directly coupled, but the terminals may be connected to two external terminals (e.g., Figure 2 The terminal connections are shown in Figure 1 and / or terminals 114, 116) of 2 are coupled.

[0053] Figure 4Capacitor 402 includes two terminals. A first terminal of capacitor 402 is coupled to the output terminal of gain stage 200, current limit circuitry 108, and the control terminal of transistor 106. Capacitor 402 may be a MOS capacitor. Capacitor 402 provides a fast loop path for high-frequency operation. Capacitor 402, connected to the feedback loop, introduces a zero to compensate for a pole at the output stage of regulator circuitry 400. Regulator circuitry 400 may also include a pole at the VAMP terminal. Equation 1 below corresponds to the frequency at which the zero is introduced due to capacitor 402 (e.g., when capacitor 404 is not included).

[0054]

[0055] In Equation 1 above, gmpass is the transconductance of pass transistor 106, Cload is the capacitance of load capacitor 220, Rfbup is the resistance of resistor 206, and Ccomp1 is the capacitance of capacitor 402. Although a zero can be used to mitigate a pole at the output stage of regulator circuitry 400, a capacitor introduces a complex conjugate zero whenever the value in the square root is less than zero. A complex conjugate zero in an open loop leads to a complex conjugate pole in a closed loop. Therefore, to mitigate the complex conjugate zero, example capacitor 404 can be added to regulator circuitry 400. The structure of capacitor 402 allows UGB to be independent of the transconductance of pass transistor 106 and decoupling capacitor 220 without affecting the output voltage. Alternatively, UGB depends on the transconductance of gain stage 200 (e.g., UGB = gm_err_amp / C0, where gm_err_amp is the transconductance of gain stage 200 and C0 corresponds to the capacitance between the control terminal and the second current terminal of transistor 106).

[0056] Figure 4 The example capacitor 404 includes two terminals. A first terminal of the capacitor 404 is coupled to and / or structured to be coupled to an output terminal (LDO_out) of the linear regulator circuitry 400, the current limit circuitry 108, the capacitor 220, the load 119, a second current terminal of the transistor 106 (e.g., directly or via an external terminal, such as Figure 1 2 and / or 2) and the first terminal of resistor 206. The second terminal of capacitor 404 is coupled to the second terminal of resistor 206, the first terminal of resistor 208, the second terminal of capacitor 402, and the second input terminal of gain stage 200. Utilizing the configuration of capacitors 402 and 404, regulator compensation circuitry 400 utilizes capacitor voltage division to compensate for poles and complex conjugate zeros. Capacitor 404 adds a degree of freedom to equation 1 above, introducing a zero at a frequency corresponding to equation 2 below, while mitigating the complex conjugate zero of equation 1.

[0057]

[0058] In Equation 1 above, Ccomp2 corresponds to the capacitance of capacitor 404. As shown in Equation 2 above, the capacitance of capacitor 404 may be reduced to a value of zero by the square root, thereby mitigating the complex conjugate zero of Equation 1 above.

[0059] Figure 5 An example regulator circuit system 500 is described, which includes Figure 2 The regulator compensation circuit system 202 combines Figure 2 An alternative circuit implementation of the regulator circuit system 102 is provided. Figure 5 Include Figure 2 Pass transistor 106 , current limiting circuitry 108 , load 119 , resistors 206 , 208 , and capacitor 220 . Figure 5 Further comprising for implementing Figure 2 Regulator compensation circuitry 501 of the regulator compensation circuitry 202. Regulator compensation circuitry 501 includes an example resistor 502 and an example capacitor 504. Figure 5 The second terminal of the current transistor 106 and the first terminal of the resistor 206 are directly coupled, but the terminals may be connected to two external terminals (e.g., Figure 2 The terminal connections are shown in Figure 1 and / or terminals 114, 116) of 2 are coupled.

[0060] Figure 5 Example resistor 502 includes two terminals. A first terminal of resistor 502 is coupled to current limit circuitry 108, an output terminal of gain stage 200, and a current terminal of transistor 106. A second terminal of resistor 502 is coupled to a first terminal of capacitor 504. Capacitor 504 includes two terminals. A first terminal of capacitor 504 is coupled to a second terminal of resistor 502. A second terminal of capacitor 504 is coupled to a second terminal of resistor 206, a first terminal of resistor 208, and a second input terminal of gain stage 200. Resistor 502 and capacitor 504 are connected in series.

[0061] exist Figure 5 In the example of , the regulator compensation circuitry 501 introduces a zero point through a resistor divider method, where the frequency at which the zero point is introduced is based on the resistance of resistors 502, 206, as shown in Equation 3 below.

[0062]

[0063] In Equation 3 above, Rcomp1 is the resistance of resistor 502. Figure 4structure, Figure 5 Regulator compensation circuitry 501 introduces a degree of freedom into Equation 1 using the resistance of resistor 502. Thus, the square root of the resistance of resistor 502 can be reduced to zero, thereby mitigating the complex conjugate zero associated with Equation 1 above (e.g., reducing complex conjugation). Complex conjugation can be more problematic when voltage regulator 500 supplies lower currents. Therefore, the resistance of resistor 502 and the capacitance of capacitor 504 can be selected to prevent complex conjugation at the lower frequency spectrum of the supplied output current while minimizing silicon area. The closed-loop response of regulator circuitry 500 can be equivalent to a second-order Butterworth filter equation, as it provides an underdamped response. The first-order Butterworth filter equation is given by Equation 4 below.

[0064]

[0065] The closed loop response may be equivalent to a second order Butterworth filter and may be adjusted to determine the resistance of resistor 502 may be calculated. The condition is given by Equation 5 below.

[0066]

[0067] If the capacitance of capacitor 504 and the resistance of resistor 206 are fixed based on equations 4 and 5 above, the resistance of resistor 502 can be determined to satisfy equation 3 above. The structure of capacitor 504 allows UGB to be independent of the transconductance of pass transistor 106 and decoupling capacitor 220 without affecting the output voltage. Alternatively, UGB depends on the transconductance of gain stage 200 (e.g., UGB = (gm_err_amp / C0)(Rfbup / (Rfbup+Rcomp1))).

[0068] Figure 6 An example regulator circuit system 600 is illustrated, which includes a combination of Figure 2 The regulator circuit system 102 Figure 2 An alternative circuit implementation of the regulator compensation circuitry 202 of FIG. 1 is provided that improves the phase margin at higher output currents. Figure 6 Include Figure 2 Pass transistor 106 , current limiting circuitry 108 , load 119 , resistors 206 , 208 , and capacitor 220 . Figure 6 Further comprising for implementing Figure 2 The regulator compensation circuit system 601 of the regulator compensation circuit system 202. The regulator compensation circuit system 601 includes Figure 5The example resistor 502 and the example capacitor 504 of the regulator compensation circuit system 601 further include the example resistor 602 and the capacitor 604. Although Figure 6 The second terminal of the current transistor 106 and the first terminal of the resistor 206 are directly coupled, but the terminals may be connected to two external terminals (e.g., Figure 2 The terminal connections are shown in Figure 1 and / or terminals 114, 116) of 2 are coupled.

[0069] Figure 6 Example resistor 602 includes two terminals. A first terminal of resistor 602 is coupled to current limit circuitry 108, the output terminal of gain stage 200, a first terminal of resistor 502, and a current terminal of transistor 106. A second terminal of resistor 602 is coupled to a first terminal of capacitor 604. Capacitor 604 includes two terminals. A first terminal of capacitor 604 is coupled to a second terminal of resistor 602. A second terminal of capacitor 604 is coupled to a second terminal of resistor 502 and a first terminal of capacitor 504. Resistor 602 and capacitor 604 are connected in series. The series connection of resistor 602 and capacitor 604 is coupled in parallel with resistor 502.

[0070] Resistor 602 and capacitor 604 are added to increase and / or otherwise improve the phase margin for high output current situations. When the output current is high (e.g., 500 milliamperes (mA)), the phase margin may decrease (e.g., from 90 degrees) to 40 degrees, thereby making the regulator circuitry less stable. As the transconductance of pass transistor 106 increases, the poles and zeros move to track the change in transconductance. The increased gap causes phase degradation. To mitigate the reduction in phase margin at high currents, the lower resistance of resistor 502 is beneficial at higher frequencies. Therefore, the example resistor 602 and capacitor 604 are included to increase the phase margin for higher frequency situations. Capacitor 604 ensures that during high frequency situations, resistors 502 and 602 are structured in parallel, thereby reducing the resistance between the output terminal of gain stage 200 and the second input terminal of gain stage 200 (e.g., via capacitor 504). During low frequency conditions, capacitor 604 prevents and / or decouples the parallel connection, and the resistance between the output terminal of gain stage 200 and the second input terminal of gain stage 200 varies with the resistance of resistor 502. The frequency at which the resistance and / or impedance begins to decrease is given by Equation 6 below.

[0071]

[0072] In Equation 6 above, Rcomp2 is the resistance of resistor 602, and Ccomp2 is the capacitance of capacitor 604. Using resistor 602 and capacitor 604, the phase margin at high frequency can be increased from 40 degrees to 78 degrees, thereby increasing the stability of regulator circuitry 600. Figure 7 In FIG, the structure of capacitor 504 allows UGB to be independent of the transconductance of pass transistor 106 and decoupling capacitor 220 without affecting the output voltage. Instead, UGB depends on the transconductance of gain stage 200 (eg, UGB = (gm_err_amp / C0)(Rfbup / (Rfbup+(Rcomp1||Rcomp2)))).

[0073] Although the parallel connected resistors 602, 604 are described in conjunction with the compensation circuitry 601, the parallel connected resistor 602 and capacitor 604 may be implemented as Figure 4 The capacitor 402 of the compensation circuit system 401 is connected in parallel.

[0074] Figure 7 An example regulator circuit system 700 is illustrated, which includes a combination of Figure 2 The regulator circuit system 102 Figure 2 An alternative circuit implementation of the regulator compensation circuitry 202 of FIG. 1 is provided that improves the phase margin at higher output currents. Figure 7 Include Figure 2 Pass transistor 106 , current limiting circuitry 108 , load 119 , resistors 206 , 208 , and capacitor 220 . Figure 7 Further comprising for implementing Figure 2 The regulator compensation circuit system 701 of the regulator compensation circuit system 202. The regulator compensation circuit system 701 includes Figure 5 The example resistor 502 and the example capacitor 504 and Figure 6 The example resistor 602 and capacitor 604. The example regulator compensation circuit system 701 further includes an example capacitor 702. Although Figure 7 The second terminal of the current transistor 106 and the first terminal of the resistor 206 are directly coupled, but the terminals may be connected to two external terminals (e.g., Figure 2 The terminal connections are shown in Figure 1 and / or terminals 114, 116) of 2 are coupled.

[0075] Figure 7Capacitor 702 has two terminals. A first terminal of capacitor 702 is coupled to current limiting circuitry 108, an output terminal of gain stage 200, a first terminal of resistor 502, a first terminal of resistor 602, and a current terminal of transistor 106. A second terminal of capacitor 702 is coupled to a second terminal of capacitor 604, a second terminal of resistor 502, and a first terminal of capacitor 504. The capacitor is coupled in parallel to resistor 502 and the series connection of resistor 602 and capacitor 604. Capacitor 702 can be added to even further improve the phase margin at high frequencies where pass transistor 106 is not operating (e.g., no gain). In this way, the poles and zeros of linear regulator 701 are based on a combination of passive elements (e.g., resistors and capacitors). The values ​​of the phase difference between the two components are provided in equations 7 and 8 below. Figure 2 The poles and zeros at the feedback point of the regulator circuit system 700.

[0076]

[0077] In equations 7 and 8 above, Ccomp3 corresponds to the capacitance of capacitor 702, and the values ​​of R' and R'comp are shown in equations 9 and 10 below.

[0078] R′ comp =R comp1 ||R comp2 (Equation 9)

[0079]

[0080] Although the parallel-connected capacitors 702 are described in conjunction with the compensation circuitry 701, the parallel-connected capacitors 702 may be implemented as Figure 4 The capacitor 402 of the compensation circuit system 401 is connected in parallel.

[0081] Figure 8 It means that Figure 1 Flowchart of method and / or example operations 800 performed and / or instantiated by the processor circuitry or any other circuitry of the power management circuitry 102 of the embodiment of the present invention. Figure 1-2 The power management circuit system 102 describes Figure 8 Although not specifically described herein, the instructions and / or operations may be described in conjunction with any type of circuitry implemented in any type of system and / or as a stand-alone circuit.

[0082] Figure 8The machine-readable instructions and / or operations 800 of the embodiment begin at block 802, where the voltage regulator circuitry 104 uses the example gain stage 200 to regulate the output voltage at the output terminal 114. As described above, the gain stage 200 compares the scaled output voltage to a reference voltage and outputs a voltage based on the difference between the scaled output voltage and the reference voltage. The output voltage is applied to the control terminal of the transistor 106 to regulate the power supply voltage to the desired output voltage using negative feedback (e.g., the transistor 106 regulates the output voltage based on the amount of voltage at the control terminal of the transistor 106).

[0083] At block 804, the example gain stage 216 of the current limiting circuitry 108 determines whether the output voltage of the gain stage 200 (e.g., VAMP corresponding to the control terminal of the pass transistor 106) meets (e.g., is greater than) a threshold voltage (e.g., VTRIG) corresponding to the output voltage at the output terminal 114. The threshold voltage corresponding to the output voltage at the output terminal 114 is the voltage at the first current terminal of the transistor 214. As described above, the current source circuitry 212 generates a current through the diode-connected transistor 214 to generate the VTRIG voltage at the first current terminal. The VTRIG voltage is the sum of the output voltage at the output terminal 114 and the VGS of the transistor 106. The VTRIG voltage is determined by the current flowing from the current source circuitry 212 through the diode transistor 214, which generates VGS with respect to the output voltage. If the gain stage 216 determines that the VAMP voltage is greater than the VTRIG voltage, the gain stage 216 determines that the output current is too high (e.g., greater than a threshold) and takes steps to reduce the output current. If the gain stage 216 determines that the VAMP voltage is lower than the VTRIG voltage, the gain stage 216 continues to allow the voltage regulator circuitry 104 to regulate the output voltage.

[0084] If the example gain stage 216 determines that the output voltage of the gain stage 200 satisfies a threshold voltage (e.g., VTRIG) corresponding to the output voltage at the output terminal 114 (block 804: YES), the gain stage 216 enables and controls the pull-down transistor 218 to reduce the voltage at the control terminal of the pass transistor 106, thereby limiting the flow of current drawn by the load 119 at the output terminal 114 (block 806), and control returns to block 804. As described above, enabling the pull-down transistor 218 causes current to be drawn from the gain stage 200, which reduces the voltage at the gate terminal of the pass transistor 106 to limit the amount of current drawn from the pass transistor 106. If the example gain stage 216 determines that the output voltage of the gain stage 200 does not satisfy the threshold voltage (e.g., VTRIG) corresponding to the output voltage at the output terminal 114 (block 804: NO), the gain stage 216 disables the pull-down transistor 218 and control returns to block 802. As described above, disabling the pull-down transistor 218 prevents the pull-down transistor 218 from reducing the voltage at the control terminal of the pass transistor 106, thereby allowing the voltage regulator circuitry 104 to regulate the output voltage without limiting the output current by the current limit circuitry 108. If, at block 808, the transistor 218 is already disabled, the gain stage 216 continues to output a signal to keep the pull-down transistor 218 disabled, allowing the voltage regulator circuitry 104 to control the output voltage.

[0085] Figure 2 Implementation Figure 1 108. However, Figure 2 One or more of the elements, processes, and / or devices described in the drawings may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0086] also, Figure 2 The gain stages 200, 216, regulator compensation circuitry 202, transistors 106, 214, 218, resistors 206, 208, and current source circuitry 212, and / or more generally, regulator circuitry 104 and / or current limit circuitry 108, may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, Figure 2Any of the gain stages 200, 216, the regulator compensation circuitry 202, the transistors 106, 214, 218, the resistors 206, 208, and the current source circuitry 212, and / or more generally, the regulator circuitry 104 and / or the current limit circuitry 108, may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs).

[0087] When reading any device or system claims of this patent that include pure software and / or firmware implementations, Figure 2 At least one of the gain stages 200, 216, regulator compensation circuitry 202, transistors 106, 214, 218, resistors 206, 208, and current source circuitry 212, and / or more generally, regulator circuitry 104 and / or current limit circuitry 108, is expressly defined herein as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., comprising software and / or firmware. Further, Figure 2 The gain stages 200, 216, regulator compensation circuitry 202, transistors 106, 214, 218, resistors 206, 208, and current source circuitry 212, and / or more generally, regulator circuitry 104 and / or current limit circuitry 108, may include in addition to or in place of Figure 2 One or more of those elements, processes, and / or devices described, and / or may include more than one of any or all of the elements, processes, and devices described. As used herein, the phrase "communicate," including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-time events.

[0088] Figure 8 The display is used for implementation Figure 1Flowcharts of example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof for the current limiting circuitry 108 of FIG. 1 and / or 2 are provided. The machine-readable instructions may be one or more executable programs or portions of executable programs for execution by a computer processor. The programs may be embodied in software stored on a non-transitory computer-readable storage medium such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disc, or memory associated with the processor, but the entire program and / or portions thereof may alternatively be executed by a device other than the processor and / or embodied in firmware or dedicated hardware.

[0089] Furthermore, despite the reference Figure 8 The flowchart illustrated in the Figures 1 and 2 describes an example procedure, but many other methods of implementing the current limit circuitry 108 may be used instead. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without executing software or firmware.

[0090] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like. The machine-readable instructions described herein may be stored as data (e.g., portions of instructions, code, representations of code, and the like) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., a server). The machine-readable instructions may require one or more of installation, modification, adaptation, update, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, and the like to be directly readable, interpretable, and / or executable by a computing device and / or another machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and stored on separate computing devices, where the parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program, such as the program described herein.

[0091] In another example, the machine-readable instructions may be stored in a state in which they can be read by a computer, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding program may be configured (e.g., to store settings, input data, record network addresses, etc.) before they can be fully or partially executed. Thus, the described machine-readable instructions and / or corresponding program encompass such machine-readable instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or program when stored or otherwise at rest or in transmission.

[0092] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0093] As mentioned above, Figure 8 The example processes of may be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on a non-transitory computer and / or machine-readable medium, such as a hard drive, flash memory, read-only memory, optical disc, digital versatile disc, cache, random access memory, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for a short period of time, as a temporary buffer and / or cache of information). As used herein, the term non-transitory computer-readable medium is expressly defined to include any type of computer-readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media.

[0094] Example methods, apparatus, and articles of manufacture have been described to improve the accuracy and / or efficiency of current limiting circuitry. The described methods, apparatus, and articles of manufacture improve the accuracy and / or efficiency of current limiting circuitry using a diode-connected device, a current source, and a gain stage.

[0095] Although certain example methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.

[0096] When identifying multiple elements or components that can be referred to individually, the descriptors "first," "second," "third," etc. are used herein. Unless otherwise specified or indicated by the context in which such descriptors are used, such descriptors do not confer any priority, physical order, placement in a list, or temporal ordering, but are merely used as labels to refer to multiple elements or components individually to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in a specific embodiment, while the same element may be referred to by a different descriptor, such as "second" or "third," in the claims. In such cases, such descriptors are used solely for convenience in referring to the multiple elements or components.

[0097] In this specification and claims, unless otherwise indicated, the terms "including" and "having" and variations thereof are inclusive, similar to the term "comprising." Unless otherwise indicated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. In another example, "about," "approximately," or "substantially" preceding a value means + / - 5% of the stated value. In another example, "about," "approximately," or "substantially" preceding a value means + / - 1% of the stated value.

[0098] As used herein, the terms "couple," "coupled," "couples," and variations thereof may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: in a first example, device A is coupled to device B; or in a second example, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not materially alter the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A. Furthermore, the terms "couple," "coupled," "couples," or variations thereof encompass indirect or direct electrical or mechanical connections.

[0099] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function at the time of manufacture by the manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0100] Despite Figure 1-7Although not all are separately labeled, the components or elements of the systems and circuits described therein have one or more conductors or terminals that allow signals to enter and / or exit the components or elements. The conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (including, for example, input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0101] As used herein, a "terminal" of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component generally refers to a conductor, such as a wire, trace, pin, pad, or other connector or interconnect, that enables the component, device, system, etc. to be electrically or mechanically connected to another component, device, system, etc. A terminal can be used, for example, to receive or provide an analog or digital electrical signal (or simply, a signal) or to electrically connect to a common or ground reference. Thus, an input terminal or input is used to receive a signal from another component, device, system, etc. An output terminal or output is used to provide a signal to another component, device, system, etc. Other terminals can be used to connect to a common, ground, or voltage reference, such as a reference terminal or ground terminal. A terminal of an IC or PCB may also be referred to as a pin (vertical conductor) or a pad (planar conductor). A node refers to the connection point or interconnection point between two or more terminals. An example number of terminals and nodes may be shown. However, depending on the specific circuit or system topology, there may be more or fewer terminals and nodes. However, in some cases, "terminal," "node," "interconnect," "pad," and "pin" are used interchangeably.

[0102] Example methods, apparatus, systems, and articles of manufacture corresponding to current limiting circuitry with controlled current variation are described herein. Further examples and combinations thereof include the following: Example 1 includes a circuit comprising: a first amplifier having a first input terminal, a second input terminal, and an output terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor being coupled to a power supply voltage terminal, the second terminal of the first transistor being structured to be coupled to the second input terminal of the first amplifier, and the control terminal of the first transistor being coupled to the output terminal of the first amplifier; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor being coupled to the control terminal of the second transistor, and the second terminal of the second transistor being coupled to the second terminal of the first transistor; and a second amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second amplifier being coupled to the first terminal of the second transistor, and the second input terminal of the second amplifier being coupled to the output terminal of the first amplifier.

[0103] Example 2 includes the circuit of Example 1, further including a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the output terminal of the first amplifier, the second terminal of the third transistor being structured to be coupled to a ground terminal, and the control terminal of the third transistor being coupled to the output terminal of the second amplifier.

[0104] Example 3 includes the circuit of Example 1, further including a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to the power supply voltage terminal, and the second terminal of the current source circuit system being coupled to the first terminal of the second transistor and the first input terminal of the second amplifier.

[0105] Example 4 includes the circuit of Example 1, wherein the second terminal of the first transistor is structured to be coupled to the second input terminal of the first amplifier via a resistor.

[0106] Example 5 includes the circuit of Example 1, further including a compensation circuit system having a first terminal and a second terminal, the first terminal of the compensation circuit system being coupled to the output terminal of the first amplifier, and the second terminal of the compensation circuit system being coupled to the second input terminal of the first amplifier.

[0107] Example 6 includes the circuit of Example 5, wherein the compensation circuit system includes: a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output terminal of the first amplifier; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the second terminal of the resistor, the second terminal of the capacitor being coupled to the second input terminal of the first amplifier.

[0108] Example 7 includes the circuit of Example 6, wherein the resistor is a first resistor and the capacitor is a first capacitor, the circuit further including: a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the output terminal of the first amplifier and the control terminal of the first transistor; and a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the second terminal of the second resistor, the second terminal of the second capacitor being coupled to the second terminal of the first resistor and the first terminal of the first capacitor.

[0109] Example 8 includes the circuit of Example 1, wherein the first input terminal of the first amplifier is a non-inverting terminal, and the second input terminal of the first amplifier is an inverting terminal.

[0110] Example 9 includes the circuit of Example 1, wherein the first input terminal of the second amplifier is an inverting terminal, and the second input terminal of the second amplifier is a non-inverting terminal.

[0111] Example 10 includes an apparatus comprising: a voltage regulator configured to control a first transistor to regulate an output voltage to a desired value; and a current limiting circuit system configured to enable a second transistor to reduce an output current when a voltage at a control terminal of the first transistor satisfies a threshold.

[0112] Example 11 includes the apparatus of Example 10, wherein the current limiting circuitry is configured to disable the second transistor when the voltage at the control terminal of the first transistor is below the threshold.

[0113] Example 12 includes the apparatus of Example 10, wherein the threshold is a sum of the output voltage and a gate-source voltage of a diode-connected transistor in the current limiting circuitry.

[0114] Example 13 includes the apparatus of Example 10, wherein the current limiting circuitry includes current source circuitry and a diode-connected transistor to generate the threshold.

[0115] Example 14 includes the apparatus of Example 10, wherein the current limit circuitry is configured to compare the voltage at the control terminal of the first transistor to the threshold value.

[0116] Example 15 includes the apparatus of Example 10, wherein reducing the output current reduces the output voltage and the voltage at the control terminal of the first transistor.

[0117] Example 16 includes the apparatus of Example 15, wherein the reduction in the output voltage reduces the threshold.

[0118] Example 17 includes the apparatus of Example 10, wherein the current limiting circuitry is configured to fix a gate-source voltage of the first transistor.

[0119] Example 18 includes a circuit comprising: a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor being coupled to the control terminal of the first transistor, and the second terminal of the first transistor being structured to be coupled to an output terminal of a voltage regulator; and a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to a power supply voltage terminal, the second terminal of the current source circuit system being coupled to the first terminal of the first transistor and the control terminal of the first transistor; an amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the amplifier being coupled to the first terminal of the first transistor and the second terminal of the current source circuit system, and the second input terminal of the amplifier being structured to be coupled to a terminal of the voltage regulator; and a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor being structured to be coupled to the terminal of the voltage regulator, the second terminal of the second transistor being coupled to a ground terminal, and the control terminal of the second transistor being coupled to the output terminal of the amplifier.

[0120] Example 19 includes the circuit of Example 18, wherein the first input terminal of the amplifier is an inverting terminal, and the second input terminal of the amplifier is a non-inverting terminal.

[0121] Example 20 includes the circuit of Example 18, wherein the amplifier is a first amplifier, and the terminal of the voltage regulator corresponds to the output of the second amplifier and the control terminal of a third transistor, and the output terminal of the voltage regulator corresponds to the terminal of the third transistor.

[0122] Example 21 includes the circuit of Example 18, wherein the first transistor is a diode-connected transistor.

[0123] Example 22 includes the circuit of Example 18, wherein the second transistor is a pull-down transistor.

[0124] Modifications of the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. A circuit comprising: a first amplifier having a first input terminal, a second input terminal, and an output terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor being coupled to a power supply voltage terminal, the second terminal of the first transistor being structured to be coupled to the second input terminal of the first amplifier, and the control terminal of the first transistor being coupled to the the output terminal of the first amplifier; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor being coupled to the control terminal of the second transistor, and the second terminal of the second transistor being coupled to the second terminal of the first transistor; as well as A second amplifier has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second amplifier being coupled to the first terminal of the second transistor, and the second input terminal of the second amplifier being coupled to the output terminal of the first amplifier.

2. The circuit of claim 1 , further comprising a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor being coupled to the output terminal of the first amplifier, the second terminal of the third transistor being structured to be coupled to a ground terminal, and the control terminal of the third transistor being coupled to the output terminal of the second amplifier.

3. The circuit of claim 1 , further comprising a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to the supply voltage terminal, and the second terminal of the current source circuit system being coupled to the first terminal of the second transistor and the first input terminal of the second amplifier. 4 . The circuit of claim 1 , wherein the second terminal of the first transistor is structured to be coupled to the second input terminal of the first amplifier via a resistor.

5. The circuit of claim 1 , further comprising compensation circuitry having a first terminal and a second terminal, the first terminal of the compensation circuitry coupled to the output terminal of the first amplifier, and the second terminal of the compensation circuitry coupled to the second input terminal of the first amplifier.

6. The circuit of claim 5 , wherein the compensation circuitry comprises: a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the output terminal of the first amplifier; and A capacitor has a first terminal and a second terminal, the first terminal of the capacitor being coupled to the second terminal of the resistor, the second terminal of the capacitor being coupled to the second input terminal of the first amplifier.

7. The circuit of claim 6 , wherein the resistor is a first resistor and the capacitor is a first capacitor, the circuit further comprising: a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the output terminal of the first amplifier and the control terminal of the first transistor; and A second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the second terminal of the second resistor, the second terminal of the second capacitor being coupled to the second terminal of the first resistor and the first terminal of the first capacitor. 8 . The circuit of claim 1 , wherein the first input terminal of the first amplifier is a non-inverting terminal, and the second input terminal of the first amplifier is an inverting terminal. 9 . The circuit of claim 1 , wherein the first input terminal of the second amplifier is an inverting terminal, and the second input terminal of the second amplifier is a non-inverting terminal.

10. A device comprising: a voltage regulator configured to control the first transistor to regulate the output voltage to a desired value; as well as Current limiting circuitry is configured to enable a second transistor to reduce output current when a voltage at a control terminal of the first transistor satisfies a threshold.

11. The apparatus of claim 10, wherein the current limiting circuitry is configured to disable the second transistor when the voltage at the control terminal of the first transistor is below the threshold.

12. The apparatus of claim 10, wherein the threshold is a sum of the output voltage and a gate-source voltage of a diode-connected transistor in the current limiting circuitry.

13. The apparatus of claim 10, wherein the current limiting circuitry comprises current source circuitry and a diode-connected transistor to generate the threshold.

14. The apparatus of claim 10, wherein the current limit circuitry is configured to compare the voltage at the control terminal of the first transistor to the threshold.

15. The apparatus of claim 10, wherein reducing the output current reduces the output voltage and the voltage at the control terminal of the first transistor.

16. The apparatus of claim 15, wherein the reduction in the output voltage lowers the threshold.

17. The apparatus of claim 10, wherein the current limiting circuitry is configured to fix a gate-source voltage of the first transistor.

18. A circuit comprising: a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor being coupled to the control terminal of the first transistor, and the second terminal of the first transistor being structured to be coupled to an output terminal of a voltage regulator; as well as a current source circuit system having a first terminal and a second terminal, the first terminal of the current source circuit system being coupled to a supply voltage terminal, the second terminal of the current source circuit system being coupled to the first terminal of the first transistor and the control terminal of the first transistor; an amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the amplifier being coupled to the first terminal of the first transistor and the second terminal of the current source circuitry, and the second input terminal of the amplifier being structured to be coupled to a terminal of the voltage regulator; as well as a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor being structured to be coupled to the terminal of the voltage regulator, the second terminal of the second transistor being coupled to a ground terminal, and the control terminal of the second transistor being coupled to the output terminal of the amplifier.

19. The circuit of claim 18, wherein the first input terminal of the amplifier is an inverting terminal, and the second input terminal of the amplifier is a non-inverting terminal.

20. The circuit of claim 18, wherein the amplifier is a first amplifier and the terminals of the voltage regulator correspond to the output of a second amplifier and a control terminal of a third transistor, the output terminal of the voltage regulator corresponding to a terminal of the third transistor.

21. The circuit of claim 18, wherein the first transistor is a diode-connected transistor.

22. The circuit of claim 18, wherein the second transistor is a pull-down transistor.

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