Utilizing virtual address (VA) spatial locality by using translation lookaside buffer (TLB) entry compression in processor-based device

Abstract

Utilizing virtual address (VA) spatial locality in a processor-based device by using translation lookaside buffer (TLB) entry compression is disclosed herein. In some aspects, a processor-based apparatus includes a TLB including a plurality of TLB entries, each TLB entry including a tag and a plurality of data portions, and further including a memory management unit (MMU). The MMU is configured to receive a memory access request including a VA, and determine that a TLB access result to the TLB for a page VA of the VA is a miss. In response, the MMU generates a TLB entry where the tag of the TLB entry includes the page VA, the plurality of data portions includes a corresponding plurality of pages PA, a first data portion of the plurality of data portions includes a page PA corresponding to the page VA, and one or more second data portions of the plurality of data portions include a corresponding PA of a subsequent sequential page VA following the page VA.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 18 / 168,857, filed on February 14, 2023, entitled “EXPLOITING VIRTUAL ADDRESS (VA) SPATIAL LOCALITY USING TRANSLATION LOOKASIDE BUFFER (TLB) ENTRY COMPRESSION IN PROCESSOR-BASED DEVICES,” which is incorporated herein by reference in its entirety. Background Art

[0003] I. Technical Field

[0004] The technology of this disclosure generally relates to translation lookaside buffers (TLBs) in processor-based devices.

[0005] II. Background Technology

[0006] Microprocessors, also referred to herein as "processors," perform computing tasks for various applications. Traditional processors utilize virtual memory, a memory management mechanism that maps memory addresses referenced by an executing process (i.e., virtual addresses, or VAs) to physical addresses (PAs) in system memory. By using virtual memory, processor-based systems can provide access to a virtual memory space larger than the actual physical memory space and enhance security between processes through memory isolation. The mapping between VAs and their corresponding PAs is accomplished using a data structure called a page table. To further improve performance, page table entries retrieved from the page table are cached in a data structure called a translation lookaside buffer (TLB) during the VA-to-PA translation process.

[0007] While using a TLB can effectively reduce memory access latency within a processor, the TLB can require a significant portion of the processor's physical area. Therefore, it may be desirable to reduce the area occupied by the TLB without affecting TLB performance, and / or to improve TLB performance without increasing the physical footprint of the TLB. Summary of the Invention

[0008] Various aspects disclosed in the specific embodiments include exploiting virtual address (VA) space locality in a processor-based device by using translation lookaside buffer (TLB) entry compression. Related apparatus and methods are also disclosed. In this regard, according to some exemplary aspects disclosed herein, a processor-based device includes a memory management unit (MMU) communicatively coupled to a TLB providing a plurality of TLB entries. Each TLB entry is configured to store a tag including a page VA and further store a plurality of data portions, each data portion storing a page physical address (PA). A first data portion of the plurality of data portions stores a page PA corresponding to the page VA of the tag (i.e., the page PA obtained by an address translation operation on the page VA). Additionally, one or more second data portions store one or more page PAs corresponding to subsequent sequential page VAs following the page VA of the tag.

[0009] In exemplary operation, an MMU is configured to receive a first memory access request including a first VA. The MMU determines that a first TLB access to a TLB for a first page VA of the first VA results in a miss, and in response, generates a TLB entry for the first page VA. Some aspects may provide that generating the TLB entry includes the MMU first performing an address translation operation to obtain a page PA corresponding to the first page VA and storing the page PA in a first data portion of the TLB entry. If one or more page PAs corresponding to subsequent sequential page VAs are contiguous in physical memory space, the MMU may, based on the address translation operation, obtain the one or more page PAs for these subsequent sequential page VAs (e.g., by obtaining descriptors for these page PAs in the same address translation operation). The MMU then stores the one or more page PAs corresponding to the subsequent sequential page VAs in corresponding one or more second data portions of the TLB entry. If the one or more page PAs are not contiguous in physical memory space, the MMU may then pre-fetch address translations for each of the subsequent sequential page VAs to obtain the one or more page PAs. The MMU then updates the one or more second data portions of the TLB entry with the one or more page PAs corresponding to the subsequent sequential page VAs.

[0010] Some aspects may provide that the MMU also receives a second memory access request including the first VA and determines that a second TLB access result of the TLB for the first page VA of the first VA is a hit. In response to the TLB hit, the MMU performs the memory access operation by using the page PA in a first data portion of the plurality of data portions in the TLB entry. Some aspects may further provide that the MMU receives a third memory access request including the second VA and determines that the second page VA of the second VA corresponds to a subsequent sequential page VA after the first page VA. Subsequently, the MMU performs a subsequent memory access operation by using the page PA of a second data portion of one or more second data portions corresponding to the subsequent sequential page VA.

[0011] On the other hand, a processor-based device is disclosed. The processor-based device includes a TLB, the TLB including multiple TLB entries, wherein each TLB entry includes a tag and multiple data portions. The processor-based device also includes an MMU, the MMU configured to receive a first memory access request including a first VA. The MMU is further configured to determine that a first TLB access result performed on the TLB for a first page VA of the first VA is a miss. The MMU is also configured to generate a TLB entry for the first page VA in response to determining that the first TLB access result performed on the TLB for the first page VA of the first VA is a miss, wherein the tag of the TLB entry includes the first page VA, the multiple data portions include corresponding multiple page PAs, a first data portion of the multiple data portions includes a page PA corresponding to the first page VA, and one or more second data portions of the multiple data portions include corresponding one or more page PAs of corresponding subsequent sequential page VAs after the first page VA.

[0012] On the other hand, a processor-based device is disclosed. The processor-based device includes a component for receiving a first memory access request including a first VA. The processor-based device also includes a component for determining that a first TLB access result of a first page VA of the first VA to the TLB of the processor-based device is a miss. The processor-based device also includes a component for generating a TLB entry for the first page VA in response to determining that the first TLB access result of the first page VA of the first VA to the TLB is a miss, wherein the TLB entry includes a tag, the tag includes the first page VA, the TLB entry includes multiple data portions, the multiple data portions include corresponding multiple page PAs, a first data portion of the multiple data portions includes a page PA corresponding to the first page VA, and one or more second data portions of the multiple data portions include corresponding one or more page PAs of corresponding subsequent sequential page VAs after the first page VA.

[0013] On the other hand, a method for exploiting VA spatial locality in a processor-based device by using TLB entry compression is disclosed. The method includes receiving, by an MMU of the processor-based device, a first memory access request including a first VA. The method also includes determining, by the MMU, that a first TLB access to a TLB of the processor-based device for a first page VA of the first VA results in a miss. The method also includes generating, by the MMU, a TLB entry for the first page VA in response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, wherein the TLB entry includes a tag, the tag includes the first page VA, the TLB entry includes multiple data portions, the multiple data portions include corresponding multiple page PAs, a first data portion of the multiple data portions includes a page PA corresponding to the first page VA, and one or more second data portions of the multiple data portions include corresponding one or more page PAs of corresponding subsequent sequential page VAs following the first page VA.

[0014] On the other hand, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor of a processor-based device to receive a first memory access request including a first VA. The computer-executable instructions also cause the processor to determine that a first TLB access to a TLB of the processor-based device for a first page VA of the first VA resulted in a miss. The computer-executable instructions also cause the processor to generate a TLB entry for the first page VA in response to determining that the first TLB access to the TLB for the first page VA of the first VA resulted in a miss, wherein the TLB entry includes a tag, the tag includes the first page VA, the TLB entry includes multiple data portions, the multiple data portions include corresponding multiple page PAs, a first data portion of the multiple data portions includes a page PA corresponding to the first page VA, and one or more second data portions of the multiple data portions include corresponding one or more page PAs of corresponding subsequent sequential page VAs after the first page VA. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of an exemplary processor-based device including a memory management unit (MMU) and a translation lookaside buffer (TLB) configured to exploit virtual address (VA) space locality by using TLB entry compression, according to some aspects;

[0016] Figure 2The block diagram illustrates exemplary operations and communication flows for using TLB entry compression according to some aspects;

[0017] Figure 3A and Figure 3B The provided flowchart illustrates a method according to some aspects of Figure 1 and Figure 2 Example operations of the MMU and TLB for exploiting VA space locality by using TLB entry compression;

[0018] Figure 4 A flowchart is provided illustrating exemplary operations for obtaining contiguous physical addresses (PAs) within a physical memory space according to some aspects;

[0019] Figure 5 A flowchart is provided illustrating exemplary operations for acquiring a PA that is not contiguous within a physical memory space according to some aspects; and

[0020] Figure 6 is a block diagram of an exemplary processor-based device that may include Figure 1 and Figure 2 The MMU and TLB in . DETAILED DESCRIPTION

[0021] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] Various aspects disclosed in the specific embodiments include exploiting virtual address (VA) space locality in a processor-based device by using translation lookaside buffer (TLB) entry compression. Related apparatus and methods are also disclosed. In this regard, according to some exemplary aspects disclosed herein, a processor-based device includes a memory management unit (MMU) communicatively coupled to a TLB providing a plurality of TLB entries. Each TLB entry is configured to store a tag including a page VA and further store a plurality of data portions, each data portion storing a page physical address (PA). A first data portion of the plurality of data portions stores a page PA corresponding to the page VA of the tag (i.e., the page PA obtained by an address translation operation on the page VA). Additionally, one or more second data portions store one or more page PAs corresponding to subsequent sequential page VAs following the page VA of the tag.

[0023] In exemplary operation, an MMU is configured to receive a first memory access request including a first VA. The MMU determines that a first TLB access to a TLB for a first page VA of the first VA results in a miss, and in response, generates a TLB entry for the first page VA. Some aspects may provide that generating the TLB entry includes the MMU first performing an address translation operation to obtain a page PA corresponding to the first page VA and storing the page PA in a first data portion of the TLB entry. If one or more page PAs corresponding to subsequent sequential page VAs are contiguous in physical memory space, the MMU may, based on the address translation operation, obtain the one or more page PAs for these subsequent sequential page VAs (e.g., by obtaining descriptors for these page PAs in the same address translation operation). The MMU then stores the one or more page PAs corresponding to the subsequent sequential page VAs in corresponding one or more second data portions of the TLB entry. If the one or more page PAs are not contiguous in physical memory space, the MMU may then pre-fetch address translations for each of the subsequent sequential page VAs to obtain the one or more page PAs. The MMU then updates the one or more second data portions of the TLB entry with the one or more page PAs corresponding to the subsequent sequential page VAs.

[0024] Some aspects may provide that the MMU also receives a second memory access request including the first VA and determines that a second TLB access result of the TLB for the first page VA of the first VA is a hit. In response to the TLB hit, the MMU performs the memory access operation by using the page PA in a first data portion of the plurality of data portions in the TLB entry. Some aspects may further provide that the MMU receives a third memory access request including the second VA and determines that the second page VA of the second VA corresponds to a subsequent sequential page VA after the first page VA. Subsequently, the MMU performs a subsequent memory access operation by using the page PA of a second data portion of one or more second data portions corresponding to the subsequent sequential page VA.

[0025] in this regard, Figure 1 1 is a schematic diagram of an exemplary processor-based device 100 including a processor 102. Processor 102 may also be referred to as a "processor core" or a "central processing unit (CPU) core," and may be an in-order processor or an out-of-order processor (OoP), and / or may be one of multiple processors 102 provided by processor-based device 100. Figure 1 In the example of FIG. 1 , the processor 102 includes an instruction processing circuit 104 including one or more instruction pipelines 10 to 10 for processing instructions 106. N These instructions are fetched by the instruction fetch circuit 110 from the instruction memory (in Figure 1The instruction memory 108 is retrieved from the processor 102 for execution. As a non-limiting example, the instruction memory 108 may be provided in the system memory of the processor-based device 100 or as part of the system memory. The processor 102 may also be provided with an instruction cache (in the Figure 1 The instruction cache 112 is used to cache the instructions 106 retrieved from the instruction memory 108 to reduce the latency of the instruction fetch circuit 110.

[0026] exist Figure 1 In the example of FIG. 1 , the instruction fetch circuit 110 is configured to provide the instruction 106 as an instruction fetch instruction 106F to one or more instruction pipelines 10 to 10 in the instruction processing circuit 104. N in order to get to the execution circuit (in the Figure 1 The instruction pipeline I0 to I1 is pre-processed before being executed. N The different processing circuits or stages across the instruction processing circuitry 104 are configured to pre-process and process the instruction fetch 106F in a series of concurrently executable steps before the instruction fetch 106F is executed by the execution circuitry 114 to improve throughput.

[0027] Continue to refer Figure 1 The instruction processing circuit 104 includes a decoding circuit 118 configured to decode the instruction fetch 106F fetched by the instruction fetch circuit 110 into a decoded instruction 106D to determine the instruction type and the required operation. The instruction type and required operation encoded in the decoded instruction 106D can also be used to determine which instruction pipeline I0 to I1 the decoded instruction 106D should be placed in. N In this example, decoded instruction 106D is placed in instruction pipelines I0 to I N The decoded instruction 106D is passed through one or more instruction pipelines and is subsequently provided to renaming circuitry 120 in instruction processing circuitry 104. Renaming circuitry 120 is configured to determine whether any register names in decoded instruction 106D should be renamed to decouple any register dependencies that may hinder parallel or out-of-order processing.

[0028] Figure 1 The instruction processing circuit 104 in the processor 102 also includes a register access circuit (in Figure 1The register access circuit 122 is labeled “register access circuitry” in the figure. The register access circuit 122 is configured to access a physical register in a physical register file (PRF) (not shown) based on a mapping entry of a logical register in a register mapping table (RMT) (not shown) mapped to a source register operand of the decoded instruction 106D, to retrieve a generated value of the executed instruction 106E in the execution circuit 114. The register access circuit 122 is further configured to provide the generated value retrieved from the executed instruction 106E as a source register operand of the decoded instruction 106D to be executed.

[0029] In addition, in the instruction processing circuit 104, in the instruction pipelines I0 to I N A scheduler circuit is set up in Figure 1 The instruction processing circuitry 104 includes a processor (labeled "scheduler circuitry" in the figure) 124, which is configured to store the decoded instruction 106D in a reserved entry until all source register operands for the decoded instruction 106D are available. The scheduler circuitry 124 issues the decoded instruction 106D to the execution circuitry 114 for execution. Write circuitry 126 is also provided in the instruction processing circuitry 104 to write or commit the generated value from the executed instruction 106E back to a memory (such as a PRF), cache memory, or system memory.

[0030] like Figure 1 As can be seen, the processor-based device 100 also includes a memory system 128 that provides an MMU 130 configured to manage memory accesses. The MMU 130 is communicatively coupled to a TLB 132 that is used to cache recently used VA to PA translations for memory pages containing instructions or data to be retrieved. It should be understood that, although for clarity, Figure 1 TLB 132 in FIG. 1 is illustrated as a separate element from MMU 130 , but in some aspects, TLB 132 may be implemented as a constituent element of MMU 130 . Figure 1 The MMU 130 is also communicatively coupled to a memory controller 134 that is configured to perform memory read and write operations on system memory 136. As a non-limiting example, system memory 136 may, in some aspects, comprise double data rate (DDR) synchronous dynamic random access memory (SDRAM).

[0031] Figure 1The MMU 130 in the processor-based device 100 is responsible for performing VA to PA address translation operations to support the virtual memory functions of the processor-based device 100. In this regard, the MMU 130 according to some aspects may include a plurality of hierarchical page tables (not shown) containing page table entries, each of which represents a mapping of a subdivision of an addressable virtual memory space having a particular size (i.e., a memory page). The mappings stored in the page table entries of the hierarchical page tables of the MMU 130 may be cached in a plurality of TLB entries 138(0) through 138(T) of the TLB 132. In this manner, frequently used VA to PA mappings do not have to be recalculated for each memory access request executed by the MMU 130.

[0032] TLB 132 may cache VA-to-PA mappings from one of multiple stages of address translation that may be performed by processor-based device 100. For example, in some aspects, processor 102 may directly execute an operating system (OS) without the use of a hypervisor or virtual machine (VM). In these aspects, TLB 132 may cache the results of stage 1 translations (i.e., VA-to-PA mappings according to the OS). Some aspects may provide that processor 102 may execute a hypervisor (not shown) that provides virtualization functionality. Within the hypervisor may be a VM (not shown), which in turn executes a guest OS (not shown). In some such aspects, TLB 132 may cache the results of stage 1 translations (i.e., mappings from the guest VA of the guest OS to the guest PA ("intermediate physical address" or "IPA")). In this context, the term "virtual address" as used herein may refer to the guest VA, while the term "physical address" may refer to the IPA. Some such aspects may provide that TLB 132 may cache the results of stage 2 translations (i.e., mappings from the IPA of the hypervisor and / or host OS to the PA). In this case, the term "virtual address" used herein may refer to IPA, and the term "physical address" may refer to PA. The functionality described herein of utilizing VA spatial locality to provide TLB entry compression is also applicable to various aspects disclosed herein.

[0033] As described above, although the use of the TLB 132 can effectively reduce memory access latency within the processor 102, the TLB 132 may require a significant portion of the physical area of ​​the processor 102. Therefore, it may be desirable to reduce the area occupied by the TLB 132 without affecting the performance of the TLB 132, and / or to improve the performance of the TLB 132 without increasing the physical footprint of the TLB 132. In this regard, in some exemplary aspects disclosed herein, the processor 102 is configured to effectively provide TLB compression by exploiting the spatial locality exhibited by VAs in the virtual memory space. In particular, each of the plurality of TLB entries 138(0) to 138(T) of the TLB 132 is configured to store a tag 140(0), 140'(0), including a page VA (not shown), and further store a plurality of data portions (in Figure 1 142(0) to 142(D), 142'(0) to 142'(D), each data portion stores a page PA (not shown). Taking TLB entry 138(0) as an example, the first data portion, such as data portion 142(0), stores a page PA corresponding to the page VA of tag 140(0) (i.e., the page PA obtained by the address translation operation of the page VA). The remaining data portions 142(1) to 142(D) of TLB entry 138(0) store page PAs corresponding to subsequent sequential page VAs following the page VA of the tag. Thus, for example, data portion 142(1) stores a page PA corresponding to the subsequent page VA in sequence following the page VA stored in data portion 142(0), and so on. Because TLB entries 138(0) through 138(T) store multiple data portions of a PA including sequential page VAs, TLB 132 may occupy a smaller area within processor 102 while maintaining performance comparable to a conventional TLB and / or achieve improved performance with minimal impact on the physical footprint of TLB 132.

[0034] In some aspects, the PAs stored in data portions 142(0) through 142(D) and / or data portions 142'(0) through 142'(D) are guaranteed to be contiguous. For example, in the case where TLB 132 stores a stage 1 translation, when the final descriptor and / or page table entry (PTE) for a VA is processed, a cache line is retrieved that contains the translation for the data portion adjacent to that VA, thereby enabling the data portions 142(0) through 142(D) and / or data portions 142'(0) through 142'(D) to be populated. However, in some aspects, such as the case where TLB 132 stores both a stage 1 translation and a stage 2 translation, the PAs stored in data portions 142(0) through 142(D) and / or data portions 142'(0) through 142'(D) may not be contiguous. As described below in conjunction with Figure 2 As detailed, in these aspects, the MMU 130 may then prefetch address translations for subsequent sequential page VAs to populate data portions 142 ( 0 ) through 142 (D) and / or data portions 142 ′ ( 0 ) through 142 ′ (D).

[0035] Figure 2 Illustrated Figure 1 Example operations of MMU 130 and TLB 132 for generating, filling, and using Figure 1 TLB entries 138(0) to 138(T) in . Figure 2 As seen, it shows Figure 1 1. The contents of TLB entry 138(0) through 138(T) are shown in greater detail as including tag 140(0) and data portions 142(0) and 142(1). Figure 2 The TLB entry 138(0) shown in the figure contains only two data portions 142(0) and 142(1), but it should be understood that the exemplary operations described below are applicable to the case where the TLB entry 138(0) contains any integer number D of data portions 142(0) to 142(D), where D>2.

[0036] Some aspects of TLB 132 may provide that the tag 140(0) and data portions 142(0) and 142(1) of a TLB entry, such as TLB entry 138(0), may include additional information or metadata. For example, tag 140(0) may also include context data (e.g., Figure 2 Context data 200, which includes information about the application and / or VM associated with TLB entry 138(0), and / or a page size indicator (indicates the size of a physical page in system memory 136). Figure 2 Similarly, in some aspects, data portions 142(0) and 142(1) may also include memory attributes (in Figure 2 Attributes in the example (labeled "Memory Attributes") 204(0) and 204(1). The TLB entry 138(0) itself may also include additional fields. Some aspects may provide that the TLB entry 138(0) may include a valid indicator (in the example Figure 2 Valid indicator 208(0) may include a bit indicator indicating whether the corresponding pages PA 206(0) and 206(1) represent a valid address translation. It should be understood that TLB entry 138(0), tag 140(0) and / or data portion 142(0) and 142(1) may include Figure 2 Other information or metadata not shown in the.

[0037] exist Figure 2 In the example of FIG, MMU 130 is configured to process a sequence 210 of memory access requests resulting from, for example, executing a memory load instruction and / or a memory store instruction (not shown). MMU 130 is configured to first receive a memory access request 212 (i.e., a memory read request or a memory write request) including a VA 214, as indicated by arrow 216. MMU 130 derives a page VA 218 for a virtual memory page of VA 214 and performs a TLB access 220 to determine whether one of TLB entries 138(0) to 138(T) stores an address translation for page VA 218. In this example, MMU 130 determines that TLB access 220 to TLB 132 results in a miss, and therefore, MMU 130 is configured to generate TLB entry 138(0) for page VA 218. Operations for generating TLB entry 138(0) may include MMU 130 first performing an address translation operation to obtain page PA 206(0) corresponding to page VA 218, and then storing page PA 206(0) in data portion 142(0) of TLB entry 138(0).

[0038] Then, the MMU 130 retrieves page PA 206(1) corresponding to the subsequent sequential page VA following page VA 218. In the event that pages PA 206(0) and 206(1) are contiguous in the physical memory space of system memory 136, the MMU 130 may retrieve page PA 206(1) corresponding to the subsequent sequential page VA following page VA 218 based on the address translation operation it performs to retrieve page PA 206(0). For example, page PA 206(1) may be retrieved during the execution of a conventional address translation operation to retrieve page PA 206(0) (e.g., by retrieving descriptors (not shown) for page PA 206(0) and page PA 206(1) in the same address translation operation). In these aspects, the MMU 130 then stores page PA 206(1) corresponding to the subsequent sequential page VA following page VA 218 in the data portion 142(1) of the TLB entry 138(0). In the event that pages PA 206(0) and 206(1) are not contiguous in the physical memory space of system memory 136, MMU 130 may then prefetch the address translation for the subsequent sequential page VA after page VA 218 to obtain page PA 206(1) (i.e., after making TLB entry 138(0) available for use within TLB 132). In these aspects, MMU 130 then updates data portion 142(1) of TLB entry 138(0) with page PA 206(1). After generating TLB entry 138(0), MMU 130 performs memory access operation 222 by using page PA 206(0) of page VA 218 of VA 214 (i.e., by using page PA 206(0) to calculate the PA of the actual memory location to be accessed).

[0039] Figure 2214. The MMU 130 in FIG. 215 later receives a memory access request 224 including VA 214, as indicated by arrow 226. The MMU 130 again derives a page VA 218 for the virtual memory page of VA 214 and performs a TLB access 228 to determine whether one of the TLB entries 138(0) through 138(T) stores the address translation for page VA 218. The TLB access 228 results in a hit, so the MMU 130 accesses TLB entry 138(0) as indicated by arrow 230 and performs a memory access operation 232 using page PA 206(0) of the data portion 142(0) of TLB entry 138(0). The MMU 130 also receives a memory access request 234 including VA 236, as indicated by arrow 238. MMU 130 derives page VA 240 for the virtual memory page of VA 236 and determines that page VA 240 corresponds to the subsequent sequential page VA following page VA 218. In response, MMU 130 performs a subsequent memory access operation 242 using page PA 206(1) of data portion 142(1).

[0040] To illustrate the Figure 1 and Figure 2 The MMU 130 and TLB 132 perform operations for exploiting VA space locality by using TLB entry compression, Figure 3A and Figure 3B A flowchart illustrating exemplary operation 300 is provided. For clarity, Figure 3A and Figure 3B When cited Figure 1 and Figure 2 It should be understood that some aspects may provide that Figure 3A and Figure 3B Some of the operations illustrated may be performed in an order different from that illustrated herein and / or may be omitted. Figure 3A The operation in starts at Figure 1 The processor-based device 100 (eg, using Figure 1 The MMU 130 in FIG. 1 receives a first VA (eg, Figure 2 214) of the first memory access request (e.g., Figure 2 212 in the memory access request) (block 302). The MMU 130 determines a first page VA for the first VA 214 (eg, Figure 2 VA 218) of the processor-based device 100 TLB (e.g., Figure 1 and Figure 2 The first TLB access (e.g., Figure 2The TLB access 220 in (block 304) results in a miss.

[0041] In response to determining that the first TLB access 220 to the TLB 132 for the first page VA 218 of the first VA 214 results in a miss, the MMU 130 generates a TLB entry for the first page VA 218 (eg, Figure 1 and Figure 2 TLB entry 138(0) in (block 306). TLB entry 138(0) includes a tag (e.g., Figure 1 and Figure 2 140(0) in FIG. 140(0)), which includes a first page VA 218 and also includes a plurality of data portions (eg, Figure 1 and Figure 2 , wherein the plurality of data portions 142 ( 0 ) to 142 ( 1 ) include a corresponding plurality of pages PA (eg, Figure 2 The first data portion of the plurality of data portions 142(0) to 142(1) is such as a plurality of pages PA 206(0) to 206(1) in FIG. Figure 1 and Figure 2 The data portion 142(0) in includes page PA corresponding to the first page VA 218 (eg, Figure 2 Additionally, one or more second data portions (eg, Figure 1 and Figure 2 The data portion 142 (1) in the first page VA 218 includes corresponding one or more pages PA of corresponding subsequent sequential pages VA after the first page VA 218 (eg, Figure 2 In the case where pages PA 206(0) to 206(1) are contiguous in physical memory space, the operations of block 306 for generating TLB entry 138(0) will be described below in conjunction with Figure 4 and in the case where pages PA 206(0) to 206(1) are not contiguous in physical memory space, the operation of block 306 for generating TLB entry 138(0) will be discussed below in conjunction with Figure 5 In some aspects, the example operations 300 may be performed in Figure 3B Continue at block 308.

[0042] Now go to Figure 3B , example operations 300 according to some aspects may continue with the MMU 130 receiving a second memory access request including the first VA 214 (eg, Figure 2224 in the memory access request 224) (block 308). The MMU 130 determines a second TLB access to the TLB 132 for the first page VA 218 of the first VA 214 (eg, Figure 2 The TLB access 228 in the TLB entry 138(0) results in a hit (block 310). In response, the MMU 130 performs a memory access operation (e.g., Figure 2 232 in the memory access operation) (block 312). Some aspects may further provide that the MMU 130 receives a second VA (eg, Figure 2 VA 236) of the third memory access request (e.g., Figure 2 234 in the memory access request) (block 314). The MMU 130 determines the second page VA of the second VA 236 (e.g., Figure 2 240) corresponding to a subsequent sequential page VA following the first page VA 218 (block 316). In response, the MMU 130 processes the first page VA 218 by using a second data portion (e.g., Figure 1 and Figure 2 to perform subsequent memory access operations (e.g., Figure 2 242 ) (block 318 ).

[0043] Figure 4 Illustrated corresponding to Figure 3A The exemplary operations 400 of block 306 in FIG. 4 may be performed by Figure 1 and Figure 2 The MMU 130 in FIG. 10 executes to generate TLB entry 138(0) if pages PA 206(0) to 206(1) are contiguous in physical memory space. For clarity, in describing Figure 4 When cited Figure 1 and Figure 2 In the Figure 4In the example operation 400, the MMU 130 first performs an address translation operation to obtain page PA 206(0) corresponding to the first page VA 218 (block 402). Subsequently, the MMU 130 stores page PA 206(0) in the first data portion 142(0) of the TLB entry 138(0) (block 404). Next, the MMU 130 obtains one or more page PAs 206(1) corresponding to subsequent sequential page VAs based on the address translation operation (block 406). As described above, the one or more page PAs 206(1) may be obtained during the performance of a conventional address translation operation to obtain page PA 206(0) (e.g., by obtaining descriptors for pages PAs 206(0) through 206(1) in the same address translation operation). Subsequently, the MMU 130 stores the one or more page PAs 206(1) corresponding to the subsequent sequential page VAs in the one or more second data portions 142(1) of the TLB entry 138(0) (block 408).

[0044] To illustrate the corresponding Figure 3A The operations of block 306 may be performed by Figure 1 and Figure 2 The MMU 130 in executes to generate TLB entry 138(0) if pages PA 206(0) to 206(1) are not contiguous in physical memory space, Figure 5 A flowchart is provided illustrating exemplary operations 500. For clarity, Figure 5 When cited Figure 1 and Figure 2 Components. Figure 5 , the exemplary operations 500 begin with the MMU 130 performing an address translation operation to obtain a page PA 206(0) corresponding to a first page VA 218 (block 502). Next, the MMU 130 stores the page PA 206(0) in the first data portion 142(0) of the TLB entry 138(0) (block 504). Subsequently, the MMU 130 pre-fetches the address translation for each of the subsequent sequential page VAs to obtain one or more page PAs 206(1) of the corresponding subsequent sequential page VAs (block 506). Subsequently, the MMU 130 updates the one or more second data portions 142(1) of the TLB entry 138(0) with the one or more page PAs 206(1) of the corresponding subsequent sequential page VAs (block 508).

[0045] According to the aspects disclosed herein and in combination Figure 1 、 Figure 2 、 Figures 3A to 3B 、 Figure 4 and Figure 5The MMU and TLB may be provided in or integrated into any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, a motor vehicle, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0046] in this regard, Figure 6 An example of a processor-based device 600 is illustrated, comprising a processor-based device incorporating Figure 1 、 Figure 2 、 Figures 3A to 3B 、 Figure 4 and Figure 5 The MMU and TLB are shown and described. In this example, the functional correspondence Figure 1 The processor-based device 600 of the processor-based device 100 in FIG. 1 includes a processor 602 including one or more CPUs 604 coupled to a cache memory 606. The CPUs 604 are also coupled to a system bus 608 and can inter-couple devices included in the processor-based device 600. As is well known, the CPUs 604 communicate with these other devices by exchanging address, control, and data information on the system bus 608. For example, the CPUs 604 can communicate bus transaction requests to the memory controller 610. Although not illustrated in FIG. Figure 6 In the embodiment, multiple system buses 608 may be provided, wherein each system bus 608 constitutes a different fabric.

[0047] Other devices may be connected to the system bus 608. Figure 6As illustrated, the devices may include, by way of example, a memory system 612, one or more input devices 614, one or more output devices 616, one or more network interface devices 618, and one or more display controllers 620. The input devices 614 may include any type of input device, including, but not limited to, input keys, switches, voice processors, and the like. The output devices 616 may include any type of output device, including, but not limited to, audio, video, other visual indicators, and the like. The network interface device 618 may be any device configured to allow data exchange to and from the network 622. The network 622 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth, or the like. ™ Network and Internet. The network interface device 618 can be configured to support any type of communication protocol desired. The memory system 612 can include a memory controller 610 coupled to one or more memory arrays 624 and a TLB 628 (e.g., Figure 1 and Figure 2 TLB 132) of the MMU 626 (e.g., Figure 1 and Figure 2 MMU 130 in the .

[0048] The CPU 604 may also be configured to access a display controller 620 via the system bus 608 to control information transmitted to one or more displays 630. The display controller 620 transmits information to be displayed to the display 630 via one or more video processors 632, which process the information to be displayed into a format suitable for the display 630. The display 630 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0049] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any desired type of information. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0050] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0051] The various aspects disclosed herein can be embodied in hardware and in instructions stored in hardware and may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative embodiment, the processor and storage medium may reside as discrete components in a remote station, a base station, or a server.

[0052] It should also be noted that the operational steps described in any one of the exemplary aspects herein are described to provide examples and discussion. The described operations can be performed in a variety of different sequences in addition to the illustrated sequence. In addition, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It will be apparent to those skilled in the art that the operational steps illustrated in the flow charts may be subject to many different modifications. Those skilled in the art will also understand that any one of a variety of different technologies and methods can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0053] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to limit the disclosure to the examples and designs described herein, but is intended to accord the disclosure the widest scope consistent with the principles and novel features disclosed herein.

[0054] Specific implementation examples are described in the following numbered clauses:

[0055] 1. A processor-based device, comprising:

[0056] a translation lookaside buffer (TLB), the translation lookaside buffer comprising a plurality of TLB entries, each TLB entry comprising a tag and a plurality of data portions; and

[0057] A memory management unit (MMU), the memory management unit being configured to:

[0058] receiving a first memory access request including a first virtual address (VA);

[0059] determining that a first TLB access to the TLB for a first page VA of the first VA results in a miss; and

[0060] In response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, generating a TLB entry for the first page VA, wherein:

[0061] The tag of the TLB entry includes the first page VA;

[0062] The plurality of data portions include a corresponding plurality of page physical addresses (PA);

[0063] A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and

[0064] One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

[0065] 2. The processor-based device of clause 1 , wherein each TLB entry in the plurality of TLB entries further comprises a plurality of valid bits, each valid bit corresponding to a data portion in the plurality of data portions.

[0066] 3. A processor-based device according to any of clauses 1 to 2, wherein:

[0067] Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA);

[0068] The plurality of pages PA are contiguous in the system memory; and

[0069] The MMU is configured to generate the TLB entry for the first page VA by being configured to:

[0070] performing an address translation operation to obtain the page PA corresponding to the first page VA;

[0071] Storing the page PA in the first data portion of the TLB entry;

[0072] Based on the address translation operation, obtaining the one or more pages PA of the corresponding subsequent sequential pages VA; and

[0073] The one or more pages PA of the corresponding subsequent sequential pages VA are stored in the one or more second data portions of the TLB entry.

[0074] 4. A processor-based device according to any of clauses 1 to 2, wherein:

[0075] Each page PA of the plurality of pages PA includes an intermediate physical address (IPA);

[0076] The plurality of pages PA are non-contiguous in the system memory; and

[0077] The MMU is configured to generate the TLB entry for the first page VA by being configured to:

[0078] performing an address translation operation to obtain the page PA corresponding to the first page VA;

[0079] Storing the page PA in the first data portion of the TLB entry;

[0080] pre-fetching the address translation of each page VA in the subsequent sequential page VA to obtain the one or more pages PA of the corresponding subsequent sequential page VA; and

[0081] The one or more second data portions of the TLB entry are updated with the one or more pages PA of the corresponding subsequent sequential pages VA.

[0082] 5. A processor-based device according to any of clauses 1 to 4, wherein the MMU is further configured to:

[0083] receiving a second memory access request including the first VA;

[0084] determining that a result of a second TLB access to the TLB for the first page VA of the first VA is a hit;

[0085] performing a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry in response to determining that the second TLB access to the TLB for the first page VA of the first VA results in a hit;

[0086] receiving a third memory access request including a second VA;

[0087] determining that a second page VA of the second VA corresponds to a subsequent sequential page VA following the first page VA; and

[0088] In response to determining that the second page VA of the second VA corresponds to the subsequent sequential page VA after the first page VA, a subsequent memory access operation is performed by using the page PA corresponding to a second data portion of the one or more second data portions of the subsequent sequential page VA.

[0089] 6. A processor-based apparatus as recited in any one of clauses 1 to 5, wherein the tag of the TLB entry further comprises one or more of a context and a page size.

[0090] 7. A processor-based device according to any of clauses 1 to 6, wherein each of the plurality of data portions further comprises one or more memory attributes.

[0091] 8. A processor-based device according to any one of clauses 1 to 7, wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0092] 9. A processor-based device, comprising:

[0093] means for receiving a first memory access request comprising a first virtual address (VA);

[0094] means for determining that a first translation lookaside buffer (TLB) access to a first page VA of the first VA of the processor-based device resulted in a miss; and

[0095] means for generating a TLB entry for the first page VA in response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, wherein:

[0096] The TLB entry includes a tag, the tag including the first page VA;

[0097] The TLB entry includes a plurality of data parts, and the plurality of data parts include a corresponding plurality of page physical addresses (PA);

[0098] A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and

[0099] One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

[0100] 10. A method for exploiting virtual address (VA) space locality by using translation lookaside buffer (TLB) entry compression, the method comprising:

[0101] Receiving, by a memory management unit (MMU) of a processor-based device, a first memory access request including a first VA;

[0102] determining, by the MMU, that a first TLB access to a TLB of the processor-based device for a first page VA of the first VA results in a miss; and

[0103] generating, by the MMU, a TLB entry for the first page VA in response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, wherein:

[0104] The TLB entry includes a tag, the tag including the first page VA;

[0105] The TLB entry includes a plurality of data parts, and the plurality of data parts include a corresponding plurality of page physical addresses (PA);

[0106] A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and

[0107] One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

[0108] 11. The method of clause 10, wherein each TLB entry in the plurality of TLB entries further comprises a plurality of valid bits, each valid bit corresponding to a data portion in the plurality of data portions.

[0109] 12. A method according to any one of clauses 10 to 11, wherein:

[0110] Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA);

[0111] The plurality of pages PA are contiguous in the system memory; and

[0112] Generating the TLB entry for the first page VA includes:

[0113] performing an address translation operation to obtain the page PA corresponding to the first page VA;

[0114] Storing the page PA in the first data portion of the TLB entry;

[0115] Based on the address translation operation, obtaining the one or more pages PA of the corresponding subsequent sequential pages VA; and

[0116] The one or more pages PA of the corresponding subsequent sequential pages VA are stored in the one or more second data portions of the TLB entry.

[0117] 13. A method according to any one of clauses 10 to 11, wherein:

[0118] Each page PA of the plurality of pages PA includes an intermediate physical address (IPA);

[0119] The plurality of pages PA are non-contiguous in the system memory; and

[0120] Generating the TLB entry for the first page VA includes:

[0121] performing an address translation operation to obtain the page PA corresponding to the first page VA;

[0122] Storing the page PA in the first data portion of the TLB entry;

[0123] pre-fetching the address translation of each page VA in the subsequent sequential page VA to obtain the one or more pages PA of the corresponding subsequent sequential page VA; and

[0124] The one or more second data portions of the TLB entry are updated with the one or more pages PA of the corresponding subsequent sequential pages VA.

[0125] 14. The method according to any one of clauses 10 to 13, further comprising:

[0126] receiving, by the MMU, a second memory access request including the first VA;

[0127] Determining, by the MMU, that a result of a second TLB access to the TLB for the first page VA of the first VA is a hit;

[0128] performing, by the MMU, a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry in response to determining that the second TLB access to the TLB for the first page VA of the first VA results in a hit;

[0129] receiving, by the MMU, a third memory access request including a second VA;

[0130] determining, by the MMU, that a second page VA of the second VA corresponds to a subsequent sequential page VA following the first page VA; and

[0131] A subsequent memory access operation is performed by the MMU using the page PA corresponding to a second data portion of the one or more second data portions of the subsequent sequential page VA in response to determining that the second page VA of the second VA corresponds to the subsequent sequential page VA following the first page VA.

[0132] 15. The method of any of clauses 10 to 14, wherein the tag of the TLB entry further comprises one or more of a context and a page size.

[0133] 16. A method according to any of clauses 10 to 15, wherein each of the plurality of data portions further comprises one or more memory attributes.

[0134] 17. A non-transitory computer-readable medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed, causing a processor of a processor-based device to:

[0135] receiving a first memory access request including a first virtual address (VA);

[0136] determining that a first translation lookaside buffer (TLB) access of the processor-based device for a first page VA of the first VA resulted in a miss; and

[0137] In response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, generating a TLB entry for the first page VA, wherein:

[0138] The TLB entry includes a tag, the tag including the first page VA;

[0139] The TLB entry includes a plurality of data parts, and the plurality of data parts include a corresponding plurality of page physical addresses (PA);

[0140] A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and

[0141] One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

[0142] 18. The non-transitory computer-readable medium of clause 17, wherein:

[0143] Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA);

[0144] The plurality of pages PA are contiguous in the system memory; and

[0145] The computer-executable instructions cause the processor to generate the TLB entry for the first page VA by causing the processor to:

[0146] performing an address translation operation to obtain the page PA corresponding to the first page VA;

[0147] Storing the page PA in the first data portion of the TLB entry;

[0148] Based on the address translation operation, obtaining the one or more pages PA of the corresponding subsequent sequential pages VA; and

[0149] The one or more pages PA of the corresponding subsequent sequential pages VA are stored in the one or more second data portions of the TLB entry.

[0150] 19. The non-transitory computer-readable medium of clause 17, wherein:

[0151] Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA);

[0152] The plurality of pages PA are non-contiguous in the system memory; and

[0153] The computer-executable instructions cause the processor to generate the TLB entry for the first page VA by causing the processor to:

[0154] performing an address translation operation to obtain the page PA corresponding to the first page VA;

[0155] Storing the page PA in the first data portion of the TLB entry;

[0156] pre-fetching the address translation of each page VA in the subsequent sequential page VA to obtain the one or more pages PA of the corresponding subsequent sequential page VA; and

[0157] The one or more second data portions of the TLB entry are updated with the one or more pages PA of the corresponding subsequent sequential pages VA.

[0158] 20. The non-transitory computer-readable medium of any one of clauses 17 to 19, wherein the computer-executable instructions further cause the processor to:

[0159] receiving a second memory access request including the first VA;

[0160] determining that a result of a second TLB access to the TLB for the first page VA of the first VA is a hit;

[0161] performing a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry in response to determining that the second TLB access to the TLB for the first page VA of the first VA results in a hit;

[0162] receiving a third memory access request including a second VA;

[0163] determining that a second page VA of the second VA corresponds to a subsequent sequential page VA following the first page VA; and

[0164] In response to determining that the second page VA of the second VA corresponds to the subsequent sequential page VA after the first page VA, a subsequent memory access operation is performed by using the page PA corresponding to a second data portion of the one or more second data portions of the subsequent sequential page VA.

Claims

1. A processor-based device, comprising: a translation lookaside buffer (TLB), the translation lookaside buffer comprising a plurality of TLB entries, each TLB entry comprising a tag and a plurality of data portions; and A memory management unit (MMU), the memory management unit being configured to: receiving a first memory access request including a first virtual address (VA); determining that a first TLB access to the TLB for a first page VA of the first VA results in a miss; and In response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, generating a TLB entry for the first page VA, wherein: The tag of the TLB entry includes the first page VA; The plurality of data portions include a corresponding plurality of page physical addresses (PA); A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

2. The processor-based device of claim 1 , wherein: Each TLB entry in the plurality of TLB entries further includes a plurality of valid bits, each valid bit corresponding to a data portion in the plurality of data portions.

3. The processor-based device of claim 1 , wherein: Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA); The plurality of pages PA are contiguous in the system memory; and The MMU is configured to generate the TLB entry for the first page VA by being configured to: performing an address translation operation to obtain the page PA corresponding to the first page VA; Storing the page PA in the first data portion of the TLB entry; Based on the address translation operation, obtaining the one or more pages PA of the corresponding subsequent sequential pages VA; as well as The one or more pages PA of the corresponding subsequent sequential pages VA are stored in the one or more second data portions of the TLB entry.

4. The processor-based device of claim 1 , wherein: Each page PA of the plurality of pages PA includes an intermediate physical address (IPA); The plurality of pages PA are non-contiguous in the system memory; and The MMU is configured to generate the TLB entry for the first page VA by being configured to: performing an address translation operation to obtain the page PA corresponding to the first page VA; Storing the page PA in the first data portion of the TLB entry; pre-fetching an address translation of each page VA in the subsequent sequential page VA to obtain the one or more pages PA of the corresponding subsequent sequential page VA; as well as The one or more second data portions of the TLB entry are updated with the one or more pages PA of the corresponding subsequent sequential pages VA.

5. The processor-based device of claim 1 , wherein: The MMU is further configured to: receiving a second memory access request including the first VA; determining that a result of a second TLB access to the TLB for the first page VA of the first VA is a hit; performing a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry in response to determining that the second TLB access to the TLB for the first page VA of the first VA results in a hit; receiving a third memory access request including a second VA; determining that a second page VA of the second VA corresponds to a subsequent sequential page VA after the first page VA; as well as In response to determining that the second page VA of the second VA corresponds to the subsequent sequential page VA after the first page VA, a subsequent memory access operation is performed by using the page PA corresponding to a second data portion of the one or more second data portions of the subsequent sequential page VA.

6. The processor-based device of claim 1 , wherein: The tag of the TLB entry also includes one or more of a context and a page size.

7. The processor-based device of claim 1 , wherein: Each of the plurality of data portions further includes one or more memory attributes.

8. The processor-based device of claim 1 , wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle assembly; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

9. A processor-based device, comprising: means for receiving a first memory access request comprising a first virtual address (VA); means for determining that a first translation lookaside buffer (TLB) access of the processor-based device for a first page VA of the first VA resulted in a miss; and means for generating a TLB entry for the first page VA in response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, wherein: The TLB entry includes a tag, the tag including the first page VA; The TLB entry includes a plurality of data parts, and the plurality of data parts include a corresponding plurality of page physical addresses (PA); A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

10. A method for exploiting virtual address (VA) space locality by using translation lookaside buffer (TLB) entry compression, the method comprising: Receiving, by a memory management unit (MMU) of a processor-based device, a first memory access request including a first VA; determining, by the MMU, that a first TLB access to a TLB of the processor-based device for a first page VA of the first VA results in a miss; as well as generating, by the MMU, a TLB entry for the first page VA in response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, wherein: The TLB entry includes a tag, the tag including the first page VA; The TLB entry includes a plurality of data parts, and the plurality of data parts include a corresponding plurality of page physical addresses (PA); A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

11. The method according to claim 10, wherein: Each TLB entry in the plurality of TLB entries further includes a plurality of valid bits, each valid bit corresponding to a data portion in the plurality of data portions.

12. The method according to claim 10, wherein: Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA); The plurality of pages PA are contiguous in the system memory; and Generating the TLB entry for the first page VA includes: performing an address translation operation to obtain the page PA corresponding to the first page VA; Storing the page PA in the first data portion of the TLB entry; Based on the address translation operation, obtaining the one or more pages PA of the corresponding subsequent sequential pages VA; and The one or more pages PA of the corresponding subsequent sequential pages VA are stored in the one or more second data portions of the TLB entry.

13. The method according to claim 10, wherein: Each page PA of the plurality of pages PA includes an intermediate physical address (IPA); The plurality of pages PA are non-contiguous in the system memory; and Generating the TLB entry for the first page VA includes: performing an address translation operation to obtain the page PA corresponding to the first page VA; Storing the page PA in the first data portion of the TLB entry; pre-fetching the address translation of each page VA in the subsequent sequential page VA to obtain the one or more pages PA of the corresponding subsequent sequential page VA; and The one or more second data portions of the TLB entry are updated with the one or more pages PA of the corresponding subsequent sequential pages VA.

14. The method according to claim 10, further comprising: receiving, by the MMU, a second memory access request including the first VA; Determining, by the MMU, that a result of a second TLB access to the TLB for the first page VA of the first VA is a hit; performing, by the MMU, a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry in response to determining that the second TLB access to the TLB for the first page VA of the first VA results in a hit; receiving, by the MMU, a third memory access request including a second VA; determining, by the MMU, that a second page VA of the second VA corresponds to a subsequent sequential page VA following the first page VA; and A subsequent memory access operation is performed by the MMU using the page PA corresponding to a second data portion of the one or more second data portions of the subsequent sequential page VA in response to determining that the second page VA of the second VA corresponds to the subsequent sequential page VA following the first page VA.

15. The method according to claim 10, wherein The tag of the TLB entry also includes one or more of a context and a page size.

16. The method according to claim 10, wherein Each of the plurality of data portions further includes one or more memory attributes.

17. A non-transitory computer-readable medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed, causing a processor of a processor-based device to: receiving a first memory access request including a first virtual address (VA); determining that a first translation lookaside buffer (TLB) access of the processor-based device for a first page VA of the first VA resulted in a miss; and In response to determining that the first TLB access to the TLB for the first page VA of the first VA results in a miss, generating a TLB entry for the first page VA, wherein: The TLB entry includes a tag, the tag including the first page VA; The TLB entry includes a plurality of data parts, and the plurality of data parts include a corresponding plurality of page physical addresses (PA); A first data portion of the plurality of data portions includes a page PA corresponding to the first page VA; and One or more second data portions of the plurality of data portions include corresponding one or more pages PA of corresponding subsequent sequential pages VA following the first page VA.

18. The non-transitory computer readable medium of claim 17, wherein: Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA); The plurality of pages PA are contiguous in the system memory; and The computer-executable instructions cause the processor to generate the TLB entry for the first page VA by causing the processor to: performing an address translation operation to obtain the page PA corresponding to the first page VA; Storing the page PA in the first data portion of the TLB entry; Based on the address translation operation, obtaining the one or more pages PA of the corresponding subsequent sequential pages VA; as well as The one or more pages PA of the corresponding subsequent sequential pages VA are stored in the one or more second data portions of the TLB entry.

19. The non-transitory computer readable medium of claim 17, wherein: Each page PA of the plurality of pages PA includes one of a PA and an intermediate physical address (IPA); The plurality of pages PA are non-contiguous in the system memory; and The computer-executable instructions cause the processor to generate the TLB entry for the first page VA by causing the processor to: performing an address translation operation to obtain the page PA corresponding to the first page VA; Storing the page PA in the first data portion of the TLB entry; pre-fetching an address translation of each page VA in the subsequent sequential page VA to obtain the one or more pages PA of the corresponding subsequent sequential page VA; as well as The one or more second data portions of the TLB entry are updated with the one or more pages PA of the corresponding subsequent sequential pages VA.

20. The non-transitory computer readable medium of claim 17, wherein: The computer-executable instructions further cause the processor to: receiving a second memory access request including the first VA; determining that a result of a second TLB access to the TLB for the first page VA of the first VA is a hit; performing a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry in response to determining that the second TLB access to the TLB for the first page VA of the first VA results in a hit; receiving a third memory access request including a second VA; determining that a second page VA of the second VA corresponds to a subsequent sequential page VA after the first page VA; as well as In response to determining that the second page VA of the second VA corresponds to the subsequent sequential page VA after the first page VA, a subsequent memory access operation is performed by using the page PA corresponding to a second data portion of the one or more second data portions of the subsequent sequential page VA.

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