Bonding structure with security die

Abstract

A joint structure is disclosed. The bonding structure may include a semiconductor element including an active circuit device and a safety die electrically connected along a bonding interface and directly bonded to a surface of the semiconductor element without an adhesive. The security die may include a security core. The secure core may include encryption logic and memory. The secure core may be configured to decrypt data to be transmitted to the active circuitry and encrypt a signal from the active circuitry.

Description

Technical Field

[0001] The field relates to a bonded structure having a security device die configured to provide encryption circuitry and / or decryption circuitry separate from a semiconductor element to which the security device die is bonded. Background Art

[0002] A semiconductor chip (e.g., an integrated device die) may include a device (which may include patterned processing circuitry and / or active circuitry) that includes security-sensitive components for sending and receiving communications containing valuable and / or proprietary information, structures, or devices. For example, such security-sensitive components and communications may include an entity's intellectual property, software or hardware security (e.g., encryption) features, private data, or any other components or data that an entity may wish to keep secure and hidden from third parties. For example, third-party bad actors may utilize various techniques to attempt to access security-sensitive components to gain economic and / or geopolitical advantage. Thus, there remains an ongoing need to improve the security of semiconductor chips. Summary of the Invention

[0003] In one embodiment, a bonding structure may include: a semiconductor element having an active circuit device; and a security die electrically connected along a bonding interface and directly bonded to a surface of the semiconductor element without an adhesive, the security die having a security core; wherein the security core contains encryption logic and memory; and wherein the security core is configured to perform at least one of decrypting a signal to be transmitted to the active circuit device and encrypting a signal received from the active circuit device.

[0004] In some embodiments, the bonding structure includes a via that electrically connects the security die to the semiconductor element. In some embodiments, the semiconductor element and the security die are hybrid bonded such that the semiconductor element and non-conductive regions of the security die are directly bonded, and the semiconductor element and conductive regions of the security die are directly bonded.

[0005] In some embodiments, the bonding structure includes a barrier material on the security core, the barrier material being configured to inhibit external access to the security core. In some embodiments, the barrier material is part of a protective element that is directly bonded to the surface of the security core. In some embodiments, the barrier material is directly bonded to the back of the security core. In some embodiments, the barrier material includes a destructive material having a hardness in the range of 20 GPa to 150 GPa on the Vickers hardness scale. In some embodiments, the barrier material includes a destructive material having a hardness of at least 80 GPa on the Vickers hardness scale. In some embodiments, the barrier material includes an abrasive material. In some embodiments, the barrier material includes a light blocking material. In some embodiments, the light blocking material is configured to block light of near infrared (NIR) wavelengths. In some embodiments, the barrier material includes an optical or infrared (IR) blocking or modifying material.

[0006] In some embodiments, an encapsulation material is provided over the semiconductor element and the security die. In some embodiments, the semiconductor element includes a first bonding layer, and wherein the security die may include a second bonding layer directly bonded to the first bonding layer without an adhesive. In some embodiments, the first bonding layer includes silicon oxide. In some embodiments, the bonding structure includes a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads. In some embodiments, the memory stores an encryption key.

[0007] In another embodiment, a bonding structure may include: a semiconductor element having an active circuit device; a security die electrically connected along a bonding interface and directly bonded to the surface of the semiconductor element without an adhesive, the security die including a security core; and a barrier material disposed on the surface of the security die, the barrier material being configured to inhibit external access to the security core.

[0008] In some embodiments, the security core includes encryption logic and memory. In some embodiments, the security core is configured to encrypt data to be transmitted to the active circuit device and decrypt signals received from the active circuit device. In some embodiments, the barrier material is part of a protective element that is directly bonded to the surface of the security die. In some embodiments, the bonding structure includes a carrier, and the security die is mechanically and electrically connected to the carrier. In some embodiments, the bonding structure includes vias electrically connecting the security die to the semiconductor element. In some embodiments, the bonding structure includes vias electrically connecting the security die to the carrier. In some embodiments, the carrier includes a plurality of conductive bumps electrically connected to the semiconductor element and the security die.

[0009] In some embodiments, the barrier material comprises a destructive material having a hardness in the range of 20 GPa to 150 GPa on the Vickers hardness scale. In some embodiments, the barrier material comprises a destructive material having a hardness of at least 80 GPa on the Vickers hardness scale. In some embodiments, the barrier material comprises an abrasive material. In some embodiments, the barrier material comprises a light blocking material. In some embodiments, the light blocking material is configured to block light in near infrared (NIR) wavelengths. In some embodiments, the barrier material comprises an optical or infrared (IR) blocking or modifying material.

[0010] In some embodiments, an encapsulation material is provided over the semiconductor element and the security die. In some embodiments, the semiconductor element includes a first bonding layer, and wherein the security die includes a second bonding layer directly bonded to the first bonding layer without an adhesive. In some embodiments, the first bonding layer includes silicon oxide. In some embodiments, the security die includes a via extending through the substrate.

[0011] In another embodiment, a method of forming a bonding structure may include: providing a security die having a security core, the security core containing encryption logic and memory; directly bonding the security die to the surface of a semiconductor element without an adhesive so that the security die and the semiconductor element are electrically connected, and the security core is configured to perform at least one of the following: decrypting a signal to be transmitted to the semiconductor element and encrypting a signal to be received from the semiconductor element.

[0012] In some embodiments, the semiconductor element includes an active circuit device. In some embodiments, the method includes connecting a via between the semiconductor element and the security die. In some embodiments, the method includes providing a barrier material on a surface of the security die, the barrier material being configured to prevent external access to the security die. In some embodiments, the method includes providing an encapsulation material over the semiconductor element and the security die. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a schematic cross-sectional side view of two elements prior to direct hybrid joining.

[0014] Figure 1B is included Figure 1A Schematic cross-sectional side view of the joined structure of two elements shown after direct hybrid joining.

[0015] Figure 2A is a schematic side cross-sectional view of a pre-assembled bonded structure including a security chiplet before being directly bonded to a semiconductor element.

[0016] Figure 2BAccording to one embodiment, Figure 2A Schematic side cross-sectional view of the joining structure of the assembly.

[0017] Figure 3 is a schematic side cross-sectional view of another bonding structure including a security chiplet and a semiconductor element connected to a carrier.

[0018] Figure 4 is a schematic side cross-sectional view of an integrated circuit die having a safety circuit arrangement disposed on a surface of the die. DETAILED DESCRIPTION

[0019] Overview

[0020] As described herein, a third party (such as a third-party bad actor) may attempt to access security-sensitive components on an integrated device die, as well as communications (e.g., signals) containing security-sensitive information to and from the integrated device die. In some device dies, the integrated device die may include a security core connected to other active circuit devices on the die to encrypt or decrypt signals processed by the other active circuit devices. Figure 4 As shown, the integrated circuit die can also be protected by providing a protective element having a barrier material along the entire back side of the die. As described herein, Figure 4 An integrated circuit die 400 is illustrated that includes a substrate 404 with devices 402 (e.g., one or more active devices, such as transistors, and / or one or more passive devices) disposed on a surface of the substrate 404, and an encapsulation layer 406 (which may include a passivation layer, such as an inorganic dielectric) that encapsulates the devices 402. Because the die 400 includes a secure core connected to other active circuit devices, a protective element including a barrier material 408 can be provided along the entire backside of the die. However, providing a protective element or barrier material over the entire die can be very expensive and time-consuming. Additional examples of protective elements with barrier materials can be found in U.S. Publication Nos. 2020 / 0328162, 2020 / 0328164, 2020 / 0371154, and 2020 / 0328165, and U.S. Application Nos. 17 / 816346 and 17 / 812675, the entire contents of which are incorporated herein by reference in their entireties. Thus, there remains a need to provide improved security for elements (such as semiconductor integrated device dies) that include security-sensitive components and / or securely transmit and / or receive security-sensitive signals.

[0021] To protect data or signals entering or leaving the device, data can be transferred to a secure core. For example, data received by the processor die can be transferred to the secure core (also referred to herein as the "encryption core") for decryption. The decrypted data can be processed by other active circuitry on the integrated device die. Alternatively or additionally, data to be transferred out of the system can be processed by the secure core to encrypt the data before being transferred to external devices.

[0022] One way to reduce the cost of protecting against hacker attacks is to pattern the security core on a separate security chiplet, rather than patterning the security core containing encryption (and / or decryption) logic and memory on the integrated device die itself. The security chiplet can be thinned and use, for example, barrier materials to prevent hacker attacks. The security chiplet can be directly hybrid bonded to the integrated device die. By patterning the security core on the security chiplet, the protection of the entire host chip can be eliminated, which can reduce processing costs. The communication speed between the main processor and the security chiplet can also be increased because there can be additional connectors between the main processor and the security chiplet. The security chiplet provides a versatile option that can be used with a variety of host processors or other types of integrated device dies. Therefore, various embodiments disclosed herein include a security die or chiplet (having encryption and / or decryption circuit devices) that is directly bonded to an integrated device die having active circuit devices.

[0023] Examples of direct bonding methods and direct bonding structures

[0024] Various embodiments disclosed herein relate to direct-bonded structures in which two or more elements may be directly bonded to one another without an intervening adhesive. Figure 1A and Figure 1B Schematically illustrates a process for forming a direct bonded structure without an intermediate adhesive, according to some embodiments. Figure 1A and Figure 1BIn the embodiment of the present invention, the bonding structure 100 includes two elements 102 and 104, which can be directly bonded to each other without an intermediate adhesive. Two or more semiconductor elements 102 and 104 (such as integrated device dies, wafers, etc.) can be stacked or bonded to form the bonding structure 100. The conductive features 106a of the first element 102 (for example, exposed ends of contact pads, vias (for example, TSVs) or electrodes that penetrate the substrate) can be electrically connected to the corresponding conductive features 106b of the second element 104. Any suitable number of elements can be stacked in the bonding structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) can be stacked sideways adjacent to each other along the first element 102. In some embodiments, the additional elements stacked sideways can be smaller than the second element. In some embodiments, the additional elements stacked sideways can be twice as small as the second element.

[0025] In some embodiments, elements 102 and 104 are directly bonded to each other without adhesive. In various embodiments, the non-conductive field region including a non-conductive material or a dielectric material can be used as the first bonding layer 108a of the first element 102, and this first bonding layer can be directly bonded to the corresponding non-conductive field region, and this non-conductive field region includes a non-conductive material or a dielectric material as the second bonding layer 108b of the second element 104, without the need for adhesive. Non-conductive bonding layers 108a and 108b can be arranged on the corresponding front sides 114a and 114b of device parts 110a and 110b, such as semiconductor (for example, silicon) parts of elements 102, 104. Active devices and / or circuit devices can be patterned and / or otherwise arranged in device parts 110a and 110b or on device parts 110a and 110b. Active devices and / or circuitry may be disposed at or near the front sides 114a and 114b of the device portions 110a and 110b, and / or at or near the opposing back sides 116a and 116b of the device portions 110a and 110b. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer 108a of the first element 102. In some embodiments, the non-conductive bonding layer 108a of the first element 102 may be directly bonded to the corresponding non-conductive bonding layer 108b of the second element 104 using a dielectric-to-dielectric bonding technique. For example, a non-conductive or dielectric-to-dielectric bond may be formed without an adhesive using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, each of which is incorporated herein by reference in its entirety and for all purposes. It should be understood that in various embodiments, the bonding layer 108a and / or 108b may include a non-conductive material, such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or may include carbon, such as silicon carbide, silicon carbonitride, low-K dielectric materials, SICOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials including diamond surfaces. Although containing carbon, such carbon-containing ceramic materials may be considered inorganic. In some embodiments, the dielectric material does not include a polymeric material, such as an epoxy resin, a resin, or a molding material.

[0026] In various embodiments, a direct hybrid bond can be formed without an intermediate adhesive. For example, the non-conductive bonding surfaces 112a and 112b can be polished to a high smoothness. The bonding surfaces 112a and 112b can be cleaned and exposed to plasma and / or an etchant to activate the surfaces 112a and 112b. In some embodiments, the surfaces 112a and 112b can be terminated with a substance after activation or during activation (e.g., during a plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process can be performed to break the chemical bonds at the bonding surfaces 112a and 112b, and the termination process can provide additional chemicals at the bonding surfaces 112a and 112b, which improves the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step, for example, plasma activation and termination of the surfaces 112a and 112b. In other embodiments, the bonding surfaces 112a and 112b can be terminated in a separate process to provide additional substances for direct bonding. In various embodiments, the termination substance can include nitrogen. For example, in some embodiments, (one or more) bonding surfaces 112a, 112b can be exposed to nitrogen-containing plasma. In addition, in some embodiments, bonding surfaces 112a and 112b can be exposed to fluorine. For example, there can be one or more fluorine peaks at or near the bonding interface 118 between the first element 102 and the second element 104. Therefore, in the direct bonding structure 100, the bonding interface 118 between the two non-conductive materials (e.g., bonding layers 108a and 108b) can include a very smooth interface with a higher nitrogen content and / or fluorine peak at the bonding interface 118. Additional examples of activation and / or termination treatments can be found in U.S. Patents Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference as a whole and for all purposes.

[0027] In various embodiments, the conductive features 106a of the first element 102 can also be directly bonded to the corresponding conductive features 106b of the second element 104. For example, hybrid bonding techniques can be used to provide direct conductor-to-conductor bonding along a bonding interface 118 that includes covalently directly bonded non-conductive-to-non-conductive (e.g., dielectric-to-dielectric) surfaces prepared as described above. In various embodiments, direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988 can be used to form direct conductor-to-conductor (e.g., conductive feature 106a-to-conductive feature 106b) and hybrid dielectric-to-dielectric bonding, each of which is incorporated herein by reference in its entirety and for all purposes.

[0028] For example, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (e.g., inorganic dielectric surfaces) can be prepared and directly bonded to each other without an intermediate adhesive as described above. Conductive contact features (e.g., conductive features 106a and 106b, which can be at least partially surrounded by a non-conductive dielectric field region within bonding layers 108a, 108b) can also be directly bonded to each other without an intermediate adhesive. In various embodiments, conductive features 106a, 106b can include discrete pads at least partially embedded in the non-conductive field region. In some embodiments, the conductive contact features can include exposed contact surfaces of through-substrate vias (TSVs). In some embodiments, the respective conductive features 106a and 106b can be recessed below the dielectric field region or outer (e.g., upper) surface (non-conductive bonding surfaces 112a and 112b) of the non-conductive bonding layers 108a and 108b, for example, by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, within a range of 2 nm to 20 nm, or within a range of 4 nm to 10 nm. In various embodiments, the size of the recesses in the opposing elements can be designed such that the total gap between the opposing contact pads is less than 15 nm, or less than 10 nm, prior to direct bonding. In some embodiments, the non-conductive bonding layers 108a and 108b can be directly bonded to each other at room temperature without an adhesive, and subsequently, the bonded structure 100 can be annealed. Upon annealing, the conductive features 106a and 106b can expand and contact each other to form a metal-to-metal direct bond. Advantageously, direct bonding interconnects or The technology enables a high density of conductive features 106a and 106b to be connected across a direct bonding interface 118 (e.g., a regular array of small pitch or fine pitch). In some embodiments, the pitch of the conductive features (such as conductive traces embedded in the bonding surface of one of the bonding elements) 106a and 106b can be less than 40 microns, or less than 10 microns, or even less than 2 microns. For some applications, the ratio of the pitch of the conductive features 106a and 106b to one of the dimensions of the bonding pad (e.g., diameter) is less than 5, or less than 3, and sometimes ideally less than 2. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonding elements can be in the range of between 0.3 microns and 20 microns, for example, in the range of 0.3 microns to 3 microns. In various embodiments, the conductive features 106a and 106b and / or the traces can include copper, although other metals may be suitable.

[0029] Thus, in a direct bonding process, the first component 102 can be bonded directly to the second component 104 without an intermediate adhesive. In some arrangements, the first component 102 can include a singulated component, such as a singulated integrated device die. In other arrangements, such as Figure 1A and Figure 1B As shown, the first component 102 may include a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., dozens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second component 104 may include a singulated component, such as a singulated integrated device die, such as Figure 1A and Figure 1B As shown. In other arrangements, the second element 104 may include a carrier or substrate (e.g., a wafer). Thus, the embodiments disclosed herein may be applied to wafer-to-wafer, die-to-die, or die-to-wafer bonding processes. In a wafer-to-wafer (W2W) process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush and may include markings indicating the singulation process (e.g., saw markings if a saw singulation process is used).

[0030] As described herein, the first element 102 and the second element 104 can be directly bonded to each other without adhesive, which is different from deposition process. In a kind of application, the width of the first element 102 in the bonding structure is similar to the width of the second element 104. In some other embodiments, the width of the first element 102 in the bonding structure 100 is different from the width of the second element 104. Similarly, the width or area of ​​the larger element in the bonding structure can be at least 10% larger than the width or area of ​​the smaller element. Therefore, the first element 102 and the second element 104 can include non-deposition elements. In addition, different from the deposition layer, the direct bonding structure 100 can include a defective area along the bonding interface 118, wherein there is a nanometer-scale space (nano void (nanovoid)). Nano void can be formed due to the activation (for example, being exposed to plasma) of the bonding surface 112a and 112b. As described above, the bonding interface 118 can include the material concentration from activation and / or last chemical treatment process. For example, in the embodiment utilizing nitrogen plasma to activate, a nitrogen peak can be formed at the bonding interface 118. The nitrogen peak can be detected using secondary ion mass spectrometry (SIMS) technology. In various embodiments, for example, nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace the OH groups on the hydrolysis (OH termination) surface with NH2 molecules, resulting in a nitrogen-terminated surface. In an embodiment in which oxygen plasma is utilized for activation, an oxygen peak can be formed at the bonding interface 118. In some embodiments, the bonding interface 118 can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, a direct bond can include a covalent bond, which is stronger than a van der Waals bond. The bonding layers 108a and 108b can also include a polished surface that is planarized to a high degree of smoothness.

[0031] In various embodiments, the metal-to-metal bond between the contact pads 106a and 106b can be combined so that copper grains grow into each other across the bonding interface 118. In some embodiments, the copper can have grains oriented along 111 crystal planes for improved copper diffusion across the bonding interface 118. The bonding interface 118 can extend substantially completely to at least a portion of the bonded conductive features 106a and 106b so that there is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer (e.g., which can include copper) can be provided below the conductive features 106a and 106b. However, in other embodiments, there can be no barrier layer below the conductive features 106a and 106b, for example, as described in U.S. Patent No. 11,195,748, which is incorporated herein by reference in its entirety and for all purposes.

[0032] Advantageously, the use of the hybrid bonding techniques described herein allows for extremely small pitches between adjacent contact pads 106a and 106b and / or extremely small pad sizes. For example, in various embodiments, the pitch p (i.e., the distance from edge to edge or center to center) between adjacent conductive features 106a (or 106b) may be as small as 1 / 4. Figure 1A The major lateral dimensions (e.g., pad diameter) may be in the range of 0.5 μm to 50 μm, in the range of 0.75 μm to 25 μm, in the range of 1 μm to 25 μm, in the range of 1 μm to 10 μm, or in the range of 1 μm to 5 μm. In addition, the major lateral dimensions (e.g., pad diameter) may also be small, for example, in the range of 0.25 μm to 30 μm, in the range of 0.25 μm to 5 μm, or in the range of 0.5 μm to 5 μm.

[0033] Example embodiments of engagement structures

[0034] Figure 2A A semiconductor element 202 is illustrated having a bonding layer 208a (e.g., an inorganic dielectric) on a device portion 210 and a security die 204 (also referred to herein as a "security chiplet" and "security chip") having a second bonding layer 208b before bonding. In some embodiments, the first bonding layer 208a may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon nitride. The device portion 210 may include a semiconductor material patterned with one or more devices 211 (e.g., one or more active devices, such as transistors, and / or one or more passive devices). Each of the semiconductor element 202 and the security die 204 may have corresponding conductive contact pads 206a, 206b that are configured to provide an electrical connection to the other element. The contact pads 206a, 206b may include discrete conductive pads disposed in a non-conductive field region 208a, 208b (e.g., a non-conductive bonding layer).

[0035] The security die 204 (also referred to herein as a cryptographic chiplet or a secure chiplet) may include a security core 205 that includes silicon and contains encryption and / or decryption logic and memory patterned on the surface of the die. In various embodiments, the memory of the security core 205 may store encryption keys. In some embodiments, the security core 205 may be a chiplet that may also be hardened by software and / or hardware. Furthermore, in some embodiments, the security core 205 may be made very thin and have a reduced footprint so as to beneficially reduce the vertical and horizontal size of the security die 204. For example, the security die 204 including the security core 205 may have an area in the range of 50 microns by 50 microns to 150 microns by 150 microns, an area in the range of 75 microns by 75 microns to 125 microns by 125 microns, or an area in the range of 90 microns by 90 microns to 110 microns by 110 microns. The security core 205 can be configured to decrypt data to be transmitted to a device 211 disposed in or on the device region 210. The decrypted data or signal can be transmitted to the device 211 by means of conductive contact features 206a, 206b across the bonding interface 218 and traces (not shown) in the metallization layer above the semiconductor element 202. The device 211 can process the decrypted signal or data in any suitable manner. In some embodiments, the processed data or signal can be transmitted to the security core 205, which can encrypt the processed signal received from the active circuit or device 211. In some embodiments, the security method provided by the security core 204 can include decrypting the data transmitted to the semiconductor element 202 before being processed by the device 211 of the semiconductor element 202 (which can include patterned processing circuit devices and / or active circuit devices). In some embodiments, the security method provided by the security die 204 additionally or alternatively includes encrypting data or signals transmitted from the semiconductor element 202 to the security die 204 via the contact features 206 a , 206 b .

[0036] In various embodiments, the security die 204 may include a protective or barrier material 220 to provide an anti-hacking structure to prevent third parties from attempting to intrude into the security die 204. In some embodiments, the barrier material 220 may be part of a protective element that is directly bonded (e.g., using a dielectric-to-dielectric bonding technique such as that used by Adeia, Inc. of San Jose, California). technology) to a surface (e.g., a back surface) of the security die 204 to inhibit external access to the security core 205. The protection element 220 may be bonded directly to the back of the security die 204. In other embodiments, the barrier material 220 may be deposited on one or more surfaces of the security die 204. By including the barrier material 220 on the chip rather than on the entire integrated circuit die 202, processing time and cost can be reduced. The cost of the protection chip 204 alone can be relatively low. In some embodiments, the barrier material 220 can be part of a discrete protection element that is bonded directly to the back of the security die 204. In other embodiments, the barrier material 220 may alternatively be deposited on the back of the security die 204 and / or the security core 205.

[0037] The barrier material 220 may include a physically destructive material (e.g., an abrasive material and / or a hard material) that is configured to physically damage or destroy a tool attempting to access the device 211 of the semiconductor element 202, or otherwise prevent physical or mechanical access to the device 211. The barrier material 220 may have a high shear modulus, a high bulk modulus, and may not exhibit plastic deformation. For example, a material having a hardness of at least 80 GPa (e.g., as measured according to Vickers hardness) may be used for the destructive material. In various embodiments, the destructive material may have a hardness of at least 20 GPa, at least 30 GPa, or at least 50 GPa. For example, the destructive material may have a hardness in the range of 20 GPa to 150 GPa, in the range of 40 GPa to 150 GPa, or in the range of 80 GPa to 150 GPa, as measured on the Vickers scale. In another example, the abrasive or destructive material may have a higher hardness than typical materials used in semiconductor chips. For example, the hardness of the destructive material can be higher than the hardness of Si, SiO, SiN, SiON, SiCN, etc. In some embodiments, the first hardness of the barrier material 220 is greater than the second hardness of the semiconductor element 202 or the third hardness of the material at the bonding interface between the semiconductor element 202 and the security tube core 204. Barrier materials including abrasive materials and / or hard materials are described in at least the disclosure of paragraph

[0024] of U.S. Publication 2020 / 0328162, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. Additional examples of protective elements can be found in U.S. Publications 2020 / 0328164, 2020 / 0371154, and 2020 / 0328165.

[0038] In various embodiments, as described above, the barrier material 220 may alternatively or additionally include a light blocking material configured to block light and / or an electromagnetic absorbing or dissipative material that blocks electromagnetic waves. For example, the barrier material 220 may be selected to block light having a wavelength in the range of 700nm to 1mm, in the range of 750nm to 2500nm, or in the range of 800nm ​​to 2500nm. Alternatively or additionally, the barrier material 220 may be selected or shaped to scatter incident light. Alternatively or additionally, the barrier material 220 may be conductive and may effectively act as an electromagnetic shield. The barrier material 220 may additionally or alternatively absorb electromagnetic waves. In various embodiments, the barrier material 220 may be selected to block near infrared (NIR) and focused ion beam (FIB) tomographic intrusion attempts. In another embodiment, the barrier material 220 may include or may be deposited with one or more layers of optical or infrared filters. Thin film filters can be used to filter out or modify light or IR light that shines through them in any direction, such as light incident on a circuit to trigger a response, or light emitted from a circuit to detect a response to a hacking technique. Barrier materials including light-blocking materials are described in at least paragraphs

[0023] ,

[0025] , and

[0030] , as disclosed in at least U.S. Publication No. 2020 / 0328162, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. Additional examples of protective elements with light-blocking properties can be found in U.S. Patent Application Nos. 17 / 816,346 and 17 / 812,675.

[0039] Figure 2B A bonding structure 200 according to an embodiment is shown, wherein a security die 204 is bonded to a semiconductor element 202 , eg, using a direct hybrid bonding technique. Figure 2B The barrier material 220 in may be part of a protective element that is directly bonded to the security die 204. Figure 2B As shown, the semiconductor element 202 can have a plurality of contact pads 206a on a front side 214a, and the security die 204 can have a plurality of contact pads 206b on a front side 214b, wherein the first plurality of contact pads 206a is directly bonded to the second plurality of contact pads 206b. The semiconductor element 202 can be bonded (e.g., directly bonded without an intermediate adhesive) to the security die 204 along bonding surfaces 212a and 212b, wherein the contact pads 206a are electrically connected to the contact pads 206b.

[0040] and Figure 2A and Figure 2B compared to, Figure 4An integrated surface die 400 is shown that includes a substrate 404 with devices 402 (e.g., one or more active devices, such as transistors, and / or one or more passive devices) disposed on a surface of the substrate 404 and an encapsulation layer 406 encapsulating the devices 402. The devices 402 may include a secure processing circuit device for providing encryption and / or decryption for the die 400. Because the die 400 does not include a security chiplet such as the security die 204, additional protection features such as protective elements 408 may be provided along the entire length of the die to protect the die. Additionally, the secure processing circuit device is disposed above the surface of the substrate 404, which takes up valuable horizontal space. Advantageously, the secure processing circuit device is disposed above the surface of the substrate 404, which takes up valuable horizontal space. Figure 4 The use of the security die 204 may reduce the footprint compared to the secure die 400 .

[0041] Figure 3 and Figure 2A-2B Unless otherwise stated, Figure 3 The components in can be used with Figure 2A-2B Components with the same number in the same or substantially similar. Figure 3 As shown, the bonded structure 200 including the semiconductor element 302 and the security die 304 can also be electrically and mechanically connected to a carrier 322 to form a package assembly 300. In some embodiments, the semiconductor element 302 and the security die 304 can be connected to the carrier 322 in a flip-chip configuration, for example, by means of a plurality of solder balls 324 or other conductive adhesive. In other embodiments (e.g., embodiments in which the external device includes another die, an interposer, or a wafer), Figure 2B The bonding structure 200 can be directly bonded to an external device. Each of the first semiconductor element 302, the security die 304, and the carrier 322 can have a corresponding conductive contact pad 306 that is configured to provide an electrical connection to the other element. The contact pad 306 can include a discrete conductive pad disposed in a corresponding non-conductive field region 308 (e.g., a non-conductive bonding layer). Once connected, an underfill material 313 can be applied around the solder balls 324. The underfill material can include an insulating material that isolates the solder balls 324 from each other and connects the carrier 322 to the bonding structure 200.

[0042] In this configuration, the semiconductor element 302 can have a plurality of contact pads 306a on the front side 314a, and the security die 304 can have a first plurality of contact pads 306b on the front side 314b and also include a second plurality of contact pads 306c on the back side 314c. The carrier 322 can include a plurality of contact pads 306d on the front side 314d. The semiconductor element 302 can be bonded (e.g., directly bonded without an intermediate adhesive) to the security die 304, wherein the plurality of contact pads 306a is electrically connected to the plurality of contact pads 306b by means of vias 317. The contact pads 306b on the security die 304 can be directly bonded to the upper surface of the vias 317. The plurality of contact pads 306c at the back side of the security die 304 can be electrically connected to the plurality of contact pads 306d on the carrier 322 via conductive bumps or solder balls 324. In some embodiments, the carrier 322 may also include conductive bumps or solder balls 326 to connect the carrier to external devices (such as a system board or other devices). In some embodiments, the first semiconductor 302 and the security core 304 may be at least partially encapsulated in an encapsulation material 309, which includes an organic dielectric (e.g., a polymer such as a molding compound) or an inorganic dielectric (such as silicon oxide, etc.). As shown, the via 317 may extend through the non-conductive field region 308 to connect the device 311 of the semiconductor element 302 to the pad 306c of the security core 304 (e.g., by means of a direct hybrid bond between the non-conductive area and the pad 306c of the security core 304 and the non-conductive field region 308 and the via 317). In addition, the via 317 may extend from the device 311 through the non-conductive field region 308 and the encapsulation material 309 to connect the device 311 to the solder ball 324.

[0043] In some embodiments, vias 316 can connect the security chip 304 to solder balls 324, which are connected to the carrier 322. As shown, the vias 316 can extend through the barrier material 320 disposed above and / or around the security chip 304. In some embodiments, a plurality of through-substrate vias (TSVs) (not shown) can extend through the security chip 304 to provide electrical communication between the front and back sides of the security chip 304, for example, electrically connecting the carrier 322 to the device 311 of the semiconductor element 302. When bonded and / or assembled, the vias 316 can provide an additional security measure to prevent stripping and / or hacking attacks caused by the inability to access the security die 304 without interrupting the connection (e.g., cutting or severing the vias). In some embodiments, if in a flip-chip configuration, the bonded structure 300 can become inoperable when the carrier 322 is disconnected from the vias 316. For example, the carrier 322 can be connected to other devices and / or circuit devices, such as the device 311 and / or the security die, which can monitor signals to determine whether the direct connection has been broken. If carrier 322 is removed from first semiconductor element 302 and security die 304, the removal may trigger a signal indicating the removal (e.g., detected by a change in impedance, current, voltage, etc.) along via 316. Such removal may interrupt power to the components of bond structure 300, rendering bond structure 300 inoperable.

[0044] Any portion of any of the steps, processes, structures, and / or devices disclosed or described in one example of the present disclosure may be combined or used (or substituted) with any other portion of any of the steps, processes, structures, and / or devices disclosed or described in a different example or flowchart. The examples described herein are not intended to be separated or isolated from each other. Combinations, variations, and some implementations of the disclosed features are all within the scope of the present disclosure.

[0045] Although the operations may be depicted in the drawings or described in the specification in a particular order, these operations do not need to be performed in the particular order or sequence shown, or all operations need not be performed to achieve the desired result. Other operations not depicted or described may be incorporated into the example methods and processes. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the described operations. In addition, in some implementations, the operations may be rearranged or reordered. In addition, the separation of the various components in the above implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described components and systems may generally be integrated together in a single product or packaged into multiple products. In addition, some implementations are also within the scope of this disclosure.

[0046] As used herein, directional terms, such as "top," "bottom," "proximal," "distal," "longitudinal," "lateral," and "end," are used in the context of the examples shown. However, the present disclosure should not be limited to the orientations shown. In fact, other orientations are possible and within the scope of the present disclosure. As used herein, terms related to a circle, such as diameter or radius, should be understood as not requiring a perfectly circular structure, but should apply to any suitable structure having a cross-sectional area that can be measured from side to side. Generally, terms related to shape, such as "circular," "cylindrical," "semi-circular," or "semi-cylindrical," or any related or similar terms, need not strictly conform to the mathematical definition of a circle or cylinder or other structure, but can encompass reasonably close approximations.

[0047] Unless specifically stated otherwise, or understood otherwise in the context of use, conditional language, such as "may," "could," "might," or "might," is generally intended to convey that certain examples include or exclude certain features, elements, and / or steps. Thus, such conditional language is generally not intended to imply that one or more examples require a feature, element, and / or step in any way.

[0048] Unless specifically stated otherwise, linking language such as the phrase "at least one of X, Y, and Z" should be understood along with the context and is generally used to convey that an item, term, etc. can be X, Y, or Z. Thus, such linking language is generally not intended to imply that certain examples require the presence of at least one of X, at least one of Y, and at least one of Z.

[0049] As used herein, the terms "approximately," "about," and "substantially" refer to an amount that is close to the stated amount and still performs the desired function or achieves the desired result. For example, in some examples, as the context dictates, the terms "approximately," "about," and "substantially" may refer to an amount that is less than or equal to 10% of the stated amount. As used herein, the term "generally" refers to a value, amount, or characteristic that primarily includes or tends toward a particular value, amount, or characteristic. As an example, in some examples, as the context dictates, the term "generally parallel" may refer to a deviation from perfect parallelism that is less than or equal to 20°. All ranges are inclusive.

[0050] Several illustrative examples of joint structures and related systems and methods have been disclosed. Although the present disclosure has been described in terms of certain illustrative examples and uses, other examples and other uses, including examples and uses that do not provide all of the features and advantages set forth herein, are also within the scope of the present disclosure. Components, elements, features, actions, or steps may be arranged or performed differently than described, and components, elements, features, actions, or steps may be combined, merged, added, or omitted in various examples. All possible combinations and subcombinations of the elements and components described herein are intended to be included in the present disclosure. No one or group of features is necessary or indispensable.

[0051] Certain features described in this disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually in multiple implementations or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a claimed combination may, in some cases, be deleted from that combination, and the combination may be claimed as a subcombination or a variation of the subcombination.

[0052] Furthermore, although illustrative examples have been described, any examples having equivalent elements, modifications, omissions, and / or combinations thereof are also within the scope of this disclosure. Furthermore, although certain aspects, advantages, and novel features are described herein, not all such advantages may be achieved according to any particular example. For example, some examples within the scope of this disclosure may achieve one or a group of advantages taught herein without necessarily achieving other advantages taught or proposed herein. Furthermore, some examples may achieve advantages different from those taught or proposed herein.

[0053] Some examples have been described in conjunction with the accompanying drawings. The drawings may or may not be drawn and / or shown to scale, but such proportions should not be limiting, as sizes and proportions other than those shown are contemplated and are within the scope of the disclosed invention. Distances, angles, etc. are illustrative only and do not necessarily have an exact relationship to the actual size and layout of the illustrated devices. Components may be added, deleted, and / or rearranged. In addition, any specific features, aspects, methods, properties, characteristics, qualities, attributes, elements, etc. described herein in conjunction with the various examples may be used in all other examples described herein. In addition, any method described herein may be practiced using any device suitable for performing the steps described.

[0054] For the purpose of summarizing the present disclosure, certain aspects, advantages and features of the present invention are described herein. According to any specific example of the present invention disclosed herein, not all or any such advantages must be realized. No aspect of the present disclosure is necessary or indispensable. In many examples, devices, systems and methods can be configured differently from those shown in the figures or descriptions herein. For example, the various functionalities provided by the shown modules can be combined, rearranged, added or deleted. In some implementations, additional or different processors or modules can perform some or all of the functionalities described with reference to the examples described and illustrated in the accompanying drawings. Many implementation variations are possible. Any one of the features, structures, steps or processes disclosed in this specification may be included in any example.

Claims

1. A bonding structure, comprising: Semiconductor components, including active circuit devices; as well as A security die electrically connected along a bonding interface and directly bonded to the surface of the semiconductor element without adhesive, the security die comprising a security core, The secure core includes cryptographic logic and memory, and The secure core is configured to perform at least one of: decrypting a signal to be transmitted to the active circuit device and encrypting a signal received from the active circuit device. 2 . The bonding structure according to claim 1 , further comprising a via electrically connecting the security die and the semiconductor element.

3. The bonding structure according to claim 1, wherein the semiconductor element and the security die are hybrid bonded such that the semiconductor element and the non-conductive region of the security die are directly bonded, and the semiconductor element and the conductive region of the security die are directly bonded. 4 . The bonded structure of claim 1 , further comprising a barrier material over the security core, the barrier material configured to inhibit external access to the security core.

5. The bonded structure of claim 4, wherein the barrier material is part of a protection element that is directly bonded to a surface of the security die.

6. The bonded structure according to any one of claims 4 to 5, wherein the barrier material is bonded directly to the back side of the security die.

7. The joined structure of claim 4, wherein the barrier material comprises a destructive material having a hardness in the range of 20 GPa to 150 GPa on the Vickers hardness scale.

8. A joined structure according to any one of claims 4 to 7, wherein the barrier material comprises a destructive material having a hardness of at least 80 GPa on the Vickers hardness scale.

9. A joined structure according to any one of claims 4 to 8, wherein the barrier material comprises an abrasive material.

10. The joined structure of any one of claims 4 to 9, wherein the barrier material comprises a light blocking material. The bonded structure of claim 10 , wherein the light blocking material is configured to block light at near infrared (NIR) wavelengths.

12. A joined structure according to any one of claims 4 to 11, wherein the barrier material comprises an optical or infrared (IR) blocking or modifying material.

13. The bonded structure according to any one of claims 1 to 12, wherein an encapsulation material is provided over the semiconductor element and the security die. 14 . The bonded structure according to claim 1 , wherein the semiconductor element comprises a first bonding layer, and wherein the security die comprises a second bonding layer bonded directly to the first bonding layer without adhesive. The bonding structure according to claim 14 , wherein the first bonding layer comprises silicon oxide. 16 . The bonding structure according to claim 14 , further comprising a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads.

17. The joining structure according to any one of claims 1 to 16, wherein the memory stores an encryption key.

18. A bonding structure, comprising: Semiconductor components, including active circuit devices; a security die electrically connected along a bonding interface and directly bonded to the surface of the semiconductor element without an adhesive, the security die comprising a security core; as well as A barrier material is disposed over a surface of the security core, the barrier material being configured to inhibit external access to the security core. The bonded structure of claim 18 , wherein the secure core comprises cryptographic logic and memory. 20 . The bonding structure according to claim 18 , wherein the security core is configured to encrypt data to be transmitted to the active circuit device and decrypt signals received from the active circuit device.

21. A bonded structure according to any one of claims 18 to 20, wherein the barrier material is part of a protection element which is bonded directly to a surface of the security die.

22. The bonded structure according to any one of claims 18 to 21, further comprising a carrier, the security die being mechanically and electrically connected to the carrier. 23 . The bonding structure according to claim 18 , further comprising a via electrically connecting the security die and the semiconductor element.

24. The bonding structure according to any one of claims 22 to 23, further comprising a via electrically connecting the security die and the carrier.

25. The bonded structure according to any one of claims 22 to 24, wherein the carrier comprises a plurality of conductive bumps electrically connected to the semiconductor element and the security die.

26. A joined structure according to any one of claims 18 to 25, wherein the barrier material comprises a destructive material having a hardness in the range of 20 GPa to 150 GPa on the Vickers hardness scale.

27. A joined structure according to any one of claims 18 to 26, wherein the barrier material comprises a destructive material having a hardness of at least 80 GPa on the Vickers hardness scale.

28. A joined structure according to any one of claims 18 to 27, wherein the barrier material comprises an abrasive material.

29. The joined structure of any one of claims 18 to 28, wherein the barrier material comprises a light blocking material.

30. The bonded structure of claim 29, wherein the light blocking material is configured to block light in the near infrared (NIR) wavelength.

31. A joined structure according to any one of claims 18 to 30, wherein the barrier material comprises an optical or infrared (IR) blocking or modifying material.

32. The bonded structure of any one of claims 18 to 31 , wherein an encapsulation material is provided over the semiconductor element and the security die.

33. The bonded structure of any one of claims 18 to 32, wherein the semiconductor element comprises a first bonding layer, and wherein the security die comprises a second bonding layer bonded directly to the first bonding layer without an adhesive. The bonding structure of claim 33 , wherein the first bonding layer comprises silicon oxide.

35. The bonding structure according to any one of claims 18 to 34, wherein the security die further comprises a via extending through the substrate.

36. A method of forming a bonded structure, the method comprising: Providing a secure die having a secure core, the secure core including cryptographic logic and memory; The security core is directly bonded to the surface of a semiconductor element without adhesive so that the security core and the semiconductor element are electrically connected, and the security core is configured to perform at least one of the following: decryption of signals to be transmitted to the semiconductor element and encryption of signals to be received from the semiconductor element.

37. The method of claim 36, wherein the semiconductor element comprises an active circuit device.

38. The method of any one of claims 36 to 37, further comprising connecting vias between the semiconductor element and a security die.

39. The method of any one of claims 36 to 38, further comprising providing a barrier material over a surface of the security die, the barrier material being configured to prevent external access to the security die.

40. The method of any one of claims 36 to 39, further comprising providing an encapsulation material over the semiconductor element and the security die.

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