Detection method for back drilling depth and offset degree

Abstract

The invention relates to a method for detecting back drilling depth and offset degree, which comprises the following steps of: arranging a back drilling module: arranging the back drilling module in a board edge area of a printed circuit board (PCB), and drilling a test back drilling hole with the same depth as a back drilling hole to be tested on the back drilling module; determining a back drilling depth range and a test layer; a gradient copper-avoiding ring test module is arranged: a copper-avoiding ring is arranged outside each back drilling hole, and a test point is arranged in front of and behind each copper-avoiding ring respectively, that is, a copper-avoiding ring unit is formed between two adjacent test points; the test holes comprise two short-circuit test holes and four open-circuit test holes, a circuit is arranged on each layer of board, and the two short-circuit test holes and the two open-circuit test holes respectively form a communication loop with the circuit; performing a depth test; and carrying out offset degree detection. According to the invention, the test back drilling hole and the detection module are arranged in the board edge area of the printed circuit board, so that non-destructive, rapid and accurate detection is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board manufacturing, and in particular to a method for detecting backdrill depth and deviation. Background Art

[0002] Backdrilling is a crucial process in the production of printed circuit boards (PCBs). This involves removing copper from sections of through-holes that don't serve any connection or transmission function, preventing residual copper from causing signal distortion. However, controlling backdrill depth is a key factor influencing signal integrity during backdrilling quality control. Currently, metallographic section analysis is widely used for PCB backdrilling quality monitoring. The specific process involves physically cutting backdrilled samples during the first article verification phase, observing the cross-sectional morphology using a metallographic microscope, manually measuring the backdrill depth (STUB value), and estimating the average drill depth using multiple cross-sectional samples.

[0003] However, this approach has the following drawbacks: (1) Destructive testing: The slicing process is irreversible, resulting in a loss of 3-5% in the qualified product rate; (2) Poor timeliness: A single test takes a long time, about 1-2 hours, which cannot meet the needs of rapid line change; (3) Loss of spatial dimension: Traditional slicing can only obtain single-point two-dimensional data and cannot track the drilling axis offset. The X / Y direction deviation ≥ 0.05mm will affect the signal integrity, so the detection of the offset is also important; (4) Process control blind spot: Only first-piece confirmation can be performed, and real-time quality feedback in continuous production cannot be achieved.

[0004] Therefore, the present invention proposes a method for detecting backdrilling depth and deviation to overcome the above problems. Summary of the Invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings and provide a method for detecting backdrill depth and offset. By setting a test backdrill hole and a detection module in the board edge area of ​​a printed circuit board, non-destructive, fast and accurate detection is achieved.

[0006] The object of the present invention is achieved like this: A method for detecting backdrill depth and deviation includes the following: Set up the backdrill module: A backdrill module is provided in the board edge area of ​​the printed circuit board PCB, and a test backdrill hole having the same depth as the backdrill hole to be tested is drilled on the backdrill module; Determine the backdrill depth range and test layer: When determining the backdrill depth range, set the three adjacent layers of the corresponding depth as test layers based on the number of circuit board layers required for the backdrill depth. Set up a gradient copper ring test module: set up a copper ring outside each back-drilled hole, and set up a test point before and after the copper ring, that is, a copper ring unit is formed between two adjacent test points; set up n copper rings with increasing copper ring amount gradient; Set up 6 test holes around the PTH hole: the test holes include 2 short-circuit test holes and 4 open-circuit test holes. There is a circuit on each layer of the board, and the 2 short-circuit test holes and 2 open-circuit test holes form a connecting loop with the circuit respectively; Perform depth testing; Perform deviation detection.

[0007] Furthermore, in the gradient copper avoidance ring test module, the single-side copper avoidance amount of the copper avoidance ring is gradually increased by 12.7μm radius increments to achieve micron-level offset detection, that is, the single-side copper avoidance amount of the nth copper avoidance ring = the initial copper avoidance ring radius r1 + ( n- 1) × 12.7 μm .

[0008] Furthermore, in the gradient copper ring avoidance test module, the diameter D1 of the copper ring avoidance is dynamically bound to the aperture D of the back-drilled hole, and the diameter D1 of the copper ring avoidance is D Back drilling + 2× single-side copper avoidance.

[0009] Furthermore, in the gradient copper loop avoidance test module, the aperture tolerance is compensated by a 1.2 times coefficient, that is, the copper loop avoidance line width = backdrilling aperture tolerance × 1.2.

[0010] Furthermore, in the gradient copper loop avoidance test module, the ring spacing of the copper loop avoidance is ≥ 2×the copper loop avoidance line width.

[0011] Furthermore, the depth test includes: testing the continuity between each group of test holes. If there is a continuity between a group of test holes, it means that the test layers corresponding to the group of test holes are conductive, and the backdrilling depth has not reached this layer; conversely, if there is an open circuit between a group of test holes, it means that the test layers corresponding to the test holes are disconnected, and the backdrilling depth has reached this layer.

[0012] Furthermore, the offset detection includes: in the normal state, IN-OUT is conductive; when the backdrill offset touches a certain copper avoidance ring, the specific trigger ring number is judged through an independent test point to determine the offset.

[0013] Furthermore, the welding ring of the connecting loop formed by the two short-circuit test holes and the two open-circuit test holes and the circuit is at least 0.1 mm larger than a single side of the test hole.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a method for detecting backdrill depth and deviation, including a gradient copper ring avoidance design system, a daisy chain topology network, and a depth determination target design. This method can effectively overcome the shortcomings of existing technologies and improve production efficiency and product quality. It has the following advantages: (1) Non-destructive testing: avoids the loss of qualified product rate caused by physical cutting and improves production efficiency.

[0015] (2) Rapid detection: The detection and analysis results are fast, which can meet the needs of rapid line change and improve production efficiency.

[0016] (3) Multi-dimensional detection: It can track the offset of the drilling axis and provide more comprehensive detection data.

[0017] (4) Real-time quality feedback: Ability to provide real-time feedback of quality information during continuous production, and timely discover and correct problems in the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a top view of the gradient copper ring avoidance test module of the present invention.

[0019] Figure 2 This is a schematic diagram of the first layer circuit board surface of the present invention.

[0020] Figure 3 This is a schematic diagram of the second layer circuit board surface of the present invention.

[0021] Figure 4 This is a schematic diagram of the third layer circuit board surface of the present invention.

[0022] Figure 5 This is a schematic diagram of the 4th layer circuit board surface of the present invention.

[0023] Figure 6 This is a schematic diagram of the 6th layer circuit board surface of the present invention.

[0024] Figure 7 Schematic diagram of the backdrilling depth requirement structure of Example 1 of the present invention.

[0025] in: PTH hole 1, copper ring 2, back drill hole 3, test point 4, test hole 5. DETAILED DESCRIPTION

[0026] To better understand the technical solution of the present invention, the following detailed description is provided with reference to the relevant illustrations. It should be understood that the following specific embodiments are not intended to limit the specific implementation of the technical solution of the present invention; they are merely examples of possible implementations of the technical solution of the present invention. It should be noted that references herein to the positional relationships of various components, such as component A being located above component B, are based on the relative positions of the components in the illustrations and are not intended to limit the actual positional relationships of the components. Example 1

[0027] See also Figure 1-Figure 7 , Figure 1 A top view of the gradient copper loop avoidance test module of the present invention is drawn. As shown in the figure, a backdrill depth and offset detection method of the present invention is based on a gradient copper loop avoidance test module of Example 1. The gradient copper loop avoidance test module includes multiple PTH holes 1, copper loop avoidance rings 2, backdrill holes 3, test points 4, and test holes 5 arranged on a 6-layer PCB circuit board.

[0028] The first layer circuit board is provided with n+1 test points 4 and n PTH holes 1 arranged equidistantly, and a PTH hole 1 is provided at the center position between two adjacent test points 4, that is, a test point 4 is provided on the left and right sides of each PTH hole 1; There are 6 test holes 5 between two adjacent test points 4. These 6 test holes 5 are arranged equidistantly around the PTH hole 1 between the two test points 4 to form a regular hexagon with the PTH hole 1 as the center. The test hole on the upper left of the PTH hole 1 is test hole No. 1 (i.e., endpoint No. 1), the test hole on the lower left of the PTH hole 1 is test hole No. 4, the test hole on the upper right of the PTH hole 1 is test hole No. 3, the test hole on the lower right of the PTH hole 1 is test hole No. 2, the test hole directly above the PTH hole 1 is test hole No. 5, and the test hole directly below the PTH hole 1 is test hole No. 6.

[0029] A cross circuit is set on the second layer circuit board, and a back-drilled hole 3 is set on the PTH hole 1. The aperture D of the back-drilled hole 3 is larger than the aperture of the PTH hole 1. A connecting line passing through the back-drilled hole 3 is set between the No. 1 test hole and the No. 2 test hole, and a connecting line passing through the back-drilled hole 3 is set between the No. 3 test hole and the No. 4 test hole, thereby forming a cross circuit.

[0030] The third layer circuit board is provided with n copper avoidance rings 2 with increasing copper avoidance gradients, a copper avoidance ring 2 is provided outside each back-drilled hole 3, and the copper avoidance ring 2 is provided between the front and rear test points 4, forming a copper avoidance ring unit between two adjacent test points 4; The first copper ring (No. 1 copper ring) is the copper ring outside the back-drilled hole between the first test point and the second test point. The second copper ring (No. 2 copper ring) is the copper ring outside the back-drilled hole between the second test point and the third test point. The third copper ring (No. 3 copper ring) is the copper ring outside the back-drilled hole between the third test point and the fourth test point. And so on. The nth copper ring (No. n copper ring) is the copper ring outside the back-drilled hole between the nth test point and the n+1th test point.

[0031] A line is set on the fourth layer circuit board, and a connecting line is set between the No. 5 test hole and the No. 6 test hole, thereby forming a line.

[0032] The sixth-layer circuit board is provided with the same PTH holes 1 , test points 4 and test holes 5 as those of the first-layer circuit board, and a back-drilled hole 3 is provided on the PTH hole 1 .

[0033] Therefore, see Figure 1 , 6 layers of circuit boards are stacked to form a daisy chain topology network, and the connection architecture is as follows: Test point → Avoid copper loop 1 → Test point 1 → Avoid copper loop 2 → ... → Avoid copper loop N → Test point N.

[0034] Radius step algorithm: Based on the theoretical backdrilling aperture, the single-side copper avoidance amount is increased step by step by 0.5mil (12.7μm) radius increments to achieve micron-level offset detection; the single-side copper avoidance amount of the nth ring = initial copper avoidance radius r1 + ( n- 1) × 12.7 μm .

[0035] Diameter correlation design: To ensure that the design parameters are directly related to the production process, the diameter D1 of the copper ring 2 is dynamically bound to the aperture of the back-drilled hole 3 (hereinafter referred to as the back-drilled aperture) D. The diameter of the copper ring D1 = D Back drilling + 2× single-side copper avoidance.

[0036] Tolerance coverage: Backdrilling aperture fluctuation: During the drilling process, the actual aperture may fluctuate within the tolerance range (e.g. ±15μm) due to factors such as drill bit wear and mechanical vibration. Failure risk of copper rings: If the copper ring width is designed based solely on theoretical values ​​(e.g., 15 μm in this embodiment), a backdrilled aperture with a positive tolerance (+15 μm) may result in: drilling through the copper ring (misjudged as an offset exceeding the tolerance) or bridging between adjacent copper rings (false short circuit alarm). Therefore, in this embodiment, a 1.2x factor is used to compensate for the aperture tolerance to ensure that the copper ring remains fully functional even if the backdrilled aperture exceeds the tolerance. Copper ring line width = backdrill hole diameter tolerance × 1.2. In this embodiment: tolerance ±15 μm → line width ≥ 18 μm.

[0037] Ring spacing design: Ring spacing ≥ 2× copper avoidance ring line width. In this embodiment: 18μm line width → 36μm spacing.

[0038] Specific implementation data: 1. Backdrilling hole diameter D = 500μm, initial single-side copper avoidance = 30μm (diameter increment 60μm); 2. The copper avoidance amount on one side of the third ring = 30 + 2 × 12.7 = 55.4 μm → The diameter of the copper ring = 500 + 2 × 55.4 = 610.8 μm; 3. Copper loop width: 15 μm × 1.2 = 18 μm ⇒ The tolerance of the positive aperture can be up to +18 μm; 4. Copper ring spacing design: line width = 18μm, ring spacing = 30μm (2 times the line width).

[0039] A backdrill depth detection method of the first embodiment is based on the above-mentioned gradient copper ring avoidance test module and includes the following contents: S1. Set up the backdrill module; A backdrill module is provided in the board edge area of ​​the printed circuit board PCB, and a test backdrill hole having the same depth as the backdrill hole to be tested is drilled on the backdrill module; S2. Determine the backdrilling depth range and test layer; When determining the backdrill depth range, set the three adjacent layers of the corresponding depth as test layers based on the number of circuit board layers required for the backdrill depth. Determine the backdrill depth range. Based on the number of circuit board layers required for the backdrill depth, i.e., layers 2-4, set as test layers. S3, set up the gradient copper ring avoidance test module; S3.1. Set up 6 test holes around the PTH hole: the test holes include 2 short-circuit test holes and 4 open-circuit test holes. There is a circuit on each layer of the board. The 2 short-circuit test holes and 2 open-circuit test holes form a connecting loop with the circuit. The solder ring is at least 0.1mm larger than the single side of the test hole. S3.2, set up the copper ring according to the gradient; S4, depth test; Test the continuity between each group of test holes. If there is a continuity between a group of test holes, it means that the test layers corresponding to this group of test holes are connected and the backdrilling depth has not reached this layer. Conversely, if there is a disconnection between a group of test holes, it means that the test layers corresponding to this group of test holes are disconnected and the backdrilling depth has reached this layer.

[0040] Specific implementation data: 1. See Figure 7 , taking a 6-layer board as an example: Layer 2 (protective layer): horizontal straight lines, line width 5mil, end points connected to PTH holes; Layer 4 (needs to be interrupted): cross-connection line, line width 3mil, end point connected to PTH hole.

[0041] Electrical logic: Layer 2 endpoints 5-6 are connected; The 1-2 and 3-4 endpoints of Layer 4 are open; Test result: The back drilling depth is qualified (L4 is interrupted but L2 is not damaged).

[0042] 2. Take 8-layer board as an example: Layer 2 (needs to be interrupted): cross-connection line, line width 3mil, end point connected to PTH hole; Layer 4 (protective layer): horizontal straight line, line width 5mil, end point connected to PTH hole.

[0043] Electrical logic: The 1-2 and 3-4 endpoints of Layer 2 are open: Perform a power-on test on the circuit connected to the test hole in the L2 layer of the PCB board. If the test result is an open circuit, it is determined that the backdrilled hole has passed through the L2 layer board; The 5-6 terminals of Layer4 are connected: Perform a power-on test on the circuit connected to the test hole in the L4 layer of the PCB board. If the test result is continuity, it is determined that the backdrilled hole has not interrupted the L4 layer board; Test result: The back drilling depth is qualified (L2 is broken but L4 is not damaged).

[0044] A backdrill offset detection method of the first embodiment is based on the above-mentioned gradient copper ring avoidance test module and includes the following contents: S1, normal state: when the copper rings are not in contact with the back drill, IN-OUT is conductive; S2, offset trigger: When the backdrill offset touches a copper hole ring, IN → the ring → open circuit; S3. Precise positioning: Through independent test points (test point 1-test point n), determine the specific trigger ring number and calculate the offset based on the copper ring number. If test point 3 is conductive, the offset is ≤55.4μm.

[0045] Working principle: The present invention provides a method for detecting backdrill depth and deviation, the core innovations of which are as follows: (1) Gradient copper ring avoidance design system: Radius step algorithm: Based on the theoretical backdrilling aperture, the single-side copper avoidance amount is increased step by step in 0.5mil (12.7μm) radius increments to achieve micron-level offset detection.

[0046] Diameter-linked design: The diameter of the copper ring is dynamically bound to the back-drilled hole diameter to ensure that the design parameters are directly linked to the production process.

[0047] Tolerance coverage: The hole diameter tolerance is compensated by a factor of 1.2, ensuring that the copper ring can maintain full functionality even if the back-drilled hole diameter is out of tolerance.

[0048] Ring spacing design: Ring spacing ≥ 2× copper ring width.

[0049] (2) Daisy chain topology network (through the daisy chain topology network, accurate positioning of backdrill offset is achieved): Connection structure: test point → copper loop 1 → test point 1 → copper loop 2 → ... → copper loop N → test point N.

[0050] Detection mechanism: In normal state, IN-OUT is conductive. When the backdrill offset touches a copper avoidance ring, the specific trigger ring number is determined through independent test points to determine the offset amount.

[0051] (3) Depth determination target design (determine the backdrilling depth through depth determination target design): Test holes: including 2 short-circuit test holes and 4 open-circuit test holes. There is a circuit on each layer of the board. The test holes and the circuits form a connected loop. The welding ring is at least 0.1mm larger than the single side of the test hole.

[0052] Test layer: According to the number of circuit board layers required by the backdrilling depth, set three adjacent layers with corresponding depths as test layers.

[0053] Backdrill module: A backdrill module is set in the edge area of ​​the printed circuit board PCB, and a test backdrill hole with the same depth as the backdrill hole to be tested is drilled on the backdrill module.

[0054] Test logic: Test the continuity between each group of test holes. If there is a continuity between a group of test holes, it means that the test layers corresponding to this group of test holes are connected and the backdrilling depth has not reached this layer. Conversely, if there is an open circuit between a group of test holes, it means that the test layers corresponding to this group of test holes are disconnected and the backdrilling depth has reached this layer.

[0055] The above are only specific application examples of the present invention and do not constitute any limitation on the scope of protection of the present invention. Any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the scope of protection of the present invention.

Claims

1. A method for detecting backdrilling depth and deviation, characterized in that: Includes the following: Set up the backdrill module: A backdrill module is provided in the board edge area of ​​the printed circuit board PCB, and a test backdrill hole having the same depth as the backdrill hole to be tested is drilled on the backdrill module; Determine the backdrill depth range and test layer: When determining the backdrill depth range, set the three adjacent layers of the corresponding depth as test layers based on the number of circuit board layers required for the backdrill depth. Set up a gradient copper ring test module: set up a copper ring outside each back-drilled hole, and set up a test point before and after the copper ring, that is, a copper ring unit is formed between two adjacent test points; set up n copper rings with increasing copper ring amount gradient; Set up 6 test holes around the PTH hole: the test holes include 2 short-circuit test holes and 4 open-circuit test holes. There is a circuit on each layer of the board, and the 2 short-circuit test holes and 2 open-circuit test holes form a connecting loop with the circuit respectively; Perform depth testing; Perform deviation detection.

2. The method for detecting backdrill depth and deviation according to claim 1, wherein: In the gradient copper avoidance ring test module, the single-side copper avoidance amount of the copper avoidance ring is gradually increased by 12.7μm radius increments to achieve micron-level offset detection, that is, the single-side copper avoidance amount of the nth copper avoidance ring = the initial copper avoidance ring radius r1 + ( n- 1) × 12.7 μm .

3. The method for detecting backdrill depth and deviation according to claim 1, wherein: In the gradient copper ring avoidance test module, the diameter D1 of the copper ring is dynamically bound to the back-drilled hole diameter D. The diameter D1 of the copper ring avoidance is D Back drilling + 2× single-side copper avoidance.

4. The method for detecting backdrill depth and deviation according to claim 1, wherein: In the gradient copper loop avoidance test module, the aperture tolerance is compensated by a 1.2 times coefficient, that is, the copper loop line width = backdrilling aperture tolerance × 1.

2.

5. The method for detecting backdrilling depth and deviation according to claim 1, wherein: In the gradient copper loop avoidance test module, the copper loop spacing must be ≥ 2 × the copper loop line width.

6. The method for detecting backdrill depth and deviation according to claim 1, wherein: The depth test includes: testing the continuity between each group of test holes. If there is a continuity between a group of test holes, it means that the test layers corresponding to the group of test holes are connected and the backdrilling depth has not reached this layer. Conversely, if there is an open circuit between a group of test holes, it means that the test layers corresponding to the test holes are disconnected and the backdrilling depth has reached this layer.

7. The method for detecting backdrill depth and deviation according to claim 1, wherein: The offset detection includes: in the normal state, IN-OUT is conductive; when the backdrill offset touches a certain copper avoidance ring, the specific trigger ring number is determined through independent test points to determine the offset amount.

8. The method for detecting backdrill depth and deviation according to claim 1, wherein: The two short-circuit test holes and the two open-circuit test holes form a connecting loop with the circuit, and the welding ring thereof is at least 0.1 mm larger than a single side of the test hole.

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