A loop control method and system based on RISC-V extension

Abstract

The application discloses a loop control method and system based on RISC-V extension, and self-defines a loop control instruction in a main operation code and instruction coding space reserved by RISC-V; a fetch instruction module, a decoding module, a state control register and a hardware loop control module are designed, the decoding module writes loop information into the state control register, the hardware loop control module reads the loop information from the state control register, and arbitration is performed in combination with a control signal of the decoding module and an instruction address; when a current address does not reach a loop end, an enabling signal is sent to make the fetch instruction module fetch instructions in sequence; when the current address reaches a last instruction of a loop segment and a loop number is not zero, a loop start address is sent to the fetch instruction module to make it continue to loop, and a conditional jump instruction for existing loop judgment is saved; for an assembly instruction part for loop control, the assembly instruction part is replaced by the loop control instruction extended by the application, and performance loss caused by a loop program can be effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the field of computer instruction technology, and specifically relates to a loop control method and system based on RISC-V extension. Background Art

[0002] With the development of computing technology, the demand for digital signal processing is increasing. Digital signal processing involves fixed-point, floating-point, real, and complex numbers. Common algorithms include fast Fourier transforms, filtering, and vector-related calculations. These algorithms are logically complex and computationally intensive.

[0003] The instruction set mainly refers to the interface description between hardware and software. It is the part of computer architecture related to program design. It contains a series of opcodes, namely operation codes (machine language), and basic commands executed by specific processors.

[0004] Designers at the software layer design and write code based on the instruction set as the design specification and reference standard. When designing the processor, hardware designers design specific decoding and operation circuits to support the operation of these instructions according to the instructions specified in the instruction set.

[0005] When the processor architecture is fixed, for software programmers, when designing a function or a program, the number of instructions generated and the time it takes to execute each instruction largely determine its performance.

[0006] Instruction sets are divided into two categories based on their characteristics: complex instruction set computing (CISC) and reduced instruction set computing (RISC).

[0007] The RISC-V instruction set is a concise instruction set architecture with technical advantages such as low power consumption, low cost, open source, and modularity. Compared to mainstream frameworks like x86 or ARM architecture, RISC-V is relatively compact and has high program execution efficiency. Furthermore, RISC-V is organized in a modular format, with simple and standardized coding that makes it easy to design and expand. However, RISC-V has fewer instructions and is not as powerful as CISC. For example, algorithms in the field of digital signal processing often contain a large number of loops, and during the execution of a loop, the execution of a loop body requires the implementation of loop parameter changes, judgments, and jump instructions. The implementation of judgments and jumps, in particular, consumes a large number of cycles when implemented in hardware circuits, resulting in a longer execution time for the entire instruction. Summary of the Invention

[0008] The purpose of the present invention is to provide a loop control method and system based on RISC-V extension, which customizes loop control instructions in the main opcode reserved by RISC-V and part of the customized extended coding space reserved for users, realizes zero hardware overhead, shortens instruction execution time, and significantly improves processor performance.

[0009] The present invention is achieved by adopting the following technical solutions:

[0010] A loop control method based on RISC-V extension is proposed, including:

[0011] In the main opcode and reserved instruction encoding space reserved by RISC-V, the custom loop control instructions RPTB and RPTBI are defined; RPTB selects opcode = 1011011 as the opcode, the function code funct3 is defined as 000, and the encoding format is RPTB #uimm8, rs1, uimm8 is an unsigned immediate number used to specify the loop body length, rs1 is a register, indicating the number of loops read from the register, and the number of loops is rs1+1; RPTBI selects opcode = 1011011 as the opcode, the function code funct3 is defined as 001, and the encoding format is RPTBI #uimm8_1, #uimm8_2, uimm8_1 is an unsigned immediate number used to specify the loop body length, uimm8_2 is an unsigned immediate number used to indicate the number of loops, and the number of loops is uimm8_2+1;

[0012] The processor is designed with an instruction fetch module, a decoding module, a status control register and a hardware loop control module. After obtaining the loop control instruction, the decoding module writes the loop information into the address specified by the status control register. The loop information includes the length of the loop code segment, the number of loops, the loop start address and the loop enable status. The hardware loop control module reads the loop information from the status control register and arbitrates in combination with the control signal of the decoding module and the instruction address: when the current address has not reached the end of the loop, an enable signal is sent to enable the instruction fetch module to continue fetching instructions in sequence; when the current address reaches the last instruction of the loop segment and the number of loops has not returned to zero, the loop start address is sent to the instruction fetch module to enable it to continue looping. The hardware loop control module controls the instruction fetch address based on the pipeline information of the current decoding level and the loop information, and sends the program counter value of the next instruction to the instruction fetch module.

[0013] In some embodiments of the present invention, the processor adopts a static single-issue structure, and the pipeline is divided into eight stages, the first three stages are for value acquisition, and the last five stages are for execution;

[0014] The instruction fetch function is divided into a three-stage pipeline, the decoding function is completed by a one-stage pipeline, the fixed-point operation and memory access operation are completed by a three-stage pipeline, and the floating-point operation is completed by a four-stage pipeline; the hardware loop instruction controls the instruction execution order of the pipeline.

[0015] In some embodiments of the present invention, the pause control signal sent by the decoding module to the pipeline is shared with the hardware loop control module. When the pipeline pauses, the hardware loop control module also enters a pause state.

[0016] In some embodiments of the present invention, the interface signals implemented by the hardware loop control module include:

[0017] Interaction with the instruction fetch module includes: output o_hwloop_ifu_end_pc, loop end address; output o_hwloop_ifu_start_pc, loop start address; output o_hwloop_ifu_enable, loop process decoding module enable, high level is valid;

[0018] Interaction with the decoding module includes: input i_hwloop_idu_pc, the current PC value, used for PC comparison; input i_hwloop_idu_stall, the pipeline pause signal;

[0019] The interaction with the status control register includes: input i_hwloop_csr_start_pc, loop start address; input i_hwloop_csr_length, loop block length; input i_hwloop_csr_num, loop number; input i_hwloop_csr_he, loop enable, high-level loop is valid; output o_hwloop_csr_num, real-time loop number, update status control register; output o_hwloop_csr_he, loop enable; output o_hwloop_csr_we, status control register write enable signal.

[0020] A loop control system based on RISC-V extension is proposed, including:

[0021] The analysis unit is used to analyze the existing algorithm and find calculations that can use extended instructions; analyze the assembly code of the algorithm and extract assembly instructions that can be optimized;

[0022] An optimization unit, configured to replace the extracted assembly instructions that can be optimized with loop control instructions in the loop control method based on RISC-V extension as described above;

[0023] Instruction fetch module, used to obtain loop control instructions;

[0024] The decoding module is used to obtain the loop control instruction from the instruction fetch module and write the loop information into the address specified by the status control register. The loop information includes the loop code segment length, the number of loops, the loop start address and the loop enable status.

[0025] The hardware loop control module is used to read the loop information from the status control register and arbitrate in combination with the control signal of the decoding module and the instruction address: when the current address has not reached the end of the loop, an enable signal is sent to enable the instruction fetch module to continue fetching instructions in sequence; when the current address reaches the last instruction of the loop segment and the number of loops has not returned to zero, the loop start address is sent to the instruction fetch module to enable it to continue the loop; the hardware loop control module controls the instruction fetch address based on the pipeline information of the current decoding level and the loop information, and sends the program counter value of the next instruction to the instruction fetch module.

[0026] Compared with the prior art, the advantages and positive effects of the present invention are as follows: in the loop control method and system based on RISC-V extension proposed by the present invention, a custom loop control instruction is defined in the main operation code and reserved instruction encoding space reserved by RISC-V, and the loop body length and the number of loops are defined; an instruction fetch module, a decoding module, a state control register and a hardware loop control module are designed; the decoding module obtains the loop control instruction from the instruction fetch module and writes the loop information into the address specified by the state control register; the hardware loop control module reads the loop information from the state control register and performs arbitration based on the control signal of the decoding module and the instruction address; when the current address does not reach the end of the loop, an enable signal is sent to enable the instruction fetch module to fetch instructions in sequence; when the current address reaches the last instruction of the loop segment and the number of loops has not returned to zero, the loop start address is sent to the instruction fetch module to enable it to continue the loop, thereby eliminating the conditional jump instruction for existing loop judgment; for the assembly instruction part for loop control, it is replaced with the loop control instruction extended by the present invention, which can effectively reduce the performance loss caused by the loop program.

[0027] Other features and advantages of the present invention will become more apparent after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The design idea of ​​the loop control method based on RISC-V extension proposed by the present invention;

[0029] Figure 2 The architecture of the hardware loop control in the present invention;

[0030] Figure 3 It is the RISC-V basic instruction format;

[0031] Figure 4 This is the processor core pipeline division in the method of the present invention. DETAILED DESCRIPTION

[0032] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0033] This invention comprehensively considers the characteristics of RISC-V and signal processing fields, and proposes a zero-overhead hardware loop control instruction based on the digital signal processing instruction set system of the reduced instruction set on the basis of the RISC-V architecture, such as Figure 1 As shown in the figure, in terms of software design, the RISC-V instruction set is used for instruction extension (RPTB and RPTBI). In terms of hardware design, hardware implementation (instruction fetch, decoding, hardware loop control, status control register) is carried out according to the extended instructions to reduce the number of instructions required for the hardware to execute a unified program, improve the performance of the processor, and solve the problems of large computational complexity and complex logic in the field of digital signal processing.

[0034] RISC-V defines six basic instruction formats, such as Figure 3 As shown, they are: R-type instructions for register-register operations, I-type instructions for short immediate and memory load operations, S-type instructions for memory store operations, B-type instructions for conditional jump operations, U-type instructions for long immediate and J-type instructions for unconditional jumps.

[0035] The lower 7 bits (inst[6:0]) of the standard are called the operation code (opcode). When the lower two bits (inst[1:0]) are 00, 01, or 10, it indicates a compressed instruction (RVC), with a 16-bit instruction encoding length. When the lower two bits are 11, it indicates an uncompressed instruction. When bits 3-5 are 111, the instruction encoding length is greater than 32 bits. For other opcode values, the instruction encoding is 32 bits.

[0036] inst[6:2] is called the major opcode. There are 32 major opcodes in total, as shown in Table 1 below:

[0037] Table 1 RISC-V main opcode encoding distribution

[0038]

[0039] In the table, the first row represents the binary encoding of inst[4:2] bits, and the first column represents the binary encoding of inst[6:5] bits. The bold black font represents the primary opcodes used by RISC-V basic instructions; custom0~3 are the four primary opcodes reserved by RISC-V for user-defined extended instructions; reserved is reserved for future extensions of the RISC-V standard and cannot be used by users; there are also some instruction codes used by RISC-V instruction extensions that are not adopted by this system, as well as two primary opcodes (48b) corresponding to >32-bit instruction codes.

[0040] The loop control instruction proposed in the present invention is extended on the RISC-V standard instruction set, occupying the four reserved RISC-V main opcodes and part of the RVC reserved for user-defined extended coding space.

[0041] The zero-overhead hardware loop control instructions designed in this invention are divided into register-based RPTB and immediate-valued RPTBI instructions, collectively referred to as RPTB instructions. The loop count of register-based RPTB instructions is determined by reading the value in the register, while the loop count of immediate-valued RPTBI instructions is set by the user.

[0042] (1) RPTB instruction.

[0043] Instruction syntax: RPTB #uimm8, rs1.

[0044] Instruction Description: This instruction indicates that the subsequent instructions will be executed cyclically.

[0045] The loop body length is specified by the unsigned immediate value uimm8, and the number of loops is rs1+1. Not all instructions can be executed in the loop. Subsequent instructions cannot be interrupted during the loop execution.

[0046] (2)RPTBI instruction.

[0047] Instruction syntax: RPTBI #uimm8_1, #uimm8_2.

[0048] Instruction Description: This instruction indicates that the subsequent instructions will be executed cyclically.

[0049] uimm8_1 is an 8-bit unsigned immediate value, ranging from 0 to 255, indicating the length of the loop body; uimm8_2 is an 8-bit unsigned immediate value, ranging from 0 to 255, indicating the number of loops, which is uimm8_2+1. Not all instructions can be executed in a loop. Subsequent instructions cannot be interrupted during the loop execution. This is shown in Table 2 below:

[0050] Table 2 Loop control instruction encoding

[0051]

[0052] In the table, the first row indicates the number of bits, the second row indicates the number of binary coded bits of the RPTB instruction, and the third row indicates the number of binary coded bits of the RPTBI instruction, where uimm indicates a parameter.

[0053] [14:12] corresponds to funct3, [6:0] corresponds to pocode. By decoding the two, the corresponding instructions can be determined. For example, the 32-bit encoding shown in Table 3 below:

[0054] 32'b0_00001000_000__00000_001_10000_1011011; The corresponding instruction is: RPTBI 16,8.

[0055] Table 3 RPTBI instruction encoding

[0056]

[0057] In the table, the first row indicates the number of bits, the second row indicates the number of encoding bits of the RPTBI instruction, and the third row indicates the binary encoding value of the RPTBI instruction, where uimm indicates the parameter.

[0058] The hardware loop control structure of the processor design is as follows Figure 2 As shown in the figure, it consists of an instruction fetch module, a decoding module, a status control register, and a hardware loop control module:

[0059] After obtaining the loop control instruction, the decoding module writes the loop information into the corresponding address of the status control register. The loop information includes: the length of the loop code segment, the number of loops, the loop start address and the loop enable status.

[0060] The hardware loop control module reads loop information from the status register and uses the decoder module's control signal and instruction address to perform arbitration. If the current address has not reached the end of the loop, it sends an enable signal to the instruction fetch module to continue fetching instructions sequentially. If the current address reaches the last instruction in the loop and the loop count has not returned to zero, it sends the loop start address to the instruction fetch module to continue the loop. During this process, the decoder module shares the pause control signal sent to the pipeline with the hardware loop control module. When the pipeline pauses, the hardware loop control module also enters a pause state.

[0061] The processor of the present invention adopts a static single-issue structure, and the pipeline is as follows Figure 4As shown, the processor is divided into eight stages. The first three stages are instruction fetch (F1, F2, and F3). Decoding is performed using a one-stage pipeline (ID stage). Fixed-point operations and memory accesses are aligned using a three-stage pipeline (execute, store, and writeback stages). Floating-point operations are performed using a four-stage pipeline (FX1, FX2, FX3, and FWB stages). After the decoding stage, the processor core pipeline is divided into a fixed-point pipeline and a floating-point pipeline, respectively. These two pipelines execute in parallel, increasing instruction-level parallelism and improving instruction throughput. Hardware loop instructions control the order in which instructions are executed in the pipeline.

[0062] The interface signals implemented by the hardware loop control module are shown in Table 4 below:

[0063] Table 4 Hardware loop control module interface signals

[0064]

[0065] The hardware loop control module obtains instruction information from the decoder module, including the starting program counter (PC), loop length, and loop count, from the RPTB. This information is then written to the control status register. Based on the pipeline information of the current decoder stage (current program counter value, stall signals, etc.), combined with the loop information in the control status register, the hardware loop control module controls the instruction fetch address and sends the program counter value for the next instruction to the instruction fetch unit.

[0066] The following is a comparative explanation of the loop control method proposed by the present invention and the existing loop control method in conjunction with the application process.

[0067] The processor's hardware loop control module is used to set status information such as the loop coefficient register (Loop Count). The processor will continuously fetch and execute instructions based on the loop status information. Each time a loop is completed, the Loop Count value will decrease by 1. The loop will continue until the Loop Count value reaches 0 and the soul ring is exited. For example, the following calculation program:

[0068] for (int i = 0; i <n; i = i + 1) {

[0069] total = total + ai;

[0070] }

[0071] The corresponding RISC-V instruction program segment is as follows:

[0072] # Start of for loop.

[0073] addi x1, zero, 0

[0074] bge x1, x2, _joinPoint

[0075] _forLoop:

[0076] add x5, x5, x3 # x5 stores the value of total, x3 stores the value of a

[0077] addi x1, x1, 1

[0078] blt x1, x2, _forLoop

[0079] _joinPoint:

[0080] # Code after loop.

[0081] When executing the above program, the processor uses conditional jump instructions to check the branch condition. If the loop condition is met, the processor uses the blt instruction to jump to the start of the forLoop code segment. However, when the processor executes a software loop, it loses clock cycles, affecting instruction execution time and performance.

[0082] Replacing the conditional jump instructions used in loop condition checks with the RPTB instruction of the present invention effectively reduces the performance loss associated with loop programs. As shown below, during the compilation phase, the processor can determine the loop length and number of iterations. The RPTB instruction replaces the blt instruction. The code segment enclosed by the "#" block is looped until the target number of iterations is reached, thus reducing clock cycle loss by eliminating the need for conditional jump instructions.

[0083] # Start of for loop.

[0084] addi x1, zero, 0

[0085] RPTB #repeat code in # n time

[0086] #################################

[0087] add x5, x5, x3 # total = total + a , x5 stores the value of total, x3 stores the value of a

[0088] #################################

[0089] _joinPoint:

[0090] # Code after loop.

[0091] When applying the extended loop control instructions described above, the first step is to analyze existing algorithms to identify calculations that can use the extended instructions. Secondly, the algorithm's assembly code is analyzed to extract assembly instructions that can be optimized and replace them with the loop control instructions proposed in this invention. For digital signal processing functions, a significant portion of the function segments use for loops to calculate results. This design, while increasing hardware complexity, supports loop instructions, resulting in significant performance improvements.

[0092] It should be pointed out that the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A loop control method based on RISC-V extension, characterized in that: include: In the RISC-V reserved main opcode and reserved instruction encoding space, customize the loop control instructions RPTB and RPTBI; RPTB selects opcode=1011011 as the operation code, function code funct3 is defined as 000, and the encoding format is RPTB #uimm8,rs1, uimm8 is an unsigned immediate value used to specify the loop body length, rs1 is a register, indicating the number of loops read from the register, and the number of loops is rs1+1; RPTBI selects opcode=1011011 as the operation code, function code funct3 is defined as 001, and the encoding format is RPTBI #uimm8_1, #uimm8_2, uimm8_1 is an unsigned immediate value used to specify the loop body length, uimm8_2 is an unsigned immediate value used to indicate the number of loops, and the number of loops is uimm8_2+1; The processor is designed with an instruction fetch module, a decoding module, a state control register, and a hardware loop control module. After obtaining the loop control instruction, the decoding module writes loop information into the address specified by the state control register. The loop information includes the loop code segment length, the number of loops, the loop start address, and the loop enable status. The hardware loop control module reads the loop information from the status control register and performs arbitration based on the control signal of the decoding module and the instruction address: if the current address has not reached the end of the loop, it sends an enable signal to enable the instruction fetch module to continue fetching instructions in sequence; When the current address reaches the last instruction of the loop segment and the number of loops has not returned to zero, the loop start address is sent to the instruction fetch module to enable it to continue the loop; the hardware loop control module controls the instruction fetch address based on the pipeline information of the current decoding level and the loop information, and sends the program counter value of the next instruction to the instruction fetch module.

2. The loop control method based on RISC-V extension according to claim 1, characterized in that: The processor adopts a static single-issue structure, and the pipeline is divided into eight stages, the first three stages are for value acquisition, and the last five stages are for execution; The instruction fetch function is divided into a three-stage pipeline, the decoding function is completed by a one-stage pipeline, the fixed-point operation and memory access operation are completed by a three-stage pipeline, and the floating-point operation is completed by a four-stage pipeline; the hardware loop instruction controls the instruction execution order of the pipeline.

3. The loop control method based on RISC-V extension according to claim 2, characterized in that: The pause control signal sent by the decoding module to the pipeline is shared with the hardware loop control module. When the pipeline pauses, the hardware loop control module also enters a pause state.

4. The loop control method based on RISC-V extension according to claim 1, characterized in that: The interface signals implemented by the hardware loop control module include: Interaction with the instruction fetch module includes: output o_hwloop_ifu_end_pc, loop end address; output o_hwloop_ifu_start_pc, loop start address; output o_hwloop_ifu_enable, loop process decoding module enable, high level is valid; Interaction with the decoding module includes: input i_hwloop_idu_pc, the current PC value, used for PC comparison; input i_hwloop_idu_stall, the pipeline pause signal; The interaction with the status control register includes: input i_hwloop_csr_start_pc, loop start address; input i_hwloop_csr_length, loop block length; input i_hwloop_csr_num, loop number; input i_hwloop_csr_he, loop enable, high-level loop is valid; output o_hwloop_csr_num, real-time loop number, update status control register; output o_hwloop_csr_he, loop enable; output o_hwloop_csr_we, status control register write enable signal.

5. A loop control system based on RISC-V extension, characterized in that: include: An analysis unit, used to analyze the assembly code of an existing algorithm and extract assembly instructions for loop control; An optimization unit, configured to replace the extracted assembly instructions capable of performing loop control with loop control instructions in the loop control method based on RISC-V extension according to claim 1; Instruction fetch module, used to obtain loop control instructions; The decoding module is used to obtain the loop control instruction from the instruction fetch module and write the loop information into the address specified by the status control register. The loop information includes the loop code segment length, the number of loops, the loop start address and the loop enable status. The hardware loop control module is used to read the loop information from the status control register and perform arbitration based on the control signal of the decoding module and the instruction address: when the current address has not reached the end of the loop, it sends an enable signal to enable the instruction fetch module to continue fetching instructions in sequence; When the current address reaches the last instruction of the loop segment and the number of loops has not returned to zero, the loop start address is sent to the instruction fetch module to enable it to continue the loop; the hardware loop control module controls the instruction fetch address based on the pipeline information of the current decoding level and the loop information, and sends the program counter value of the next instruction to the instruction fetch module.

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