Method for calculating heat distribution of large-scale three-dimensional integrated circuit 3DIC based on finite element

Abstract

The invention discloses a finite element-based calculation method for heat distribution of a large-scale three-dimensional integrated circuit (3DIC). The method comprises the following steps of: establishing a large-scale 3DIC model; performing heat distribution calculation on the established large-scale 3DIC model; for an existing heat dissipation method, 3DIC is systematically looked up, and important parameters in the aspects of geometry, heat dissipation, heat sources and the like are collected; parameterizing geometry, heat dissipation, a heat source and the like; establishing a large-scale 3DIC model database; performing heat distribution calculation on the database model; collecting a database model heat distribution calculation result, and inputting the result into a database; and establishing an artificial intelligence / machine learning optimization system. According to the method, the finite element analysis FEA technology with an accurate solving function is combined with an efficient XSim calculation tool, high accuracy and calculation efficiency are achieved, the super-strong performance of comprehensively simulating thermal behaviors of the whole packaging large model and the surrounding thermal environment of the whole packaging large model is achieved, and the heat distribution calculation problem of large three-dimensional integrated circuit 3DIC packaging is solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a method for calculating the thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite elements. Background Art

[0002] Three-dimensional integrated circuit (3DIC) technology increases the integration density of electronic devices by vertically stacking chip layers. This not only improves the integration density of integrated circuits but also significantly enhances the functionality and flexibility of electronic devices. By shortening interconnect lengths, 3DIC technology reduces power consumption and increases transmission speed, making it crucial for applications such as high-performance computing and mobile devices. Furthermore, 3DIC technology is driving the development of emerging technologies such as artificial intelligence and the Internet of Things, while enabling device miniaturization and portability, improving manufacturing efficiency and cost-effectiveness, and bringing new opportunities to the development of the supply chain and industrial chain.

[0003] Internationally, 3DIC technology is still in its early stages of development, and many so-called 3DIC solutions actually utilize 2.5D technology. Leading companies such as TSMC and Samsung, while making progress in 3DIC packaging technology, primarily employ 2.5D integration solutions and have not widely adopted 3DIC technology.

[0004] China is also developing rapidly in 3DIC packaging technology. Local companies such as SMIC and Hua Hong Semiconductor are increasing their R&D investment to improve their technology level. Yangtze Memory has also made great progress in 3DIC packaging technology. The cooperation between domestic universities, research institutions and enterprises is becoming increasingly close, jointly promoting the research and application of 3DIC and related thermal management technologies. Some domestic companies and research institutions are also developing their own simulation software. Although there is still a certain gap compared with the international advanced level, it has shown good application prospects in specific fields and applications. For example, Liu Hancheng et al. [8] constructed a geometric model of TSV chip / adapter board and used Flowtherm software for finite element simulation analysis to propose a structured model of TSV equivalent thermal conductivity. The model verified the influence of pitch, aspect ratio and filling material on 3DIC equivalent thermal conductivity, and further improved the accuracy of the model through parameter fitting. Based on Liu Hancheng's research, Xiao Chengdi et al. fully considered the influence of SiO2 layer on lateral thermal conductivity and proposed a method for establishing an equivalent thermal conductivity model for cylindrical TSV containing SiO2 layer. Cheng Zhiqiang et al.

[10] combined the equivalent modeling method and took the warpage caused by temperature increase as an influencing factor for thermal coupling evaluation.

[0005] Although 3DIC technology has great development potential, it still faces many challenges in practical application, including thermal management, interconnect technology, material compatibility, manufacturing process, design and simulation, testing and verification, cost-effectiveness, standardization and compatibility, intellectual property and patents, environment and sustainability, etc. These issues need to be solved through technological innovation, interdisciplinary cooperation, and the formulation of industry standards.

[0006] When designing 3DIC structures, heat dissipation is a primary consideration. As industries like artificial intelligence continue to demand more computing power from chips, the heat generated by these chips is also rapidly increasing. For example, the GPU chip layer consumes hundreds of watts of power, and when combined with the heat from dozens of other chip layers, the total power consumption of the entire structure can reach kilowatts. Imagine the challenge of fitting a heat source of hundreds or even kilowatts into a confined volume of 10 x 10 x 1 cubic millimeters while simultaneously ensuring the internal temperature does not exceed approximately 85°C.

[0007] Since huge heat is generated inside the 3DIC structure, it is natural to consider how to dissipate the heat.

[0008] Typically, a heat sink (fan, liquid heat sink, etc.) is installed on the chip. In two-dimensional structures, these heat sinks are in direct contact with the chip, making heat dissipation relatively easy. However, in three-dimensional structures, the high-heat source layer and the heat sink may be separated by many other chip layers, making it difficult for the heat from the high-heat source layer to be transferred to the heat sink. Therefore, the heat dissipation problem of three-dimensional 3DIC structures becomes more difficult.

[0009] Song Jianhao and others mentioned that as the integration of chips continues to increase, the power consumption per unit area also increases, which causes the chip temperature to rise, thereby affecting the performance and reliability of the chip and directly affecting the yield of chip manufacturing.

[0010] Thermal management is a primary consideration in 3D integrated circuit (3DIC) structural design and optimization. With the rapid development of 3D integrated circuit (3DIC) technology, the need for accurate calculation and optimization of thermal distribution has become increasingly urgent. Research has shown that improper thermal management can not only lead to performance degradation and reduced reliability, but can even cause device failure. Extremely low manufacturing yields due to poor thermal management are the most critical issue facing 3DICs. Effective thermal management methods and solutions, such as the use of thermal simulation software and advanced materials, are crucial for the widespread adoption of 3DIC integration. This not only improves chip energy efficiency but also extends its lifespan, thereby boosting overall system performance. By simulating 3DIC models and understanding the internal thermal distribution, engineers can optimize the layout of various electronic components and chip layers and adjust heat dissipation accordingly. In short, accurate 3DIC thermal distribution calculation is a top priority for 3DIC thermal management. Accurate thermal distribution calculation is an indispensable cornerstone of sound thermal management design.

[0011] First, it's important to clarify that the thermal distribution designers require is the thermal distribution of the entire 3DIC package, taking into account the thermal effects of its surroundings. Due to the complexity of the problem, accurately calculating 3DIC thermal distribution presents an insurmountable gap between academia and industry. The difficulties arise primarily from the following aspects. First, the 3DIC model is enormous. It consists of tens of thousands of TSVs, each made of several different materials. Furthermore, it comprises dozens of vertically stacked chip layers, including the CPU, GPU, and memory layers. Second, the components of the 3DIC model vary widely in size. TSVs are a few microns in size, while the chip size is 10 mm, a thousand-fold difference. Finally, the thermal environment is complex: a 3DIC package is surrounded by various other heat sources, and internally, heat sources are distributed across dozens of chip layers, with their relative positions varying widely. Heat dissipation involves various heat sinks, heat dissipation layers, and heat dissipation channels. These combined difficulties make the entire 3DIC calculation model extremely large, making accurate thermal distribution calculation within an acceptable timeframe nearly impossible.

[0012] Even global industry leaders like Synopsis, Cadence, Ansys, and Abacus are powerless to address this computational challenge. The lack of efficient electronic design automation (EDA) tools to accurately calculate temperature distribution makes effective heat dissipation difficult to address. Although a variety of EDA tools and methodologies have been developed, such as thermal analysis software based on the finite element method (FEM), these tools still face computational complexity and efficiency challenges when handling large-scale 3DIC thermal distribution calculations. Furthermore, many researchers have attempted to simplify 3DIC models to reduce thermal distribution calculations to a simpler problem, such as using finite element methods and equivalent thermal network methods. However, these approaches have their own limitations, such as inaccurate calculations and the inability to account for the thermal effects of the surrounding thermal environment.

[0013] In short, 3DIC technology will be the main direction of chip packaging in the future, but its widespread adoption in production still faces many challenges. The primary challenge is accurately calculating the thermal distribution of large-scale 3DICs in complex thermal environments. On the one hand, the semiconductor industry urgently needs a method that can quickly and accurately calculate the thermal distribution of large-scale 3DICs in complex thermal environments to design reliable semiconductor products that can be mass-produced. Summary of the Invention

[0014] The technical problem to be solved by the present invention is to accurately calculate the thermal distribution of large-scale 3DIC in a complex thermal environment. To solve the above problem, a calculation method for the thermal distribution of large-scale three-dimensional integrated circuit 3DIC based on finite element is provided.

[0015] The object of the present invention is achieved in the following manner: A finite element-based calculation method for the thermal distribution of large-scale three-dimensional integrated circuits (3DICs). S1: Establish a large-scale 3DIC model; S2: Calculate the thermal distribution of the large-scale 3DIC model; S3: Systematically review existing heat dissipation methods and 3DIC, collect important parameters such as geometry, heat dissipation, and heat source; parameterize geometry, heat dissipation, and heat source; S4: Establish a large-scale 3DIC model database; perform thermal distribution calculations on the database models; S5: Collect the thermal distribution calculation results of the database model and input them into the database; S6: Build AI / machine learning optimization systems.

[0016] Said S1 specifically includes: Geometric structure construction: Based on the multi-layer stacking architecture of 3D integrated circuits, a three-dimensional structure consisting of logic layer, storage layer, and interposer layer is constructed; Conductive via modeling: High-density TSVs are set in the target area with a pitch of 10μm, made of copper, and with a diameter set according to process parameters. TSVs are ignored in non-target areas to simplify the model. Material parameter definition: Assign physical properties to each layer of material, including density, thermal conductivity, and specific heat capacity, which can be directly called through the material library or entered manually.

[0017] Said S2 specifically includes: Heat source configuration: Intermediary layer: Divide into 16 heat source areas, each 2.5mm×2.75mm, with a 0.8W point heat source set at the center. The total power is calculated as follows: P_interposer=16×0.8W=12.8W, xPU layer: The top xPU layer evenly distributes a 45W surface heat source. The power density is calculated as follows: qxPU=45W / (10mm×11mm)=0.409W / mm^2, Storage layer: 0.4W uniform surface heat source is applied to each DRAM layer. Total storage layer power: P_DRAM = 9 × 0.4W = 3.6W, Boundary condition settings: The top and sides are water-cooled, with a convection coefficient of 13,000 W / m²・K and an ambient temperature of 40°C. The bottom substrate is approximately insulating, with a convection coefficient of 4 W / m²・K and an initial temperature of 26°C; Finite element analysis FEA solution: An efficient sparse matrix solver is used to mesh the model with tetrahedral or hexahedral elements. The steady-state temperature distribution is calculated through the heat conduction differential equation. Parallel computing technology is used to accelerate the solution. The preconditioned conjugate gradient method PCG is used to solve the sparse matrix. Combined with OpenMP parallel computing technology, the steady-state solution can be completed within 15-30 minutes on an 8-core CPU.

[0018] The S3 specifically includes: Parameter classification and extraction: Geometric parameters: number of layers, thickness of each layer, TSV pitch / diameter / density, chip size, target area location; Heat dissipation parameters: convection coefficient of each surface, ambient temperature, thermal conductivity of materials; Heat source parameters: power density of each layer W / mm², heat source distribution method; Parametric model building: The above parameters are defined as adjustable variables to form a standardized input file, which supports user customization or loading from preset templates.

[0019] The S4 specifically includes: Model classification storage: Classify by technical architecture, number of layers, and application scenarios, and store geometric model files, material parameter tables, and heat source configuration plans; Parametric template library: preset parameter combinations for typical scenarios; Data association mechanism: Establishes a mapping relationship between geometric parameters, heat source parameters, and heat dissipation parameters, supporting fast retrieval through keywords.

[0020] The S5 specifically includes: Result data extraction: Extract key indicators from FEA calculation results, including temperature distribution cloud map of each layer, maximum temperature and average temperature of the target area, and heat flow path vector diagram; Structured storage: Result data is categorized by model ID, parameter combination, and calculation timestamp, and stored in a database table. Fields include model name, number of layers, TSV spacing, top convection coefficient, DRAM maximum temperature, and calculation time. Data Verification Mechanism: Ensure data accuracy through manual calculation or verification against commercial software, with an error range of less than 5%.

[0021] The S6 specifically includes: Training data preparation: extract historical calculation data from the database, normalize it and divide it into training set and validation set; Model construction: A neural network is used to model the parameter-temperature mapping relationship. The input is the geometry / heat dissipation / heat source parameter vector, and the output is the target area maximum temperature and heat flow distribution prediction. Optimization algorithm integration: Combining gradient descent or Bayesian optimization, with the constraint of "DRAM area maximum temperature ≤ 85°C," optimizes variables including TSV spacing, top convection coefficient, and heat source power distribution, and outputs the optimal design parameter combination. Closed-loop application: Automatically import the optimized parameters into the modeling module, generate a new model and calculate the thermal distribution, iterating until the design goals are met, forming an automated design process of "modeling-calculation-optimization".

[0022] Beneficial effects of the present invention: The present invention combines finite element analysis (FEA) technology with precise solution capabilities with the efficient XSim calculation tool, achieving high accuracy and computational efficiency, as well as superior performance in comprehensively simulating the thermal behavior of the entire large package model and its surrounding thermal environment, thereby solving the difficult problem of calculating the thermal distribution of large three-dimensional integrated circuit (3DIC) packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is the technical roadmap of the present invention.

[0024] Figure 2 It is a BBCube 3D structure.

[0025] Figure 3 This is a top view of the thermal distribution results of one of the 12 small and medium-sized models selected by the present invention.

[0026] Figure 4 This is the top view of BBCube3D.

[0027] Figure 5 It is a heat distribution map. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0030] A method for calculating thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element analysis, the method comprising: S1: Establish a large-scale 3DIC model; S2: Calculate the thermal distribution of the large-scale 3DIC model; S3: Systematically review existing heat dissipation methods and 3DIC, collect important parameters such as geometry, heat dissipation, and heat source; parameterize geometry, heat dissipation, and heat source; S4: Establish a large-scale 3DIC model database; perform thermal distribution calculations on the database models; S5: Collect the thermal distribution calculation results of the database model and input them into the database; S6: Build AI / machine learning optimization systems.

[0031] The 3DIC model established in the S1 is a BBCube 3D model, which consists of 21 layers, with the insertion layer at the bottom and the logic layer xPU layer at the top, both of which are simulated using silicon SI material; the middle 19 layers correspond to 9 DRAM layers, and each DRAM layer is modeled using one SI layer and one SIO2 layer; the thickness of the middle interlayer and CPU / GPU layer is 0.03 mm, while the thickness of the SIO2 layer is 0.004 mm, and the thickness of the SI layer is 0.006 mm.

[0032] Said S1 specifically includes: Geometric Structure Construction: Based on the multi-layer stacking architecture of 3D integrated circuits (3DIC), a three-dimensional structure consisting of logic, memory, and interposer layers is constructed. Based on typical chip-on-wafer-on-substrate (CoWoS) or wafer-on-wafer (WoW) stacking technologies, a 21-layer 3D structure is designed, including a bottom interposer layer (0.03mm thick, made of silicon), a top compute layer (xPU layer, 0.03mm thick, made of silicon), and 19 intermediate memory layers (each layer is composed of alternating 0.006mm silicon and 0.004mm silicon dioxide layers).

[0033] Through-hole via (TSV) modeling: High-density TSVs are set in the target area (e.g., 2.5mm×2.75mm), with a pitch of 10μm, made of copper, and a diameter set according to process parameters. TSVs are ignored in non-target areas to simplify the model.

[0034] Material parameter definition: Assign physical properties to each layer of material, including density, thermal conductivity, and specific heat capacity (e.g., the thermal conductivity of silicon is 105 W / m・K, silicon dioxide is 138 W / m・K, and copper is 401 W / m・K). These properties can be directly called from the material library or entered manually.

[0035] Said S2 specifically includes: Heat source configuration: Interposer: Divide into 16 heat source areas (each 2.5mm×2.75mm), set a 0.8W point heat source at the center, and calculate the total power as follows: , xPU layer: The top xPU layer evenly distributes a 45W surface heat source. The power density is calculated as follows: Storage layer: 0.4W uniform surface heat source is applied to each DRAM layer. Total storage layer power: Boundary condition settings: The top and sides are water-cooled, with a convection coefficient of 13,000 W / m²・K and an ambient temperature of 40°C. The bottom substrate is approximately insulating, with a convection coefficient of 4 W / m²・K and an initial temperature of 26°C.

[0036] Finite Element Analysis (FEA) solves: An efficient sparse matrix solver is used to mesh the model (tetrahedral or hexahedral elements). The steady-state temperature distribution is calculated using the heat conduction differential equation (3D Poisson's equation). Parallel computing technology is used to accelerate the solution. The preconditioned conjugate gradient method (PCG) is used to solve the sparse matrix. Combined with OpenMP parallel computing technology, the steady-state solution can be completed within 15-30 minutes on an 8-core CPU.

[0037] The S3 specifically includes: Parameter classification and extraction: Geometric parameters: number of layers, thickness of each layer, TSV pitch / diameter / density, chip size (e.g., 10mm×11mm), target area location; Heat dissipation parameters: convection coefficient of each surface (top, side, bottom), ambient temperature, thermal conductivity of the material; Heat source parameters: power density of each layer (W / mm²), heat source distribution method (uniform distribution, concentrated point heat source).

[0038] Parametric model building: Define the above parameters as adjustable variables to form a standardized input file (such as a script or table), which supports user customization or loading from preset templates, such as storing parameter configurations in XML or JSON format.

[0039] The S4 specifically includes: Model classification storage: Classified by technical architecture (CoWoS / WoW / BBCube), number of layers (4 to 32 layers), and application scenarios (HPC / AI / storage-intensive), storing geometric model files (STL / STEP format), material parameter tables, and heat source configuration plans.

[0040] Parameterized template library: Preset parameter combinations for typical scenarios, such as high-bandwidth memory (HBM) models and near-memory computing architecture models, including configuration templates for different TSV densities (10μm / 20μm pitch) and cooling solutions (water cooling / air cooling / phase change material).

[0041] Data association mechanism: Establishes a mapping relationship between geometric parameters, heat source parameters, and heat dissipation parameters, supporting fast search by keywords (such as "10-layer DRAM stack + bottom insulation").

[0042] The S5 specifically includes: Result data extraction: Extract key indicators from FEA calculation results, including temperature distribution cloud maps of each layer, maximum temperature (MT) of the target area (such as DRAM layer), average temperature, and heat flow path vector diagram.

[0043] Structured storage: Result data is categorized by model ID, parameter combination, and calculation timestamp, and stored in a database table (such as an SQL database). Fields include model name, number of layers, TSV spacing, top convection coefficient, DRAM maximum temperature, and calculation time.

[0044] Data Verification Mechanism: Ensure data accuracy by manually calculating (e.g., lumped parameter method) or verifying results against commercial software (e.g., Ansys) to keep the error within 5%.

[0045] The S6 specifically includes: Training data preparation: Historical calculation data (≥1000 sets of parameter-temperature samples) are extracted from the database and divided into a training set (80%) and a validation set (20%) after normalization.

[0046] Model construction: A neural network (such as a convolutional neural network (CNN) or a graph neural network (GNN)) is used to model the parameter-temperature mapping relationship. The input is a geometric / heat dissipation / heat source parameter vector, and the output is the prediction of the maximum temperature and heat flow distribution in the target area.

[0047] Optimization algorithm integration: Combined with gradient descent or Bayesian optimization, with the constraint of "DRAM area maximum temperature ≤ 85°C", optimization variables include TSV spacing, top convection coefficient, and heat source power distribution, and outputs the optimal design parameter combination.

[0048] Closed-loop application: The optimized parameters are automatically imported into the modeling module (S1), a new model is generated and the thermal distribution is calculated. The process is iterated until the design goals are met, forming an automated design process of "modeling-calculation-optimization".

[0049] The 3DIC model established in S1 is a BBCube 3D model, such as Figure 2 As shown, it consists of 21 layers, of which the insertion layer is at the bottom and the xPU layer is at the top, and both layers are simulated using silicon SI material; the middle 19 layers correspond to 9 DRAM layers, and each DRAM layer is modeled using one SI layer and one SIO2 layer; the thickness of the middle interlayer and the CPU / GPU layer is 0.03 mm, while the thickness of the SIO2 layer is 0.004 mm, and the thickness of the SI layer is 0.006 mm.

[0050] We have done a preliminary evaluation of the algorithm speed. Figure 2Our algorithm can calculate the thermal distribution of the entire BBCube in about 25 minutes on a typical laptop computer for a large 3DIC model (10 x 11 x 0.2 mm³, 21,728 TSVs, 10 memory chip layers, 10 isolation layers, one high-performance computing chip layer, and one logic chip layer). Typically, even using approximate algorithms, thermal distribution calculations for such a large model would take days or even weeks (see Samsung Electronics article). Our calculation speed is over a thousand times faster than the technology used by leading semiconductor companies like Samsung.

[0051] We also conducted a preliminary assessment of computational accuracy. Our results were compared with those from precise EDA / FEA calculations, and the error between the two was calculated. Since commercial EDA / FEA software cannot solve large models, we selected a set of 12 small and medium-sized models for calculation and comparison. Comparing the heat distribution results at each node, the maximum relative error between our algorithm and the commercial EDA software on this set of models was only 0.4°C, fully demonstrating the accuracy and reliability of our algorithm.

[0052] Figure 3 Shown is a top-down view of the thermal distribution results for one of our 12 selected small and medium-sized models. The model measures 4x4 mm and contains four chip layers. The white vertical bars represent multiple TSVs. The heat source is asymmetric, with a total heat output of 21 watts. The maximum error in the thermal distribution between our algorithm and commercial EDA software is 0.8°C per node. The maximum temperature of the entire package is 183.44°C, and the maximum relative error per node is 0.43%. Compared to the 3% error reported by Samsung Electronics, our calculations are sufficiently accurate.

[0053] In summary, the first and most significant innovation of this research is the application of the developed XSim software to 3DIC thermal distribution calculations. Combined with FEA methods, this provides a fast, accurate, and comprehensive thermal management solution for chip packaging. This groundbreaking approach surpasses existing methods in academia and industry worldwide, providing strong support for the development and application of 3DIC technology and potentially propelling electronic system design and optimization into a new era.

[0054] Leveraging our leading edge in advanced simulation platforms, we analyzed the performance of various 3D IC designs, calculated the temperature distribution of a single design under different parameter settings, and established a database and optimization system. This work, an application and extension of our first innovation, will provide optimized solutions for 3D IC design. The specific work is described below.

[0055] 3DIC model parameterization We are concerned about changes in the external thermal environment of the 3DIC model, changes in heat distribution caused by different internal heat sources and different heat dissipation devices, especially the heat distribution in the storage area. The external thermal environment can be represented by parameters such as the intensity and geometric shape of the heat source. The study of internal heat sources mainly focuses on the heat source distribution within each chip layer and the position of the chip layer in the entire three-dimensional architecture. For example: the number, position and internal heat source distribution of the GPU layers in the entire three-dimensional architecture can be used as different parameters. In terms of heat dissipation devices, we will explore various cutting-edge heat dissipation methods, such as fans, air cooling, water cooling, and various types of liquid cooling. We will also explore the shape and position of heat dissipation devices, such as heat dissipation layers, heat dissipation pipes of different sizes and their positions.

[0056] Calculate the thermal distribution of the 3DIC model and establish a database Calculate the thermal distribution of 3DIC models with different parameter settings. Due to the huge number of different parameter combinations, it is a huge task to model each model, perform thermal analysis, verify the results, collect data and build a database.

[0057] 3DIC model structure optimization system Based on the 3DIC model database, a design optimization system and machine learning mechanism are established. For users with different chip packaging requirements, this system will calculate the optimized design solution.

[0058] The implementation of the present invention is carried out according to the following 11 tasks.

[0059] 1. Build a large-scale 3DIC model, including the complex external thermal environment, complex internal heat source distribution, and complex heat dissipation system.

[0060] 2. Complete thermal distribution calculations for the large-scale 3DIC model on a laptop computer in less than half an hour. This required repeated refinement and optimization of the XSim algorithm.

[0061] 3. Perform thermal distribution calculations on the large-scale 3DIC model to verify the accuracy of the results.

[0062] 4. Conduct a systematic review of existing heat dissipation methods and 3DIC, collecting important parameters on geometry, heat dissipation, heat sources, etc.

[0063] 5. Parameterize geometry, heat dissipation, heat source, etc.

[0064] 6. Establish a large-scale 3DIC model database. Create 3DIC models for various meaningful parameter combinations. The database size is approximately 200 models.

[0065] 7. Perform heat distribution calculation on the database model.

[0066] 8. Verify the thermal distribution calculation results of the database model to ensure that the completion time is within 30 minutes and the calculation results are accurate.

[0067] 9. Collect the thermal distribution calculation results of the database model and input them into the database.

[0068] 10. Build AI / machine learning optimization systems.

[0069] 11. Cooperate with at least one semiconductor company to improve their 3DIC integrated circuit design capabilities with our research results, and improve our optimization system based on their needs.

[0070] The details are as follows: The basic model of the present invention is a complete BBCube (such as Figure 2 As shown). The size of the model is 10 mm × 11 mm. The BBCube 3D model consists of 21 layers, with the interposer layer at the bottom and the xPU layer at the top, both of which are simulated using silicon (SI) material. The middle 19 layers correspond to 9 DRAM layers, each of which is modeled using one SI layer and one SIO2 layer. The thickness of the middle interlayer and the CPU / GPU layer is 0.03 mm, while the thickness of the SIO2 layer is 0.004 mm and the thickness of the SI layer is 0.006 mm. We focus on an area of ​​2.5 mm × 2.75 mm, in which TSVs with a pitch of 10 nm are created. There are 21,728 TSVs. Below Figure 4 Showing a closer look at this model.

[0071] After the model was built, we defined material parameters to ensure simulation accuracy. For each component, we set the following thermophysical properties: copper (COPPER) with a density of 8.93 g / cc, a thermal conductivity of 401 W / m•K, and a specific heat capacity of 0.385 J / g•°C; silicon (SI) with a density of 2.329 g / cc, a thermal conductivity of 105 W / m•K, and a specific heat capacity of 0.713 J / g•°C; and silicon dioxide (SIO2) with a density of 2.65 g / cc, a thermal conductivity of 138 W / m•K, and a specific heat capacity of 0.74 J / g•°C. These parameters are crucial for accurate thermal distribution calculations, as shown in Table 1 below.

[0072] When setting boundary conditions, we set the chip's power density (e.g., 5 W / cm²) and heat flow boundary conditions to simulate actual heat dissipation. The initial temperature also needs to be set (e.g., 25°C) to more realistically reflect thermal behavior in an actual operating environment. When selecting the computational mesh, we use a finer mesh in XSim, which helps improve the accuracy of the calculation results, especially for complex 3DIC structures.

[0073] 2. Perform thermal distribution calculations on the large-scale 3DIC model.

[0074] To ensure that the task can be completed on a laptop within half an hour, this requires repeated improvement and optimization of the XSim algorithm.

[0075] 3. Verification of the accuracy of calculation results.

[0076] We verify the calculation results through two methods: manual verification and comparison with the calculation results of FEA / EDA tools.

[0077] Manual verification We run the FEA thermal distribution calculation of the BBCube model in XSim software and obtain the temperature distribution range of the model. Figure 5 As shown, the temperature range of the model is from 70.87°C to 83.30°C from the lowest to the highest, respectively.

[0078] Below we perform a hand calculation to estimate this model.

[0079] Assume that the initial temperature of BBCube is 26℃ and the ambient temperature is 40℃. Let A be the average value of the heat distribution of BBCube at time t, and let D be the temperature difference: Since TSV is smaller than BBCube and SI and SIO2 parameters are close, we assume that the entire BBCube model is SI. The mass of BBCube is: Energy required to keep the BBCube temperature rising by 1°C: The total heat source is 58.2 (J / s). If the simulation runs for T seconds, the total heat generated is: Next we calculate the heat dissipated through the 6 faces of the BBCube.

[0080] .

[0081] Energy dissipated through the top and four sides in T seconds: For the bottom energy flux q: , The bottom area is: , Substituting in: The optimized 3DIC packaging technology of the present invention will reduce the increase in energy consumption caused by overheating, lower the energy consumption of electronic products during use, and help reduce greenhouse gas emissions.

[0082] The present invention can extend the service life of products, reduce the generation of electronic waste, and improve the recycling rate of resources by improving the thermal efficiency of integrated circuits.

[0083] The technical achievements of the present invention will support the development of green manufacturing processes, reduce environmental pollution during the production process, and meet the requirements of environmental protection and sustainable development.

[0084] The above is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several changes and improvements can be made without departing from the overall concept of the present invention, and these should also be regarded as the scope of protection of the present invention.

Claims

1. A method for calculating the thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element method, characterized by: The method comprises: S1: Establish a large-scale 3DIC model; S2: Calculate the thermal distribution of the large-scale 3DIC model; S3: Systematically review existing heat dissipation methods and 3DIC, collect important parameters such as geometry, heat dissipation, and heat source; parameterize geometry, heat dissipation, and heat source; S4: Establish a large-scale 3DIC model database; perform thermal distribution calculations on the database models; S5: Collect the thermal distribution calculation results of the database model and input them into the database; S6: Build AI / machine learning optimization systems.

2. The method for calculating thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element analysis according to claim 1, characterized in that: Said S1 specifically includes: Geometric structure construction: Based on the multi-layer stacking architecture of 3D integrated circuits, a three-dimensional structure consisting of logic layer, storage layer, and interposer layer is constructed; Conductive via modeling: High-density TSVs are set in the target area with a pitch of 10μm, made of copper, and with a diameter set according to process parameters. TSVs are ignored in non-target areas to simplify the model. Material parameter definition: Assign physical properties to each layer of material, including density, thermal conductivity, and specific heat capacity, which can be directly called through the material library or entered manually.

3. The method for calculating thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element analysis according to claim 1, characterized in that: Said S2 specifically includes: Heat source configuration: Intermediary layer: Divide into 16 heat source areas, each 2.5mm×2.75mm, and set a 0.8W point heat source at the center. The total power is calculated as follows: P_interposer=16×0.8W=12.8W, xPU layer: The top xPU layer evenly distributes a 45W surface heat source. The power density is calculated as follows: qxPU=45W / (10mm×11mm)=0.409W / mm^2, Storage layer: 0.4W uniform surface heat source is applied to each DRAM layer. Total storage layer power: P_DRAM = 9 × 0.4W = 3.6W, Boundary condition settings: The top and sides are water-cooled, with a convection coefficient of 13,000 W / m²・K and an ambient temperature of 40°C. The bottom substrate is approximately insulating, with a convection coefficient of 4 W / m²・K and an initial temperature of 26°C; Finite element analysis FEA solution: An efficient sparse matrix solver is used to mesh the model with tetrahedral or hexahedral elements. The steady-state temperature distribution is calculated through the heat conduction differential equation. Parallel computing technology is used to accelerate the solution. The preconditioned conjugate gradient method PCG is used to solve the sparse matrix. Combined with OpenMP parallel computing technology, the steady-state solution can be completed within 15-30 minutes on an 8-core CPU.

4. The method for calculating thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element analysis according to claim 1, characterized in that: The S3 specifically includes: Parameter classification and extraction: Geometric parameters: number of layers, thickness of each layer, TSV pitch / diameter / density, chip size, target area location; Heat dissipation parameters: convection coefficient of each surface, ambient temperature, thermal conductivity of materials; Heat source parameters: power density of each layer W / mm², heat source distribution method; Parametric model building: The above parameters are defined as adjustable variables to form a standardized input file, which supports user customization or loading from preset templates.

5. The method for calculating thermal distribution of large-scale three-dimensional integrated circuits (3DICs) based on finite element analysis according to claim 1, characterized in that: The S4 specifically includes: Model classification storage: Classify by technical architecture, number of layers, and application scenarios, and store geometric model files, material parameter tables, and heat source configuration plans; Parametric template library: preset parameter combinations for typical scenarios; Data association mechanism: Establishes a mapping relationship between geometric parameters, heat source parameters, and heat dissipation parameters, supporting fast retrieval through keywords.

6. The method for calculating thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element analysis according to claim 1, characterized in that: The S5 specifically includes: Result data extraction: Extract key indicators from FEA calculation results, including temperature distribution cloud map of each layer, maximum temperature and average temperature of the target area, and heat flow path vector diagram; Structured storage: Result data is categorized by model ID, parameter combination, and calculation timestamp, and stored in a database table. Fields include model name, number of layers, TSV spacing, top convection coefficient, DRAM maximum temperature, and calculation time. Data Verification Mechanism: Ensure data accuracy through manual calculation or verification against commercial software, with an error range of less than 5%.

7. The method for calculating thermal distribution of a large-scale three-dimensional integrated circuit (3DIC) based on finite element analysis according to claim 1, characterized in that: The S6 specifically includes: Training data preparation: extract historical calculation data from the database, normalize it and divide it into training set and validation set; Model construction: A neural network is used to model the parameter-temperature mapping relationship. The input is the geometry / heat dissipation / heat source parameter vector, and the output is the target area maximum temperature and heat flow distribution prediction. Optimization algorithm integration: Combining gradient descent or Bayesian optimization, with the constraint of "DRAM area maximum temperature ≤ 85°C," optimizes variables including TSV spacing, top convection coefficient, and heat source power distribution, and outputs the optimal design parameter combination. Closed-loop application: Automatically import optimized parameters into the modeling module, generate a new model, and calculate the thermal distribution. Iterate until the design goals are met, forming an automated design process of "modeling-calculation-optimization".

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