A MOSFET device modeling method based on multi-level calibration

Abstract

The present invention discloses a MOSFET device modeling method based on multi-level calibration, relates to the technical field of semiconductor device modeling, and is used to solve the technical problem that existing MOSFET device modeling leads to excessive systematic deviation of device-circuit performance under process fluctuations. The MOSFET device modeling method based on multi-level calibration of the present invention comprises: establishing an initial model of the MOSFET device; performing device-level electrical characteristic calibration; reconstructing a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region based on the initial model, extracting distributed parasitic parameters and embedding them as boundary conditions into the initial model to generate a circuit-level simulation entity including real parasitic effects; matching the rise / fall time and propagation delay of the inverter by iteratively adjusting the contacts; triggering a reverse backtracking process when the deviation between the circuit dynamic performance and the measured data exceeds a threshold, and reversely adjusting the parasitic node parameters or the initial model corresponding to the device; and completing the MOSFET device modeling when the deviation is less than or equal to the threshold.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device modeling, and more particularly to a MOSFET device modeling method based on multi-level calibration. Background Art

[0002] As semiconductor process nodes continue to shrink, device physical effects and process fluctuations are increasingly impacting the performance and reliability of integrated circuits. In advanced process development and reliability assessment, there is an urgent need to establish device models that combine physical accuracy with circuit practicality to accurately characterize the underlying device structural characteristics, parasitic effects, and their interactions with the process environment. Traditional modeling methods have significant limitations in balancing physical detail with circuit simulation efficiency, resulting in insufficient prediction accuracy in complex circuit scenarios, making it difficult to support reliability analysis requirements under advanced processes.

[0003] Current mainstream device modeling technologies can be divided into two categories: semiconductor process and device simulation (technology computer aided design, TCAD) physical simulation models and integrated circuit simulation (SPICE) models. TCAD technology constructs device models by solving semiconductor physics equations, accurately reflecting physical field characteristics such as carrier transport and electric field distribution. However, its high computational complexity makes it difficult to directly use in large-scale circuit simulations. SPICE models describe device behavior using abstract mathematical equations, offering the advantage of efficient simulation. However, their parameterized representations separate the device's physical essence and fail to reveal the underlying mechanisms of reliability issues such as process fluctuations and hot carrier degradation.

[0004] Based on device parameters obtained from SPICE models or transmission electron microscopy (TEM) sections, a TCAD model can be reverse engineered, and parameter calibration can be performed by comparing IV / CV characteristic curves. Existing MOSFET device modeling uses geometrically equivalent simplified gate-all-around structures, but ignores the impact of layout parasitics on circuit dynamic performance. While parasitic parameter back-annotation methods can extract layout RC parameters, they lack a linkage mechanism with the TCAD physical model, making it impossible to correct device parameters. This can lead to significant systematic deviations in device-circuit performance under process fluctuations. Summary of the Invention

[0005] The present invention aims to provide a MOSFET device modeling method based on multi-level calibration to address the technical problem of existing MOSFET device modeling causing excessive systematic deviations in device-circuit performance under process fluctuations. In view of this, the present invention achieves this goal through the following solution.

[0006] The present invention provides a MOSFET device modeling method based on multi-level calibration, comprising:

[0007] Establish an initial model of the MOSFET device based on the geometric parameters provided by the process design kit;

[0008] Adjust the parameters of the initial model based on the current-voltage and capacitance-voltage characteristic curves of the circuit simulation model of the MOSFET device to complete the device-level electrical characteristic calibration;

[0009] Reconstructing a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region based on the initial model, extracting distributed parasitic parameters and embedding them as boundary conditions into the initial model to generate a circuit-level simulation entity including real parasitic effects; and iteratively adjusting contacts to match the rise / fall time and propagation delay of the inverter.

[0010] A closed-loop iterative mechanism is established, and a threshold is set. When the deviation between the circuit dynamic performance and the measured data exceeds the threshold, a reverse backtracking process is triggered to reversely adjust the parasitic node parameters or the initial model corresponding to the device; when the deviation is less than or equal to the threshold, the MOSFET device modeling is completed.

[0011] Compared with the prior art, the MOSFET device modeling method based on multi-level calibration of the present invention implements device-level electrical characteristic calibration after establishing an initial model of the MOSFET device and adjusting the parameters of the initial model through current-voltage and capacitance-voltage characteristic curves. Furthermore, for the inverter, a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region is reconstructed based on the initial model, and distributed parasitic parameters are extracted and embedded into the initial model as boundary conditions to generate a circuit-level simulation entity including real parasitic effects. By iteratively adjusting the contacts, the rise / fall time and propagation delay of the inverter can be matched. Furthermore, a closed-loop iterative mechanism is established. By setting a threshold, a reverse backtracking process is triggered when the deviation between the circuit dynamic performance and the measured data exceeds the threshold, and the parasitic node parameters or the initial model corresponding to the device are reversely adjusted. When the deviation is less than or equal to the threshold, the modeling of the MOSFET device is achieved. The above technical solution of the present invention constructs a precise device model through first-level device-level calibration and second-level circuit-level calibration, constructing a technical chain of three-dimensional model reconstruction, TCAD embedding, dynamic calibration, and closed-loop iteration. This achieves closed-loop calibration of the entire chain of physical structure, parasitic effects, and circuit performance, eliminating systematic process-circuit deviations during the modeling process. This technical solution of the present invention solves the technical problem of excessive systematic deviations in device-circuit performance under process fluctuations caused by existing MOSFET device modeling.

[0012] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the geometric parameters include the gate length, gate width, gate oxide thickness and junction depth of the MOSFET device.

[0013] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the initial model is a semiconductor process and device simulation model;

[0014] In the process of establishing the semiconductor process and device simulation model, a Gaussian distribution doping distribution model is adopted and multiple physical models are configured to characterize the threshold voltage drift caused by short channel effect and quantum confinement by coupling and solving the quantum-corrected drift-diffusion equation and Poisson's equation;

[0015] The physical models include a unified mobility model, a Shockley-Read-Hall-Auger composite model, and a density gradient quantum correction model.

[0016] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, in the process of establishing the semiconductor process and device simulation model, the silicon substrate, gate oxide layer, polysilicon gate, and trench isolation structure are constructed in sequence according to the geometric parameters through Boolean operation strategy.

[0017] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the reconstructing of the three-dimensional geometric structure including the metal interconnect layer, the contact hole array and the well region based on the initial model includes:

[0018] Build a P substrate and define key parameter variables and the basic framework of the three-dimensional tetrahedron device;

[0019] Set the process generation direction to be the same as the vertical stacking direction of the device structure, and set the processing method of geometric Boolean operations to retain the properties of the first geometry;

[0020] Define a gate-side oxygen layer made of silicon dioxide and an isolation layer made of silicon nitride, apply a fillet operation to specified vertices on the isolation layer, define a global parameter to represent the radius of the fillet, and smooth the edge area of ​​the isolation layer.

[0021] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the reconstructing of the three-dimensional geometric structure including the metal interconnect layer, the contact hole array and the well region based on the initial model further includes:

[0022] Define the electrode, define the contact above the gate, define the contact below the substrate, and define both sides of the gate;

[0023] After defining the active area windows of the source and drain, define Gaussian doping in the following order: doping type, peak doping concentration and position, doping depth and value, and Gaussian distribution influencing factor;

[0024] The peak doping concentration is added to the defined window to define the doping.

[0025] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the reconstructing of the three-dimensional geometric structure including the metal interconnect layer, the contact hole array and the well region based on the initial model further includes:

[0026] Define the grid strategy, including:

[0027] First, define the maximum and minimum grid spacing of the global grid coordinate axes, then define the grid near the channel, and add a grid refinement script to the channel to define multiple grid sizes;

[0028] The NMOS is defined in the negative direction of the substrate, and the PMOS and the n-well below are defined in the positive direction of the substrate. The distribution of the metal layer is the same as the connection method of the NMOS and PMOS of the inverter. At the same time, the metal layer is opened according to the layout, and the material and size parameters of the contact hole are defined according to the connection object (such as source / drain active area or polysilicon gate).

[0029] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the basic framework of the three-dimensional tetrahedron device is defined, including:

[0030] Silicon is used as the substrate, silicon dioxide is used as the gate oxide layer and the oxide filled in the trench, and polysilicon is used as the gate.

[0031] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, after establishing the closed-loop iteration mechanism, the parasitic parameter distribution is analyzed to locate abnormal nodes;

[0032] Retroactively adjust the physical parameters of MOSFET devices or the geometric model of the layout, and re-verify the correlation between the current-voltage characteristics of a single MOSFET device and semiconductor process and device simulations.

[0033] Furthermore, in the MOSFET device modeling method based on multi-level calibration of the present invention, the circuit dynamic performance includes noise margin and power consumption;

[0034] The abnormal nodes include high-resistance contact holes, interconnected capacitance nodes and parasitic capacitance nodes;

[0035] The physical parameters include trap density, doping concentration and interface state density. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0037] Figure 1 A schematic flow chart of a MOSFET device modeling method based on multi-level calibration according to the present invention;

[0038] Figure 2 Schematic diagram comparing the IV characteristics of the SPICE model and the TCAD model before calibration in Example 3 of the present invention;

[0039] Figure 3 Schematic diagram comparing the IV characteristics of the calibrated SPICE model and the TCAD model in Example 3 of the present invention;

[0040] Figure 4 Schematic diagram of the inverter layout in Example 3 of the present invention;

[0041] Figure 5 Schematic diagram of the VTC curve before calibration in Example 3 of the present invention;

[0042] Figure 6 Schematic diagram of the VTC curve after calibration in Example 3 of the present invention;

[0043] Figure 7 Schematic diagram of the closed-loop iterative mechanism in Example 3 of the present invention. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0045] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0047] Based on device parameters obtained from SPICE models or transmission electron microscopy (TEM) sections, a TCAD model can be reverse engineered, and parameter calibration can be performed by comparing IV / CV characteristic curves. Existing MOSFET device modeling uses geometrically equivalent simplified gate-all-around structures, but ignores the impact of layout parasitics on circuit dynamic performance. While parasitic parameter back-annotation methods can extract layout RC parameters, they lack a linkage mechanism with the TCAD physical model, making it impossible to correct device parameters. This can lead to significant systematic deviations in device-circuit performance under process fluctuations.

[0048] In order to solve the above technical problems, the present invention provides a MOSFET device modeling method based on multi-level calibration, comprising:

[0049] Establish an initial model of the MOSFET device based on the geometric parameters provided by the process design kit;

[0050] Adjust the parameters of the initial model based on the current-voltage and capacitance-voltage characteristic curves of the circuit simulation model of the MOSFET device to complete the device-level electrical characteristic calibration;

[0051] Reconstructing a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region based on the initial model, extracting distributed parasitic parameters and embedding them as boundary conditions into the initial model to generate a circuit-level simulation entity including real parasitic effects; and iteratively adjusting contacts to match the rise / fall time and propagation delay of the inverter.

[0052] A closed-loop iterative mechanism is established, and a threshold is set. When the deviation between the circuit dynamic performance and the measured data exceeds the threshold, a reverse backtracking process is triggered to reversely adjust the parasitic node parameters or the initial model corresponding to the device; when the deviation is less than or equal to the threshold, the MOSFET device modeling is completed.

[0053] Under the above technical solution, in the MOSFET device modeling method based on multi-level calibration of the present invention, after establishing the initial model of the MOSFET device, the parameters of the initial model are adjusted through the current-voltage and capacitance-voltage characteristic curves to achieve device-level electrical characteristic calibration; further, for the inverter, the three-dimensional geometric structure including the metal interconnection layer, the contact hole array and the well region is reconstructed based on the initial model, and the distributed parasitic parameters are extracted and embedded into the initial model as boundary conditions to generate a circuit-level simulation entity including real parasitic effects; by iteratively adjusting the contacts, the rise / fall time and propagation delay of the inverter can be matched; further, a closed-loop iterative mechanism is established, and by setting a threshold, a reverse backtracking process is triggered when the deviation between the circuit dynamic performance and the measured data exceeds the threshold, and the parasitic node parameters or the initial model corresponding to the device are reversely adjusted; when the deviation is less than or equal to the threshold, the modeling of the MOSFET device is achieved. The above-mentioned technical solution of the present invention constructs a precise device model through first-level device-level calibration and second-level circuit-level calibration, constructing a technical chain of three-dimensional model reconstruction, TCAD embedding, dynamic calibration, and closed-loop iteration. This achieves closed-loop calibration of the entire chain of physical structure, parasitic effects, and circuit performance, eliminating process-circuit systematic deviations during the modeling process. The above-mentioned technical solution of the present invention solves the technical problem of excessive systematic deviations in device-circuit performance under process fluctuations caused by existing MOSFET device modeling. The above-mentioned MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device is a semiconductor device widely used for switching purposes and amplifying electronic signals in electronic devices.

[0054] In order to better understand the present invention, the content of the present invention is further explained below in conjunction with specific examples, but the content of the present invention is not limited to the following examples.

[0055] Example 1

[0056] See also Figure 1 This embodiment provides a MOSFET device modeling method based on multi-level calibration, including:

[0057] Step 1: Establish an initial model of the MOSFET device based on the geometric parameters provided by the process design kit;

[0058] Step 2: Adjust the parameters of the initial model according to the current-voltage and capacitance-voltage characteristic curves of the circuit simulation model of the MOSFET device to complete the device-level electrical characteristic calibration;

[0059] Step 3: Based on the initial model, the 3D geometry of the metal interconnect layer, contact hole array, and well region is reconstructed. Distributed parasitic parameters are extracted and embedded into the initial model as boundary conditions to generate a circuit-level simulation entity that includes realistic parasitic effects. Contacts are iteratively adjusted to match the inverter's rise / fall time and propagation delay.

[0060] Step 4: Establish a closed-loop iteration mechanism and set a threshold. When the deviation between the circuit dynamic performance and the measured data exceeds the threshold, trigger the reverse backtracking process and reversely adjust the parasitic node parameters or the initial model corresponding to the device. When the deviation is less than or equal to the threshold, the MOSFET device modeling is completed.

[0061] Example 2

[0062] This embodiment provides a MOSFET device modeling method based on multi-level calibration, including:

[0063] S100, builds an initial model of the MOSFET device based on the geometric parameters provided by the process design kit;

[0064] Furthermore, the geometric parameters include gate length, gate width, gate oxide thickness and junction depth of the MOSFET device;

[0065] Furthermore, the initial model is a semiconductor process and device simulation model; the process of establishing the semiconductor process and device simulation model includes:

[0066] S101 uses a Gaussian doping distribution model and configures multiple physical models to characterize the threshold voltage drift caused by short channel effects and quantum confinement by coupling the quantum-corrected drift-diffusion equation and the Poisson equation. The physical models include the unified mobility model, the Shockley-Read-Hall-Auger composite model, and the density gradient quantum correction model.

[0067] S102, constructing a silicon substrate, a gate oxide layer, a polysilicon gate, and a trench isolation structure in sequence through a Boolean operation strategy according to the geometric parameters;

[0068] S200, adjusting parameters of the initial model according to current-voltage and capacitance-voltage characteristic curves of the circuit simulation model of the MOSFET device to complete device-level electrical characteristic calibration;

[0069] S300, reconstructing a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region based on the initial model, extracting distributed parasitic parameters and embedding them as boundary conditions into the initial model to generate a circuit-level simulation entity including real parasitic effects; and iteratively adjusting contacts to match the rise / fall time and propagation delay of the inverter.

[0070] Furthermore, the reconstructing of a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region based on the initial model includes:

[0071] S301, constructing a P substrate and defining key parameter variables and a basic framework of a three-dimensional tetrahedron device; wherein the basic framework of the three-dimensional tetrahedron device is defined as: using silicon as the substrate, silicon dioxide as the gate oxide layer and oxide filling in the trench, and polysilicon as the gate;

[0072] S302 , setting a process generation direction to be the same as a vertical stacking direction of the device structure, and setting a processing method for geometric Boolean operations to retain the properties of the first geometric body;

[0073] S303, defining a gate side oxygen layer made of silicon dioxide and an isolation layer made of silicon nitride, applying a fillet operation to specified vertices on the isolation layer; defining a global parameter to represent the radius of the fillet, and smoothing the edge area of ​​the isolation layer;

[0074] S304, defining electrodes, defining contacts above the gate, defining contacts below the substrate, and defining both sides of the gate;

[0075] S305, after defining the source and drain windows, define Gaussian doping in order of doping type, peak doping concentration and position, doping depth and value, and Gaussian distribution influencing factor;

[0076] S306, adding the peak doping concentration to the defined window to define the doping;

[0077] S307, defining grid strategy;

[0078] Furthermore, the grid strategy definition includes:

[0079] S3071, first define the maximum and minimum grid spacing of the global grid coordinate axis, then define the grid near the channel, and add a grid refinement script to the channel to define multiple grid sizes;

[0080] S3072, define NMOS in the negative direction of the substrate, and define PMOS and the lower n-well in the positive direction of the substrate,

[0081] S3073, the distribution of the metal layer is the same as the connection method of the inverter NMOS and PMOS. At the same time, the metal layer is opened according to the layout structure, and the contact is defined to be the same type as the active area below;

[0082] S400, establishing a closed-loop iteration mechanism, setting a threshold, triggering a reverse backtracking process when the deviation between the circuit dynamic performance and the measured data exceeds the threshold, reversely adjusting the parasitic node parameters or the initial model corresponding to the device; when the deviation is less than or equal to the threshold, completing the MOSFET device modeling;

[0083] Analyze the distribution of parasitic parameters to locate abnormal nodes, retroactively adjust the physical parameters of the MOSFET device or the geometric model of the layout, and re-verify the correlation between the current-voltage variation characteristics of a single MOSFET device and the semiconductor process and device simulation; the circuit dynamic performance includes noise margin and power consumption; the abnormal nodes include high-resistance contact holes, interconnect resistance nodes, and parasitic capacitance nodes; the physical parameters include trap density, doping concentration, and interface state density.

[0084] Example 3

[0085] This embodiment provides a MOSFET device modeling method based on multi-level calibration, including:

[0086] Step 1: Establish an initial semiconductor process and device simulation model of the MOSFET device, namely the TCAD (technology computer aided design) model, based on the geometric parameters of the MOSFET device, such as gate length, gate width, gate oxide thickness, and junction depth, provided by the Process Design Kit (PDK).

[0087] Based on the structure editor in TCAD software, this embodiment uses a parametric approach to construct NMOS and PMOS device models for the 55nm process node. The modeling process strictly adheres to the geometric parameters provided by the PDK, including key dimensions such as gate length, gate width, gate oxide thickness, and junction depth. Through Boolean operations, the silicon substrate, gate oxide layer, polysilicon gate, and shallow trench isolation structure are sequentially constructed to ensure that the spatial position and size of each material layer meet process specifications.

[0088] Furthermore, a layered strategy is adopted to implement the doping profile, specifically: a uniform doping distribution is defined in the substrate region (NMOS is doped with boron, and the PMOS substrate region is doped with arsenic / phosphorus to form an N-well, with a boron-doped P-type active region defined in the well), while Gaussian doping distributions are adopted in the source and drain regions to simulate the diffusion gradient in the actual process; when constructing the three-dimensional MOSFET device structure using the TCAD tool, a Gaussian distribution doping distribution model is adopted, and physical models such as the unified mobility model, the SRH+Auger composite model (i.e., the Shockley-Read-Hall-Auger composite model), and the density gradient quantum correction model are configured; by coupling the solution of the quantum-corrected drift-diffusion equation and the Poisson equation, the threshold voltage drift caused by the short channel effect and quantum confinement is accurately characterized.

[0089] Furthermore, the electrode system is realized by precisely defining the metal contact area, with four-terminal contacts of gate, source, drain and substrate. Among them, the source and drain contacts eliminate geometric overlap through Boolean subtraction of the metal coverage area; the mesh division adopts an adaptive optimization strategy, and multi-layer encryption is performed on areas such as the channel and junction. At the same time, a mesh refinement script is added to the channel to define multiple mesh sizes to ensure the simulation accuracy of the electric field distribution and carrier transport; the final generated MOSFET device structure is discretized through a tetrahedral mesh and saved in a standardized format for subsequent electrical simulation.

[0090] Furthermore, after the initial modeling of the MOSFET device level is completed by the structure editor, the physical simulation parameters are set in the calibration process to simulate the ID-VG curve. The ID-VG curve is the relationship curve between the drain-source current (ID) and the gate-source voltage (VG). The electron mobility, hole mobility and interface trap density are adjusted to ensure that the doping distribution gradient conforms to the physical structure under the ion implantation process limit constraint; further, the parameter setting type and power supply voltage variable are defined to make it easier to control the type and voltage of the transistor in the visual interface; the next step is to read the file, define the electrode and apply zero bias, and define the main physical model used. There are recombination generation models, bandgap narrowing models and high-field mobility saturation models. The next step is to define the output parameters, mainly including the concentration mobility of electrons and holes, etc., then define the mathematical formulas used, and finally define the solution method; further, in the mathematical solution, first define the number of iterations, and the equations used in the solution, such as Poisson's equation, current density and current continuity equation; then define the solution method, use the quasi-static solution method, set the initial value, minimum step size, maximum step size and growth value, and reach the target value to pull the drain and gate to the set voltage respectively, save the data as a new curve file, and complete the solution of the ID-VG curve.

[0091] Furthermore, the calibrated NMOS and PMOS are used for cascade operation. Based on the module of the calibrated output transfer curve in the physical simulator, the two devices are connected using the system mixed simulation command. The connection method is the same as that of the inverter. The source of the NMOS is connected to the substrate contact and then to the ground, and the source of the PMOS is connected to the contact of the N-well lead and then to the power supply. The gate and drain of the two are connected to each other to form a complete inverter connection relationship. During the simulation process, special attention is paid to key physical mechanisms such as quantum confinement effect, drain-induced barrier lowering (DIBL) effect and self-heating effect. The calibration process includes strict iterative verification: after each parameter adjustment, the transfer characteristic curve (ID-VG) and output characteristic curve (Id-Vd) are re-simulated and quantitatively compared with the SPICE simulation data. Key performance indicators include threshold voltage (Vth) and off-state current (Ioff). The entire calibration process is controlled by automated scripts to ensure the traceability of parameter adjustment and the reproducibility of results. The comparison between the SPICE model and TCAD data before and after calibration is as follows: Figure 2 and Figure 3 As shown, Figure 2 and Figure 3 In the middle, the horizontal axis V gs Indicates the voltage between the gate and source, the vertical axis I d Indicates the drain current.

[0092] Step 2: Perform circuit-level secondary calibration. Model the inverter layout in the 55nm standard cell library, and build a CMOS inverter model based on the reinforced and calibrated inverter layout. The basic structural information refers to the specific layout structure of the corresponding MOSFET device. The doping information, voltage conditions, and contact design resistance are derived from the parameter files provided by the process manufacturer. The geometric parameters and process parameters are derived from the design files, parameter extraction files, SPICE models, and design rule files provided by the process manufacturer. Furthermore, at the electrical connection level, based on the connection relationship of the inverter, the gates and drains of the discrete NMOS and PMOS are connected (input and output are connected), the source of the PMOS tube is connected to the N-well contact, a nominal voltage of 1.2V is added, and the source of the NMOS tube is connected to the P-type substrate contact and then to the ground terminal.

[0093] Furthermore, based on the device model established in step 1, the inverter reconstructs a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region in the TCAD environment, and extracts the distributed parasitic resistance / capacitance network by solving. Different from the traditional schematic back-annotation method, this embodiment directly embeds the parasitic parameters as boundary conditions into the TCAD physical model to generate a circuit-level simulation entity including real parasitic effects. Specifically, first, a P substrate is constructed, and key parameter variables are defined. Then, the "growth direction" of the process is set to the vertical stacking direction of the device structure, and a three-dimensional tetrahedron is defined to constitute the basic framework of the device, including a substrate made of Si (silicon) and SiO2 The gate oxide layer is made of silicon dioxide and the oxide filled in the trench, and the gate is made of PolySi (polycrystalline silicon); the gate side oxide layer is defined with SiO2 as the material and the isolation layer is made of Nitride (nitride) as the material; the next step is to define the electrode, define the contact above the gate, define the contact below the substrate, and define the source and drain on the left and right sides of the gate; next, define the doping situation, first define the source and drain windows, and then define Gaussian doping, in order of doping type, peak doping concentration and position, doping depth and value, and Gaussian distribution influencing factor; finally, apply the defined doping concentration to the defined window to realize the definition of doping.

[0094] Further define the grid strategy, first define the maximum grid spacing and minimum grid spacing of the XYZ axis in the global grid coordinates, then define the grid near the channel, and add a grid refinement script to the channel to define multiple grid sizes; finally, define NMOS in the negative direction of the substrate, PMOS and the Nwell (i.e., n-well) below in the positive direction of the substrate, and the distribution of the metal layer introduced above is the same as the connection method of the inverter NMOS and PMOS. At the same time, holes are opened on the metal layer according to the layout structure, and the contact definition is the same as the active area type below; then uniformly update the MESH strategy to make the grid distribution more logical; the inverter layout diagram is shown as follows Figure 4 By iteratively adjusting parameters such as contact resistance and metal line capacitance, the rise / fall time and propagation delay of the inverter are matched; the comparison of the inverter VTC curve before and after calibration is shown in the figure below. Figure 5 and Figure 6 As shown, Figure 5 and Figure 6 In the middle, the horizontal axis V in Indicates the input voltage, the vertical axis V out Indicates the output voltage.

[0095] Step 3, conduct process-circuit joint verification. Through the modeling of the above steps, combined with the netlist post-simulation results provided by the process manufacturer, a secondary calibration is performed; further, to ensure the consistency of multi-level calibration, a closed-loop iteration mechanism is established: a threshold is set. When the deviation between the circuit dynamic performance (such as noise tolerance, power consumption) and the measured data exceeds the preset threshold, the reverse backtracking process is triggered; specifically, first analyze the parasitic parameter distribution to locate abnormal nodes (such as high-resistance contact holes), then retrospectively adjust the device physical parameters (trap density) or layout geometry model, and re-verify whether the IV characteristics of the single device are still consistent with the TCAD data; after systematic parameter optimization and iterative verification, the consistency between the TCAD model and the benchmark process data has been significantly improved; the simulation results of the MOSFET device characteristics are highly consistent with the process design kit data, and key parameters such as threshold voltage and off-state current are all converged to the engineering application tolerance range. This verification process fully confirms the model's predictive capabilities in dimensions such as static characteristics, dynamic response and parasitic effects through cross-comparison of experimental and simulation data, meeting the accuracy requirements of radiation hardening design for device-level models. The closed-loop iteration process diagram is shown below. Figure 7 As shown, further see Figure 7 ,exist Figure 7 The first stage is the initial calibration phase. Initial device-level calibration involves building an initial MOSFET TCAD model based on the geometric parameters of the Process Design Kit (PDK). Static characteristic curves are calibrated, generating parasitic parameters, reconstructing the 3D geometry (metal interconnect layers / contact hole arrays), and extracting the distributed RC parasitic network through solution. Circuit-level calibration then completes, embedding parasitic parameters as boundary conditions into the TCAD model to generate a circuit-level simulation entity. Finally, the parasitic parameters are fed back to iteratively adjust the contact resistance and capacitance to match the inverter's dynamic performance. The second stage is the verification and optimization phase. After calibration, the IV characteristics of individual devices are checked to ensure they still match the initial TCAD data. If verification fails, physical parameters (trap density, doping concentration) or geometric parameters are adjusted inversely. Device static characteristics and circuit dynamic performance are simultaneously optimized, updating device and circuit parameters and outputting an optimized global parameter set. The third phase is a closed-loop iteration. The TCAD model is updated based on the new parameters. A new parasitic RC network is extracted based on the optimized geometry, and the new parasitic parameters are embedded. The circuit timing characteristics are re-matched, and metal layer opening / contact definitions are dynamically adjusted. The device-level model is re-verified, and finally, the IV characteristics are re-verified for consistency. If any deviations still exist, the abnormal nodes are corrected retroactively. Further optimization is performed until the final multi-objective trade-off is achieved, and the final model is output after calibration.

[0096] In the above-mentioned solution of the present invention, the CMOS inverter is a basic logic circuit, mainly used to invert the phase of the input signal by 180 degrees. Its operating principle is based on PMOS and NMOS field-effect transistors. When the input is high, the NMOS turns on, the PMOS turns off, and the output is low. Conversely, when the input is low, the NMOS turns off, the PMOS turns on, and the output is high. CMOS inverters have low power consumption, high input impedance, and good anti-interference capabilities, and are widely used in digital circuits, logic gates, data storage, and other fields. The VTC curve refers to the relationship between input voltage and output voltage in digital circuits.

[0097] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0098] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A MOSFET device modeling method based on multi-level calibration, characterized in that: include: Establish an initial model of the MOSFET device based on the geometric parameters provided by the process design kit; Adjust the parameters of the initial model based on the current-voltage and capacitance-voltage characteristic curves of the circuit simulation model of the MOSFET device to complete the device-level electrical characteristic calibration; Reconstructing a three-dimensional geometric structure including a metal interconnect layer, a contact hole array, and a well region based on the initial model, extracting distributed parasitic parameters and embedding them as boundary conditions into the initial model to generate a circuit-level simulation entity including real parasitic effects; and iteratively adjusting contacts to match the rise / fall time and propagation delay of the inverter. A closed-loop iterative mechanism is established, and a threshold is set. When the deviation between the circuit dynamic performance and the measured data exceeds the threshold, a reverse backtracking process is triggered to reversely adjust the parasitic node parameters or the initial model corresponding to the device; when the deviation is less than or equal to the threshold, the MOSFET device modeling is completed.

2. The MOSFET device modeling method based on multi-level calibration according to claim 1, characterized in that: The geometric parameters include gate length, gate width, gate oxide thickness and junction depth of the MOSFET device.

3. The MOSFET device modeling method based on multi-level calibration according to claim 2, characterized in that: The initial model is a semiconductor process and device simulation model; In the process of establishing the semiconductor process and device simulation model, a Gaussian distribution doping distribution model is adopted and multiple physical models are configured to characterize the threshold voltage drift caused by short channel effect and quantum confinement by coupling and solving the quantum-corrected drift-diffusion equation and Poisson's equation; The physical models include a unified mobility model, a Shockley-Read-Hall-Auger composite model, and a density gradient quantum correction model.

4. The MOSFET device modeling method based on multi-level calibration according to claim 3, characterized in that: In the process of establishing the semiconductor process and device simulation model, the silicon substrate, gate oxide layer, polysilicon gate, and trench isolation structure are constructed in sequence according to the geometric parameters through Boolean operation strategy.

5. The MOSFET device modeling method based on multi-level calibration according to claim 4, characterized in that: The reconstructing of a three-dimensional geometric structure including a metal interconnection layer, a contact hole array, and a well region based on the initial model comprises: Build a P substrate and define key parameter variables and the basic framework of the three-dimensional tetrahedron device; Set the process generation direction to be the same as the vertical stacking direction of the device structure, and set the processing method of geometric Boolean operations to retain the properties of the first geometry; Define a gate-side oxygen layer made of silicon dioxide and an isolation layer made of silicon nitride, apply a fillet operation to specified vertices on the isolation layer, define a global parameter to represent the radius of the fillet, and smooth the edge area of ​​the isolation layer.

6. The MOSFET device modeling method based on multi-level calibration according to claim 5, characterized in that: The reconstructing of the three-dimensional geometric structure including the metal interconnection layer, the contact hole array and the well region based on the initial model further includes: Define the electrode, define the contact above the gate, define the contact below the substrate, and define both sides of the gate; After defining the source and drain windows, define Gaussian doping in the following order: doping type, peak doping concentration and position, doping depth and value, and Gaussian distribution influencing factor; The peak doping concentration is added to the defined window to define the doping.

7. The MOSFET device modeling method based on multi-level calibration according to claim 6, characterized in that: The reconstructing of the three-dimensional geometric structure including the metal interconnection layer, the contact hole array and the well region based on the initial model further includes: Define the grid strategy, including: First, define the maximum and minimum grid spacing of the global grid coordinate axes, then define the grid near the channel, and add a grid refinement script to the channel to define multiple grid sizes; The NMOS is defined in the negative direction of the substrate, and the PMOS and the n-well below are defined in the positive direction of the substrate. The distribution of the metal layer is the same as the connection method of the inverter NMOS and PMOS. At the same time, holes are opened on the metal layer according to the layout structure, and the contact is defined to be the same type as the active area below.

8. The MOSFET device modeling method based on multi-level calibration according to claim 7, characterized in that: The basic framework of the three-dimensional tetrahedron device is defined, including: Silicon is used as the substrate, silicon dioxide is used as the gate oxide layer and the oxide filled in the trench, and polysilicon is used as the gate.

9. The MOSFET device modeling method based on multi-level calibration according to claim 8, characterized in that: After the closed-loop iterative mechanism is established, the parasitic parameter distribution is analyzed to locate abnormal nodes; Retroactively adjust the physical parameters of MOSFET devices or the geometric model of the layout, and re-verify the correlation between the current-voltage variation characteristics of a single MOSFET device and semiconductor process and device simulations.

10. The MOSFET device modeling method based on multi-level calibration according to claim 9, characterized in that: The circuit dynamic performance includes noise margin and power consumption; The abnormal nodes include high-resistance contact holes, interconnected capacitance nodes and parasitic capacitance nodes; The physical parameters include trap density, doping concentration and interface state density.

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