Memory, storage system and electronic equipment

Abstract

The invention provides a memory, a memory system and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the size of the memory. The memory includes a plurality of memory blocks and a peripheral circuit device. The plurality of memory blocks are arranged in a first direction; the storage block comprises a storage part and a connecting part which are arranged along a second direction; the first direction and the second direction are crossed directions; a peripheral circuit device stacked with the memory block; the peripheral circuit device comprises a plurality of output sub-circuits arranged in the first direction, and in the stacking direction, one first output sub-circuit is overlapped with the connecting parts of at least two storage blocks; wherein in the first direction, the distance between the boundaries, far away from each other, of the two storage blocks located on the two outermost sides is larger than the distance between the boundaries, far away from each other, of the two output sub-circuits located on the two outermost sides. The memory is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory, a storage system, and an electronic device. Background Art

[0002] As semiconductor industry technology continues to advance, the size of memory continues to shrink.

[0003] The memory includes a memory array device and a peripheral circuit device that are electrically connected to each other. The size of the peripheral circuit device is relatively large, which is not conducive to reducing the overall size of the memory. Summary of the Invention

[0004] In one aspect, a memory is provided, comprising: a plurality of memory blocks and a peripheral circuit device. The plurality of memory blocks are arranged along a first direction. The memory blocks include a storage portion and a connection portion arranged along a second direction. The first direction and the second direction intersect. A peripheral circuit device is stacked with the memory blocks. The peripheral circuit device includes a plurality of output sub-circuits arranged along the first direction, wherein, along the stacking direction, one of the first output sub-circuits overlaps with the connection portions of at least two of the memory blocks. In particular, along the first direction, the distance between the mutually distant boundaries of the two memory blocks located on the outermost sides is greater than the distance between the mutually distant boundaries of the two output sub-circuits located on the outermost sides.

[0005] In some embodiments, along the first direction, the sum of sizes of the plurality of storage blocks is greater than the sum of sizes of the plurality of output sub-circuits.

[0006] In some embodiments, the connection portions of every m adjacent memory blocks are connected to every n adjacent output sub-circuits, where m>n≥1. The sum of the dimensions of the m memory blocks along the first direction is greater than the sum of the dimensions of the n output sub-circuits along the first direction.

[0007] In some embodiments, one of the output sub-circuit is connected to connection portions of at least two of the storage blocks.

[0008] In some embodiments, the output subcircuit includes a plurality of output cells, each of which includes at least two transistors. The output cells of the plurality of output subcircuits are arranged in multiple rows and columns. Along the first direction, a ratio of the size of one storage block to the size of one output cell is greater than or equal to 5 / 6.

[0009] In some embodiments, the output unit includes a first transistor and a second transistor, wherein the source and drain of the first transistor and the second transistor are both arranged along the first direction, and the source of the first transistor is shared with the source of the second transistor.

[0010] In some embodiments, the output subcircuit includes a plurality of transistors including high-voltage transistors.

[0011] In some embodiments, the peripheral circuit device includes a word line driver, and the word line driver includes the plurality of output sub-circuits.

[0012] In some embodiments, the storage portion of the memory block includes multiple stacked gate line layers, the connection portion of the memory block includes multiple connection structures, one connection structure is connected to one gate line layer, and one output sub-circuit is connected to multiple connection structures.

[0013] In some embodiments, the peripheral circuit device further includes at least one first circuit, which overlaps with a connection portion of at least one memory block along the stacking direction, and is arranged along the first direction with the plurality of output sub-circuits.

[0014] In some embodiments, the at least one first circuit includes at least one of a bit line driver, a page buffer, a voltage generator, and a logic circuit.

[0015] In another aspect, a storage system is provided, comprising: a controller and the memory according to any one of the above embodiments, wherein the controller is coupled to the memory and configured to control the memory to store data.

[0016] On the other hand, an electronic device is provided, comprising: the storage system described in the above embodiment, and a circuit board connected to the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, etc. involved in the embodiments of the present disclosure.

[0018] Figure 1 is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0019] Figure 2 is a structural diagram of a storage system according to some embodiments of the present disclosure;

[0020] Figure 3 is a structural diagram of a memory according to some embodiments of the present disclosure;

[0021] Figure 4 is a top view of a memory according to some embodiments of the present disclosure;

[0022] Figure 5 is a top view of a memory according to one implementation manner;

[0023] Figure 6A is a top view of yet another memory according to some embodiments of the present disclosure;

[0024] Figure 6B is a top view of yet another memory according to some embodiments of the present disclosure;

[0025] Figure 7 is a structural diagram of another memory according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0027] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "horizontal", "inside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0028] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0029] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0030] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0031] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0032] like Figure 1 As shown, some embodiments of the present disclosure provide an electronic device 3000, which can include any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, etc. The electronic device 3000 can include a storage system 1000 configured to implement data storage, as described below, and a circuit board 2000 electrically connected to the storage system. The circuit board 2000 is used to provide electrical signals, etc. to the storage system 1000.

[0033] like Figure 2 As shown, some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 is used in the above-mentioned electronic device 3000. The storage system 1000 includes a memory 100 and a controller 200. The controller 200 is coupled to the memory 100 and is used to control the memory 100 to store data.

[0034] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into various types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other electronic devices with memory.

[0035] In some examples, the storage system 1000 includes a controller 200 and a memory 100. The storage system 1000 can be integrated into a memory card, for example. The memory card includes one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0036] In other examples, such as Figure 2 As shown, the memory system 1000 includes a controller 200 and a plurality of memories 100 .

[0037] Exemplarily, the storage system 1000 includes a controller 200 and four memories 100. The storage system 1000 may be integrated into a solid state drive (SSD), for example.

[0038] In some examples, in storage system 1000, controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0039] In other examples, in the storage system 1000 , the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0040] In some examples, the controller 200 may be configured to manage data stored in the memory 100 and communicate with an external device (eg, a host).

[0041] In some examples, the controller 200 may also be configured to control operations of the memory 100 , such as read, erase, and program operations.

[0042] In some examples, controller 200 may also be configured to manage various functions regarding data stored or to be stored in memory 100 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0043] In some examples, the controller 200 is also configured to process error correction codes on data read from or written to the memory 100 .

[0044] It is easy to understand that the controller 200 can also perform any other suitable functions, such as formatting the memory 100. For another example, the controller 200 can communicate with an external device (eg, a host) via at least one of various interface protocols.

[0045] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0046] The controller 200 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0047] like Figure 3 As shown, some embodiments of the present disclosure further provide a memory 100 that can be used in the memory system 1000 in the above embodiments. The memory 100 includes: a memory array device 10 and a peripheral circuit device 20.

[0048] like Figure 4 As shown, a memory array device 10 includes a plurality of memory blocks 11 arranged along a first direction X. The memory blocks 11 include a memory portion 101 and a connection portion 102 arranged along a second direction Y. The first direction X and the second direction Y are two intersecting directions parallel to the plane where the memory array device 10 is located.

[0049] The angle between the first direction X and the second direction Y is in the range of 75° to 120°. For example, the angle between the first direction X and the second direction Y can be 75°, 85°, 90°, 105° or 120°.

[0050] The storage unit 101 is connected to the connection unit 102. The storage unit 101 may include a core region, and the connection unit 102 may include a step region or a self-aligned contact (SCT) region. The storage unit 101 includes a memory cell array for implementing storage functions, and the connection unit 102 is used to interconnect the storage unit 101.

[0051] For example, the storage portion 101 and the connection portion 102 in the same storage block 11 may have equal or substantially equal dimensions along the first direction X. The dimensions of each storage block 11 in the storage array device 10 along the first direction X may be equal or substantially equal. The plurality of storage blocks 11 are arranged in an interspaced arrangement, with a first gap G1 defined between adjacent storage blocks 11. The widths of the plurality of first gaps G1 may be equal. Isolation structures, etc., may be formed within the first gaps G1 to separate adjacent storage blocks 11.

[0052] The peripheral circuit device 20 is stacked with the memory block 11 in the memory array device 10. For example, the peripheral circuit device 20 is stacked on one side of the memory array device 10 along the thickness direction. The peripheral circuit device 20 and the memory array device 10 can be fabricated on different wafers and then stacked and electrically connected, including but not limited to bonding.

[0053] The peripheral circuit device 20 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0054] In some embodiments, as Figure 7As shown, the peripheral circuit device 20 may include a page buffer, a bit line driver (also called a column decoder), a word line driver (also called a row decoder), a voltage generator, a control logic, a register, and a data input / output circuit (I / F). It should be understood that in some examples, the peripheral circuit device 20 may also include Figure 7 Other additional circuits not shown.

[0055] The page buffer can be configured to read data from the memory array device 10 and program (write) data to the memory array device 10 according to control signals from the control logic. In one example, the page buffer can store data (write data) programmed into a selected page of the memory array device 10. In another example, the page buffer can output the read data during a program verification operation to ensure that the data has been correctly programmed into the corresponding memory cells of the selected word line of the memory array device 10 or the aforementioned memory block.

[0056] The bit line driver may operate in response to control signals provided by the control logic to select one or more memory strings in the memory array device 10. The word line driver may operate in response to control signals provided by the control logic and select / deselect selected rows of the memory array device 10. The word line driver may also be configured to supply voltages generated from the voltage generator to selected word lines and unselected word lines of the memory array device 10. The word line driver may also be configured to perform an erase operation on memory cells coupled to one or more selected word lines in the memory array device 10.

[0057] The voltage generator may use an external power supply voltage or an internal power supply voltage to generate various voltages required by the memory array device 10, such as a program voltage, a read voltage, a pass voltage, a verification voltage, a bit line voltage, etc., and combinations thereof.

[0058] The control logic may be coupled to various circuits such as the voltage generator, page buffer, word line driver, bit line driver, and data input / output circuit, and may be configured to control the operation of each circuit. The control logic may generate an operation signal in response to a command or control signal from the memory controller. Registers may be coupled to the control logic, where the registers include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of the aforementioned various circuits.

[0059] The data input / output circuit can be coupled to the control logic and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic, as well as buffer status information received from the control logic and relay them to the host. The data input / output circuit can also be coupled to the bit line driver and act as a data input / output interface and data buffer to buffer data and relay it to or from the memory array device 10.

[0060] like Figure 4 As shown, the peripheral circuit device 20 includes a plurality of output sub-circuits 21 arranged along a first direction X. In some embodiments, a word line driver may include an output sub-circuit 21, and the output sub-circuit 21 is used, for example, to output a set voltage to select / deselect a selected row of the memory array device 10. In some other embodiments, other circuits in the peripheral circuit device 20 may also include an output sub-circuit 21, which will not be enumerated here.

[0061] It can be understood that the at least two storage blocks 11 mentioned above refer to at least two storage blocks 11 that are sequentially adjacent to each other along the first direction X.

[0062] like Figure 4 As shown, among the multiple output sub-circuits 21, a second gap G2 exists between any two adjacent output sub-circuits 21. In some cases, the boundary between two adjacent output sub-circuits 21 is non-linear, such as a zigzag line, and the size of the zigzag-shaped second gap G2 is uniform (the second gap G2 includes multiple linear portions connected in sequence, each having equal dimensions along a direction perpendicular to the second gap). In other cases, the boundary between two adjacent output sub-circuits 21 is linear, and the width of the linear second gap G2 (the dimension of the second gap G2 along a direction perpendicular to the second gap) is uniform.

[0063] Exemplarily, the sizes of the second gaps G2 are equal or substantially equal. For example, the widths of the plurality of linear second gaps G2 are equal or substantially equal. The sizes of the plurality of zigzag-line second gaps G2 are equal or substantially equal. The sizes of the zigzag-line second gaps G2 are or substantially equal to the sizes of the linear second gaps G2.

[0064] Thus, the multiple output sub-circuits 21 can be arranged more regularly, which is beneficial to reducing the area or space occupied by the multiple output sub-circuits 21 and further beneficial to achieving a miniaturized design of the memory 100 .

[0065] Along the stacking direction, one output sub-circuit 21 overlaps with the connection portions 102 of at least two memory blocks 11. For example, along the stacking direction, one output sub-circuit 21 overlaps with the connection portions 102 of two memory blocks 11. For another example, one output sub-circuit 21 overlaps with the connection portions 102 of three memory blocks 11.

[0066] Wherein, along the first direction X, the distance L1 between the boundaries of the two storage blocks 11 located on the outermost sides away from each other is greater than the distance L2 between the boundaries of the two output sub-circuits 21 located on the outermost sides away from each other.

[0067] Since the multiple memory blocks 11 in the memory array device 10 are arranged along the first direction X, the distance L1 between the boundaries of the two outermost memory blocks 11 that are separated from each other along the first direction X can be considered as the size of the area occupied by the multiple spaced-apart memory blocks 11 in the first direction X, which includes the size of the multiple first gaps G1 in the first direction X. Since the multiple output sub-circuits 21 in the peripheral circuit device 20 are arranged along the first direction X, the distance L2 between the boundaries of the two outermost output sub-circuits 21 that are separated from each other along the first direction X can be considered as the size of the area occupied by the multiple spaced-apart output sub-circuits 21 in the peripheral circuit device 20 in the first direction X, which includes the size of the multiple second gaps in the first direction X.

[0068] Therefore, the size of the area occupied by the multiple output sub-circuits 21 in the peripheral device in the first direction X can be made relatively small, so that the size of the multiple storage blocks 11 covered by the multiple output sub-circuits 21 in the first direction X is small, so that the parts NG of the multiple storage blocks 11 not covered by the multiple output sub-circuits 21 along the first direction X can be covered (for details, please refer to Figure 4 ), setting other structures in the peripheral circuit device 20 (such as the first circuit 22 mentioned below, etc.) is beneficial to reducing the size of the multiple storage blocks 11 in the first direction X, reducing the size of the peripheral circuit device 20, and further helping to compress the size of the memory, which is beneficial to realizing the miniaturization design of the memory 100 and the electronic device 3000.

[0069] In some examples, such as Figure 4 As shown, the peripheral circuit device 20 further includes at least one first circuit 22 .

[0070] Along the stacking direction, at least one first circuit 22 overlaps with the connection portion 102 of at least one memory block 11 , and the at least one first circuit 22 and the plurality of output sub-circuits 21 are arranged along the first direction X.

[0071] Therefore, the space or size saved by the multiple output sub-circuits 21 in the first direction X can be occupied by the first circuit 22, thereby saving the area or space occupied by the peripheral circuit device 20, reducing the size of the peripheral circuit device 20, and further reducing the size of the memory 100 and the electronic device 3000, and optimizing the design space of the first circuit 22 in the peripheral circuit device 20.

[0072] Specifically, the at least one first circuit 22 includes at least one of the bit line driver, the page buffer, the voltage generator, and the logic circuit mentioned in the above embodiments.

[0073] Thus, the design positions and design spaces of the bit line driver, page buffer, voltage generator and logic circuit can be made more selective, which is beneficial to reducing the size of the peripheral circuit device 20 and further reducing the size of the memory 100 and the electronic device 3000.

[0074] It is understood that the relationship between the size of the storage block 11 along the first direction X and the width of the first gap G1 can be set according to actual needs. The relationship between the size of the output sub-circuit 21 and the second gap G2 can also be set according to actual needs, and the embodiments of the present disclosure are not limited to this.

[0075] The size of the storage block 11 along the first direction X is much larger than the width of the first gap G1. Therefore, the width of the first gap G1 is negligible compared to the storage block 11. The size of the area occupied by the multiple storage blocks 11 in the first direction X (i.e., the distance L1 between the boundaries of the two outermost storage blocks 11 along the first direction X) can be approximately equal to the sum of the sizes of the multiple storage blocks 11 in the first direction X. Similarly, the size of the output sub-circuit 21 in the first direction X (i.e., the distance L2 between the boundaries of the two outermost output sub-circuits 21 along the first direction X) is much larger than the size of the second gap in the first direction X. Therefore, the size of the second gap in the first direction X is negligible compared to the output sub-circuit 21. The size of the area occupied by the multiple output sub-circuits 21 in the first direction X can be approximately equal to the sum of the sizes of the multiple output sub-circuits 21 in the first direction X.

[0076] Exemplarily, along the first direction X, the sum of sizes of the plurality of storage blocks 11 is greater than the sum of sizes of the plurality of output sub-circuits 21 .

[0077] Thus, the size occupied by the multiple output sub-circuits 21 in the first direction X can be made smaller, and the size of the peripheral circuit device 20 can be reduced, which is conducive to realizing the miniaturization design of the memory 100 and the electronic device 300.

[0078] In some examples, one output sub-circuit 21 is connected to connection portions of at least two storage blocks 11 .

[0079] For example, one output sub-circuit 21 is connected to the connection portions 102 of two memory blocks 11 .

[0080] For another example, one output sub-circuit 21 is connected to the connection portions 102 of three storage blocks 11 .

[0081] Therefore, the number of output sub-circuits 21 can be reduced to a certain extent, and the size or volume of the peripheral circuit device 20 can be reduced, which is conducive to the miniaturization design of the memory 100 and the electronic device 300.

[0082] In one implementation, Figure 5 As shown, the four connected storage blocks 11 and the two output sub-circuits 21 have equal or substantially equal dimensions along the first direction X, and the four connected storage blocks 11 and the two output sub-circuits 21 form a repeating unit. However, the above arrangement is not conducive to the miniaturization design of the memory.

[0083] In the embodiments of the present disclosure, Figure 4 As shown, a connection portion 102 is provided for every m adjacent storage blocks 11, connected to every n adjacent output sub-circuit 21, where m>n≥1. For the m storage blocks 11 and n output sub-circuits 21 connected, the sum of the dimensions of the m storage blocks 11 along the first direction X is greater than the sum of the dimensions of the n output sub-circuits 21 along the first direction X.

[0084] For example, if m is 4 and n is 2, the connection portions 102 of every four adjacent storage blocks 11 are connected to every two adjacent output sub-circuits 21, and the sum of the sizes of the four storage blocks 11 along the first direction X is smaller than the sum of the sizes of the two output sub-circuits 21 along the first direction X.

[0085] In this way, it can be ensured that the sum of the sizes of the n output sub-circuits 21 in the first direction X is small, and the size occupied on the connecting parts 102 of the m storage blocks 11 connected thereto is small, thereby ensuring that the size occupied by the multiple output sub-circuits 21 in the first direction X is small, so that other circuit structures can be set in the multiple storage blocks 11 in the first direction X, reducing the size of the peripheral circuit device 20, which is conducive to saving space, and further realizing the miniaturization design of the memory 100 and the electronic device 300.

[0086] In some examples, such as Figure 4 As shown, the output sub-circuit 21 includes a plurality of output units 211, each of which is connected to the storage unit 101 of the corresponding storage block 11. Figure 6AAs shown, each output unit 211 includes at least two transistors 212. The multiple output units 211 of the multiple output sub-circuits 21 are arranged in multiple rows and columns.

[0087] For example, the multiple output units 211 of the same output sub-circuit 21 are arranged in two rows and multiple columns. The multiple output units 211 of two adjacent output sub-circuits 21 are arranged in three rows and multiple columns.

[0088] Along the first direction X, a ratio of the size of one storage block 11 to the size of one output unit 211 is greater than or equal to 5 / 6.

[0089] For example, along the first direction X, the ratio of the size of one storage block 11 to the size of one output unit 211 may be 5:6, 1:1, 2:3, 4:5, or 6:5.

[0090] By adopting the above-mentioned setting method, the size of the multiple output units 211 in the multiple output sub-circuits 21 along the first direction X can be smaller, and the size of the multiple storage blocks 11 not covered by the multiple output units 211 can be larger, which is conducive to saving space and realizing the miniaturization design of the memory 100 and the electronic device 300.

[0091] The peripheral circuit device 20 includes a high voltage (HV) device area, a low voltage (LV) device area and a low-low voltage device area, and the output sub-circuit 21 is located in the high voltage device area. Figure 6A As shown, the output sub-circuit 21 includes multiple transistors 212, and the multiple transistors 212 include high-voltage transistors. When the output sub-circuit 21 is applied to a word line driver and outputs a set voltage for selecting a selected row, the output sub-circuit 21 including the high-voltage transistors can output high voltage, which helps to improve the high-voltage resistance and breakdown resistance characteristics of the transistors 212 and the output sub-circuit 21, and thus helps to improve the performance of the memory 100.

[0092] For example, the voltage value output by the high-voltage transistor is greater than or equal to 20V, and the voltage value output by the low-voltage transistor is less than or equal to 8V.

[0093] In some examples, such as Figure 6A As shown, the output unit 211 includes a first transistor 213 and a second transistor 214. For example, the first transistor 213 and the second transistor 214 are both high-voltage transistors.

[0094] For example, the voltage values ​​output by the first transistor 213 and the second transistor 214 may both be greater than or equal to 20V.

[0095] The voltage value output by the first transistor 213 and the voltage value output by the second transistor 214 may be in the same range or in different ranges.

[0096] The source 215 and the drain 216 of the first transistor 213 and the second transistor 214 are both arranged along the first direction X.

[0097] The gate 217 of the first transistor 213 is located between its source 215 and drain 216. The gate 217 of the second transistor 214 is located between its source 215 and drain 216. The source 215 of the first transistor 213 is shared with the source 215 of the second transistor 214.

[0098] As a result, the size occupied by the output unit 211 in the first direction X can be made smaller, which is beneficial for reducing the size of the output sub-circuit 21 in the first direction X, reducing the size of the peripheral circuit device 20, and facilitating the miniaturization of the memory 100 and the electronic device 300, thereby avoiding the source of the first transistor 213 and the source of the second transistor 214 from occupying a large size in the first direction X. The manufacturing process of the output unit 211 can also be simplified.

[0099] like Figure 7 As shown, when the multiple output sub-circuits 21 are applied to a word line driver, the word line driver may further include a control circuit, which is electrically connected to the multiple output sub-circuits 21. For example, the control circuit is electrically connected to the gate of the first transistor 213 and the gate of the second transistor 214 in the output sub-circuit 21, and is also electrically connected to the source of the first transistor 213 and the second transistor 214.

[0100] Thus, the size of the word line driver can be reduced, and the size or volume of the memory 100 can be reduced.

[0101] In some examples, such as Figure 6A As shown, the storage portion 101 of the storage block 11 includes a plurality of gate line layers 1011 stacked together, and the connection portion 102 of the storage block 11 includes a plurality of connection structures 1021. One layer of gate line layer 1011 is connected to at least one connection structure 1021, for example, one layer of gate line layer 1011 is connected to one connection structure 1021. In other words, each layer of gate line layer 1011 has a corresponding connection relationship with at least one first connection structure 1021. The connection structure 1021 can penetrate the film layer above the gate line layer 1011 to which it needs to be connected along the thickness direction of the storage array device 10, thereby achieving connection with the gate line layer 1011.

[0102] like Figure 6B As shown, one output sub-circuit 21 is connected to a plurality of connection structures 1021 .

[0103] For example, an output sub-circuit 21 includes six output units 211. The storage portion 101 of a memory block 11 includes six stacked gate line layers 1011, each gate line layer 1011 being connected to a connection structure 1021. A connection structure 1021 is connected to the drain 216 of a transistor 212 of an output unit 211 in the output sub-circuit 21. The six gate line layers 1011 of the same memory block 11 are connected to the six output units 211 in the same output sub-circuit 21 via six connection structures 1021, for example, to the drain 216 of a transistor 212 of each output unit 211.

[0104] Thus, the gate line layer 1011 in the memory block 11 can be connected to the output sub-circuit 21 by using the connection structure 1021 , so as to receive a signal from the word line driver.

[0105] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: include: A plurality of storage blocks are arranged along a first direction; the storage blocks include storage portions and connection portions arranged along a second direction; the first direction and the second direction are intersecting directions; A peripheral circuit device is stacked with the memory block; the peripheral circuit device includes a plurality of output sub-circuits arranged along the first direction, and along the stacking direction, one of the first output sub-circuits overlaps with a connection portion of at least two of the memory blocks; Wherein, along the first direction, the distance between the boundaries of the two storage blocks located on the outermost sides is greater than the distance between the boundaries of the two output sub-circuits located on the outermost sides.

2. The memory according to claim 1, wherein Along the first direction, the sum of sizes of the plurality of storage blocks is greater than the sum of sizes of the plurality of output sub-circuits.

3. The memory according to claim 1, wherein: One of the output sub-circuits is connected to the connection portions of at least two of the storage blocks.

4. The memory according to claim 3, wherein: The connection portion of each adjacent m storage blocks is connected to each adjacent n output sub-circuit, m>n≥1; The sum of sizes of the m storage blocks along the first direction is greater than the sum of sizes of the n output sub-circuits along the first direction.

5. The memory according to claim 1, wherein: The output subcircuit includes a plurality of output units, each of which includes at least two transistors; the plurality of output units of the plurality of output subcircuits are arranged in a plurality of rows and columns; Along the first direction, a ratio of a size of the storage block to a size of the output unit is greater than or equal to 5 / 6.

6. The memory according to claim 5, wherein: The output unit includes a first transistor and a second transistor; The source and drain of the first transistor and the second transistor are both arranged along the first direction, and the source of the first transistor is shared with the source of the second transistor.

7. The memory according to claim 1, wherein: The output sub-circuit includes a plurality of transistors including high-voltage transistors.

8. The memory according to any one of claims 1 to 7, wherein: The peripheral circuit device includes a word line driver including the plurality of output sub-circuits.

9. The memory according to claim 8, wherein: The storage portion of the storage block includes a plurality of gate line layers stacked together, and the connection portion of the storage block includes a plurality of connection structures, wherein one connection structure is connected to one gate line layer. One output sub-circuit is connected to a plurality of the connection structures.

10. The memory according to claim 1, wherein: The peripheral circuit device further includes at least one first circuit; Along the stacking direction, at least one of the first circuits overlaps with a connection portion of at least one of the memory blocks, and at least one of the first circuits and the plurality of output sub-circuits are arranged along the first direction.

11. The memory according to claim 10, wherein: The at least one first circuit includes at least one of a bit line driver, a page buffer, a voltage generator, and a logic circuit.

12. A storage system, characterized in that: include: A controller and a memory according to any one of claims 1 to 11; wherein the controller is coupled to the memory and is used to control the memory to store data.

13. An electronic device, characterized in that: The electronic device includes the storage system according to claim 12, and a circuit board connected to the storage system.

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