Universal nonvolatile memory chip for providing LPDDR interface and electronic equipment

Abstract

The invention provides a universal nonvolatile memory chip providing an LPDDR interface and electronic equipment, and the memory chip comprises a control module which is electrically connected with an upper computer and controls the storage behavior of the memory chip; the memory supports row and column addressing and random access, provides parallel data, allows the control module to call firmware in the memory, and controls a system of the memory chip to be started instantly; the interface module is electrically connected between the memory and the control module; in a memory cell of a memory, a source electrode or a drain electrode of the memory cell is in a floating state. The invention provides a universal nonvolatile memory chip for providing an LPDDR interface and electronic equipment, which can support instant start-up of a system on the basis of low power consumption.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a universal non-volatile storage chip and electronic equipment providing an LPDDR interface. Background Art

[0002] Low-power double data rate SDRAM (LPDDR) is known for its low power consumption and compact size, specifically for use in mobile electronic products. LPDDR interfaces between the central processing unit (CPU) and memory modules for low-power or mobile applications. Because memory modules require refresh cycles to retain data, they still consume considerable resources and cannot meet the growing demand for low power consumption.

[0003] NOR flash memory is a non-volatile flash memory technology. As device sizes shrink, the gate length of NOR flash memory decreases, which can lead to current breakdown. Consequently, it's difficult to balance storage efficiency, reliability, and low power consumption in storage devices. Summary of the Invention

[0004] The object of the present invention is to provide a universal non-volatile memory chip and electronic equipment providing an LPDDR interface, which can support instant system startup on the basis of low power consumption.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a universal non-volatile memory chip providing an LPDDR interface, comprising:

[0007] A control module is electrically connected to the host computer and controls the storage behavior of the storage chip;

[0008] a memory supporting row and column addressing and random access, and providing parallel data, wherein the control module is allowed to call firmware in the memory and control the instant startup of the system of the memory chip; and

[0009] an interface module electrically connected between the memory and the control module;

[0010] In the memory cell of the memory, a source electrode or a drain electrode of the memory cell is in a floating state.

[0011] In one embodiment of the present invention, the memory chip is electrically connected to an external power supply device, and the external power supply device provides an external power supply voltage for the memory, wherein the external power supply voltage includes 1V.

[0012] In one embodiment of the present invention, the memory chip includes an internal power supply module, which is electrically connected to the memory cell of the memory and supplies power to a non-floating electrode in the memory cell, wherein the internal power supply voltage of the memory is greater than 1V.

[0013] In one embodiment of the present invention, in the memory chip, the interface module is electrically connected to the memory through a plurality of pins and wiring harnesses, wherein the refresh pins of the memory are floating, or the number of the refresh pins of the memory is set to zero.

[0014] In one embodiment of the present invention, the memory stores pre-installed firmware, and when the memory chip is powered on again, the control module calls and executes the pre-installed firmware in the memory.

[0015] In one embodiment of the present invention, the memory chip includes a read-write circuit, which is electrically connected to the control module and the memory, wherein the output channels of the read-write circuit include 32 channels and 16 channels, and the output channels output data on the rising edge and / or falling edge of the clock.

[0016] In one embodiment of the present invention, the storage behavior includes reading user data, writing user data, erasing user data, adjusting the working mode of the storage chip, and running the firmware in the memory after power-on.

[0017] In one embodiment of the present invention, the memory chip includes a substrate, allowing the memory, the read / write circuit, and the control module to be disposed on the same substrate.

[0018] In one embodiment of the present invention, the memory is a NOR flash memory.

[0019] The present invention also provides an electronic device, comprising any one of the above-mentioned universal non-volatile memory chips providing an LPDDR interface, wherein the system starts immediately when the electronic device is started.

[0020] As described above, the present invention provides a universal non-volatile memory chip and electronic device with an LPDDR interface. The memory chip provided by the present invention can retain data content without refreshing, thereby reducing chip power consumption. Furthermore, the memory chip provided by the present invention can operate at a voltage of 1.0V and can continue to shrink in size in accordance with Moore's Law without gate breakdown due to current. Furthermore, the memory chip and electronic device provided by the present invention can start up instantly after the system is started, reducing the system startup delay and significantly improving the efficiency of system calls.

[0021] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 FIG. 1 is a schematic diagram of the structure of a memory chip in one embodiment of the present invention.

[0024] Figure 2 FIG. 1 is a schematic structural diagram of a storage unit in an embodiment of the present invention.

[0025] In the figure: 100, memory chip; 110, memory; 120, state machine; 131, row pre-decoder; 132, column pre-decoder; 133, column decoder; 141, address register; 142, address buffer; 143, mode register; 144, column address counter; 145, burst counter; 146, data output controller; 151, input buffer; 152, write data register; 153, sense amplifier; 154, input / output gating circuit; 155, output buffer; 156, data bus; 157, data select transmitter; 158, data select receiver; 200, memory cell. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0027] NOR flash memory includes multiple memory cells 200, each of which can be a floating gate field-effect transistor (FET). Each memory cell 200 includes at least a tunnel oxide layer, a floating gate layer, and a control gate layer. Multiple memory cells 200 can be disposed on the same substrate. The tunnel oxide layer is disposed on the substrate, the floating gate layer is disposed on the tunnel oxide layer, and the control gate layer is disposed on the floating gate layer. When the control gate layer is energized, electrons can pass through the tunnel oxide layer and reach the floating gate layer, thereby changing the stored data. The multiple memory cells 200 of the NOR flash memory are connected in parallel, allowing each memory cell 200 to independently read and write data. This improves the efficiency of reading data from the NOR flash memory. However, due to its inherent structural limitations, NOR flash memory has a low storage density, making it difficult to adapt to the trend of ever-shrinking devices. In particular, when the device gate length is less than 130 nm, the gate of the NOR flash memory is susceptible to current breakdown. The memory chip 100 provided by the present invention includes a memory 110, wherein the memory 110 is a NOR flash memory. The memory 110 includes a storage array, and the storage array includes a plurality of storage units 200 that store data independently of each other.

[0028] See also Figure 1As shown, the memory chip 100 provided by the present invention includes a control module, a memory 110 and an interface module. The control module is electrically connected to the host computer and controls the storage behavior of the memory chip 100. In this embodiment, the control module can be a microprocessor, for example, a reduced instruction system computer (RISC), and specifically an ARM processor. In this embodiment, the storage behavior of the memory chip 100 includes the reading of user data, the writing of user data, the erasing of user data and the adjustment of the working mode of the memory chip 100, as well as the operation of the firmware in the memory 110 after power-on, etc. The memory 110 supports row and column addressing and random access, and the memory 110 provides parallel data. The control module can directly call the firmware in the memory 110 and control the system instant startup of the memory chip 100. Based on the memory chip 100 provided by the present invention, it can be used to manufacture a variety of electronic devices, such as digital devices with storage functions, electronic devices with high requirements for startup speed, electronic devices with high requirements for low power consumption, etc. For example, the electronic device provided by the present invention can be a mobile smart device, a portable consumer electronic device, an Internet of Things and embedded system, an automotive-related electronic device and an AI device, etc. Among them, the interface module is electrically connected between the memory 110 and the control module. In this embodiment, the interface module includes a port and a wiring harness. It should be noted that the wiring harness described in the present invention is not limited to the wiring harness on the circuit board, but can also be the metal wiring in the field of integrated circuits. Among them, the memory chip 100 provided by the present invention is a general-purpose non-volatile memory chip 100 that provides an LPDDR interface.

[0029] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, a memory 110 includes multiple memory cells 200. In this embodiment, the memory 110 is, for example, a NOR flash memory. The multiple memory cells 200 in the memory 110 are independent of each other. The memory cells 200 may be floating gate field effect transistors. The memory cells 200 include a floating gate, a control gate, a source electrode, and a drain electrode. The source electrode or the drain electrode of the memory cell 200 is in a floating state. In one embodiment of the present invention, the memory chip 100 is electrically connected to an external power supply device, which provides an external power supply voltage to the memory 110. In this embodiment, the external power supply voltage may be 1V, thereby maintaining low power consumption of the memory chip 100. In this embodiment, the memory chip 100 includes an internal power supply module, which is electrically connected to the memory cells 200 of the memory 110 and supplies power to a non-floating electrode of the memory cell 200. The internal power supply voltage of the memory 110 is greater than 1V. In this embodiment, the source electrode voltage of the memory 110 is, for example, 7V, and the drain electrode is in a floating state. The floating state may be that the voltage value of the drain electrode is greater than 0V and less than 1V. When the gate length of the storage unit 200 is reduced, the electrode at one end of the memory 110 is not grounded, and no excessive current will appear between the two electrodes, so the gate can be guaranteed not to be broken down. The memory chip 100 provided by the present invention can adapt to the shrinking device size under Moore's Law, and more memory cells 200 can be placed in a unit area, thereby improving the storage density. When the area of ​​the memory chip 100 remains unchanged, the memory chip 100 provided by the present invention can not only meet the low power consumption requirements and improve the life of the storage device, but also realize the instant startup of the chip system or electronic device system after startup, and can improve the storage capacity.

[0030] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in the memory chip 100, the interface module is electrically connected to the memory 110 through a plurality of pins and a wiring harness, wherein the refresh pin of the memory 110 is floating, or the number of refresh pins of the memory 110 is set to zero. In this embodiment, the memory chip 100 is a low-power memory (Low Power Double Data Rate SDRAM, LPDDR). Specifically, the memory 110 can be electrically connected to the control module through the LPDDR interface, and the interface voltage can be as low as 1.0V. In the present invention, the memory chip 100 can achieve data retention without relying on refresh, thereby saving the power consumption of the memory chip 100 and improving the life of the memory chip 100.

[0031] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, pre-installed firmware is stored in memory 110. When the memory chip 100 is powered on again, the control module calls and executes the pre-installed firmware in memory 110. The present invention does not limit the content of the pre-installed firmware, and it can be changed or adjusted according to the device firmware design requirements. Before the memory chip 100 leaves the factory, the pre-installed firmware is written to memory 110 to complete the installation. When the memory chip 100 is powered on again, the pre-installed firmware can be directly called from memory 110 without having to read the firmware to any storage location.

[0032] See also Figure 1 As shown, in one embodiment of the present invention, the memory chip 100 includes a state machine 120 and a read / write circuit. The state machine 120 is provided with multiple control pins and is electrically connected to a control module or a host computer through the control pins and a wiring harness. The multiple control pins are respectively used to receive multiple clock signals CLK, clock enable signal CKE, chip select signal CS, row address strobe signal RAS, column address strobe signal CAS, write operation control signal WE, low byte data mask signal LDM, high byte data mask signal UDM, etc. The state machine 120 is electrically connected to the decoder.

[0033] See also Figure 1As shown, in one embodiment of the present invention, the read / write circuit includes an address strobe module, a decoding module, and an input / output control module. The address strobe module includes an address register 141, an address buffer 142, a mode register 143, a column address counter 144, a burst counter 145, and a data output controller 146. In this embodiment, the address register 141 is used to temporarily store the address information sent by the control module. The address information is used to locate the storage unit 200 to be called. During the read / write operation of the memory chip 100, the address register 141 receives and stores the target address, wherein the target address includes a row address and a column address. The target address can be used to locate the specified storage unit 200 in the storage array of the memory 110. In combination with the row address strobe signal RAS and the column address strobe signal CAS, the address register 141 can determine the specific address where the read / write operation occurs, thereby ensuring that the address information remains stable during the operation and avoiding errors caused by address changes. The address buffer 142 is electrically connected to the address register 141 and is used to enhance the driving capability of the address strobe signal and isolate external signals from the internal circuitry of the memory chip 100, thereby improving the stability and anti-interference capability of the address strobe signal and ensuring accurate transmission of address information. In this embodiment, the address buffer 142 is capable of receiving the address strobe signal from the control module and amplifying and shaping the address strobe signal to ensure that the address strobe signal can be reliably transmitted to the internal circuitry of the memory chip 100. The mode register 143 is electrically connected to the address register 141, the burst counter 145, and the data output controller 146 and is used to configure the operating mode and parameters of the memory chip 100. In this embodiment, the mode register 143 stores configuration information for the memory chip 100, such as burst length, delay time from read command issuance to data output, read and write timing, etc. The control module can write configuration data to the mode register 143 through a predetermined instruction, such as the MRS (Mode Register Set) command. During initialization or operation, the contents of the mode register 143 determine the behavior of the memory 110. The configuration of the mode register 143 can enhance the flexibility of the memory chip 100 and optimize the performance of the memory chip 100 , thereby dynamically adjusting the operating mode of the memory 110 according to system requirements.

[0034] See also Figure 1As shown, in one embodiment of the present invention, column address counter 144 is electrically connected to state machine 120 and burst counter 145 and is used to generate consecutive column addresses. Column address counter 144 supports burst read and write operations. When a read or write command is received, column address counter 144 starts from an initial column address. Based on the configured burst length, column address counter 144 automatically increments to generate consecutive column addresses. The increment step size is determined by the configuration of memory 110; for example, the step size can be set to 1 or 2. The generated incremented column addresses can be used to access consecutive columns in the memory array 110. Column address counter 144 reduces the number of column address transmissions by the control module, improves data transmission efficiency, and enables the memory chip 100 provided by the present invention to support burst mode operation and adapt to continuous data read and write scenarios. Burst counter 145 is electrically connected to mode register 143, column address counter 144, and data output controller 146 and is used to track the amount of data in a burst transmission to ensure the correct completion of the burst operation. In this embodiment, burst counter 145 is initialized at the start of a burst operation and is initially set to the configured burst length. Each time a data unit, such as a byte or word, is transmitted, the burst counter 145 decrements. When the burst counter 145 reaches 0, the burst operation is complete. During a burst operation, the burst counter 145 works in conjunction with the column address counter 144 to ensure sequential data transmission, simplify the control flow of the memory chip 100, and reduce the complexity of the control signals. The data output controller 146 is electrically connected to the burst counter 145, the mode register 143, and the input / output control module, and is responsible for managing the output timing and drive of the data, ensuring that the data is output within the correct clock cycle. During a read operation of the memory chip 100, the data output controller 146 determines the data output timing based on the column address strobe delay and the burst length. The column address strobe delay is the delay from the issuance of the read command to the output of the data. The data output controller 146 reads data from the memory array of the memory 110 and outputs the data to the control module via the data bus 156. The data output controller 146 manages the data drive strength to ensure signal integrity and optimize the stability and reliability of data transmission.

[0035] See also Figure 1As shown, in one embodiment of the present invention, the decoding module includes a row pre-decoder 131, a column pre-decoder 132, and a column decoder 133. The row pre-decoder 131 is electrically connected to the state machine and the memory, and is used to perform preliminary decoding on the row address, thereby reducing the load and complexity of the final row decoder. The column pre-decoder 132 is electrically connected to the state machine and the memory, and is used to perform preliminary decoding on the column address, thereby reducing the load and complexity of the final column decoder 133. The column decoder 133 is electrically connected to the column decoder 133 and the memory, and is used to perform final decoding on the column address to select the target column. In this embodiment, the column decoder 133 receives an intermediate signal from the column pre-decoder 132. The column select line is generated based on the received intermediate signal, the target column is activated, and the target memory cell is selected. After the target row and column are activated, the target memory cell in the memory is selected, and the data read and write operation is completed.

[0036] See also Figure 1 As shown, in one embodiment of the present invention, the input / output control module includes an input buffer 151, a write data register 152, a sense amplifier 153, an input / output gating circuit 154, an output buffer 155, a data bus 156, a data strobe transmitter 157, and a data strobe receiver 158. The input buffer 151 is used to receive the digital signal DS sent by the control module and temporarily store the write data transmitted from the control module. In this embodiment, when a write operation begins, the input buffer 151 receives the write data from the data bus 156 and buffers and shapes the write data to ensure the integrity and stability of the input signal. The buffered write data is then transferred to the write data register 152, awaiting writing to the storage array of the memory 110. In this embodiment, the input buffer 151 includes a buffer and logic circuitry. The write data register 152 is electrically connected to the input buffer 151 and the memory 110, and is used to temporarily store the write data transmitted from the input buffer 151 and transmit the write data to the memory 110. In this embodiment, during a write operation, write data register 152 writes the write data to a specified address in memory 110 according to the column address and timing requirements. After the write is complete, write data register 152 is cleared and ready to receive the next batch of write data. The write register not only ensures that the write data is written to memory 110 according to the correct timing and address, but also supports burst write operations, improving data write efficiency.

[0037] See also Figure 1As shown, in one embodiment of the present invention, sense amplifier 153 is electrically connected to memory 110 and input / output gating circuit 154 and is used to amplify and read data from memory cell 200. In this embodiment, during a read operation, target memory cell 200 in memory 110 is activated. The data in memory cell 200 is transmitted to the bit line in the form of a weak voltage signal. Sense amplifier 153 is connected to the bit line, detects and amplifies the weak voltage signal of the data, and converts the voltage signal into a logic high level 1 or a logic low level 0. The amplified data is transmitted to output buffer 155 and prepared for transmission to data bus 156. Input / output gating circuit 154 is electrically connected to output buffer 155 and sense amplifier 153 and is used to control the input and output paths of data, ensuring that data is transmitted at the correct time. In this embodiment, input / output gating circuit 154 opens the output path, and sense amplifier 153 transmits the read data to output buffer 155 through input / output gating circuit 154. Input / output gating circuit 154 controls the timing of data output based on timing signals. During non-operation, the gating circuit closes the input / output path to prevent data conflicts and interference. The output buffer 155 is electrically connected to the data bus 156 and the input / output gating circuit 154, and reads data to the data bus 156 to ensure that the signal can be reliably transmitted to the control module. During the read operation, the output buffer 155 receives data from the sense amplifier 153, buffers and drives the data, and enhances the strength and stability of the signal. In this embodiment, the output buffer 155 sends the data to the data bus 156 according to the timing requirements. In this embodiment, the channel between the output buffer 155 and the input / output gating circuit 154 is a 32-bit channel, and the connection channel between the output buffer 155 and the data bus 156 is a 16-bit channel. In the present invention, the output buffer 155 can output data on the rising edge and / or the falling edge of the clock.

[0038] See also Figure 1As shown, in one embodiment of the present invention, a data strobe transmitter 157 is electrically connected to the output buffer 155 and generates and transmits a DQS signal during a write operation to synchronize the transmission of write data. The DQS signal is a clock signal synchronized with the data signal. The edges of the DQS signal, including rising and falling edges, indicate the valid window for data. The control module samples the write data based on the DQS signal. During a write operation, the data strobe transmitter 157 generates the DQS signal according to the timing requirements of the control module. The data strobe transmitter 157 ensures that the DQS signal is aligned with the timing of the write data. A data strobe receiver 158 is electrically connected to the data strobe transmitter 157 and receives and processes the DQS signal during a read operation to synchronize the sampling of read data. In this embodiment, during a read operation, the data strobe transmitter 157 generates the DQS signal and transmits it to the control module. The data strobe receiver 158 receives the DQS signal and samples the read data using the rising and falling edges of the signal. The center alignment feature of the DQS signal ensures that data is sampled within a stable window. The data strobe receiver 158 may also include a calibration circuit to calibrate the phase of the DQS signal.

[0039] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the memory chip 100 is formed on a wafer, and the memory chip 100 includes a substrate, wherein the memory 110, the read-write circuit, the input-output control module and the control module can be arranged on the same substrate and packaged into a chip as a whole.

[0040] The present invention provides a universal non-volatile memory chip and electronic device providing an LPDDR interface. The chip includes a control module, a memory, and an interface module. The control module is electrically connected to a host computer and controls the storage behavior of the memory chip. The memory supports row and column addressing and random access, and provides parallel data, allowing the control module to call firmware from the memory and control the instant system startup of the memory chip. The interface module is electrically connected between the memory and the control module. In the storage cells of the memory, the source electrode or the drain electrode of the storage cell is in a floating state. The present invention provides a universal non-volatile memory chip and electronic device providing an LPDDR interface, which can retain data content without requiring a refresh, thereby reducing chip power consumption. The memory chip provided by the present invention can operate at a voltage of 1.0V and can continue to shrink in size in accordance with Moore's Law without gate breakdown due to current. Furthermore, the memory chip and electronic device provided by the present invention can start up instantly after the system starts up, reducing the system startup delay and significantly improving the efficiency of system calls.

[0041] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A universal non-volatile memory chip providing an LPDDR interface, characterized in that: include: A control module is electrically connected to the host computer and controls the storage behavior of the storage chip; a memory, the memory supporting row and column addressing and random access, and the memory providing parallel data, wherein the control module is allowed to call firmware in the memory and control the instant startup of the system of the memory chip; as well as An interface module, electrically connected between the memory and the control module, wherein the interface module supports the LPDDR protocol and allows the voltage of the interface module to reach 1V; In the memory cell of the memory, a source electrode or a drain electrode of the memory cell is in a floating state.

2. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: The memory chip is electrically connected to an external power supply device, and the external power supply device provides an external power supply voltage for the memory.

3. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: The memory chip includes an internal power supply module, which is electrically connected to the memory cell of the memory and supplies power to a non-floating electrode in the memory cell, wherein the internal power supply voltage of the memory includes 1V.

4. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: In the memory chip, the interface module is electrically connected to the memory through a plurality of pins and wiring harnesses, wherein the refresh pins of the memory are floating, or the number of the refresh pins of the memory is set to zero.

5. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: The memory stores pre-installed firmware, and when the memory chip is powered on again, the control module calls and executes the pre-installed firmware in the memory.

6. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: The memory chip includes a read-write circuit, which is electrically connected to the control module and the memory, wherein the output channels of the read-write circuit include 32 channels and 16 channels, and the output channels output data on the rising edge and / or falling edge of the clock.

7. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: The storage behavior includes reading out user data, writing user data, erasing user data, adjusting the working mode of the storage chip, and calling the firmware in the memory after power-on.

8. The universal non-volatile memory chip providing an LPDDR interface according to claim 7, characterized in that: The memory chip includes a substrate, allowing the memory, the read / write circuit, and the control module to be arranged on the same substrate.

9. The universal non-volatile memory chip providing an LPDDR interface according to claim 1, wherein: The memory is a NOR flash memory.

10. An electronic device, characterized in that: The invention comprises a universal non-volatile memory chip providing an LPDDR interface as claimed in any one of claims 1 to 9, and the system starts immediately when the electronic device is started.

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