Flash memory decoding system and method based on low-density parity check
By combining the flexible switching of bit flip and weighted bit flip modules in the flash decoding system, the problems of high power consumption and low efficiency in the flash decoding process are solved, and the power consumption and time are reduced when errors occur.
Patent Information
- Application Number
- CN202410265463.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-09-09
AI Technical Summary
In the prior art, the flash memory decoding process consumes high power and has low efficiency, especially when reading the flash memory multiple times with relatively few errors causes delay and waste of power.
A flash memory decoding system based on low-density parity check is adopted, combined with a bit flip module and a weighted bit flip module, and flexibly switched through a controller to reduce power consumption and improve decoding efficiency.
The decoding power consumption is reduced when data errors occur, and the decoding time is reduced when the data error rate is low, thereby improving the decoding efficiency.
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Figure CN120614010A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data storage, and in particular to a flash memory decoding system and method based on low-density parity check. Background Art
[0002] Flash memory is a non-volatile storage technology widely used in mobile devices, solid-state drives (SSDs), and other electronic devices. It is known for its fast read and write speeds, durability, and low energy consumption. As data storage needs grow and technology advances, flash memory density continues to increase, but this also brings challenges to data reliability, especially in multi-level cell (MLC) and triple-level cell (TLC) flash memory.
[0003] To maintain data reliability and improve storage efficiency, efficient error correction coding technology is required. Low-density parity-check (LDPC) codes are widely used in flash memory due to their efficient error correction capabilities. Due to the flash memory's usage environment, the decoding algorithms used in flash memory are generally hard decoding. These include the bit flipping (BF) algorithm, the weighted bit flipping (WBF) algorithm, and other improved algorithms based on the WBF algorithm.
[0004] In existing technologies, when decoding using the BF algorithm or weighted bit flipping alone, the threshold voltage is adjusted multiple times to read the flash memory to obtain soft information about the bits—that is, the confidence level of each bit. However, multiple flash memory reads introduce additional delays, which wastes decoding time and power consumption even when errors are minor.
[0005] Therefore, there is an urgent need to provide a more reliable low-density parity check (LDPC)-based flash memory decoding solution. Summary of the Invention
[0006] The object of the present invention is to provide a flash memory decoding system and method based on low-density parity check (LDPC) to solve the problems of high decoding power consumption and low decoding efficiency in the prior art when data errors occur.
[0007] In order to achieve the above object, the present invention provides the following technical solutions:
[0008] In a first aspect, the present invention provides a flash memory decoding system based on low-density parity check, the system comprising at least:
[0009] Variable and verification module, confidence acquisition module, flip function operation module and controller; the flip function operation module includes a bit flip module and a weighted bit flip module;
[0010] The controller is used to control the startup of the variable and verification module and obtain the verification results of the variable and verification module; the controller is also used to control the switching between the bit flip module and the weighted bit flip module;
[0011] The confidence acquisition module is used to read data confidence from the flash memory; the flip function operation module receives the verification information of the variable and verification module; the variable and verification module iterates based on the information to be flipped given by the flip function operation module and outputs a decoding result.
[0012] Compared with the prior art, the present invention provides a flash memory decoding system and method based on low-density parity check, the system including a variable and check module, a confidence acquisition module, a flip function operation module and a controller; the flip function operation module includes a bit flip module and a weighted bit flip module; the controller is used to control the startup of the variable and check module and obtain the verification results of the variable and check module; it is also used to control the switching between the bit flip module and the weighted bit flip module; the confidence acquisition module is used to read data confidence from the flash memory; the flip function operation module receives the verification information of the variable and check module; the variable and check module iterates based on the information to be flipped provided by the flip function operation module, and outputs the decoding result. In the present invention, a bit flip module and a weighted bit flip module are provided at the same time, and a controller is used to flexibly control the switching between the bit flip module and the weighted bit flip module in combination with other information. When a data error occurs, the bit flip module and the weighted bit flip module are flexibly switched, and the variable and verification module iterates the information to be flipped provided by the bit flip module or the weighted bit flip module to complete the verification. Therefore, the decoding power consumption can be reduced when a data error occurs, and the decoding time can be reduced when the data error rate is low, thereby improving the decoding efficiency.
[0013] In a second aspect, the present invention provides a flash memory decoding method based on low-density parity check, the method being applied to a flash memory decoding system based on low-density parity check; the method comprising:
[0014] Reading data from the flash memory based on a flash memory read signal and initializing variable node data;
[0015] Verify the initialized variable node data. If the verification is correct, output the current variable node data.
[0016] If the verification is wrong, the decoding phase begins, and the confidence acquisition module and the bit flipping module are started to obtain the data confidence and the information to be flipped;
[0017] The controller controls the switching between the bit flip module and the weighted bit flip module according to the verification result, and obtains the to-be-flipped information provided by the bit flip module or the weighted bit flip module;
[0018] Before completing the confidence acquisition, the variable and verification module iterates through the information to be flipped provided by the bit flipping module or the weighted bit flipping module until the preset conditions are met and the decoding is completed.
[0019] The technical effects achieved by the method-type solutions provided in the second aspect are the same as those achieved by the system-type solutions provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0021] Figure 1 A schematic structural diagram of a low-density parity check (LDPC)-based flash memory 5 decoding system provided by the present invention;
[0022] Figure 2 A schematic flow chart of a flash memory 5 decoding method based on low-density parity check provided by the present invention;
[0023] Figure 3 This is a flow chart of switching between the BF module and the WBF module provided by the present invention.
[0024] Reference numerals
[0025] 1-Variable and verification module, 2-Confidence acquisition module, 3-Flip function operation module, 4-Controller, 5-Flash memory. DETAILED DESCRIPTION
[0026] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.
[0027] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0028] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.
[0029] Low-density parity-check (LDPC) codes are widely used in flash memory due to their efficient error correction capabilities. The bit-flipping algorithm is simple and easy to implement in hardware, making it suitable for fast decoding. In applications, weighted bit-flipping (WBF) algorithms or improved algorithms based on weighted bit-flipping (BF algorithms that consider soft information will be collectively referred to as WBF algorithms) are used to improve decoding performance. To obtain the soft information (i.e., the confidence level of each bit) of these bits, the threshold voltage is adjusted multiple times to read the flash memory. However, multiple reads of the flash memory incur additional latency, which can waste decoding time and power consumption even when errors are minor.
[0030] To address the problems in the prior art, the present invention proposes an LDPC decoding method for flash memory. Compared to the traditional decoding module based on the WBF algorithm, this method uses both BF and WBF algorithm operation modules and flexibly switches them through the controller 4. This reduces decoding power consumption when data errors occur, and reduces decoding time when the data error rate is low. Next, the solution provided by the embodiments of this specification is described in conjunction with the accompanying drawings:
[0031] Example 1
[0032] In this embodiment, a flash memory decoding system based on low density parity check is provided. Figure 1 As shown, the system may include at least:
[0033] Variable and verification module 1, confidence acquisition module 2, flip function operation module 3 and controller 4; the flip function operation module 3 includes a bit flip module and a weighted bit flip module;
[0034] The controller 4 is used to control the startup of the variable and verification module 1 and obtain the verification results of the variable and verification module 1; the controller 4 is also used to control the switching between the bit flip module and the weighted bit flip module;
[0035] The confidence acquisition module 2 is used to read data confidence from the flash memory 5; the flip function operation module 3 receives the verification information of the variable and verification module 1; the variable and verification module 1 iterates based on the information to be flipped given by the flip function operation module 3 and outputs the decoding result.
[0036] More specifically, the variable and verification module 1 may include variable nodes and verification nodes; the variable and verification module 1 may obtain initial data from the flash memory 5; the flip function operation module 3 includes a BF module or a WBF module, and there is information interaction between the flip function operation module 3 and the variable and verification module 1. The variable and verification module 1 sends verification information to the flip function operation module 3, feeds back the verification result to the controller 4, and outputs the decoding result; the controller 4 controls the variable and verification module 1 to start, and controls the flip function operation module 3 to switch states.
[0037] Figure 1 In the structure, the system includes a variable and verification module 1, a confidence acquisition module 2, a flip function operation module 3 and a controller 4; the flip function operation module 3 includes a bit flip module and a weighted bit flip module; the controller 4 is used to control the startup of the variable and verification module 1 and obtain the verification results of the variable and verification module 1; it is also used to control the switching between the bit flip module and the weighted bit flip module; the confidence acquisition module is used to read data confidence from the flash memory 5; the flip function operation module 3 receives the verification information of the variable and verification module 1; the variable and verification module 1 iterates based on the information to be flipped given by the flip function operation module 3, and outputs the decoding result. In the present invention, a bit flip module and a weighted bit flip module are provided at the same time, and a controller 4 is used to flexibly control the switching between the bit flip module and the weighted bit flip module in combination with other information. When an error occurs in the data, the bit flip module and the weighted bit flip module are flexibly switched, and the variable and verification module 1 iterates the information to be flipped given by the bit flip module or the weighted bit flip module to complete the verification; therefore, the decoding power consumption can be reduced when an error occurs in the data, and the decoding time can be reduced when the data error rate is low, thereby improving the decoding efficiency.
[0038] based on Figure 1The present specification also provides some specific implementations of the system, which will be described below.
[0039] As an optional implementation, a counter is configured in the controller 4 .
[0040] The counter is used to record the number of times that the weighted bit flip module operation is not entered during the reading process, or the number of times that the weighted bit flip module operation is entered during the reading process;
[0041] If the weighted bit flip module operation is not entered for multiple consecutive readings and the number of times reaches a limit, the controller 4 turns off the weighted bit flip module and the confidence acquisition module 2;
[0042] If the data is read multiple times in succession and the number of times reaches a limit, the controller 4 only turns on the confidence acquisition module 2 when an error occurs in the data.
[0043] When entering the decoding stage, the confidence acquisition module 2 and the bit flipping module are started at the same time; before completing the confidence reading, the variable and verification module 1 iterates through the information to be flipped given by the bit flipping module.
[0044] In the low-density parity check-based flash memory 5 decoding system of Example 1, when performing a decoding operation, the corresponding method steps are as described in Example 2, and are described in detail below:
[0045] Example 2
[0046] like Figure 2 As shown, the present invention provides a flash memory decoding method based on low-density parity check. The implementation process may include the following steps:
[0047] Step 210: Read data from the flash memory based on the flash memory read signal and initialize variable node data.
[0048] Flash memory is an electrically erasable programmable read-only memory (EEPROM) that has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, and small size.
[0049] Step 220: Verify the initialized variable node data. If the verification is correct, output the current variable node data.
[0050] When the verification is correct, the current variable node data can be directly output. When the verification is wrong, decoding is required.
[0051] Step 230: If the verification is wrong, the decoding phase is entered, and the confidence acquisition module and the bit flipping module are started to obtain the data confidence and the information to be flipped.
[0052] During decoding, the confidence acquisition module and the bit flipping module are started simultaneously. The confidence acquisition module completes the confidence reading, and the bit flipping module determines the information to be flipped.
[0053] Step 240: The controller controls the switching between the bit flipping module and the weighted bit flipping module according to the verification result, and obtains the to-be-flipped information provided by the bit flipping module or the weighted bit flipping module.
[0054] The BF and WBF algorithm operation modules are used at the same time, and are flexibly switched through the controller.
[0055] Step 250: Before completing the confidence acquisition, the variable and verification module iterates the information to be flipped provided by the bit flipping module or the weighted bit flipping module until the preset conditions are met and the decoding is completed.
[0056] based on Figure 2 The present specification also provides some specific implementation methods of the method, which are described below.
[0057] Optionally, a counter is configured in the controller; the counter is used to record the number of times that the weighted bit flip module operation is not entered during the reading process, or the number of times that the weighted bit flip module operation is entered during the reading process;
[0058] The controller controls the switching between the bit flip module and the weighted bit flip module according to the verification result, which may specifically include:
[0059] If the weighted bit flip module operation is not entered for multiple consecutive readings and the number of times reaches a limit, the controller turns off the weighted bit flip module and the confidence acquisition module;
[0060] If the data is read multiple times in succession and the number of times of entering the weighted bit flip module operation reaches a limit value, the controller only turns on the confidence acquisition module when an error occurs in the data.
[0061] Optionally, the controller controls switching between the bit flipping module and the weighted bit flipping module according to the verification result, and obtains the to-be-flipped information provided by the bit flipping module or the weighted bit flipping module, which may specifically include:
[0062] If the verification result is still wrong after the confidence level is obtained, the weighted bit flip module is started, the variable node is reinitialized, and the bit flip module is stopped at the same time;
[0063] The variable and verification module iterates through the information to be flipped provided by the weighted bit flipping module; if the verification is correct, the variable stage data is output and the circuit state is initialized to wait for the next reading;
[0064] During the iteration process, if the flip function values corresponding to all variable nodes are lower than the preset minimum flip threshold, the bit flip module is switched back to continue to complete the subsequent flip iterations.
[0065] Optionally, after switching from the weighted bit flipping module to the bit flipping module, the current decoding will not switch back to the weighted bit flipping module.
[0066] Optionally, the value of the minimum flip threshold is determined according to the used check matrix, the specific weighted bit flip decoding algorithm, the flip function and the current health status of the flash memory data;
[0067] After determining the check matrix and the flip function, the initial minimum flip threshold is determined by simulating and analyzing an iterative process based on weighted bit flipping;
[0068] The value of the minimum flip threshold satisfies: when all flip function values are less than the minimum flip threshold, the number of remaining error bits needs to be less than N; when the number of error bits is less than N, the bit error rate of bit flip decoding is less than 1%; the more bits with low confidence, the smaller the minimum flip threshold, where N is a positive integer greater than 1.
[0069] The overall decoding process may include:
[0070] When receiving the flash memory read signal, read the data from the flash memory and initialize the variable node data.
[0071] The check node checks the data row. If the check is correct (correct when the check node is all 0), the current variable node data is output, otherwise it enters decoding.
[0072] After entering the decoding phase, the confidence acquisition module and the BF module are simultaneously activated. Before completing the confidence reading, the variable and verification module iterates using the pending flip information provided by the BF module. If the verification is correct during this period, the variable stage data is output and the circuit state is initialized to wait for the next reading.
[0073] If the verification result is still wrong after the confidence level is obtained, the WBF module is started, the variable nodes are reinitialized, and the BF module is stopped. In this stage, the variable and verification modules iterate based on the information to be flipped given by the WBF module. During this period, if the verification is correct, the variable stage data is output and the circuit state is initialized to wait for the next reading. During the iteration process, if the flip function values E corresponding to all variable nodes are lower than the preset minimum flip threshold μL When , it indicates that the number of remaining error bits is small. It then switches back to the BF module and continues with the subsequent flipping iterations. After switching from the WBF module to the BF module, the decoding will not switch back to the WBF module.
[0074] The lowest flip threshold μ in the above process L The value of μ depends on the H parity check matrix used, the specific WBF module decoding algorithm and its flip function, and the current flash memory data health status. L After determining the H matrix and the flip function, the value is determined through simulation analysis based on the iterative process of the WBF module. L The value of needs to satisfy: all flip function values are less than μ L When the number of error bits is less than N, the number of remaining error bits must be less than N. N satisfies: when the number of error bits is less than N, the bit error rate of BF module decoding must be less than 1%; in addition, μ L As the overall reliability of the data changes, the more bits with low confidence, the larger μ L It should be smaller.
[0075] Specifically, when switching between BF module and WBF module, the process can be combined with Figure 3 To explain:
[0076] When starting to decode, first perform a check, and output the result if the check is correct;
[0077] If the check error occurs, it is further determined whether the soft information has been obtained. If the soft information has been obtained, the remaining error amount is estimated based on the flip value and all (E n ) is less than μ L If so, switch to BF module for calculation; if all(E n ) is not less than μ L , then switch to the WBF module operation, perform bit flipping according to the to-be-flipped information provided by the bit flipping module or the weighted bit flipping module, update the variable information iterative operation, and cyclically check until the conditions are met and the decoding is completed.
[0078] Optionally, after a check node detects a data error, confidence acquisition and BF decoding are performed in parallel. If BF decoding fails, WBF decoding is switched to BF decoding. This achieves both the fast decoding speed of BF decoding and the high performance of WBF decoding.
[0079] At the end of the WBF decoding phase, the decoding module switches to the BF decoding module. This means that when a large number of bit errors occur, WBF decoding corrects most of them, while the remaining minor errors are handled by the BF decoding module. Replacing WBF decoding with BF decoding helps reduce power consumption during the decoding process without compromising overall decoding performance.
[0080] If the reading process repeatedly enters the WBF module for decoding, it indicates poor overall data reliability. In this case, running the BF module in parallel with the confidence reading process is meaningless; disabling the BF module can help reduce power consumption. Similarly, if the reading process repeatedly fails to enter the WBF module for decoding, it indicates good overall data reliability. In this case, BF decoding meets requirements, and disabling the WBF module and the confidence acquisition module can help reduce power consumption.
[0081] Compared to traditional decoding modules based on the WBF algorithm, this method uses both BF and WBF algorithm modules and flexibly switches them through a controller. This reduces decoding power consumption when data errors occur and reduces decoding time when the data error rate is low.
[0082] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0083] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.
Claims
1. A flash memory decoding system based on low-density parity check, characterized in that: The system shall at least include: Variable and verification module, confidence acquisition module, flip function operation module and controller; the flip function operation module includes a bit flip module and a weighted bit flip module; The controller is used to control the startup of the variable and verification module and obtain the verification results of the variable and verification module; the controller is also used to control the switching between the bit flip module and the weighted bit flip module; The confidence acquisition module is used to read data confidence from the flash memory; the flip function operation module receives the verification information of the variable and verification module; the variable and verification module iterates based on the information to be flipped given by the flip function operation module and outputs a decoding result.
2. The low-density parity check (LDPC)-based flash memory decoding system according to claim 1, wherein: If the verification result is still wrong after the confidence level is obtained, the weighted bit flipping module is started, the variable node is reinitialized, and the bit flipping module is stopped at the same time; The variable and verification module iterates based on the information to be flipped provided by the weighted bit flipping module, outputs the variable phase data if the verification is correct, and initializes the circuit state to wait for the next reading.
3. The low-density parity check (LDPC)-based flash memory decoding system according to claim 2, wherein: During the iteration process, if the flip function values corresponding to all variable nodes are lower than the preset minimum flip threshold, the bit flip module is switched back to continue to complete the subsequent flip iterations.
4. The low-density parity check (LDPC)-based flash memory decoding system according to claim 1, wherein: A counter is configured in the controller; The counter is used to record the number of times that the weighted bit flip module operation is not entered during the reading process, or the number of times that the weighted bit flip module operation is entered during the reading process; If the weighted bit flip module operation is not entered for multiple consecutive readings and the number of times reaches a limit, the controller turns off the weighted bit flip module and the confidence acquisition module; If the data is read multiple times in succession and the number of times of entering the weighted bit flip module operation reaches a limit value, the controller only turns on the confidence acquisition module when an error occurs in the data.
5. The low-density parity check (LDPC)-based flash memory decoding system according to claim 1, wherein: When entering the decoding stage, the confidence acquisition module and the bit flipping module are started simultaneously; Before completing the confidence reading, the variable and verification module iterates through the information to be flipped provided by the bit flipping module.
6. A flash memory decoding method based on low-density parity check, characterized in that: The method is applied to a flash memory decoding system based on low-density parity check; the method comprises: Reading data from the flash memory based on a flash memory read signal and initializing variable node data; Verify the initialized variable node data. If the verification is correct, output the current variable node data. If the verification is wrong, the decoding phase begins, and the confidence acquisition module and the bit flipping module are started to obtain the data confidence and the information to be flipped; The controller controls the switching between the bit flip module and the weighted bit flip module according to the verification result, and obtains the to-be-flipped information provided by the bit flip module or the weighted bit flip module; Before completing the confidence acquisition, the variable and verification module iterates through the information to be flipped provided by the bit flipping module or the weighted bit flipping module until the preset conditions are met and the decoding is completed.
7. The flash memory decoding method based on low-density parity check according to claim 6, characterized in that: The controller controls the switching between the bit flip module and the weighted bit flip module according to the verification result, and obtains the to-be-flipped information provided by the bit flip module or the weighted bit flip module, specifically including: If the verification result is still wrong after the confidence level is obtained, the weighted bit flip module is started, the variable node is reinitialized, and the bit flip module is stopped at the same time; The variable and verification module iterates through the information to be flipped provided by the weighted bit flipping module; if the verification is correct, the variable stage data is output and the circuit state is initialized to wait for the next reading; During the iteration process, if the flip function values corresponding to all variable nodes are lower than the preset minimum flip threshold, the bit flip module is switched back to continue to complete the subsequent flip iterations.
8. The flash memory decoding method based on low-density parity check according to claim 7, characterized in that: After switching from the weighted bit flipping module to the bit flipping module, the current decoding will not switch back to the weighted bit flipping module.
9. The flash memory decoding method based on low-density parity check according to claim 7, characterized in that: The value of the minimum flip threshold is determined based on the used check matrix, the specific weighted bit flip decoding algorithm, the flip function and the current health status of the flash memory data; After determining the check matrix and the flip function, the initial minimum flip threshold is determined by simulating and analyzing an iterative process based on weighted bit flipping; The value of the minimum flip threshold satisfies: when all flip function values are less than the minimum flip threshold, the number of remaining error bits needs to be less than N; when the number of error bits is less than N, the bit error rate of bit flip decoding is less than 1%; the more bits with low confidence, the smaller the minimum flip threshold, where N is a positive integer greater than 1.
10. The flash memory decoding method based on low-density parity check according to claim 6, characterized in that: The controller is configured with a counter; the counter is used to record the number of times that the weighted bit flip module operation is not entered during the reading process, or the number of times that the weighted bit flip module operation is entered during the reading process; The controller controls the switching between the bit flip module and the weighted bit flip module according to the verification result, specifically including: If the weighted bit flip module operation is not entered for multiple consecutive readings and the number of times reaches a limit, the controller turns off the weighted bit flip module and the confidence acquisition module; If the data is read multiple times in succession and the number of times of entering the weighted bit flip module operation reaches a limit value, the controller only turns on the confidence acquisition module when an error occurs in the data.