Image sensor

Abstract

An image sensor includes a plurality of pixels arranged in a matrix. Each of the plurality of pixels includes a photodiode configured to operate in both a linear mode in which the photodiode displays a linear response to an amount of light incidence and a photovoltaic mode in which the photodiode displays a logarithmic response to the amount of light incidence; a pixel source follower transistor configured to output a signal voltage corresponding to a signal generated based on an output of the photodiode; a pixel switching transistor configured to turn on / off an output of the pixel source follower transistor; a holding capacitor connected to an output terminal of the pixel switching transistor and configured to hold a voltage corresponding to an output of the photodiode; and an output source follower circuit configured to output the voltage held by the holding capacitor as a signal voltage to the analog-to-digital converter.

Description

Technical Field

[0001] The present disclosure generally relates to a noise and distortion countermeasure for images captured in an image sensor that includes a photodiode. Background Art

[0002] The image sensor includes a photodiode in each of pixel circuits and detects an amount of charge generated based on light entering each of the photodiodes.

[0003] A photodiode has a logarithmic region, in which the photodiode operates with forward bias (at high brightness), and a linear region, in which the photodiode operates with reverse bias and partial forward bias (at low brightness). In the logarithmic region, the photodiode exhibits a logarithmic response to the amount of incident light, and this operating mode is called the photovoltaic mode. In the linear region, the photodiode exhibits a linear response to the amount of incident light, and this operating mode is called the linear mode.

[0004] Thermal noise known as kTC noise occurs in the linear region of photodiode operation at low brightness. KTC noise is caused by the switching of a reset transistor, which resets the accumulated charge of the photodiode. KTC noise is an offset shift in the photodiode's output voltage after a reset, which is not fixed in the direction of the shift. Consequently, kTC noise degrades the quality of reproduced images.

[0005] Furthermore, in a case where a moving object is imaged, when the exposure time shifts among lines, the image is distorted. Summary of the Invention

[0006] An image sensor according to the present disclosure includes a plurality of pixels arranged in a matrix, and includes an A / D converter, a frame memory, and a conversion function block. Each of the plurality of pixels includes: a photodiode configured to operate in both a linear mode and a photovoltaic mode, wherein the linear mode exhibits a linear response to the amount of incident light, and the photovoltaic mode exhibits a logarithmic response to the amount of incident light; a pixel source follower transistor configured to output a signal voltage corresponding to a signal generated based on the output of the photodiode; a pixel switching transistor configured to turn on / off the output of the pixel source follower transistor; a holding capacitor connected to the output of the pixel switching transistor and configured to hold a voltage corresponding to the output of the photodiode; and an output source follower circuit configured to output the voltage held by the holding capacitor as a signal voltage. The A / D converter converts the signal voltage output from the output source follower circuit of each of the plurality of pixels into digital signal data. The frame memory stores the digital signal data for one frame period. The conversion function block generates an optical signal related to the amount of incident light based on the current signal data and the signal data of the previous frame. The plurality of pixels arranged in a matrix turn on pixel switching transistors at the same timing and hold signal voltages in holding capacitors.

[0007] In the image sensor according to the present disclosure, it is not necessary to reset the photodiode. Therefore, noise mixing can be reduced. In addition, since the pixels are driven at the same timing, the occurrence of distortion in the imaging of moving objects can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments of the present disclosure will be explained based on the following figures, in which:

[0009] Figure 1 is a diagram showing a premise configuration of a pixel circuit according to the embodiment.

[0010] Figure 2 It shows that Figure 1 A timing diagram of the operation of the circuit in the premise configuration.

[0011] Figure 3 is a diagram showing an image sensor in which pixels each having a premise configuration are arranged in a two-dimensional manner.

[0012] Figure 4 It shows Figure 3 A timing diagram of the operation of the image sensor.

[0013] Figure 5 is a diagram showing a configuration of a pixel circuit according to an embodiment.

[0014] Figure 6 It shows Figure 5Timing diagram of the operation of the pixel circuit.

[0015] Figure 7 is a diagram showing a configuration of an image sensor according to an embodiment.

[0016] Figure 8 It shows Figure 7 A timing diagram of the operation of the image sensor.

[0017] Figure 9 is a diagram showing a configuration according to Modification 1.

[0018] Figure 10 is a diagram showing a configuration according to Modification 2.

[0019] Figure 11 is a timing chart showing the operation according to Modification 2.

[0020] Figure 12 : is a graph showing the relationship of the signal (output voltage) V2 with respect to the signal current Isig in the case where no negative pulse is applied.

[0021] Figure 13 : is a graph showing the relationship of the signal (output voltage) V2 with respect to the signal current Isig in the case where a negative pulse is applied.

[0022] Figure 14 dV2 / dIsig at the voltage V1 of 0 V and −0.7 V in the case where the negative pulse application period tmod is changed.

[0023] Figure 15 is a diagram showing a configuration according to Modification 3.

[0024] Figure 16 is a timing chart showing the operation according to Modification 3.

[0025] Figure 17 is a diagram showing a configuration according to Modification 4.

[0026] Figure 18 is a timing chart showing the operation according to Modification 4.

[0027] Figure 19 is a diagram showing a configuration according to Modification 5. DETAILED DESCRIPTION

[0028] The following describes embodiments of the present disclosure with reference to the accompanying drawings. The following embodiments do not limit the present disclosure, and configurations obtained by combining multiple examples in a selective manner are also included in the present disclosure.

[0029] Prerequisite circuit configuration

[0030] Figure 1 is a diagram showing a premise configuration of a pixel circuit according to the embodiment.

[0031] The sensor chip 10 includes a plurality of pixels 12 on a semiconductor substrate (eg, a silicon substrate). The sensor chip 10 includes the plurality of pixels 12 arranged in a matrix in horizontal and vertical directions. Figure 1 Only one pixel 12 is shown.

[0032] The pixel 12 includes a photodiode PD. The photodiode PD includes a PN junction and generates charges by incident light. The photodiode PD in this example generates electrons by incident light, and as the amount of incident light increases, the output voltage Vpd increases to the negative side.

[0033] Furthermore, the photodiode PD has two modes: a linear mode and a photovoltaic mode. In the linear mode, the photodiode PD exhibits a linear response to the amount of incident light under reverse bias and forward bias. In the photovoltaic mode, the photodiode PD exhibits a logarithmic response to the amount of incident light under forward bias. When the amount of incident light is small, the photodiode PD operates in the linear mode, whereas when the amount of incident light is large, the photodiode PD operates in the photovoltaic mode.

[0034] The source follower circuit 144 is connected to the output terminal of the photodiode PD and includes a source follower transistor SF configured by an n-channel metal-oxide-semiconductor field effect transistor (MOSFET) and a row selection transistor SEL configured by an n-channel MOSFET.

[0035] The output terminal of the photodiode PD is connected to the gate of a source follower transistor SF. The drain of the source follower transistor SF is connected to a predetermined power supply, and the source is connected to the drain of the row select transistor SEL. The source of the row select transistor SEL is connected to the output line 16. A row select line connected to a vertical scanning circuit described below is connected to the gate of the row select transistor SEL.

[0036] Therefore, when the row selection line becomes a high level (H level), the row selection transistor SEL is turned on, and a voltage corresponding to the gate voltage of the source follower transistor SF is output to the output line 16. The output of the photodiode PD is supplied to the gate of the source follower transistor SF, and a signal (signal voltage) corresponding to the output voltage of the photodiode PD is output to the output line 16. In other words, a signal related to the amount of light incident on the photodiode PD is output to the output line 16. The output line 16 is provided corresponding to each column, and the sources of the row selection transistors SEL of the plurality of pixels 12 arranged in the vertical direction are connected to one output line 16.

[0037] One end of the load capacitor CL is connected to the output line 16. The other end of the load capacitor CL is connected to a predetermined power supply (e.g., ground). The output line 16 is a line that is long in the vertical direction (column direction), and the parasitic capacitance generated in the output line 16 is relatively large. Therefore, the parasitic capacitance can be used as the load capacitor CL.

[0038] The output line 16 is connected to an analog to digital (AD) converter (ADC) 20. Therefore, the signal voltages of the plurality of pixels 12 in the row selected by the row selection line are supplied to the AD converter 20.

[0039] The AD converter 20 converts the supplied analog signal voltage into digital signal data. The obtained signal data is supplied to both the frame memory 22 and the conversion function block 24. The frame memory 22 stores the signal data of one frame. When the data of the current frame is input to the frame memory 22, the signal data of the previous frame is output from the frame memory 22. The output end of the frame memory 22 is connected to the conversion function block 24, and the signal data of the previous frame is supplied to the conversion function block 24. Note that the frame is represented by Fr as appropriate.

[0040] The current signal V2 (of the current frame) and the signal V1 of the previous frame (the last frame) are supplied to a conversion function block 24. This conversion function block 24 includes a Lambert W function and outputs an optical signal for each pixel in the current frame based on the two input data. In other words, the conversion function block 24 removes the influence of the last signal V1 from the current signal V2 to obtain an optical signal corresponding to the amount of light incident on the current frame.

[0041] In the disclosed embodiment, a reset circuit for resetting the output of the photodiode PD to a predetermined voltage is not provided. Therefore, at the start of a frame, the photodiode PD retains the accumulated charge of the last frame. The conversion function block 24 obtains an optical signal corresponding to the incident light intensity of the current frame based on the signal V2 of the current frame and the signal data of the last frame. In this case, the conversion cannot be calculated using elementary functions. Instead, the Lambert W function can be used.

[0042] The Lambert W function is an inverse function of a linear variable x and an exponential function ex. In other words, the Lambert W function is a general term of the function W obtained as a branch of the inverse relationship of the function f(z) = zez, where ez is an exponential function, z is an optional complex number, and W satisfies z = f-1(zez) = W(zez).

[0043] The photodiode PD includes a linear region and a logarithmic region. Therefore, the expression for obtaining the signal current Isig corresponding to the two inputs of the signals V1 and V2 can be determined by applying the Lambert W function. The Lambert W function is a commonly used function included in the built-in functions of the spreadsheet software (Microsoft Excel®) available from Microsoft Corporation and can be used as appropriate.

[0044] Furthermore, based on various experiments, simulations, and the like, a table can be created in advance to determine the solution for the optical signal Isig based on two inputs (signal V1 and signal V2). Thus, the optical signal can be obtained by referring to this table. Furthermore, an approximate expression can be registered, and the calculation result can be output.

[0045] Figure 2 It shows Figure 1 1 is a timing diagram of the operation of the circuit in FIG. When the row select transistors SEL of the pixels 12 in one row (one horizontal row) are turned on, a signal corresponding to the output of the photodiode PD of the corresponding row is read out to the output line 16. The readout signal is supplied to the AD converter (ADC) 20 and AD converted, and the signal V2 of the current frame of the pixels 12 on one horizontal row is output. The signal V2 is supplied to the frame memory 22 and the conversion function block 24. In addition, a signal related to the light incident amount of the current frame (the signal of one horizontal row) is output from the conversion function block 24. An image signal of one frame can be obtained by repeating this operation for each horizontal row during one frame period.

[0046] In the above Figure 1 In the pixel circuit in FIG, a reset transistor for supplying a predetermined reset voltage to the output terminal of the photodiode PD to reset the accumulated charge of the photodiode PD is not provided. This makes it possible to reduce the charge-voltage conversion capacitance C at the output terminal of the photodiode PD.

[0047] In existing image sensors using a photodiode PD, a transfer gate is often provided at the output terminal of the photodiode PD. Figure 1 In the configuration in which no transfer gate is provided, the charge-voltage conversion capacitance C is reduced to approximately 1 / 2 compared to that of existing image sensors.

[0048] As described above, since the charge-voltage conversion capacitance C can be reduced in the above-mentioned premise configuration, the sensitivity of the pixel circuit can be improved to about 1.4 times to about 2 times compared with the existing pixel circuit.

[0049] Configuring the image sensor through prerequisite configuration

[0050] Figure 3 is a diagram showing an image sensor 100 in which pixels each have a predefined configuration and are arranged in a two-dimensional manner. A pixel array 110 includes pixels 12 arranged in m columns and n rows (m*n) as described above, i.e., includes m pixels in the horizontal direction and n pixels in the vertical direction. A vertical scanning circuit (V-scan) 112 sequentially selects rows of pixels 12 in the vertical direction. The pixels in each column are connected to an AD converter (ADC) 20 via a readout line in the vertical direction. A horizontal scanning circuit (H-scan) 114 is connected to the ADC 20, and image signals of the corresponding pixels are sequentially output from the horizontal scanning circuit (H-scan) 114.

[0051] Figure 4 is a timing chart illustrating the operation of the image sensor 100 .

[0052] In the (k-1)th row, the row selection transistor SEL is turned on, and the signal obtained during one vertical period (1Fr) in the photodiode PD is supplied to the ADC 20. Thereafter, the exposure of the next 1V begins. The readout signal is supplied to the ADC 20, and the readout signal is converted into a digital signal V2. The above operation is performed simultaneously on the m pixels on one horizontal row. Thereafter, the horizontal scanning circuit (H-scan) 114 sequentially supplies the digital signals of the m pixels to the frame memory 22 and the conversion function block 24. The signal V1 of the previous frame is read out from the frame memory 22, and the signal V1 is supplied to the conversion function block 24. The conversion function block 24 determines the signal current Isig based on the supplied signal V1 and signal V2, and outputs the determined signal current Isig. The signal current Isig is determined by the conversion function block 24 based on the digital signal V2 and signal V1 stored in the frame memory 22 1Fr ago. Signal processing is performed on the m pixels.

[0053] Global shutter

[0054] In the above Figure 1 and Figure 3In the case of a configuration such as the one in FIG, when pixels are arranged two-dimensionally, a rolling shutter operation is implemented in which the accumulation time is shifted between rows. In other words, the accumulation time for one row and the accumulation time for the next row are shifted by one horizontal period. Therefore, a problem with the rolling shutter operation is that when imaging a moving object, the reproduced image is distorted.

[0055] Figure 5 is a diagram showing the configuration of a pixel circuit according to an embodiment. Figure 1 The pixel configuration in FIG is obtained by adding a pixel source follower transistor SFd, a load transistor Load, a transfer transistor Tran, and a transfer capacitor Cgl. The pixel source follower transistor SFd, the load transistor Load, and the transfer transistor Tran are all n-channel field effect transistors (FETs).

[0056] More specifically, the output terminal of the photodiode PD is connected to the gate of the pixel source follower transistor SFd. The drain of the pixel source follower transistor SFd is connected to the power supply, and the source is connected to the power supply (e.g., ground) via the load transistor Load. The drain of the transfer transistor Tran is connected to the source of the pixel source follower transistor SFd, and the source of the transfer transistor Tran is connected to one end of the transfer capacitor Cgl and the gate of the source follower transistor SF. The other end of the transfer capacitor Cgl is connected to the power supply (e.g., ground).

[0057] The drain of the source follower transistor SF is connected to the power supply, the source is connected to the drain of the row selection transistor SEL, and the source of the row selection transistor SEL is connected to the output line 16. The configuration of the source follower transistor SF and the row selection transistor SEL is the same as Figure 1 The configuration of the circuit in.

[0058] Figure 6 It shows Figure 5 1 is a timing diagram of the operation of the circuit in FIG. When the accumulation period of one frame ends, the transfer transistor Tran is turned on, and the output signal of the photodiode PD is transferred to and accumulated in the transfer capacitor Cgl. Thereafter, the transfer transistor Tran is turned off, and the row select transistor SEL is turned on to read the signal out of the pixel via the source follower transistor SF.

[0059] Image sensor configuration

[0060] Figure 7 1 is a diagram showing the configuration of the image sensor 100 according to the embodiment. As shown in the figure, the basic configuration is the same as Figure 3In the configuration of FIG, however, in addition to the pixel array 110, the vertical scanning circuit (V-scan) 112, the AD converter (ADC) 20, and the horizontal scanning circuit (H-scan) 114, the image sensor 100 further includes a global shutter control unit (GS-control) 218. The global shutter control unit (GS-control) 218 ​​controls the turn-on timing of the transfer transistor Tran.

[0061] Figure 8 It shows Figure 7 1 is a timing diagram of the operation of the image sensor in FIG. As shown in the figure, at the end of the accumulation period of the (n-1)th frame, the transfer transistors Tran of the pixels (all pixels) 12 on all horizontal rows are turned on at the same timing. Therefore, the signals at the same timing are held in the transfer capacitors Cgl of all pixels. Thereafter, the transfer transistors Tran of the pixels (all pixels) 12 on all horizontal rows are turned off at the same timing.

[0062] Next, during the accumulation period of the nth frame, the vertical scanning circuit (V-scan) 112 sequentially operates to turn on the row select transistors SEL of the pixels 12 on one horizontal row, row by row. In other words, the following operation is repeated sequentially: in this operation, the row select transistors SEL of the pixels on the (k-1)th row are turned on, and then the row select transistors SEL of the pixels on the kth row are turned on at a timing delayed by 1H. Therefore, the signal of the (n-1)th frame is sequentially output during the signal accumulation period of the nth frame. Since the transfer transistors Tran of the pixels (all pixels) 12 on all horizontal rows are turned off during the nth Fr accumulation period, the signal of the (n-1)th frame is read out independently of the nth Fr signal.

[0063] In the above manner, in the image sensor 100 according to the embodiment of the present disclosure, the signal accumulation period of all pixels can be made the same, and image signals can be output while reading out horizontal lines sequentially shifted in the vertical direction in a conventional manner.

[0064] Even in this example, the reset transistor RST is not used in the pixel circuit, and noise caused by the reset transistor RST can be reduced.

[0065] In addition, the signal V2 of the current frame is supplied to the frame memory 22, and the signal V1 of the previous frame is output from the frame memory 22. The conversion function block 24 outputs a signal current (Isig) as an optical signal based on the signal V2 of the current frame and the signal V1 of the previous frame. The configuration of the conversion function block 24 is as described above.

[0066] Modified form 1

[0067] Figure 9 is a diagram showing a configuration according to Modification 1. Figure 5 In the pixel circuit according to the embodiment of the present disclosure shown in FIG, the reset transistor RST is omitted to achieve miniaturization of the pixel and signal integration of the global shutter. However, in the configuration described, Figure 1 Compared with the configuration in FIG. 1 , a pixel source follower transistor SFd, a load transistor Load, a transfer transistor Tran, and a transfer capacitor Cgl are added to the pixel. Therefore, the semiconductor chip on which the pixel 12 is mounted cannot be sufficiently miniaturized.

[0068] US9338381 discloses providing one pixel circuit on two chips in a divided manner.

[0069] Figure 9 is a diagram showing a configuration according to Modification 1. In Modification 1, the pixel source follower transistor SFd and the load transistor Load are arranged on the pixel chip 122, and the transfer transistor Tran, the transfer capacitor Cgl, the source follower transistor SF, the row select transistor SEL, and the AD converter (ADC) are arranged on the circuit chip 124. The lines from the pixel source follower transistor SFd and the transfer transistor Tran are connected by a pixel contact 126 provided on both chips.

[0070] Use of the configuration makes it possible to simplify the configuration of the pixel circuit on the pixel chip 122 and achieve miniaturization.

[0071] exist Figure 9 In the circuit shown in FIG, the dark current of each of the source of the pixel source follower transistor SFd, the drain of the load transistor Load, and the source of the transfer transistor Tran is much greater than the dark current of the photodiode PD. In order to suppress the influence of the dark current, it is effective to increase the current flowing through the pixel source follower transistor SFd.

[0072] When the sum of the dark currents of the source of the pixel source follower transistor SFd, the drain of the load transistor Load, and the source of the transfer transistor Tran is represented by Idrk, the equivalent dark current Ideq converted into the output of the photodiode PD is obtained as follows:

[0073] Ideq=Idrk 2 / Idd

[0074] Where Idd is the drain current of the pixel source follower transistor SFd. When assuming Idrk=1000 (1000: number of electrons)*q / s (q: elementary charge) and Ideq=1 (1: number of electrons)*q / s (target dark current=1 electron / s), Idd=about 0.16 pA is obtained.

[0075] Therefore, causing a drain current of 0.16 pA or more to flow through the pixel source follower transistor SFd makes it possible to ignore an increase in dark current caused by the addition of the pixel source follower transistor SFd.

[0076] Note that the influence of the dark current of the drain of the transfer transistor Tran can be suppressed by increasing the transfer capacitor Cgl.

[0077] Modified Form 2

[0078] Figure 10 is a diagram showing a configuration according to Modification 2. Figure 11 is a timing chart showing the operation according to Modification 2.

[0079] A negative pulse is applied to the drain voltage VD of the pixel source follower transistor SFd, and the output voltage of the photodiode PD is modulated by the drain-gate capacitance (gate capacitance) Cgd of the pixel source follower transistor SFd. In other words, a negative pulse is applied to the voltage VD during a predetermined application period tmod, which lowers the voltage. Normally, the voltage VD is 2.8V, and the voltage V1 is assumed to be between 0V and -0.7V, with the negative pulse set to -0.2V.

[0080] Figure 12 and Figure 13 Each of the graphs shows the relationship between the signal (output voltage) V2 and the signal current Isig. Figure 12 shows the case where no negative pulse is applied, and Figure 13 A case where a negative pulse is applied is shown. In this example, one frame period (1Fr) is set to 33ms, and the negative pulse application period tmod is set to 8ms.

[0081] When a negative pulse is applied to the voltage VD as described above, a negative pulse is applied to the output terminal of the photodiode PD via the capacitor Cgd of the pixel source follower transistor SFd, and the voltage at the output terminal of the photodiode PD decreases. Therefore, the photodiode PD is placed in a state similar to a state in which the accumulated charge is large.

[0082] Therefore, if Figure 13 As shown in FIG, in the region where the voltage V1 is greater than 0.2 V, the influence of the voltage V1 is reduced and the slope of V2 with respect to Isig is improved. This means that the signal response is improved in the V1 range exceeding 0.2 V.

[0083] Figure 14dV2 / dIsig at the voltage V1 of 0 V and -0.7 V is shown in the case where the negative pulse application period tmod is changed. When the negative pulse application period tmod is extended, dV2 / dIsig at the voltage V1 of 0 V deteriorates.

[0084] Therefore, it is found that in the case where one frame period is 33ms, a negative pulse application period tmod of about 3ms to about 8ms is appropriate. In other words, the negative pulse application period tmod is preferably set to a period shorter than half a frame period.

[0085] Modified form 3

[0086] Figure 15 is a diagram showing a configuration according to Modification 3. Figure 16 is a timing chart showing the operation according to Modification 3.

[0087] In Modification 2, the gate capacitance of the pixel source follower transistor SFd is used, while in Modification 3, the capacitor Cc is connected to the output terminal of the photodiode PD, and a negative pulse is applied to the output terminal of the photodiode PD via the capacitor Cc. In this case, the negative pulse is preferably applied during a period shorter than half a frame period.

[0088] With this configuration, effects similar to those according to Modification 2 can be achieved.

[0089] Modified Form 4

[0090] As described above, in an image sensor according to an embodiment of the present disclosure, a reset transistor is omitted from the pixel circuit. In situations where such an image sensor is used for an in-vehicle camera, flickering of light-emitting diodes (LEDs) in the logarithmic region becomes a problem. For example, US20210084243A1 proposes using a peak hold circuit to suppress flicker caused by LEDs.

[0091] Figure 17 is a diagram showing a configuration according to Modification 4, and shows a configuration in which a peak hold circuit 14 is inserted between the photodiode PD and the pixel source follower transistor SFd to suppress LED flicker.

[0092] The peak hold circuit 14 includes a p-channel peak hold transistor PH, an n-channel switching transistor SWsig, and a hold capacitor Csig.

[0093] The drain of the peak hold transistor PH is connected to the pulse-driven injection power supply, and the source is connected to the drain of the switching transistor SWsig. The source of the switching transistor SWsig is connected to the power supply (eg, ground) and the gate of the pixel source follower transistor SFd via the holding capacitor Csig.

[0094] The load transistor Load, the transfer transistor Tran and the transfer capacitor Cgl are connected by a circuit similar to Figure 5 The pixel source follower transistor SFd, the load transistor Load, and the transfer transistor Tran are all n-channel FETs.

[0095] Figure 18 is a timing diagram showing the operation according to Modification 4. When the accumulation time of the (n-1)th frame ends, the transfer transistor Tran is turned on, while the switching transistor SWsig is turned off. Therefore, the voltage held in the holding capacitor Csig in the (n-1)th frame is transferred to the transfer capacitor Cgl via the pixel source follower transistor SFd and the transfer transistor Tran.

[0096] The operation is performed simultaneously on pixels arranged together in a two-dimensional manner. In other words, the signal accumulation time is the same among all pixels.

[0097] After the signal voltage is held in the transfer capacitors Cgl of all pixels in the above-described manner, the transfer transistors Tran are turned off.

[0098] Next, the switching transistor SWsig is turned on, and in this state, the injection power supply connected to the drain of the peak hold transistor PH is set to a high level for a short period. Thus, holes are injected into the holding capacitor Csig via the peak hold transistor PH and the switching transistor SWsig. Furthermore, in the state in which the switching transistor SWsig is turned on, a voltage corresponding to the voltage at the output terminal of the photodiode PD (the signal voltage of the nth frame) is accumulated in the holding capacitor Csig.

[0099] On the other hand, the signal voltage is held in the transfer capacitors Cgl of all pixels. Therefore, the row selection transistors SEL of the pixels on each horizontal row are sequentially turned on, and the signals of the pixels in each row are sequentially read out and supplied to the AD converter 20. Thus, the signal of the (n-1)th frame is supplied to the AD converter 20.

[0100] The AD converter 20 performs AD conversion to supply the current signal V2 (digital signal) of each pixel to the frame memory 22 and the conversion function block 24. The signal V1 of the previous frame is supplied from the frame memory 22 to the conversion function block 24. The conversion function block 24 uses a conversion table based on the signal V1 of the previous frame of the frame memory 22 and the current signal V2 to output the real signal Isig.

[0101] In this way, signals are accumulated at the same timing in all pixels, and LED flicker can be removed by the peak hold circuit.

[0102] Modified Form 5

[0103] Figure 19 is a diagram showing a configuration according to Modification 5. In Modification 5, two switching transistors, namely, a switching transistor SWodd and a switching transistor SWeve, are connected to the peak hold circuit 14. Furthermore, a holding capacitor Codd and a gate of a source follower transistor SF1 are connected to the switching transistor SWodd, and a holding capacitor Ceve and a gate of a source follower transistor SF2 are connected to the switching transistor SWeve.

[0104] With this configuration, the two hold capacitors Codd and Ceve can separately hold signals. In this example, in odd-numbered frames, the switching transistor SWodd is turned on, and the signal of that frame is accumulated in the hold capacitor Codd. At this time, the switching transistor SWeve is turned off, and the hold capacitor Ceve holds the signal of the previous even-numbered frame. In this state, the source follower transistors SF2 of the pixels in each horizontal row are sequentially turned on to supply the signals of the even-numbered frames to the AD converter 20. This allows the real signals of the even-numbered frames to be output from the conversion function block 24.

[0105] In the next even-numbered frame, the switching transistor SWeve is turned on, and the switching transistor SWodd is turned off. Therefore, the signal of the even-numbered frame can be accumulated in the holding capacitor Ceve, and the signal of the odd-numbered frame can be read out from the holding capacitor Codd.

[0106] Furthermore, when the on / off timing of the switching transistor SWodd and the on / off timing of the switching transistor SWeve are set to the same timing in all pixels, the accumulation time can be set to be the same in all pixels.

[0107] Note that at the start of integration, holes are injected into the retention capacitor Codd and the retention capacitor Ceve in a manner similar to the above case.

Claims

1. An image sensor, comprising: a plurality of pixels, wherein each pixel of the plurality of pixels comprises: a photodiode configured to operate in both a linear mode and a photovoltaic mode, wherein the linear mode comprises a linear response to an incident light amount and the photovoltaic mode comprises a logarithmic response to an incident light amount; a pixel source follower transistor configured to output a signal voltage corresponding to a signal generated based on an output of the photodiode; a pixel switch transistor configured to switch on or off the output of the pixel source follower transistor; a holding capacitor connected to an output terminal of the pixel switching transistor and configured to hold a voltage corresponding to the output of the photodiode; and an output source follower circuit configured to output the voltage held by the holding capacitor as an output signal voltage; an analog-to-digital converter, wherein the analog-to-digital converter converts the output signal voltage output from the output source follower circuit of each of the plurality of pixels into digital signal data; a frame memory, wherein the frame memory stores the digital signal data of one frame period; A conversion function block, wherein the conversion function block generates an optical signal related to the incident light amount based on digital signal data of a current frame and digital signal data of a previous frame, wherein the pixel switching transistors of the plurality of pixels of the entire image sensor are turned on at the same timing and the voltage is maintained in the holding capacitor. 2 . The image sensor according to claim 1 , wherein the conversion function block generates the optical signal according to the digital signal data of the current frame and the digital signal data of the previous frame using a Lambertian W function. 3 . The image sensor according to claim 1 , wherein the conversion function block comprises a table for obtaining the optical signal according to the digital signal data of the current frame and the digital signal data of the previous frame. 4 . The image sensor according to claim 1 , wherein the pixel source follower transistor is driven in a state in which a charge exists or no charge exists in a channel of the pixel source follower transistor.

5. The image sensor according to claim 1 , wherein the current flowing through the source of the pixel source follower transistor is made greater than Idrk 2 Divided by Ideq, where Idrk is the sum of dark currents generated from the pixel source follower transistor, the load transistor, and the pixel switch transistor, and Ideq is a value obtained by dividing the number of elementary charges q by time in seconds (=q / s).

Images