Variable resistance memory device

Abstract

A variable resistance memory device includes: a substrate at least partially defining a peripheral region surrounding a cell region; a lower insulating layer in the cell region and the peripheral region; a magnetic tunnel junction structure in the cell region; a capping layer conformally covering both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell region; a buried insulating layer burying the magnetic tunnel junction structure in the cell region; and an interlayer insulating layer covering a second portion of the lower insulating layer in the peripheral region. The buried insulating layer and the interlayer insulating layer include respective tapered contact surfaces. Respective vertical contact surfaces of the buried insulating layer and the interlayer insulating layer contact each other at an interface extending in a vertical direction from a top surface of a second portion of the lower insulating layer in the peripheral region to a first height.

Description

[0001] Cross-references to related applications

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0032181 filed on March 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present inventive concept relates to a variable resistance memory device. More particularly, the present inventive concept relates to a variable resistance memory device including a magnetic tunnel junction structure. Background Art

[0004] With the recent trend toward higher speeds and lower power consumption in electronic products, semiconductor devices embedded in these products are becoming increasingly demanding in terms of fast read / write operations and low operating voltages. In response to this demand, highly integrated variable resistance memory devices have emerged as the next generation of memory devices, as they enable high-speed read and write operations and are nonvolatile. In particular, much research has been conducted on variable resistance memory devices that utilize the magnetoresistive properties of magnetic tunnel junctions (MTJs). Summary of the Invention

[0005] Some example embodiments of the inventive concepts provide a variable resistance memory device having improved reliability.

[0006] Technical problems to be solved by some exemplary embodiments of the present inventive concept are not limited to the above-mentioned technical problems, and those of ordinary skill in the art will understand other technical problems from the following description.

[0007] According to some example embodiments of the inventive concepts, there is provided a variable resistance memory device.

[0008] According to some example embodiments of the present invention, a variable resistance memory device may include: a substrate at least partially defining a cell region and a peripheral region, the peripheral region surrounding the cell region. The variable resistance memory device may include: a plurality of first plugs on the substrate in the cell region, the plurality of first plugs including cell plugs and via plugs; a second plug on the substrate in the peripheral region; a lower insulating layer in both the cell region and the peripheral region, the lower insulating layer covering both the plurality of first plugs and the second plugs; a magnetic tunnel junction structure in the cell region and passing through the lower insulating layer to electrically connect to the cell plugs; a capping layer in the cell region, the capping layer conformally covering both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell region; a buried insulating layer in the cell region, the buried insulating layer burying the magnetic tunnel junction structure; and an interlayer insulating layer at least partially in the peripheral region, the interlayer insulating layer covering a second portion of the lower insulating layer in the peripheral region. Respective contact surfaces of the buried insulating layer and the interlayer insulating layer may contact each other at a boundary between the cell region and the peripheral region. The contact surface of the interlayer insulating layer may include a tapered contact surface having a tapered shape that at least partially defines an overall horizontal width of the interlayer insulating layer in a horizontal direction parallel to the top surface of the substrate, such that the overall horizontal width of the interlayer insulating layer gradually decreases toward the substrate in a vertical direction perpendicular to the top surface of the substrate, and the contact surface of the buried insulating layer may include a separate tapered contact surface having a tapered shape that at least partially defines an overall horizontal width of the buried insulating layer in the horizontal direction, such that the overall horizontal width of the buried insulating layer gradually increases in the vertical direction toward the substrate. The contact surface of the interlayer insulating layer and the contact surface of the buried insulating layer may include respective vertical contact surfaces that contact each other at an interface extending in a vertical direction from the top surface of the second portion of the lower insulating layer in the peripheral region to a first height above the top surface of the second portion of the lower insulating layer in the peripheral region.

[0009] According to some example embodiments of the present invention, a variable resistance memory device may include: a substrate at least partially defining a cell region and a peripheral region, the peripheral region surrounding the cell region. The variable resistance memory device may include: a cell plug and a via plug on the substrate in the cell region; a peripheral plug on the substrate in the peripheral region; a lower insulating layer at least partially overlapping each of the cell plug, the via plug, and the peripheral plug in a vertical direction perpendicular to a top surface of the substrate in both the cell region and the peripheral region; a magnetic tunnel junction structure on the lower insulating layer in the cell region, the magnetic tunnel junction structure including a stack of a lower electrode, a magnetic tunnel junction pattern, and an upper electrode, the magnetic tunnel junction structure passing through the lower insulating layer to be electrically connected to the cell plug; a capping layer in the cell region conformally covering both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell region; a buried insulating layer in the cell region filling a space between adjacent magnetic tunnel junction structures; and an interlayer insulating layer in the peripheral region covering a second portion of the lower insulating layer in the peripheral region. The buried insulating layer and the interlayer insulating layer may contact each other at a boundary between the cell region and the peripheral region, the boundary extending from the top surface of the lower insulating layer to a first height in a vertical direction, and the lower electrode having a thickness greater than or equal to the first height. The interlayer insulating layer may have a tapered shape having a horizontal width in a horizontal direction that gradually decreases in the vertical direction from the top surface of the interlayer insulating layer to the first height toward the substrate, and the buried insulating layer may have a tapered shape having a horizontal width in a horizontal direction that gradually increases in the vertical direction from the top surface of the buried insulating layer to the first height toward the substrate, the horizontal direction being parallel to the top surface of the substrate.

[0010] According to some example embodiments of the present invention, a variable resistance memory device may include: a substrate at least partially defining a cell region and a peripheral region, the peripheral region surrounding the cell region. The variable resistance memory device may include: a cell plug and a via plug on the substrate in the cell region; a peripheral plug on the substrate in the peripheral region; a lower insulating layer, in both the cell region and the peripheral region, the lower insulating layer at least partially overlapping with each of the cell plug, the via plug, and the peripheral plug in a vertical direction, the vertical direction being perpendicular to a top surface of the substrate; a magnetic tunnel junction structure on the lower insulating layer in the cell region, the magnetic tunnel junction structure including a lower electrode, a magnetic tunnel junction pattern, and an upper electrode stacked in sequence, the magnetic tunnel junction structure passing through the lower insulating layer to be electrically connected to the cell plug; a capping layer, in the cell region, the capping layer conformally covering the magnetic tunnel junction structure and the lower insulating layer. The first portion of the capping layer in the cell region; a buried insulating layer, the buried insulating layer comprising: a first buried insulating layer in the cell region, filling a space between adjacent magnetic tunnel junction structures in a horizontal direction parallel to the top surface of the substrate, so that no gap exists between adjacent magnetic tunnel junction structures in the horizontal direction; and a second buried insulating layer, in the cell region, the second buried insulating layer extending in the horizontal direction, the second buried insulating layer covering both the uppermost surface of the capping layer and the top surface of the first buried insulating layer; and an interlayer insulating layer, in the peripheral region, the interlayer insulating layer covering the lower insulating layer, the interlayer insulating layer being formed of a material different from that of the buried insulating layer. The buried insulating layer and the interlayer insulating layer may contact each other at a boundary between the cell region and the peripheral region, the boundary extending in the vertical direction from the top surface of the lower insulating layer to a first height, and the lower electrode having a thickness greater than or equal to the first height. The interlayer insulating layer may have a tapered shape having a horizontal width in a horizontal direction that gradually decreases in a vertical direction from a top surface of the interlayer insulating layer to a first height toward the substrate, and the buried insulating layer has a tapered shape having a horizontal width in a horizontal direction that gradually increases in a vertical direction from a top surface of the buried insulating layer to the first height toward the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a circuit diagram illustrating a cell array of a variable resistance memory device according to some example embodiments;

[0013] Figure 2 is a diagram illustrating a method according to some example embodiments Figure 1 A circuit diagram of a magnetoresistive memory unit;

[0014] Figure 3 is a diagram illustrating a method according to some example embodiments Figure 2 A perspective view of a magnetoresistive memory cell;

[0015] Figure 4 is a plan view for describing a variable resistance memory device according to some example embodiments;

[0016] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 is a cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to a process sequence according to some example embodiments;

[0017] Figure 13 is a diagram illustrating a configuration of a data processing system including a variable resistance memory device according to some example embodiments; and

[0018] Figure 14 is a diagram illustrating a configuration of a data processing system including a variable resistance memory device according to some example embodiments. DETAILED DESCRIPTION

[0019] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same elements are represented by the same reference numerals, and repeated description thereof will be omitted.

[0020] In addition, unless an explicit expression such as "one" or "single" is used, expressions written in the singular may be interpreted as singular or plural. Terms including ordinal numbers such as first and second may be used to describe various elements, but the elements are not limited to these terms. These terms may be used to distinguish one component from another.

[0021] Throughout the specification, the term "connected" not only means that two or more components are directly connected, but also means that two or more components are indirectly connected through another component. In addition, unless explicitly described to the contrary, the word "include" and variations such as "comprises" or "comprising" will be understood to mean including the elements stated but not excluding any other elements.

[0022] It will be understood that when an element (e.g., a layer, film, region, or substrate) is referred to as being "on" another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly above" another element, there are no intervening elements. Furthermore, when an element is referred to as being "above" or "on" a reference element, the element can be above or below the reference element, or horizontally adjacent to the reference element, and is not necessarily referred to as being "above" or "on" in a direction opposite to gravity.

[0023] It will be understood that elements and / or characteristics of elements (e.g., structures, surfaces, directions, etc.) that may be referred to as being “perpendicular”, “parallel”, “coplanar”, etc. relative to other elements and / or characteristics of other elements (e.g., structures, surfaces, directions, etc.) may be “perpendicular”, “parallel”, “coplanar”, etc., respectively, relative to other elements and / or characteristics of other elements or may be “substantially perpendicular”, “substantially parallel”, “substantially coplanar”, respectively, relative to other elements and / or characteristics of other elements.

[0024] Elements and / or features of elements (e.g., structures, surfaces, directions, etc.) that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other elements and / or features of other elements will be understood to be “perpendicular,” “parallel,” or “coplanar,” respectively, relative to other elements and / or features of other elements within manufacturing tolerances and / or material tolerances, and / or having a deviation in magnitude and / or angle from being “perpendicular,” “parallel,” or “coplanar,” respectively, relative to other elements and / or features of other elements that is equal to or less than 10% (e.g., a tolerance of ±10%).

[0025] It will be understood that elements and / or characteristics of elements may be recited herein as being “equivalent,” “identical,” or “equal” to other elements and / or characteristics of other elements, and it will be further understood that elements and / or characteristics of elements recited herein as being “equivalent,” “identical,” or “equal” to other elements and / or characteristics of other elements may be “equivalent,” “identical,” or “equal” or “substantially equivalent,” “substantially identical,” or “substantially equal” to the characteristics of other elements and / or other elements. Elements and / or characteristics of elements that are “substantially equivalent,” “substantially identical,” or “substantially equal” to the characteristics of other elements and / or other elements will be understood to include elements and / or characteristics of elements that are equivalent, identical, or equal to the characteristics of other elements and / or other elements within manufacturing tolerances and / or material tolerances. Elements and / or characteristics of elements that are equivalent or substantially equivalent, equal or substantially equal, and / or identical or substantially identical to the characteristics of other elements and / or other elements may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition. Although the terms "same," "equal," or "equivalent" may be used in the description of some example embodiments, it should be understood that some imprecision may exist. Therefore, when an element or characteristic is referred to as being equal, equivalent, or identical to another element or characteristic, it should be understood that the element or characteristic is identical to the other element or characteristic within a desired manufacturing or operating tolerance (e.g., ±10%).

[0026] It will be understood that elements and / or characteristics of elements described herein as being "substantially" the same, equal, and / or equivalent include elements and / or characteristics of elements having a relative difference in magnitude of 10% or less. Furthermore, regardless of whether an element and / or characteristic of an element is qualified as "substantially," it will be understood that these elements and / or characteristics of an element should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the element and / or characteristic of the element.

[0027] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. Furthermore, when the terms "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the geometric shape is not required to be precise, but that the tolerance of the shape is within the scope of the present disclosure. Furthermore, regardless of whether a numerical value or shape is modified as "about" or "substantially," it will be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween (e.g., increments of 0.1%).

[0028] As described herein, when an operation is described as being performed, or an effect such as a structure is described as being established “by” or “via” performing an additional operation, it will be understood that the operation can be performed and / or the effect / structure can be established “based on” the additional operation, which may include performing the additional operation alone or in combination with other additional operations.

[0029] As described herein, an element described as being “spaced apart” from another element generally and / or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as “separated” from another element may be understood to be isolated from directly contacting the other element generally and / or in a particular direction (e.g., isolated from directly contacting the other element in a vertical direction, isolated from directly contacting the other element in a laterally or horizontal direction, etc.). Similarly, elements described as being “spaced apart” from each other generally and / or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as separated from each other may be understood to be isolated from directly contacting each other generally and / or in a particular direction (e.g., isolated from directly contacting each other in a vertical direction, isolated from directly contacting each other in a laterally or horizontal direction, etc.). Similarly, a structure described herein as being between two other structures to separate the two other structures from each other may be understood to be configured to isolate the two other structures from directly contacting each other.

[0030] Because the present invention allows for various variations and numerous exemplary embodiments, some exemplary embodiments will be illustrated in the drawings and described in the detailed description. However, this is not intended to limit the scope of the present invention to specific embodiments, but it should be understood that the present invention encompasses all variations, equivalents, and / or alternatives that do not depart from the spirit and technical scope of the present invention. In the description of some exemplary embodiments, certain detailed explanations of related art may be omitted when it is deemed that they may unnecessarily obscure the main purpose of the present invention.

[0031] Figure 1 is a circuit diagram illustrating a cell array of a variable resistance memory device according to some example embodiments. Figure 2 is a diagram illustrating a method according to some example embodiments Figure 1 Circuit diagram of a magnetoresistive memory cell. Figure 3 is a diagram illustrating a method according to some example embodiments Figure 2 A perspective view of a magnetoresistive memory cell. Figure 4 is a plan view for describing a variable resistance memory device according to some example embodiments.

[0032] Reference together Figures 1 to 4 In some example embodiments, the variable resistance memory device VRM may be a magnetoresistive memory device.

[0033] like Figure 1 As shown, the magnetoresistive memory device may be a magnetoresistive random access memory (MRAM). The variable resistance memory device VRM may include a magnetic tunnel junction (MTJ) as a variable resistance layer.

[0034] The variable resistance memory device VRM may include a magnetoresistive memory cell array 10. The magnetoresistive memory cell array 10 may be referred to as a cell array and may be connected to a write driver 12, a selection circuit 14, a source line voltage generator 18, and a sense amplifier 16.

[0035] The magnetoresistive memory cell array 10 may include a plurality of magnetoresistive memory cells 10u. The magnetoresistive memory cell 10u may be simply referred to as a memory cell. The magnetoresistive memory cell array 10 may include a plurality of word lines WL1 to WLm and a plurality of bit lines BL1 to BLn (n and m are each independently any positive integer). The magnetoresistive memory cell array 10 may include a magnetoresistive memory cell 10u between each of the plurality of word lines WL1 to WLm and each of the plurality of bit lines BL1 to BLn.

[0036] The magnetoresistive memory cell array 10 may include a plurality of cell transistors MN11 to MNmn including respective gates connected to individual word lines among a plurality of word lines WL1 to WLm, and a plurality of magnetic tunnel junctions MTJ11 to MTJmn, each of which is connected between an individual cell transistor among the plurality of cell transistors MN11 to MNmn and a bit line among a plurality of bit lines BL1 to BLn to at least partially include a variable resistance layer.

[0037] The write driver 12 may be connected to the plurality of bit lines BL1 to BLn. The write driver 12 may generate a program current based on write data, and the write driver 12 may provide the program current to the plurality of bit lines BL1 to BLn.

[0038] The selection circuit 14 may selectively connect the plurality of bit lines BL1 to BLn to the sense amplifier 16 in response to a plurality of column selection signals CSL_s1 to CSL_sn. The sense amplifier 16 may generate output data DOUT by amplifying a difference between an output voltage signal of the selection circuit 14 and a reference voltage VREF.

[0039] Sources (e.g., individual sources) of the plurality of cell transistors MN11 to MNmn may be connected to a source line SL. To magnetize the plurality of magnetic tunnel junctions MTJ11 to MTJmn in the magnetoresistive memory cell array 10, a voltage higher than the voltage applied to the plurality of bit lines BL1 to BLn may be applied to the source line SL. The source line voltage generator 18 may generate a source line drive voltage VSL and may provide the source line drive voltage VSL to the source line SL of the magnetoresistive memory cell array 10.

[0040] like Figure 2 and Figure 3 As shown, the magnetoresistive memory cell 10u may include, for example, a cell transistor MN11, which is an NMOS transistor, and a magnetic tunnel junction MTJ11. The cell transistor MN11 includes a gate connected to a word line WL1 and a source connected to a source line SL. The magnetic tunnel junction MTJ11 is connected between the drain of the cell transistor MN11 and the bit line BL1.

[0041] like Figure 2 and Figure 3 As shown, the magnetic tunnel junction MTJ11 may include a pinned layer PL having a fixed constant magnetization direction, a free layer FL magnetized in a direction of a magnetic field applied from the outside, and a tunnel barrier layer TBL formed as an insulating layer between the pinned layer PL and the free layer FL.

[0042] In some example embodiments, the fixed layer PL may include at least one of iron manganese (FeMn), iridium manganese (IrMn), platinum manganese (PtMn), manganese oxide (MnO), manganese sulfide (MnS), manganese tellurium (MnTe), manganese fluoride (MnF2), iron fluoride (FeF2), iron chloride (FeCl2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), chromium (Cr), iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), or rhodium (Rh).

[0043] In some example embodiments, the free layer FL may be a ferromagnetic material including at least one of iron (Fe), nickel (Ni), or cobalt (Co).

[0044] In some example embodiments, the tunnel barrier layer TBL may include aluminum oxide (AlO) or magnesium oxide (MgO).

[0045] The magnetic tunnel junction MTJ 11 may be included in a memory cell at least partially including a spin transfer torque (STT)-MRAM.

[0046] For a write operation of the STT-MRAM, a logic high voltage may be applied to the word line WL1 to turn on the cell transistor MN11 , and a write current may be applied between the bit line BL1 and the source line SL.

[0047] For a read operation of the STT-MRAM, a logic high voltage may be applied to the word line WL1 to turn on the cell transistor MN11, and a read current may be applied from the bit line BL1 to the source line SL to determine data stored in the magnetoresistive memory cell 10u based on a resistance value of the magnetic tunnel junction MTJ11 relative to the read current.

[0048] The resistance value of the magnetic tunnel junction MTJ11 varies depending on the magnetization direction of the free layer FL. For example, in the magnetic tunnel junction MTJ11, the magnetization directions of the free layer FL and the fixed layer PL may be parallel to each other. In this case, the magnetic tunnel junction MTJ11 may have a low resistance value, and data (e.g., 0) may be read. Furthermore, the magnetic tunnel junction MTJ11 may be arranged so that the magnetization direction of the free layer FL is antiparallel to the magnetization direction of the fixed layer PL. In some example embodiments, the magnetic tunnel junction MTJ11 may have a high resistance value, and data (e.g., 1) may be read.

[0049] Although a horizontal magnetic device is shown in which the magnetization directions of the free layer FL and the pinned layer PL of the magnetic tunnel junction MTJ11 are horizontal, in other embodiments, a vertical magnetic device in which the magnetization directions of the free layer FL and the pinned layer PL are vertical may be used.

[0050] like Figure 4 As shown, the variable resistance memory device VRM may include a cell area CA and a peripheral area PA surrounding the cell area CA. In some example embodiments, the variable resistance memory device VRM may include a boundary area between the cell area CA and the peripheral area PA.

[0051] The unit area CA may include Figure 1 The area where the magnetoresistive memory cell array 10 is located. In addition, the cell area CA may be Figure 1 and Figure 2 The area where the magnetoresistive memory unit 10u is located.

[0052] Peripheral circuits and peripheral transistors of the magnetoresistive memory cell array 10 for controlling the cell area CA may be located in the peripheral area PA. That is, the peripheral area PA may be an area where core / peripheral circuits are located.

[0053] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 2 is a cross-sectional view illustrating a method of manufacturing a variable resistance memory device according to a process sequence according to some example embodiments.

[0054] Reference Figure 5 , a substrate 101 having a cell area CA and a peripheral area PA separated therefrom may be prepared. In some example embodiments, the substrate 101 may be understood to have and / or at least partially define the cell area CA and the peripheral area PA, such that the peripheral area PA partially or completely surrounds the cell area CA in a plan view (e.g., in an XY plane extending along the X-axis and Y-axis directions).

[0055] The substrate 101 may be a semiconductor wafer including silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some example embodiments, the substrate 101 may have an impurity-doped well or an impurity-doped structure as a conductive region.

[0056] Although not shown, cell transistors may be formed on the substrate 101 in the cell region CA. The cell transistors may be buried gate transistors. In addition, peripheral circuit transistors may be formed on the substrate 101 in the peripheral region PA. The peripheral circuit transistors may be planar transistors.

[0057] A base insulating layer 110 may be formed on the substrate 101 , and a plurality of first plugs 111 and a plurality of second plugs 112 may be formed through the base insulating layer 110 .

[0058] Specifically, in the cell area CA, a plurality of first plugs 111 may be formed, connected to the cell transistors or to lower metal lines (not shown). For example, the plurality of first plugs 111 may be formed on the substrate 101 in the cell area CA (e.g., on a portion of the substrate 101 that is in the cell area CA and / or that at least partially defines the cell area CA). The plurality of first plugs 111 may include cell plugs 111 a and via plugs 111 b. The cell plugs 111 a may be connected to the cell transistors, and the via plugs 111 b may be connected to the lower metal lines. Furthermore, in the peripheral area PA, a plurality of second plugs 112 may be formed, connected to the peripheral circuit transistors. For example, the plurality of second plugs 112 may be formed on the substrate 101 in the peripheral area PA (e.g., on a portion of the substrate 101 that is in the peripheral area PA and / or that at least partially defines the peripheral area PA). It will be understood that elements described herein as “in” the cell area CA or the peripheral area PA may be understood as being on portions of the substrate 101 in and / or at least partially defining the cell area CA or the peripheral area PA, respectively.

[0059] Reference Figure 6 A lower insulating layer 120 may be formed over the cell area CA and the peripheral area PA, covering both the plurality of first plugs 111 and the plurality of second plugs 112 (e.g., at least partially overlapping both the plurality of first plugs 111 and the plurality of second plugs 112 in the Z-axis direction). The lower insulating layer 120 may be understood to extend within both the cell area CA and the peripheral area PA, and therefore, may extend between the cell area CA and the peripheral area PA. The Z-axis direction may extend perpendicular to the in-plane direction of the substrate 101 (e.g., perpendicular to the top surface 101s of the substrate 101). The X-axis and Y-axis directions may each extend parallel to the in-plane direction of the substrate 101 (e.g., parallel to the top surface 101s of the substrate 101) and may extend perpendicular to each other.

[0060] The lower insulating layer 120 may include a first lower insulating layer 121 and a second lower insulating layer 123 formed on the first lower insulating layer 121. The first lower insulating layer 121 and the second lower insulating layer 123 may include different materials.

[0061] In some example embodiments, the first lower insulating layer 121 may be formed of a SiCN film, a SiOC film, a SiOF film, a SiCH film, a SiOCH film, or any combination thereof.

[0062] In some example embodiments, the second lower insulating layer 123 may be formed of a tetraethoxysilane (TEOS) film, but is not limited thereto.

[0063] In some example embodiments, the thickness of the second lower insulating layer 123 formed in the peripheral area PA (e.g., thickness in the Z-axis direction) may be less than the thickness of the second lower insulating layer 123 formed in the cell area CA (e.g., thickness in the Z-axis direction). That is, the second lower insulating layer 123 may have a stepped portion to have a greater height in the cell area CA than in the peripheral area PA. As a result, the height of the top surface 123s of the second lower insulating layer 123 may exhibit a step change from a first height H1 on the substrate 101 in the cell area CA to a smaller second height H2 on the substrate 101 in the peripheral area PA. This step change in the height of the top surface 123s of the second lower insulating layer 123 may be located at the boundary BA between the cell area CA and the peripheral area PA. In some example embodiments, the stepped portion may be formed by additionally performing an etching process on the peripheral area PA.

[0064] As described herein, the “height,” “level,” “vertical level,” etc., of an element, structure, surface, etc., may refer to the distance of the element, structure, surface, etc. from a reference position (e.g., substrate 101, top surface 101s of substrate 101, etc.) in the Z-axis direction. Thus, when an element is described as having a greater or lesser height than another element, it will be understood that the element is at a greater or lesser distance, respectively, in the Z-axis direction from a reference position (e.g., substrate 101, top surface 101s of substrate 101, etc.).

[0065] Next, in the cell region CA, a pad electrode 113 may be formed that passes through the lower insulating layer 120 (e.g., extends in the Z-axis direction) and contacts and is electrically connected to the cell plug 111 a. The pad electrode 113 may be formed only on the cell plug 111 a among the plurality of first plugs 111, and may not be formed on the via plug 111 b among the plurality of first plugs 111 (e.g., may not overlap with the via plug 111 b among the plurality of first plugs 111 in the Z-axis direction), and may not be formed on the plurality of second plugs 112 (e.g., may not overlap with the plurality of second plugs 112 in the Z-axis direction).

[0066] Reference Figure 7 , a preliminary lower electrode 131P may be formed in the cell area CA and the peripheral area PA. The preliminary lower electrode 131P may be formed to cover both the upper portion (e.g., top surface) of the cell area CA and the upper portion (e.g., top surface) of the peripheral area PA (e.g., to cover the top surface 123s of the second lower insulating layer 123 in both the cell area CA and the peripheral area PA). Due to chemical mechanical polishing, the top surface 131Ps1 of the preliminary lower electrode 131P in the cell area CA and the top surface 131Ps2 of the preliminary lower electrode 131P in the peripheral area PA may be at the same level (e.g., the same distance from the top surface 101s of the substrate 101 in the Z-axis direction, coplanar on the XY plane, etc.). That is, due to the height of the second lower insulating layer 123 in the cell area CA (e.g., Figure 6 The first height H1 shown in FIG. 1 is greater than the height of the second lower insulating layer 123 in the peripheral area PA (eg, Figure 6 The step portion is formed by the difference between the second height H2 shown in FIG. Figure 6 ), a thickness T2 of the preliminary lower electrode 131P in the peripheral area PA (eg, in the Z-axis direction) may be greater than a thickness T1 of the preliminary lower electrode 131P in the cell area CA (eg, in the Z-axis direction). In some example embodiments, the preliminary lower electrode 131P may include TiN.

[0067] Reference Figure 8In the cell area CA, a magnetic tunnel junction structure 130 including a lower electrode 131 obtained by etching a portion of the preliminary lower electrode 131P and contacting and electrically connected to the pad electrode 113 may be formed.

[0068] The magnetic tunnel junction structure 130 may be located at the intersection of the first direction (X direction) and the second direction (Y direction) in the mesh structure. Furthermore, the magnetic tunnel junction structure 130 may constitute (e.g., at least partially comprise) a memory cell. The magnetic tunnel junction structure 130 may be formed on a cell plug 111a among the plurality of first plugs 111 in the cell area CA (e.g., formed only on a cell plug 111a among the plurality of first plugs 111 in the cell area CA). That is, each individual magnetic tunnel junction structure 130 may be electrically connected to an individual cell plug 111a among the plurality of first plugs 111 in the cell area CA via an individual pad electrode 113. In some example embodiments, the pad electrode 113 may be considered part of the magnetic tunnel junction structure 130. In some example embodiments, the pad electrode 113 may not exist and / or may be part of the lower electrode 131 as a single piece of a single material, so that the magnetic tunnel junction structure 130 may be understood to pass through the lower insulating layer 120 (e.g., at least the lower electrode 131 may pass through the lower insulating layer 120) to be electrically connected to the cell plug 111a.

[0069] In some example embodiments, the magnetic tunnel junction structure 130 may have a stacked structure of a lower electrode 131, a magnetic tunnel junction pattern 133, and an upper electrode 135. The magnetic tunnel junction pattern 133 may constitute a variable resistance layer and may include Figure 2 and Figure 3 The pinned layer PL, the tunnel barrier layer TBL, and the free layer FL, the lower electrode 131, and the upper electrode 135 may each include a metal or a metal nitride.

[0070] In some example embodiments, in the process of forming the magnetic tunnel junction structure 130, a portion of the second lower insulating layer 123 may be further etched so that the second lower insulating layer 123 of the cell area CA has a round top surface. Figure 8 As shown, the second lower insulating layer 123 may have a rounded top surface 123s1 including a curved portion in the cell area CA, and a flat top surface (eg, a planar top surface 123s2) in the peripheral area PA.

[0071] Reference Figure 9A capping layer 140 may be formed above the cell area CA and the peripheral area PA, which conformally covers (e.g., directly contacts and covers in the Z-axis, X-axis, and / or Y-axis directions) the entire magnetic tunnel junction structure 130, as well as the top surface of the lower insulating layer 120 in the cell area CA (e.g., the circular top surface 123s1 of the second lower insulating layer 123) and the top surface 131s of the lower electrode 131 in the peripheral area PA (e.g., on the substrate 101 in the peripheral area PA). Therefore, the capping layer 140 can be understood as conformally covering (e.g., directly contacting) a first portion of the lower insulating layer 120 in the cell area CA (including, for example, the first portion 123a of the second lower insulating layer 123), and can be indirectly on a second portion of the lower insulating layer 120 in the peripheral area PA (including, for example, the second portion 123b of the second lower insulating layer 123), such that the lower electrode 131 in the peripheral area PA is between the capping layer 140 and the second portion of the lower insulating layer 120 in the peripheral area PA.

[0072] The capping layer 140 may be formed to protect the magnetic tunnel junction structure 130 (e.g., to isolate or encapsulate the portion of the magnetic tunnel junction structure 130 exposed from the lower insulating layer 120 from the external environment). The capping layer 140 may cover the top surface 130t and side surfaces 130s of the magnetic tunnel junction structure 130 and may extend between adjacent (e.g., neighboring) magnetic tunnel junction structures 130. Therefore, the capping layer 140 may be referred to as an encapsulation layer.

[0073] The capping layer 140 may include an insulating material, for example, silicon nitride (SiN).

[0074] In this case, the capping layer 140 can be continuously formed without being disconnected even at the boundary surface between the cell area CA and the peripheral area PA (e.g., at the boundary BA). That is, the capping layer 140 can be uniformly applied even at the boundary surface between the cell area CA and the peripheral area PA, and therefore, the lower electrode 131 and / or the second lower insulating layer 123 of the peripheral area PA may not be exposed. For example, as shown in the figure, the capping layer 140 can be continuously extended between adjacent or neighboring magnetic tunnel junction structures 130 in the cell area CA as a single piece of single material.

[0075] Reference Figure 10A buried insulating layer 151 may be formed over the cell area CA and the peripheral area PA, and the buried insulating layer 151 formed in the peripheral area PA may be removed. As a result, the buried insulating layer 151 may be on the capping layer 140 in the cell area CA, or the buried insulating layer 151 may be present only in the cell area CA (e.g., on the cell area CA) and may not be present in the peripheral area. For example, the buried insulating layer 151 may not be on any top surface 131s of the lower electrode 131 in the peripheral area PA in the Z-axis direction. In some example embodiments, the buried insulating layer 151 in the peripheral area PA may be removed using an etch-back process. In this case, the lower electrode 131 formed in the peripheral area PA may serve as an etch stopper, thereby preventing the second lower insulating layer 123 from being exposed. As shown, the buried insulating layer 151 may bury (e.g., isolate or encapsulate) the magnetic tunnel junction structure 130, the capping layer 140, and the like in the cell area CA.

[0076] The buried insulating layer 151 may include a first buried insulating layer 151a and a second buried insulating layer 151b formed on the first buried insulating layer 151a. The first buried insulating layer 151a and the second buried insulating layer 151b may include different materials such that the first buried insulating layer 151a and the second buried insulating layer 151b may have different total material compositions.

[0077] like Figure 10 As shown, in the cell area CA, the first buried insulating layer 151a may fill between the magnetic tunnel junction structures 130 (e.g., between adjacent magnetic tunnel junction structures 130 in the X-axis and / or Y-axis directions) without any gaps. For example, the first buried insulating layer 151a may fill the entire space defined between the capping layers 140 covering the magnetic tunnel junction structures 130 in the X-axis and / or Y-axis directions, such that no gaps (e.g., empty spaces including gas, vacuum, etc.) exist between the magnetic tunnel junction structures 130 in the X-axis and / or Y-axis directions. Furthermore, the second buried insulating layer 151b may be formed to cover the top surfaces 130t of the magnetic tunnel junction structures 130 (e.g., overlap the top surfaces 130t of the magnetic tunnel junction structures 130 in the Z-axis direction), wherein the top surfaces 130t of the magnetic tunnel junction structures 130 may not at least partially overlap with the first buried insulating layer 151a in the Z-axis direction. As shown in the figure, the second buried insulating layer 151b can be formed to conformally cover (e.g., directly contact and cover) the uppermost surface 140t of the capping layer 140 that can be exposed from the first buried insulating layer 151a (e.g., the uppermost surface of the capping layer 140 in the Z-axis direction), so that the second buried insulating layer 151b can conformally cover both the uppermost surface 140t of the capping layer 140 and the top surface 151at of the first buried insulating layer 151a.

[0078] In some example embodiments, the first buried insulating layer 151 a may include, but is not limited to, silicon oxide (SiO) formed by using a high density plasma (HDP) chemical vapor deposition process.

[0079] In some example embodiments, the second buried insulating layer 151 b may be formed of a SiCN film, a SiOC film, a SiOF film, a SiCH film, a SiOCH film, or any combination thereof.

[0080] Reference Figure 11 , the lower electrode 131 of the peripheral area PA (e.g., the lower electrode 131 in the peripheral area PA) may be removed. Through the above process, a zigzag portion may remain around the boundary between the cell area CA and the peripheral area PA (see portion AA). For example, the contact surface 151s of the buried insulating layer 151 may include a tapered contact surface 151sa (also interchangeably referred to herein as an inclined contact surface) and a vertical contact surface 151sb that collectively define a zigzag shape. More specifically, a zigzag portion may be formed because a boundary (e.g., defined by a vertical contact surface 151sb) is formed from the top surface (e.g., top surface 123s2) of the second lower insulating layer 123 to a specific height 151H1 (e.g., a specific height above the top surface 123s2 in the Z-axis direction), but a tapered boundary (e.g., defined by a tapered contact surface 151sa) is formed from the specific height 151H1 to a height 151H2 of the top surface 151t of the buried insulating layer 151. This portion (e.g., the zigzag shape defined by the contact surface 151s) may be retained by first forming the buried insulating layer 151 over the cell area CA and the peripheral area PA, removing the buried insulating layer 151 from the peripheral area PA, and then removing the lower electrode 131 from the peripheral area PA (e.g., to expose the top surface 123s2 of the second portion 123b of the second lower insulating layer 123 in the peripheral area PA). In some example embodiments, the lower electrode 131 may be removed by using a lift-off process.

[0081] Reference Figure 12 In the peripheral area PA, an interlayer insulating layer 152 may be formed covering a top surface of the second lower insulating layer 123 (eg, at least on a top surface 123s2 of a second portion 123b of the second lower insulating layer 123 in the peripheral area PA).

[0082] The interlayer insulating layer 152 formed in the peripheral area PA may include a material different from that of the buried insulating layer 151 in the cell area CA. As a result, the interlayer insulating layer 152 and the buried insulating layer 151 may have different overall material compositions.

[0083] In some example embodiments, the interlayer insulating layer 152 may be formed of a material having a low-k dielectric constant lower than that of silicon oxide. The interlayer insulating layer 152 may include a material having a low dielectric constant less than 3.9, for example, a low-k (LK) dielectric, an ultra-low-k (ULK) dielectric, or an extremely low-k (ELK) dielectric.

[0084] Even if the interlayer insulating layer 152 is formed in the peripheral area PA, at least a zigzag portion around a boundary surface (e.g., boundary BA) between the cell area CA and the peripheral area PA defined by the contact surface 151s of the buried insulating layer 151 may remain since it precedes the formation of the interlayer insulating layer 152 (see portion AA).

[0085] Finally, according to the present inventive concept, in a process of manufacturing a variable resistance memory device by using the lower electrode 131 included in the magnetic tunnel junction structure 130 as an etch stop film in the peripheral area PA, the lower insulating layer 120 in the peripheral area PA (e.g., the top surface 123s2 of the second portion 123b of the second lower insulating layer 123 in the peripheral area PA) can be kept from being exposed to the outside (e.g., the external environment at least in the Z-axis direction). Furthermore, by removing the lower electrode 131 before forming the interlayer insulating layer 152 in a subsequent process, the characteristic zigzag portion defined by the contact surface 151s (also referred to herein as the outer sidewall surface) of the buried insulating layer 151 can remain around the boundary BA between the cell area CA and the peripheral area PA.

[0086] The result is that Figure 12As shown, the buried insulating layer 151 and the interlayer insulating layer 152, respectively, have contact surfaces 151s and 152s (e.g., vertical contact surfaces 151sb and 152sb) in contact with each other at the boundary BA between the cell area CA and the peripheral area PA. As shown, the contact surface 152s (e.g., tapered contact surface 152sa) of the interlayer insulating layer 152 has a tapered shape that at least partially defines an overall horizontal width 152W of the interlayer insulating layer 152 in the X-axis direction (e.g., a horizontal direction parallel to the in-plane direction of the substrate 101) as being proportional to the distance from the substrate 101 in the Z-axis direction between a first height 152H1 and a second height 152H2 from the top surface 123s2 of the second portion 123b of the second lower insulating layer 123 in the Z-axis direction. The overall horizontal width 152W in the X-axis direction gradually decreases from the second height 152H2 to the first height 152H1 toward the substrate 101. As shown in the figure, the contact surface 151s (for example, the tapered contact surface 151sa) of the buried insulating layer 151 has a tapered shape, which at least partially defines the overall horizontal width 151W of the buried insulating layer 151 in the X-axis direction to be inversely proportional to the distance from the substrate 101 in the Z-axis direction between a first height 152H1 and a second height 152H2 from the top surface 123s2 of the second portion 123b of the second lower insulating layer 123 along the Z-axis direction, so that the overall horizontal width 151W in the X-axis direction gradually increases from the second height 152H2 to the first height 152H1 toward the substrate 101. As shown in the figure, the contact surface 152s (e.g., the vertical contact surface 152sb) of the interlayer insulating layer 152 and the contact surface 151s (e.g., the vertical contact surface 151sb) of the buried insulating layer 151 are in contact with each other and each extends in the Z-axis direction (e.g., extends vertically) to contact each other at an interface extending in the Z-axis direction (e.g., vertical direction), and thus define the following interface: the interface extending in the Z-axis direction where the contact surfaces 152s (e.g., 152sb) and 151s (e.g., 151sb) are in contact with each other extends from the top surface of the second portion of the lower insulating layer 120 (e.g., the top surface 123s2 of the second portion 123b of the second lower insulating layer 123 in the peripheral area PA) to a first height 152H1 from the top surface 123s2 in the Z-axis direction.

[0087] like Figure 12As shown, contact surfaces 151s and 152s define a zigzag boundary (e.g., interface BB) between the interlayer insulating layer 152 and the buried insulating layer 151. This boundary may include a discontinuous change in slope and / or a plane defined by contacting contact surfaces 151s and 152s along the boundary in the Z-axis direction (e.g., the distance in the Z-axis direction from the height of the top surface 123s2) from the top surface of the lower insulating layer 120 in the peripheral area PA. As shown, this discontinuous change in slope and / or the plane defined by contacting contact surfaces 151s and 152s may occur at a first height 152H1 above the top surface 123s2 of the second portion 123b of the second lower insulating layer 123.

[0088] like Figure 12 As shown, the distance from the top surface of the lower insulating layer 120 to the first height 152H1 in the Z-axis direction (e.g., the vertical direction) in the peripheral region (e.g., the distance from the top surface 123s2 to the first height 152H1 in the Z-axis direction) is less than or equal to the thickness 131t of the lower electrode 131 in the unit area CA in the Z-axis direction.

[0089] In some example embodiments, when the pad electrode 113 may not exist and / or may be part of the lower electrode 131 as a single piece of a single material, so that the magnetic tunnel junction structure 130 may be understood as passing through the lower insulating layer 120 (for example, at least the lower electrode 131 may pass through the lower insulating layer 120) to be electrically connected to the cell plug 111a, the thickness 131t of the lower electrode 131 in the Z-axis direction may be equal to or greater than the first height 152H1 from the top surface 123s2 in the Z-axis direction.

[0090] like Figure 12 As shown, the vertical height 123H2 of the top surface of the lower insulating layer 120 in the peripheral area PA (e.g., the height above the top surface 101s of the substrate 101 along the Z-axis direction) (e.g., the height of the top surface 123s2) can be less than the vertical height 123H1 of the uppermost top surface of the lower insulating layer 120 in the cell area CA (e.g., the vertical height 123H1 of the uppermost portion of the top surface 123s1 (e.g., as shown in the figure, the portion of the top surface 123s1 adjacent to the magnetic tunnel junction structure 130)).

[0091] like Figure 12As shown, the vertical height 123H2 of the top surface of the lower insulating layer 120 in the peripheral area PA (e.g., the height along the Z-axis direction above the top surface 101s of the substrate 101) (e.g., the height of the top surface 123s2) can be greater than the vertical height 123H3 of the lowermost top surface of the lower insulating layer 120 in the cell area CA (e.g., the vertical height 123H3 of the lowermost portion of the top surface 123s1 (e.g., as shown in the figure, the portion of the top surface 123s1 away from the magnetic tunnel junction structure 130, adjacent to the boundary BA and / or between adjacent magnetic tunnel junction structures 130)).

[0092] like Figure 12 As shown, a vertical height 151HL of the lowermost surface of the buried insulating layer 151 in the cell area CA (e.g., a height above the top surface 101s of the substrate 101 in the Z-axis direction) may be less than a vertical height 152HL of the lowermost surface of the interlayer insulating layer 152 in the peripheral area PA. As shown, the vertical height 152HL may be equal to a vertical height 123H2 of the top surface of the lower insulating layer 120 in the peripheral area PA (e.g., a height of the top surface 123s2).

[0093] like Figure 12 As shown, the lower insulating layer 120 (e.g., a first portion of the lower insulating layer 120 including the first portion 123 a of the second lower insulating layer 123) may be physically separated from the buried insulating layer 151 in the cell area CA (e.g., in the Z-axis direction), and the lower insulating layer 120 (e.g., a second portion of the lower insulating layer 120 including the second portion 123 b of the second lower insulating layer 123) may contact the interlayer insulating layer 152 in the peripheral area PA.

[0094] As described herein, the substrate 101 may define a cell area CA and a peripheral area PA, such that the substrate 101 includes a cell area portion 101 a in and / or defining the cell area CA, and a peripheral area portion 101 b in and / or defining the peripheral area PA. As described herein, elements, layers, etc. “in” the cell area CA may be interchangeably referred to as being on the substrate 101 in the cell area CA, vertically overlapping with the substrate 101 in the cell area CA, on the cell area CA, vertically overlapping with the cell area CA, on the cell area portion 101 a of the substrate 101, vertically overlapping with the cell area portion 101 a of the substrate 101, etc. As described herein, elements, layers, etc. “in” the peripheral area PA may be interchangeably referred to as being on the substrate 101 in the peripheral area PA, vertically overlapping with the substrate 101 in the peripheral area PA, on the peripheral area PA, vertically overlapping with the peripheral area PA, on the peripheral area portion 101b of the substrate 101, vertically overlapping with the peripheral area portion 101b of the substrate 101, etc.

[0095] Figure 13 is a diagram illustrating a configuration of a data processing system including a variable resistance memory device according to some example embodiments.

[0096] Reference Figure 13 , the data processing system 1000 may include a memory controller 1010 connected between a host and a variable resistance memory device VRM. The variable resistance memory device VRM may be a variable resistance memory device according to any example embodiment.

[0097] The memory controller 1010 may be configured to access the variable resistance memory device VRM in response to a request of a host.

[0098] The variable resistance memory device VRM may include at least one variable resistance memory device manufactured by using the above-described method of manufacturing a variable resistance memory device. The memory controller 1010 may include a processor 1011 , an operating memory 1013 , a host interface 1015 , and a memory interface 1017 .

[0099] The processor 1011 may control overall operations of the memory controller 1010, and the operating memory 1013 may store applications, data, and control signals required for operations of the memory controller 1010. The host interface 1015 may perform protocol conversion for data / control signal exchange between the host and the memory controller 1010.

[0100] The memory interface 1017 may perform protocol conversion for data / control signal exchange between the memory controller 1010 and the variable resistance memory device VRM. The configuration and operation characteristics of the variable resistance memory device VRM have been described above, and thus, a detailed description thereof will be omitted.

[0101] The data processing system 1000 according to some example embodiments may be, but is not limited to, a memory card.

[0102] Figure 14 is a diagram illustrating a configuration of a data processing system including a variable resistance memory device according to some example embodiments.

[0103] Reference Figure 14 The data processing system 1100 may include a variable resistance memory device VRM, a processor 1110 , an operation memory 1120 , and a user interface 1130 , and may further include a communication module 1140 when necessary.

[0104] The variable resistance memory device VRM may be the variable resistance memory device according to any example embodiment. The variable resistance memory device VRM may include at least one variable resistance memory device manufactured by using the above-described method of manufacturing a variable resistance memory device.

[0105] The processor 1110 may be a central processing unit. The operation memory 1120 stores application programs, data, and control signals required for the operation of the data processing system 1100. The user interface 1130 provides an environment in which a user can access the data processing system 1100 and provides the user with the data processing process and data processing results of the data processing system 1100. The configuration and operating characteristics of the variable resistance memory device VRM have been described above, and therefore, a detailed description thereof will be omitted.

[0106] The data processing system 1100 may be used as a magnetic disk device, as an internal / external memory card of a portable electronic device, as an image processor, or as a chipset for other applications.

[0107] As described herein, any device, system, module, portion, unit, controller, circuit, circuit system, and / or portion thereof according to any example embodiment may include, be included in, and / or be implemented by: one or more processing devices (e.g., hardware including logic circuitry); a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the one or more processing devices may more specifically include (but are not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, one or more processing devices may include a computer-readable storage device (e.g., a memory) storing a program of instructions, such as a solid-state drive (SSD), such as a non-transitory computer-readable storage device, and the one or more processing devices may also include a processor (e.g., a CPU) configured to execute the program of instructions to implement the functions and / or methods performed by some or all of any device, system, module, portion, unit, controller, circuit, circuit system, and / or portion thereof according to any example embodiment.

[0108] As described above, some exemplary embodiments have been shown in the drawings and described in the specification. Although certain exemplary embodiments have been described using specific terms, this is merely for the purpose of explaining the technical concept of the present invention and is not intended to limit the meaning and scope of the present invention described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent exemplary embodiments may be made based on the above. Therefore, the technical scope of the present invention should be defined by the appended claims.

[0109] While the inventive concept has been shown and described in detail with reference to certain example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A variable resistance memory device comprising: a substrate at least partially defining a cell region and a peripheral region, the peripheral region surrounding the cell region; a plurality of first plugs on the substrate in the cell region, the plurality of first plugs including cell plugs and via plugs; a second plug on the substrate in the peripheral region; a lower insulating layer covering both the plurality of first plugs and the second plugs in both the cell region and the peripheral region; a magnetic tunnel junction structure in the cell region and passing through the lower insulating layer to be electrically connected to the cell plug; a capping layer, wherein in the cell region, the capping layer conformally covers both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell region; a buried insulating layer, wherein in the cell region, the buried insulating layer buries the magnetic tunnel junction structure; as well as an interlayer insulating layer, at least partially in the peripheral region, the interlayer insulating layer covering a second portion of the lower insulating layer in the peripheral region, in, Respective contact surfaces of the buried insulating layer and the interlayer insulating layer are in contact with each other at a boundary between the cell region and the peripheral region, The contact surface of the interlayer insulating layer includes a tapered contact surface having a tapered shape, the tapered shape at least partially defining an overall horizontal width of the interlayer insulating layer in a horizontal direction parallel to the top surface of the substrate, such that the overall horizontal width of the interlayer insulating layer gradually decreases toward the substrate in a vertical direction perpendicular to the top surface of the substrate, and the contact surface of the buried insulating layer includes a separate tapered contact surface having a tapered shape, the tapered shape at least partially defining an overall horizontal width of the buried insulating layer in the horizontal direction, such that the overall horizontal width of the buried insulating layer gradually increases toward the substrate in the vertical direction, and The contact surface of the interlayer insulating layer and the contact surface of the buried insulating layer include respective vertical contact surfaces, which contact each other at an interface extending along the vertical direction from the top surface of the second portion of the lower insulating layer in the peripheral region to a first height above the top surface of the second portion of the lower insulating layer in the peripheral region.

2. The variable resistance memory device according to claim 1, wherein The boundary between the interlayer insulating layer and the buried insulating layer has a zigzag shape.

3. The variable resistance memory device according to claim 1, wherein The lower insulating layer has a rounded top surface including a curved portion in the cell region and has a flat top surface in the peripheral region.

4. The variable resistance memory device according to claim 3, wherein A vertical height of the lower insulating layer in the peripheral region is smaller than a vertical height of an uppermost top surface of the lower insulating layer in the cell region.

5. The variable resistance memory device according to claim 3, wherein A vertical height of the lower insulating layer in the peripheral region is greater than a vertical height of a lowermost top surface of the lower insulating layer in the cell region.

6. The variable resistance memory device according to claim 1, wherein The magnetic tunnel junction structure has a structure in which a lower electrode, a magnetic tunnel junction pattern, and an upper electrode are sequentially stacked in the vertical direction, and A distance from the top surface of the lower insulating layer to the first height in the peripheral region is less than or equal to a thickness of the lower electrode in the cell region.

7. The variable resistance memory device according to claim 1, wherein A vertical height of a lowermost surface of the buried insulating layer in the cell region is smaller than a vertical height of a lowermost surface of the interlayer insulating layer in the peripheral region.

8. The variable resistance memory device according to claim 1, wherein The lower insulating layer is physically spaced apart from the buried insulating layer in the cell region, and the lower insulating layer contacts the interlayer insulating layer in the peripheral region.

9. The variable resistance memory device according to claim 1, wherein A material of the buried insulating layer in the cell region and a material of the interlayer insulating layer in the peripheral region are different from each other.

10. The variable resistance memory device according to claim 1, wherein The capping layer is a single piece of single material extending continuously between adjacent magnetic tunnel junction structures in the cell region.

11. The variable resistance memory device according to claim 1 , further comprising: a plurality of magnetic tunnel junction structures, the plurality of magnetic tunnel junction structures including the magnetic tunnel junction structure, Wherein, the buried insulating layer comprises: a first buried insulating layer filling spaces between adjacent magnetic tunnel junction structures in the horizontal direction among the plurality of magnetic tunnel junction structures, so that no gaps exist between the adjacent magnetic tunnel junction structures in the horizontal direction among the plurality of magnetic tunnel junction structures; and A second buried insulating layer conformally covers both an uppermost surface of the capping layer and a top surface of the first buried insulating layer.

12. The variable resistance memory device according to claim 11, wherein The first buried insulating layer and the second buried insulating layer include different materials.

13. A variable resistance memory device comprising: a substrate at least partially defining a cell region and a peripheral region, the peripheral region surrounding the cell region; cell plugs and via plugs on the substrate in the cell region; a peripheral plug on the substrate in the peripheral region; a lower insulating layer at least partially overlapping each of the cell plug, the via plug, and the peripheral plug in a vertical direction perpendicular to a top surface of the substrate in both the cell region and the peripheral region; a magnetic tunnel junction structure on the lower insulating layer in the cell region, the magnetic tunnel junction structure comprising a lower electrode, a magnetic tunnel junction pattern, and an upper electrode stacked in sequence, the magnetic tunnel junction structure passing through the lower insulating layer to be electrically connected to the cell plug; a capping layer, wherein in the cell region, the capping layer conformally covers both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell region; a buried insulating layer, wherein in the cell region, the buried insulating layer fills a space between adjacent magnetic tunnel junction structures; as well as an interlayer insulating layer, wherein in the peripheral region, the interlayer insulating layer covers a second portion of the lower insulating layer in the peripheral region, in, The buried insulating layer and the interlayer insulating layer contact each other at a boundary between the cell region and the peripheral region, the boundary extending from the top surface of the lower insulating layer to a first height in the vertical direction, the lower electrode having a thickness greater than or equal to the first height, and The interlayer insulating layer has a tapered shape, the tapered shape having a horizontal width in a horizontal direction, the horizontal width gradually decreasing in the vertical direction from the top surface of the interlayer insulating layer to the first height toward the substrate, and the buried insulating layer has a tapered shape, the tapered shape having a horizontal width in the horizontal direction, the horizontal width gradually increasing in the vertical direction from the top surface of the buried insulating layer to the first height toward the substrate, and the horizontal direction is parallel to the top surface of the substrate.

14. The variable resistance memory device according to claim 13, wherein The lower insulating layer has a rounded top surface including a curved portion in the cell region and has a flat top surface in the peripheral region.

15. The variable resistance memory device according to claim 14, wherein A vertical height of the lower insulating layer in the peripheral region is smaller than a vertical height of an uppermost top surface of the lower insulating layer in the cell region, and A vertical height of the lower insulating layer in the peripheral region is greater than a vertical height of a lowermost top surface of the lower insulating layer in the cell region.

16. The variable resistance memory device according to claim 13, wherein The lower insulating layer is physically spaced apart from the buried insulating layer in the cell region, and the lower insulating layer contacts the interlayer insulating layer in the peripheral region.

17. The variable resistance memory device according to claim 13, wherein A material of the buried insulating layer in the cell region and a material of the interlayer insulating layer in the peripheral region are different from each other.

18. The variable resistance memory device according to claim 13, further comprising: a plurality of magnetic tunnel junction structures, the plurality of magnetic tunnel junction structures including the magnetic tunnel junction structure, Wherein, the buried insulating layer comprises: a first buried insulating layer filling spaces between adjacent magnetic tunnel junction structures in the horizontal direction among the plurality of magnetic tunnel junction structures, so that no gaps exist between the adjacent magnetic tunnel junction structures in the horizontal direction among the plurality of magnetic tunnel junction structures; and a second buried insulating layer conformally covering both the uppermost surface of the capping layer and the top surface of the first buried insulating layer, and The first buried insulating layer and the second buried insulating layer include different materials.

19. A variable resistance memory device comprising: a substrate at least partially defining a cell region and a peripheral region, the peripheral region surrounding the cell region; cell plugs and via plugs on the substrate in the cell region; a peripheral plug on the substrate in the peripheral region; a lower insulating layer at least partially overlapping each of the cell plug, the via plug, and the peripheral plug in a vertical direction perpendicular to a top surface of the substrate in both the cell region and the peripheral region; a magnetic tunnel junction structure on the lower insulating layer in the cell region, the magnetic tunnel junction structure comprising a lower electrode, a magnetic tunnel junction pattern, and an upper electrode stacked in sequence, the magnetic tunnel junction structure passing through the lower insulating layer to be electrically connected to the cell plug; a capping layer, wherein in the cell region, the capping layer conformally covers both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell region; A buried insulating layer, the buried insulating layer comprising: a first buried insulating layer in the cell region and filling a space between adjacent magnetic tunnel junction structures in a horizontal direction parallel to the top surface of the substrate so that no gap exists between the adjacent magnetic tunnel junction structures in the horizontal direction; and a second buried insulating layer, extending in the horizontal direction in the cell region, the second buried insulating layer covering both an uppermost surface of the capping layer and a top surface of the first buried insulating layer; and an interlayer insulating layer covering the lower insulating layer in the peripheral region, the interlayer insulating layer being formed of a material different from that of the buried insulating layer, in, The buried insulating layer and the interlayer insulating layer contact each other at a boundary between the cell region and the peripheral region, the boundary extending from the top surface of the lower insulating layer to a first height in the vertical direction, the lower electrode having a thickness greater than or equal to the first height, and The interlayer insulating layer has a tapered shape having a horizontal width in the horizontal direction, the horizontal width gradually decreasing in the vertical direction from the top surface of the interlayer insulating layer to the first height toward the substrate, and the buried insulating layer has a tapered shape having a horizontal width in the horizontal direction, the horizontal width gradually increasing in the vertical direction from the top surface of the buried insulating layer to the first height toward the substrate.

20. The variable resistance memory device according to claim 19, wherein The lower insulating layer has a round top surface including a curved portion in the cell region and a flat top surface in the peripheral region, and A vertical height of a top surface of the lower insulating layer in the peripheral region is smaller than a vertical height of an uppermost top surface of the lower insulating layer in the cell region, and A vertical height of a top surface of the lower insulating layer in the peripheral region is greater than a vertical height of a lowermost top surface of the lower insulating layer in the cell region.

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